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Fix misc uses of "long" variables to use "int64_t".
I don't have any evidence these particular uses are actually causing any issues, but we should avoid accidentally truncating immediate values depending on the host.
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5 files changed

+7
-8
lines changed

5 files changed

+7
-8
lines changed

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3865,7 +3865,7 @@ bool AMDGPUAsmParser::validateMIMGDim(const MCInst &Inst) {
38653865
if (DimIdx < 0)
38663866
return true;
38673867

3868-
long Imm = Inst.getOperand(DimIdx).getImm();
3868+
int64_t Imm = Inst.getOperand(DimIdx).getImm();
38693869
if (Imm < 0 || Imm >= 8)
38703870
return false;
38713871

llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -177,7 +177,7 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS,
177177
LowerCompactBranch(TmpInst);
178178
}
179179

180-
unsigned long N = Fixups.size();
180+
size_t N = Fixups.size();
181181
uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
182182

183183
// Check for unimplemented opcodes.

llvm/lib/Target/PowerPC/PPCFastISel.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ struct Address {
7474
int FI;
7575
} Base;
7676

77-
long Offset;
77+
int64_t Offset;
7878

7979
// Innocuous defaults for our address.
8080
Address()
@@ -338,7 +338,7 @@ bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
338338
break;
339339
case Instruction::GetElementPtr: {
340340
Address SavedAddr = Addr;
341-
long TmpOffset = Addr.Offset;
341+
int64_t TmpOffset = Addr.Offset;
342342

343343
// Iterate through the GEP folding the constants into offsets where
344344
// we can.
@@ -437,8 +437,7 @@ void PPCFastISel::PPCSimplifyAddress(Address &Addr, bool &UseOffset,
437437

438438
if (!UseOffset) {
439439
IntegerType *OffsetTy = Type::getInt64Ty(*Context);
440-
const ConstantInt *Offset =
441-
ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
440+
const ConstantInt *Offset = ConstantInt::getSigned(OffsetTy, Addr.Offset);
442441
IndexReg = PPCMaterializeInt(Offset, MVT::i64);
443442
assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
444443
}

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15415,7 +15415,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
1541515415
MachineFunction &MF = DAG.getMachineFunction();
1541615416
MachineMemOperand *BaseMMO =
1541715417
MF.getMachineMemOperand(LD->getMemOperand(),
15418-
-(long)MemVT.getStoreSize()+1,
15418+
-(int64_t)MemVT.getStoreSize()+1,
1541915419
2*MemVT.getStoreSize()-1);
1542015420

1542115421
// Create the new base load.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -478,7 +478,7 @@ def HI16 : SDNodeXForm<imm, [{
478478

479479
def HA16 : SDNodeXForm<imm, [{
480480
// Transformation function: shift the immediate value down into the low bits.
481-
long Val = N->getZExtValue();
481+
int64_t Val = N->getZExtValue();
482482
return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
483483
}]>;
484484
def MB : SDNodeXForm<imm, [{

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