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[llvm] Fix typos in documentation (#141078)
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llvm/docs/CommandGuide/llvm-dwarfdump.rst

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@@ -162,7 +162,7 @@ OPTIONS
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.. option:: --verify-json=<path>
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Output JSON-formatted error summary to the a file specfied by
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Output JSON-formatted error summary to the a file specified by
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<path>. Implies :option:`--verify`. The output format is described
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in the section below (:ref:`verify-json-format`).
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llvm/docs/CommandGuide/llvm-objcopy.rst

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@@ -606,7 +606,7 @@ options. For GNU :program:`objcopy` compatibility, the values are all bfdnames.
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- `elf64-loongarch`
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- `elf64-s390`
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The following formats are suppoprted by :program:`llvm-objcopy` for the
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The following formats are supported by :program:`llvm-objcopy` for the
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:option:`--output-target` only:
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- `srec`

llvm/docs/DirectX/DXContainer.rst

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@@ -222,7 +222,7 @@ is an index table, and the third block is the elements themselves, which in turn
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are separeated by input, output and patch constant or primitive elements.
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Signature elements capture much of the same data captured in the :ref:`SG1
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<ISG1>` parts. The use of an index table allows de-duplciation of data for a more
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<ISG1>` parts. The use of an index table allows de-duplication of data for a more
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compact final representation.
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The string table begins with a 32-bit unsigned integer specifying the table
@@ -430,7 +430,7 @@ Static Samplers 52 Many
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Root Signature Header
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~~~~~~~~~~~~~~~~~~~~~
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The root signature header is 24 bytes long, consisting of six 32 bit values
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The root signature header is 24 bytes long, consisting of six 32-bit values
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representing the version, number and offset of parameters, number and offset
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of static samplers, and a flags field for global behaviours:
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@@ -454,7 +454,7 @@ type having different size and fields.
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The slot of root parameters is preceded by a variable size section containing
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the header information for such parameters. Such structure is 12 bytes long,
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composed of three 32 bit values, representing the parameter type, a flag
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composed of three 32-bit values, representing the parameter type, a flag
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encoding the pipeline stages where the data is visible, and an offset
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calculated from the start of RTS0 section.
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@@ -467,7 +467,7 @@ calculated from the start of RTS0 section.
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};
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After the header information has been serialized, the actual data for each of the
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root parameters is layout in a single continous blob. The parameters can be fetch
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root parameters is layout in a single continuous blob. The parameters can be fetch
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from such using the offset information, present in the header.
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The following sections will describe each of the root parameters types and their
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''''''''''''''
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The root constants are inline 32-bit values that show up in the shader
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as a constant buffer. It is a 12 bytes long structure, two 32 bit values
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as a constant buffer. It is a 12 bytes long structure, two 32-bit values
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encoding the register and space the constant is assigned to, and
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the last 32 bits encode the number of constants being defined in the buffer.
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@@ -520,7 +520,7 @@ Descriptor tables let shaders access multiple resources through a single pointer
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to a descriptor heap.
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The tables are made of a collection of descriptor ranges. In Version 1.0, the
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descriptor range is 20 bytes, containing five 32 bit values. It encodes a range
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descriptor range is 20 bytes, containing five 32-bit values. It encodes a range
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of registers, including the register type, range length, register numbers and
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space within range and the offset locating each range inside the table.
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llvm/docs/PDB/CodeViewTypes.rst

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@@ -43,12 +43,12 @@ records -- called ``member records`` do not.
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Leaf Records
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------------
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All leaf records begin with the following 4 byte prefix:
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All leaf records begin with the following 4-byte prefix:
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.. code-block:: c++
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struct RecordHeader {
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uint16_t RecordLen; // Record length, not including this 2 byte field.
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uint16_t RecordLen; // Record length, not including this 2-byte field.
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uint16_t RecordKind; // Record kind enum.
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};
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llvm/docs/RISCV/RISCVVectorExtension.rst

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@@ -260,7 +260,7 @@ VMV0 elimination
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Because masked instructions must have the mask register in ``v0``, a specific register class ``vmv0`` is used that contains only one register, ``v0``.
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However register coalescing may end up coleascing copies into ``vmv0``, resulting in instructions with multiple uses of ``vmv0`` that the register allocator can't allocate:
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However register coalescing may end up coalescing copies into ``vmv0``, resulting in instructions with multiple uses of ``vmv0`` that the register allocator can't allocate:
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.. code-block::
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llvm/docs/SPIRVUsage.rst

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@@ -188,7 +188,7 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
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* - ``SPV_INTEL_variable_length_array``
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- Allows to allocate local arrays whose number of elements is unknown at compile time.
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* - ``SPV_INTEL_joint_matrix``
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- Adds few matrix capabilities on top of SPV_KHR_cooperative_matrix extension, such as matrix prefetch, get element coordinate and checked load/store/construct instructions, tensor float 32 and bfloat type interpretations for multuply-add instruction.
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- Adds few matrix capabilities on top of SPV_KHR_cooperative_matrix extension, such as matrix prefetch, get element coordinate and checked load/store/construct instructions, tensor float 32 and bfloat type interpretations for multiply-add instruction.
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* - ``SPV_KHR_bit_instructions``
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- Enables bit instructions to be used by SPIR-V modules without requiring the Shader capability.
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* - ``SPV_KHR_expect_assume``

llvm/docs/ScudoHardenedAllocator.rst

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@@ -36,7 +36,7 @@ The allocator combines several components that serve distinct purposes:
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- the Primary allocator: fast and efficient, it services smaller allocation
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sizes by carving reserved memory regions into blocks of identical size. There
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are currently two Primary allocators implemented, specific to 32 and 64 bit
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are currently two Primary allocators implemented, specific to 32- and 64-bit
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architectures. It is configurable via compile time options.
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- the Secondary allocator: slower, it services larger allocation sizes via the

llvm/docs/SecurityTransparencyReports.rst

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@@ -218,7 +218,7 @@ Supply chain security related issues and project services-related issues
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Details are available at https://bugs.chromium.org/p/llvm/issues/detail?id=71 |br|
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redirect: https://issuetracker.google.com/issues/42410066 |br|
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archive: https://github.com/llvm/llvm-project/issues/132187
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2. “llvmbot account suspended due to supicious login” |br|
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2. “llvmbot account suspended due to suspicious login” |br|
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Details are available at https://bugs.chromium.org/p/llvm/issues/detail?id=72 |br|
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redirect: https://issuetracker.google.com/issues/42410067 |br|
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archive: https://github.com/llvm/llvm-project/issues/132243

llvm/docs/StackMaps.rst

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@@ -144,7 +144,7 @@ destructive patching could overwrite program text or data outside the
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current function. We disallow overlapping stack map shadows so that
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the runtime does not need to consider this corner case.
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For example, a stack map with 8 byte shadow:
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For example, a stack map with 8-byte shadow:
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.. code-block:: llvm
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llvm/docs/TableGen/BackEnds.rst

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@@ -914,7 +914,7 @@ table, record with name ``Banana`` will come before the record with name
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``Pear``. Because of this, the ``lookupCEntryByEncoding`` function will always
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return a pointer to the record with name ``Banana`` even though in some cases
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the correct result can be the record with name ``Pear``. Such kind of scenario
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makes the exisitng lookup function insufficient because they always return a
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makes the existing lookup function insufficient because they always return a
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pointer to a single entry from the table, but instead it should return a range
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of results because multiple entries match the criteria sought by the lookup
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function. In this case, the definition of the lookup function needs to be

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