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[RISCV][GISel] Legalize and select G_BRINDIRECT. (#73059)
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‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

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@@ -590,6 +590,10 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
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MI.eraseFromParent();
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return true;
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}
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case TargetOpcode::G_BRINDIRECT:
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MI.setDesc(TII.get(RISCV::PseudoBRIND));
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MI.addOperand(MachineOperand::CreateImm(0));
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return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
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case TargetOpcode::G_SEXT_INREG:
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return selectSExtInreg(MI, MIB);
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case TargetOpcode::G_FRAME_INDEX: {

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

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@@ -181,6 +181,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
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getActionDefinitionsBuilder(G_BRJT).legalFor({{p0, sXLen}});
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getActionDefinitionsBuilder(G_BRINDIRECT).legalFor({p0});
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getActionDefinitionsBuilder(G_PHI)
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.legalFor({p0, sXLen})
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.widenScalarToNextPow2(0)

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv32.mir

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@@ -0,0 +1,45 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \
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# RUN: -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s
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---
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name: indirectbr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; RV32I-LABEL: name: indirectbr
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; RV32I: bb.0:
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; RV32I-NEXT: successors: %bb.1, %bb.2
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; RV32I-NEXT: liveins: $x10
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:gprjalr = COPY $x10
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; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
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; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
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; RV32I-NEXT: PseudoBRIND [[COPY]], 0
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: bb.1:
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; RV32I-NEXT: $x10 = COPY [[COPY1]]
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; RV32I-NEXT: PseudoRET implicit $x10
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: bb.2:
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; RV32I-NEXT: $x10 = COPY [[ADDI]]
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; RV32I-NEXT: PseudoRET implicit $x10
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bb.1:
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successors: %bb.2, %bb.3
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liveins: $x10
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%0:gprb(p0) = COPY $x10
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%1:gprb(s32) = G_CONSTANT i32 1
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%2:gprb(s32) = G_CONSTANT i32 0
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G_BRINDIRECT %0(p0)
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bb.2:
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$x10 = COPY %2(s32)
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PseudoRET implicit $x10
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bb.3:
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$x10 = COPY %1(s32)
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PseudoRET implicit $x10
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...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv64.mir

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@@ -0,0 +1,45 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \
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# RUN: -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s
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---
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name: indirectbr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; RV64I-LABEL: name: indirectbr
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; RV64I: bb.0:
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; RV64I-NEXT: successors: %bb.1, %bb.2
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; RV64I-NEXT: liveins: $x10
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gprjalr = COPY $x10
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; RV64I-NEXT: PseudoBRIND [[COPY]], 0
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: bb.1:
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
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; RV64I-NEXT: $x10 = COPY [[COPY1]]
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; RV64I-NEXT: PseudoRET implicit $x10
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: bb.2:
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; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
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; RV64I-NEXT: $x10 = COPY [[ADDI]]
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; RV64I-NEXT: PseudoRET implicit $x10
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bb.1:
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successors: %bb.2, %bb.3
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liveins: $x10
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%0:gprb(p0) = COPY $x10
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G_BRINDIRECT %0(p0)
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bb.2:
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%4:gprb(s64) = G_CONSTANT i64 0
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$x10 = COPY %4(s64)
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PseudoRET implicit $x10
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bb.3:
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%2:gprb(s64) = G_CONSTANT i64 1
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-brindirect-rv32.mir

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@@ -0,0 +1,42 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s
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---
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name: indirectbr
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body: |
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; CHECK-LABEL: name: indirectbr
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: G_BRINDIRECT [[COPY]](p0)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: $x10 = COPY [[C1]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: $x10 = COPY [[C]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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bb.1:
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successors: %bb.2, %bb.3
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liveins: $x10
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%0:_(p0) = COPY $x10
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%1:_(s32) = G_CONSTANT i32 1
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%2:_(s32) = G_CONSTANT i32 0
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G_BRINDIRECT %0(p0)
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bb.2:
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$x10 = COPY %2(s32)
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PseudoRET implicit $x10
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bb.3:
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$x10 = COPY %1(s32)
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PseudoRET implicit $x10
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...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-brindirect-rv64.mir

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@@ -0,0 +1,42 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s
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---
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name: indirectbr
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body: |
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; CHECK-LABEL: name: indirectbr
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
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; CHECK-NEXT: G_BRINDIRECT [[COPY]](p0)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK-NEXT: $x10 = COPY [[C]](s64)
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; CHECK-NEXT: PseudoRET implicit $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK-NEXT: $x10 = COPY [[C1]](s64)
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; CHECK-NEXT: PseudoRET implicit $x10
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bb.1:
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successors: %bb.2, %bb.3
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liveins: $x10
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%0:_(p0) = COPY $x10
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G_BRINDIRECT %0(p0)
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bb.2:
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%4:_(s64) = G_CONSTANT i64 0
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$x10 = COPY %4(s64)
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PseudoRET implicit $x10
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bb.3:
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%2:_(s64) = G_CONSTANT i64 1
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...

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