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[DivRemPairs] Pre-commit tests for PR #92627 (#92628)
The tests are added to a new AMDGPU/ subdirectory since I found the missed optimization while hacking on AMDGPU code. Also, this ensures that AMDGPU, which uses DivRemPass, is being checked for existing expected behavior.
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‎llvm/test/Transforms/DivRemPairs/AMDGPU/div-rem-pairs.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt < %s -passes=div-rem-pairs -S -mtriple=amdgcn-amd-amdhsa | FileCheck %s
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define i32 @basic(ptr %p, i32 %x, i32 %y) {
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; CHECK-LABEL: define i32 @basic(
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; CHECK-SAME: ptr [[P:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) {
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; CHECK-NEXT: [[X_FROZEN:%.*]] = freeze i32 [[X]]
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; CHECK-NEXT: [[Y_FROZEN:%.*]] = freeze i32 [[Y]]
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; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[X_FROZEN]], [[Y_FROZEN]]
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; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[DIV]], [[Y_FROZEN]]
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; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[X_FROZEN]], [[TMP1]]
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; CHECK-NEXT: store i32 [[DIV]], ptr [[P]], align 4
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; CHECK-NEXT: ret i32 [[REM_DECOMPOSED]]
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;
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%div = udiv i32 %x, %y
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%rem = urem i32 %x, %y
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store i32 %div, ptr %p, align 4
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ret i32 %rem
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}
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define i32 @no_freezes(ptr %p, i32 noundef %x, i32 noundef %y) {
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; CHECK-LABEL: define i32 @no_freezes(
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; CHECK-SAME: ptr [[P:%.*]], i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) {
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; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[X]], [[Y]]
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; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[DIV]], [[Y]]
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; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[X]], [[TMP1]]
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; CHECK-NEXT: store i32 [[DIV]], ptr [[P]], align 4
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; CHECK-NEXT: ret i32 [[REM_DECOMPOSED]]
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;
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%div = udiv i32 %x, %y
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%rem = urem i32 %x, %y
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store i32 %div, ptr %p, align 4
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ret i32 %rem
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}
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; FIXME: There should be no need to `freeze` x2 and y2 since they have defined
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; but potentially poison values.
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define i32 @poison_does_not_freeze(ptr %p, i32 noundef %x, i32 noundef %y) {
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; CHECK-LABEL: define i32 @poison_does_not_freeze(
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; CHECK-SAME: ptr [[P:%.*]], i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) {
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; CHECK-NEXT: [[X2:%.*]] = shl nuw nsw i32 [[X]], 5
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; CHECK-NEXT: [[Y2:%.*]] = add nuw nsw i32 [[Y]], 1
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; CHECK-NEXT: [[X2_FROZEN:%.*]] = freeze i32 [[X2]]
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; CHECK-NEXT: [[Y2_FROZEN:%.*]] = freeze i32 [[Y2]]
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; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[X2_FROZEN]], [[Y2_FROZEN]]
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; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[DIV]], [[Y2_FROZEN]]
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; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[X2_FROZEN]], [[TMP1]]
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; CHECK-NEXT: store i32 [[DIV]], ptr [[P]], align 4
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; CHECK-NEXT: ret i32 [[REM_DECOMPOSED]]
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;
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%x2 = shl nuw nsw i32 %x, 5
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%y2 = add nuw nsw i32 %y, 1
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%div = udiv i32 %x2, %y2
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%rem = urem i32 %x2, %y2
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store i32 %div, ptr %p, align 4
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ret i32 %rem
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}
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define i32 @poison_does_not_freeze_signed(ptr %p, i32 noundef %x, i32 noundef %y) {
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; CHECK-LABEL: define i32 @poison_does_not_freeze_signed(
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; CHECK-SAME: ptr [[P:%.*]], i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) {
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; CHECK-NEXT: [[X2:%.*]] = shl nuw nsw i32 [[X]], 5
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; CHECK-NEXT: [[Y2:%.*]] = add nuw nsw i32 [[Y]], 1
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; CHECK-NEXT: [[X2_FROZEN:%.*]] = freeze i32 [[X2]]
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; CHECK-NEXT: [[Y2_FROZEN:%.*]] = freeze i32 [[Y2]]
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[X2_FROZEN]], [[Y2_FROZEN]]
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; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[DIV]], [[Y2_FROZEN]]
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; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[X2_FROZEN]], [[TMP1]]
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; CHECK-NEXT: store i32 [[DIV]], ptr [[P]], align 4
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; CHECK-NEXT: ret i32 [[REM_DECOMPOSED]]
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;
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%x2 = shl nuw nsw i32 %x, 5
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%y2 = add nuw nsw i32 %y, 1
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%div = sdiv i32 %x2, %y2
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%rem = srem i32 %x2, %y2
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store i32 %div, ptr %p, align 4
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ret i32 %rem
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}
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define <4 x i8> @poison_does_not_freeze_vector(ptr %p, <4 x i8> noundef %x, <4 x i8> noundef %y) {
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; CHECK-LABEL: define <4 x i8> @poison_does_not_freeze_vector(
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; CHECK-SAME: ptr [[P:%.*]], <4 x i8> noundef [[X:%.*]], <4 x i8> noundef [[Y:%.*]]) {
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; CHECK-NEXT: [[X2:%.*]] = shl nuw nsw <4 x i8> [[X]], <i8 5, i8 5, i8 5, i8 5>
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; CHECK-NEXT: [[Y2:%.*]] = add nuw nsw <4 x i8> [[Y]], <i8 1, i8 1, i8 1, i8 1>
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; CHECK-NEXT: [[X2_FROZEN:%.*]] = freeze <4 x i8> [[X2]]
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; CHECK-NEXT: [[Y2_FROZEN:%.*]] = freeze <4 x i8> [[Y2]]
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; CHECK-NEXT: [[DIV:%.*]] = udiv <4 x i8> [[X2_FROZEN]], [[Y2_FROZEN]]
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; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i8> [[DIV]], [[Y2_FROZEN]]
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; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub <4 x i8> [[X2_FROZEN]], [[TMP1]]
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; CHECK-NEXT: store <4 x i8> [[DIV]], ptr [[P]], align 4
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; CHECK-NEXT: ret <4 x i8> [[REM_DECOMPOSED]]
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;
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%x2 = shl nuw nsw <4 x i8> %x, <i8 5, i8 5, i8 5, i8 5>
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%y2 = add nuw nsw <4 x i8> %y, <i8 1, i8 1, i8 1, i8 1>
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%div = udiv <4 x i8> %x2, %y2
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%rem = urem <4 x i8> %x2, %y2
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store <4 x i8> %div, ptr %p, align 4
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ret <4 x i8> %rem
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}
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define i32 @explicit_poison_does_not_freeze(ptr %p, i32 noundef %y) {
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; CHECK-LABEL: define i32 @explicit_poison_does_not_freeze(
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; CHECK-SAME: ptr [[P:%.*]], i32 noundef [[Y:%.*]]) {
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; CHECK-NEXT: [[X:%.*]] = add i32 poison, 1
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; CHECK-NEXT: [[Y2:%.*]] = add nuw nsw i32 [[Y]], 1
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; CHECK-NEXT: [[X_FROZEN:%.*]] = freeze i32 [[X]]
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; CHECK-NEXT: [[Y2_FROZEN:%.*]] = freeze i32 [[Y2]]
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; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[X_FROZEN]], [[Y2_FROZEN]]
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; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[DIV]], [[Y2_FROZEN]]
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; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[X_FROZEN]], [[TMP1]]
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; CHECK-NEXT: store i32 [[DIV]], ptr [[P]], align 4
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; CHECK-NEXT: ret i32 [[REM_DECOMPOSED]]
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;
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%x = add i32 poison, 1
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%y2 = add nuw nsw i32 %y, 1
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%div = udiv i32 %x, %y2
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%rem = urem i32 %x, %y2
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store i32 %div, ptr %p, align 4
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ret i32 %rem
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}
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define i32 @explicit_poison_does_not_freeze_signed(ptr %p, i32 noundef %y) {
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; CHECK-LABEL: define i32 @explicit_poison_does_not_freeze_signed(
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; CHECK-SAME: ptr [[P:%.*]], i32 noundef [[Y:%.*]]) {
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; CHECK-NEXT: [[X:%.*]] = add i32 poison, 1
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; CHECK-NEXT: [[Y2:%.*]] = add nuw nsw i32 [[Y]], 1
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; CHECK-NEXT: [[X_FROZEN:%.*]] = freeze i32 [[X]]
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; CHECK-NEXT: [[Y2_FROZEN:%.*]] = freeze i32 [[Y2]]
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[X_FROZEN]], [[Y2_FROZEN]]
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; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[DIV]], [[Y2_FROZEN]]
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; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[X_FROZEN]], [[TMP1]]
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; CHECK-NEXT: store i32 [[DIV]], ptr [[P]], align 4
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; CHECK-NEXT: ret i32 [[REM_DECOMPOSED]]
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;
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%x = add i32 poison, 1
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%y2 = add nuw nsw i32 %y, 1
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%div = sdiv i32 %x, %y2
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%rem = srem i32 %x, %y2
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store i32 %div, ptr %p, align 4
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ret i32 %rem
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}

‎llvm/test/Transforms/DivRemPairs/AMDGPU/lit.local.cfg

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if not "AMDGPU" in config.root.targets:
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config.unsupported = True

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