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Jim Grosbach
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ARM: Split out cost model vcvt testcases.
They had a separate RUN line already, so may as well be in a separate file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179988 91177308-0d34-0410-b5e6-96231b3b80d8
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‎test/CodeGen/ARM/vcvt-cost.ll

Lines changed: 171 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,171 @@
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; We currently estimate the cost of sext/zext/trunc v8(v16)i32 <-> v8(v16)i8
2+
; instructions as expensive. If lowering is improved the cost model needs to
3+
; change.
4+
; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -march=arm -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST
5+
%T0_5 = type <8 x i8>
6+
%T1_5 = type <8 x i32>
7+
; CHECK: func_cvt5:
8+
define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) {
9+
; CHECK: vmovl.s8
10+
; CHECK: vmovl.s16
11+
; CHECK: vmovl.s16
12+
%v0 = load %T0_5* %loadaddr
13+
; COST: func_cvt5
14+
; COST: cost of 3 {{.*}} sext
15+
%r = sext %T0_5 %v0 to %T1_5
16+
store %T1_5 %r, %T1_5* %storeaddr
17+
ret void
18+
}
19+
;; We currently estimate the cost of this instruction as expensive. If lowering
20+
;; is improved the cost needs to change.
21+
%TA0_5 = type <8 x i8>
22+
%TA1_5 = type <8 x i32>
23+
; CHECK: func_cvt1:
24+
define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) {
25+
; CHECK: vmovl.u8
26+
; CHECK: vmovl.u16
27+
; CHECK: vmovl.u16
28+
%v0 = load %TA0_5* %loadaddr
29+
; COST: func_cvt1
30+
; COST: cost of 3 {{.*}} zext
31+
%r = zext %TA0_5 %v0 to %TA1_5
32+
store %TA1_5 %r, %TA1_5* %storeaddr
33+
ret void
34+
}
35+
;; We currently estimate the cost of this instruction as expensive. If lowering
36+
;; is improved the cost needs to change.
37+
%T0_51 = type <8 x i32>
38+
%T1_51 = type <8 x i8>
39+
; CHECK: func_cvt51:
40+
define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) {
41+
; CHECK: strb
42+
; CHECK: strb
43+
; CHECK: strb
44+
; CHECK: strb
45+
; CHECK: strb
46+
; CHECK: strb
47+
; CHECK: strb
48+
; CHECK: strb
49+
%v0 = load %T0_51* %loadaddr
50+
; COST: func_cvt51
51+
; COST: cost of 19 {{.*}} trunc
52+
%r = trunc %T0_51 %v0 to %T1_51
53+
store %T1_51 %r, %T1_51* %storeaddr
54+
ret void
55+
}
56+
;; We currently estimate the cost of this instruction as expensive. If lowering
57+
;; is improved the cost needs to change.
58+
%TT0_5 = type <16 x i8>
59+
%TT1_5 = type <16 x i32>
60+
; CHECK: func_cvt52:
61+
define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) {
62+
; CHECK: vmovl.s16
63+
; CHECK: vmovl.s16
64+
; CHECK: vmovl.s16
65+
; CHECK: vmovl.s16
66+
%v0 = load %TT0_5* %loadaddr
67+
; COST: func_cvt52
68+
; COST: cost of 6 {{.*}} sext
69+
%r = sext %TT0_5 %v0 to %TT1_5
70+
store %TT1_5 %r, %TT1_5* %storeaddr
71+
ret void
72+
}
73+
;; We currently estimate the cost of this instruction as expensive. If lowering
74+
;; is improved the cost needs to change.
75+
%TTA0_5 = type <16 x i8>
76+
%TTA1_5 = type <16 x i32>
77+
; CHECK: func_cvt12:
78+
define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) {
79+
; CHECK: vmovl.u16
80+
; CHECK: vmovl.u16
81+
; CHECK: vmovl.u16
82+
; CHECK: vmovl.u16
83+
%v0 = load %TTA0_5* %loadaddr
84+
; COST: func_cvt12
85+
; COST: cost of 6 {{.*}} zext
86+
%r = zext %TTA0_5 %v0 to %TTA1_5
87+
store %TTA1_5 %r, %TTA1_5* %storeaddr
88+
ret void
89+
}
90+
;; We currently estimate the cost of this instruction as expensive. If lowering
91+
;; is improved the cost needs to change.
92+
%TT0_51 = type <16 x i32>
93+
%TT1_51 = type <16 x i8>
94+
; CHECK: func_cvt512:
95+
define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) {
96+
; CHECK: strb
97+
; CHECK: strb
98+
; CHECK: strb
99+
; CHECK: strb
100+
; CHECK: strb
101+
; CHECK: strb
102+
; CHECK: strb
103+
; CHECK: strb
104+
; CHECK: strb
105+
; CHECK: strb
106+
; CHECK: strb
107+
; CHECK: strb
108+
; CHECK: strb
109+
; CHECK: strb
110+
; CHECK: strb
111+
; CHECK: strb
112+
%v0 = load %TT0_51* %loadaddr
113+
; COST: func_cvt512
114+
; COST: cost of 38 {{.*}} trunc
115+
%r = trunc %TT0_51 %v0 to %TT1_51
116+
store %TT1_51 %r, %TT1_51* %storeaddr
117+
ret void
118+
}
119+
120+
; CHECK: sext_v4i16_v4i64:
121+
define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
122+
; CHECK: vmovl.s32
123+
; CHECK: vmovl.s32
124+
%v0 = load <4 x i16>* %loadaddr
125+
; COST: sext_v4i16_v4i64
126+
; COST: cost of 3 {{.*}} sext
127+
%r = sext <4 x i16> %v0 to <4 x i64>
128+
store <4 x i64> %r, <4 x i64>* %storeaddr
129+
ret void
130+
}
131+
132+
; CHECK: zext_v4i16_v4i64:
133+
define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
134+
; CHECK: vmovl.u32
135+
; CHECK: vmovl.u32
136+
%v0 = load <4 x i16>* %loadaddr
137+
; COST: zext_v4i16_v4i64
138+
; COST: cost of 3 {{.*}} zext
139+
%r = zext <4 x i16> %v0 to <4 x i64>
140+
store <4 x i64> %r, <4 x i64>* %storeaddr
141+
ret void
142+
}
143+
144+
; CHECK: sext_v8i16_v8i64:
145+
define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
146+
; CHECK: vmovl.s32
147+
; CHECK: vmovl.s32
148+
; CHECK: vmovl.s32
149+
; CHECK: vmovl.s32
150+
%v0 = load <8 x i16>* %loadaddr
151+
; COST: sext_v8i16_v8i64
152+
; COST: cost of 6 {{.*}} sext
153+
%r = sext <8 x i16> %v0 to <8 x i64>
154+
store <8 x i64> %r, <8 x i64>* %storeaddr
155+
ret void
156+
}
157+
158+
; CHECK: zext_v8i16_v8i64:
159+
define void @zext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
160+
; CHECK: vmovl.u32
161+
; CHECK: vmovl.u32
162+
; CHECK: vmovl.u32
163+
; CHECK: vmovl.u32
164+
%v0 = load <8 x i16>* %loadaddr
165+
; COST: zext_v8i16_v8i64
166+
; COST: cost of 6 {{.*}} zext
167+
%r = zext <8 x i16> %v0 to <8 x i64>
168+
store <8 x i64> %r, <8 x i64>* %storeaddr
169+
ret void
170+
}
171+

‎test/CodeGen/ARM/vcvt.ll

Lines changed: 0 additions & 172 deletions
Original file line numberDiff line numberDiff line change
@@ -156,175 +156,3 @@ define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind {
156156

157157
declare <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16>) nounwind readnone
158158
declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone
159-
160-
; We currently estimate the cost of sext/zext/trunc v8(v16)i32 <-> v8(v16)i8
161-
; instructions as expensive. If lowering is improved the cost model needs to
162-
; change.
163-
; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -march=arm -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST
164-
%T0_5 = type <8 x i8>
165-
%T1_5 = type <8 x i32>
166-
; CHECK: func_cvt5:
167-
define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) {
168-
; CHECK: vmovl.s8
169-
; CHECK: vmovl.s16
170-
; CHECK: vmovl.s16
171-
%v0 = load %T0_5* %loadaddr
172-
; COST: func_cvt5
173-
; COST: cost of 3 {{.*}} sext
174-
%r = sext %T0_5 %v0 to %T1_5
175-
store %T1_5 %r, %T1_5* %storeaddr
176-
ret void
177-
}
178-
;; We currently estimate the cost of this instruction as expensive. If lowering
179-
;; is improved the cost needs to change.
180-
%TA0_5 = type <8 x i8>
181-
%TA1_5 = type <8 x i32>
182-
; CHECK: func_cvt1:
183-
define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) {
184-
; CHECK: vmovl.u8
185-
; CHECK: vmovl.u16
186-
; CHECK: vmovl.u16
187-
%v0 = load %TA0_5* %loadaddr
188-
; COST: func_cvt1
189-
; COST: cost of 3 {{.*}} zext
190-
%r = zext %TA0_5 %v0 to %TA1_5
191-
store %TA1_5 %r, %TA1_5* %storeaddr
192-
ret void
193-
}
194-
;; We currently estimate the cost of this instruction as expensive. If lowering
195-
;; is improved the cost needs to change.
196-
%T0_51 = type <8 x i32>
197-
%T1_51 = type <8 x i8>
198-
; CHECK: func_cvt51:
199-
define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) {
200-
; CHECK: strb
201-
; CHECK: strb
202-
; CHECK: strb
203-
; CHECK: strb
204-
; CHECK: strb
205-
; CHECK: strb
206-
; CHECK: strb
207-
; CHECK: strb
208-
%v0 = load %T0_51* %loadaddr
209-
; COST: func_cvt51
210-
; COST: cost of 19 {{.*}} trunc
211-
%r = trunc %T0_51 %v0 to %T1_51
212-
store %T1_51 %r, %T1_51* %storeaddr
213-
ret void
214-
}
215-
;; We currently estimate the cost of this instruction as expensive. If lowering
216-
;; is improved the cost needs to change.
217-
%TT0_5 = type <16 x i8>
218-
%TT1_5 = type <16 x i32>
219-
; CHECK: func_cvt52:
220-
define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) {
221-
; CHECK: vmovl.s16
222-
; CHECK: vmovl.s16
223-
; CHECK: vmovl.s16
224-
; CHECK: vmovl.s16
225-
%v0 = load %TT0_5* %loadaddr
226-
; COST: func_cvt52
227-
; COST: cost of 6 {{.*}} sext
228-
%r = sext %TT0_5 %v0 to %TT1_5
229-
store %TT1_5 %r, %TT1_5* %storeaddr
230-
ret void
231-
}
232-
;; We currently estimate the cost of this instruction as expensive. If lowering
233-
;; is improved the cost needs to change.
234-
%TTA0_5 = type <16 x i8>
235-
%TTA1_5 = type <16 x i32>
236-
; CHECK: func_cvt12:
237-
define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) {
238-
; CHECK: vmovl.u16
239-
; CHECK: vmovl.u16
240-
; CHECK: vmovl.u16
241-
; CHECK: vmovl.u16
242-
%v0 = load %TTA0_5* %loadaddr
243-
; COST: func_cvt12
244-
; COST: cost of 6 {{.*}} zext
245-
%r = zext %TTA0_5 %v0 to %TTA1_5
246-
store %TTA1_5 %r, %TTA1_5* %storeaddr
247-
ret void
248-
}
249-
;; We currently estimate the cost of this instruction as expensive. If lowering
250-
;; is improved the cost needs to change.
251-
%TT0_51 = type <16 x i32>
252-
%TT1_51 = type <16 x i8>
253-
; CHECK: func_cvt512:
254-
define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) {
255-
; CHECK: strb
256-
; CHECK: strb
257-
; CHECK: strb
258-
; CHECK: strb
259-
; CHECK: strb
260-
; CHECK: strb
261-
; CHECK: strb
262-
; CHECK: strb
263-
; CHECK: strb
264-
; CHECK: strb
265-
; CHECK: strb
266-
; CHECK: strb
267-
; CHECK: strb
268-
; CHECK: strb
269-
; CHECK: strb
270-
; CHECK: strb
271-
%v0 = load %TT0_51* %loadaddr
272-
; COST: func_cvt512
273-
; COST: cost of 38 {{.*}} trunc
274-
%r = trunc %TT0_51 %v0 to %TT1_51
275-
store %TT1_51 %r, %TT1_51* %storeaddr
276-
ret void
277-
}
278-
279-
; CHECK: sext_v4i16_v4i64:
280-
define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
281-
; CHECK: vmovl.s32
282-
; CHECK: vmovl.s32
283-
%v0 = load <4 x i16>* %loadaddr
284-
; COST: sext_v4i16_v4i64
285-
; COST: cost of 3 {{.*}} sext
286-
%r = sext <4 x i16> %v0 to <4 x i64>
287-
store <4 x i64> %r, <4 x i64>* %storeaddr
288-
ret void
289-
}
290-
291-
; CHECK: zext_v4i16_v4i64:
292-
define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
293-
; CHECK: vmovl.u32
294-
; CHECK: vmovl.u32
295-
%v0 = load <4 x i16>* %loadaddr
296-
; COST: zext_v4i16_v4i64
297-
; COST: cost of 3 {{.*}} zext
298-
%r = zext <4 x i16> %v0 to <4 x i64>
299-
store <4 x i64> %r, <4 x i64>* %storeaddr
300-
ret void
301-
}
302-
303-
; CHECK: sext_v8i16_v8i64:
304-
define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
305-
; CHECK: vmovl.s32
306-
; CHECK: vmovl.s32
307-
; CHECK: vmovl.s32
308-
; CHECK: vmovl.s32
309-
%v0 = load <8 x i16>* %loadaddr
310-
; COST: sext_v8i16_v8i64
311-
; COST: cost of 6 {{.*}} sext
312-
%r = sext <8 x i16> %v0 to <8 x i64>
313-
store <8 x i64> %r, <8 x i64>* %storeaddr
314-
ret void
315-
}
316-
317-
; CHECK: zext_v8i16_v8i64:
318-
define void @zext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
319-
; CHECK: vmovl.u32
320-
; CHECK: vmovl.u32
321-
; CHECK: vmovl.u32
322-
; CHECK: vmovl.u32
323-
%v0 = load <8 x i16>* %loadaddr
324-
; COST: zext_v8i16_v8i64
325-
; COST: cost of 6 {{.*}} zext
326-
%r = zext <8 x i16> %v0 to <8 x i64>
327-
store <8 x i64> %r, <8 x i64>* %storeaddr
328-
ret void
329-
}
330-

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