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| 1 | +; RUN: opt -mtriple amdgcn-unknown-amdhsa -analyze -divergence -use-gpu-divergence-analysis %s | FileCheck %s |
| 2 | + |
| 3 | +declare i32 @gf2(i32) |
| 4 | +declare i32 @gf1(i32) |
| 5 | + |
| 6 | +define void @tw1(i32 addrspace(4)* noalias nocapture readonly %A, i32 addrspace(4)* noalias nocapture %B) local_unnamed_addr #2 { |
| 7 | +; CHECK: Printing analysis 'Legacy Divergence Analysis' for function 'tw1': |
| 8 | +; CHECK: DIVERGENT: i32 addrspace(4)* %A |
| 9 | +; CHECK: DIVERGENT: i32 addrspace(4)* %B |
| 10 | +entry: |
| 11 | +; CHECK: DIVERGENT: %call = tail call i32 @gf2(i32 0) #0 |
| 12 | +; CHECK: DIVERGENT: %cmp = icmp ult i32 %call, 16 |
| 13 | +; CHECK: DIVERGENT: br i1 %cmp, label %if.then, label %new_exit |
| 14 | + %call = tail call i32 @gf2(i32 0) #3 |
| 15 | + %cmp = icmp ult i32 %call, 16 |
| 16 | + br i1 %cmp, label %if.then, label %new_exit |
| 17 | + |
| 18 | +if.then: |
| 19 | +; CHECK: DIVERGENT: %call1 = tail call i32 @gf1(i32 0) #0 |
| 20 | +; CHECK: DIVERGENT: %arrayidx = getelementptr inbounds i32, i32 addrspace(4)* %A, i32 %call1 |
| 21 | +; CHECK: DIVERGENT: %0 = load i32, i32 addrspace(4)* %arrayidx, align 4 |
| 22 | +; CHECK: DIVERGENT: %cmp225 = icmp sgt i32 %0, 0 |
| 23 | +; CHECK: DIVERGENT: %arrayidx10 = getelementptr inbounds i32, i32 addrspace(4)* %B, i32 %call1 |
| 24 | +; CHECK: DIVERGENT: br i1 %cmp225, label %while.body.preheader, label %if.then.while.end_crit_edge |
| 25 | + %call1 = tail call i32 @gf1(i32 0) #4 |
| 26 | + %arrayidx = getelementptr inbounds i32, i32 addrspace(4)* %A, i32 %call1 |
| 27 | + %0 = load i32, i32 addrspace(4)* %arrayidx, align 4 |
| 28 | + %cmp225 = icmp sgt i32 %0, 0 |
| 29 | + %arrayidx10 = getelementptr inbounds i32, i32 addrspace(4)* %B, i32 %call1 |
| 30 | + br i1 %cmp225, label %while.body.preheader, label %if.then.while.end_crit_edge |
| 31 | + |
| 32 | +while.body.preheader: |
| 33 | + br label %while.body |
| 34 | + |
| 35 | +if.then.while.end_crit_edge: |
| 36 | +; CHECK: DIVERGENT: %.pre = load i32, i32 addrspace(4)* %arrayidx10, align 4 |
| 37 | + %.pre = load i32, i32 addrspace(4)* %arrayidx10, align 4 |
| 38 | + br label %while.end |
| 39 | + |
| 40 | +while.body: |
| 41 | +; CHECK-NOT: DIVERGENT: %i.026 = phi i32 [ %inc, %if.end.while.body_crit_edge ], [ 0, %while.body.preheader ] |
| 42 | +; CHECK: DIVERGENT: %call3 = tail call i32 @gf1(i32 0) #0 |
| 43 | +; CHECK: DIVERGENT: %cmp4 = icmp ult i32 %call3, 10 |
| 44 | +; CHECK: DIVERGENT: %arrayidx6 = getelementptr inbounds i32, i32 addrspace(4)* %A, i32 %i.026 |
| 45 | +; CHECK: DIVERGENT: %1 = load i32, i32 addrspace(4)* %arrayidx6, align 4 |
| 46 | +; CHECK: DIVERGENT: br i1 %cmp4, label %if.then5, label %if.else |
| 47 | + %i.026 = phi i32 [ %inc, %if.end.while.body_crit_edge ], [ 0, %while.body.preheader ] |
| 48 | + %call3 = tail call i32 @gf1(i32 0) #4 |
| 49 | + %cmp4 = icmp ult i32 %call3, 10 |
| 50 | + %arrayidx6 = getelementptr inbounds i32, i32 addrspace(4)* %A, i32 %i.026 |
| 51 | + %1 = load i32, i32 addrspace(4)* %arrayidx6, align 4 |
| 52 | + br i1 %cmp4, label %if.then5, label %if.else |
| 53 | + |
| 54 | +if.then5: |
| 55 | +; CHECK: DIVERGENT: %mul = shl i32 %1, 1 |
| 56 | +; CHECK: DIVERGENT: %2 = load i32, i32 addrspace(4)* %arrayidx10, align 4 |
| 57 | +; CHECK: DIVERGENT: %add = add nsw i32 %2, %mul |
| 58 | + %mul = shl i32 %1, 1 |
| 59 | + %2 = load i32, i32 addrspace(4)* %arrayidx10, align 4 |
| 60 | + %add = add nsw i32 %2, %mul |
| 61 | + br label %if.end |
| 62 | + |
| 63 | +if.else: |
| 64 | +; CHECK: DIVERGENT: %mul9 = shl i32 %1, 2 |
| 65 | +; CHECK: DIVERGENT: %3 = load i32, i32 addrspace(4)* %arrayidx10, align 4 |
| 66 | +; CHECK: DIVERGENT: %add11 = add nsw i32 %3, %mul9 |
| 67 | + %mul9 = shl i32 %1, 2 |
| 68 | + %3 = load i32, i32 addrspace(4)* %arrayidx10, align 4 |
| 69 | + %add11 = add nsw i32 %3, %mul9 |
| 70 | + br label %if.end |
| 71 | + |
| 72 | +if.end: |
| 73 | +; CHECK: DIVERGENT: %storemerge = phi i32 [ %add11, %if.else ], [ %add, %if.then5 ] |
| 74 | +; CHECK: DIVERGENT: store i32 %storemerge, i32 addrspace(4)* %arrayidx10, align 4 |
| 75 | +; CHECK-NOT: DIVERGENT: %inc = add nuw nsw i32 %i.026, 1 |
| 76 | +; CHECK: DIVERGENT: %exitcond = icmp ne i32 %inc, %0 |
| 77 | +; CHECK: DIVERGENT: br i1 %exitcond, label %if.end.while.body_crit_edge, label %while.end.loopexit |
| 78 | + %storemerge = phi i32 [ %add11, %if.else ], [ %add, %if.then5 ] |
| 79 | + store i32 %storemerge, i32 addrspace(4)* %arrayidx10, align 4 |
| 80 | + %inc = add nuw nsw i32 %i.026, 1 |
| 81 | + %exitcond = icmp ne i32 %inc, %0 |
| 82 | + br i1 %exitcond, label %if.end.while.body_crit_edge, label %while.end.loopexit |
| 83 | + |
| 84 | +if.end.while.body_crit_edge: |
| 85 | + br label %while.body |
| 86 | + |
| 87 | +while.end.loopexit: |
| 88 | +; CHECK: DIVERGENT: %storemerge.lcssa = phi i32 [ %storemerge, %if.end ] |
| 89 | + %storemerge.lcssa = phi i32 [ %storemerge, %if.end ] |
| 90 | + br label %while.end |
| 91 | + |
| 92 | +while.end: |
| 93 | +; CHECK: DIVERGENT: %4 = phi i32 [ %.pre, %if.then.while.end_crit_edge ], [ %storemerge.lcssa, %while.end.loopexit ] |
| 94 | +; CHECK: DIVERGENT: %i.0.lcssa = phi i32 [ 0, %if.then.while.end_crit_edge ], [ %0, %while.end.loopexit ] |
| 95 | +; CHECK: DIVERGENT: %sub = sub nsw i32 %4, %i.0.lcssa |
| 96 | +; CHECK: DIVERGENT: store i32 %sub, i32 addrspace(4)* %arrayidx10, align 4 |
| 97 | + %4 = phi i32 [ %.pre, %if.then.while.end_crit_edge ], [ %storemerge.lcssa, %while.end.loopexit ] |
| 98 | + %i.0.lcssa = phi i32 [ 0, %if.then.while.end_crit_edge ], [ %0, %while.end.loopexit ] |
| 99 | + %sub = sub nsw i32 %4, %i.0.lcssa |
| 100 | + store i32 %sub, i32 addrspace(4)* %arrayidx10, align 4 |
| 101 | + br label %new_exit |
| 102 | + |
| 103 | +new_exit: |
| 104 | + ret void |
| 105 | +} |
| 106 | + |
| 107 | +attributes #0 = { nounwind readnone } |
| 108 | +attributes #1 = { nounwind readnone } |
| 109 | +attributes #2 = { nounwind readnone } |
| 110 | +attributes #3 = { nounwind readnone } |
| 111 | +attributes #4 = { nounwind readnone } |
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