Skip to content

Commit f4fc7be

Browse files
fpgamattNipaLocal
fpgamatt
authored and
NipaLocal
committed
dt-bindings: net: Convert socfpga-dwmac bindings to yaml
Convert the bindings for socfpga-dwmac to yaml. Since the original text contained descriptions for two separate nodes, two separate yaml files were created. Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: NipaLocal <nipa@local>
1 parent f2d88d4 commit f4fc7be

File tree

4 files changed

+217
-58
lines changed

4 files changed

+217
-58
lines changed

‎Documentation/devicetree/bindings/net/altr,gmii-to-sgmii-2.0.yaml

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,49 @@
1+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2+
# Copyright (C) 2025 Altera Corporation
3+
%YAML 1.2
4+
---
5+
$id: http://devicetree.org/schemas/net/altr,gmii-to-sgmii-2.0.yaml#
6+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7+
8+
title: Altera GMII to SGMII Converter
9+
10+
maintainers:
11+
- Matthew Gerlach <matthew.gerlach@altera.com>
12+
13+
description:
14+
This binding describes the Altera GMII to SGMII converter.
15+
16+
properties:
17+
compatible:
18+
const: altr,gmii-to-sgmii-2.0
19+
20+
reg:
21+
items:
22+
- description: Registers for the emac splitter IP
23+
- description: Registers for the GMII to SGMII converter.
24+
- description: Registers for TSE control.
25+
26+
reg-names:
27+
items:
28+
- const: hps_emac_interface_splitter_avalon_slave
29+
- const: gmii_to_sgmii_adapter_avalon_slave
30+
- const: eth_tse_control_port
31+
32+
required:
33+
- compatible
34+
- reg
35+
- reg-names
36+
37+
unevaluatedProperties: false
38+
39+
examples:
40+
- |
41+
phy@ff000240 {
42+
compatible = "altr,gmii-to-sgmii-2.0";
43+
reg = <0xff000240 0x00000008>,
44+
<0xff000200 0x00000040>,
45+
<0xff000250 0x00000008>;
46+
reg-names = "hps_emac_interface_splitter_avalon_slave",
47+
"gmii_to_sgmii_adapter_avalon_slave",
48+
"eth_tse_control_port";
49+
};

‎Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml

Lines changed: 162 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,162 @@
1+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/net/altr,socfpga-stmmac.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Altera SOCFPGA SoC DWMAC controller
8+
9+
maintainers:
10+
- Matthew Gerlach <matthew.gerlach@altera.com>
11+
12+
description:
13+
This binding describes the Altera SOCFPGA SoC implementation of the
14+
Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, and Agilex7 families
15+
of chips.
16+
# TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
17+
# does not validate against net/snps,dwmac.yaml.
18+
19+
select:
20+
properties:
21+
compatible:
22+
contains:
23+
enum:
24+
- altr,socfpga-stmmac
25+
- altr,socfpga-stmmac-a10-s10
26+
27+
required:
28+
- compatible
29+
30+
properties:
31+
compatible:
32+
oneOf:
33+
- items:
34+
- const: altr,socfpga-stmmac
35+
- const: snps,dwmac-3.70a
36+
- const: snps,dwmac
37+
- items:
38+
- const: altr,socfpga-stmmac-a10-s10
39+
- const: snps,dwmac-3.74a
40+
- const: snps,dwmac
41+
42+
clocks:
43+
minItems: 1
44+
items:
45+
- description: GMAC main clock
46+
- description:
47+
PTP reference clock. This clock is used for programming the
48+
Timestamp Addend Register. If not passed then the system
49+
clock will be used and this is fine on some platforms.
50+
51+
clock-names:
52+
minItems: 1
53+
items:
54+
- const: stmmaceth
55+
- const: ptp_ref
56+
57+
iommus:
58+
maxItems: 1
59+
60+
phy-mode:
61+
enum:
62+
- gmii
63+
- mii
64+
- rgmii
65+
- rgmii-id
66+
- rgmii-rxid
67+
- rgmii-txid
68+
- sgmii
69+
- 1000base-x
70+
71+
rxc-skew-ps:
72+
description: Skew control of RXC pad
73+
74+
rxd0-skew-ps:
75+
description: Skew control of RX data 0 pad
76+
77+
rxd1-skew-ps:
78+
description: Skew control of RX data 1 pad
79+
80+
rxd2-skew-ps:
81+
description: Skew control of RX data 2 pad
82+
83+
rxd3-skew-ps:
84+
description: Skew control of RX data 3 pad
85+
86+
rxdv-skew-ps:
87+
description: Skew control of RX CTL pad
88+
89+
txc-skew-ps:
90+
description: Skew control of TXC pad
91+
92+
txen-skew-ps:
93+
description: Skew control of TXC pad
94+
95+
altr,emac-splitter:
96+
$ref: /schemas/types.yaml#/definitions/phandle
97+
description:
98+
Should be the phandle to the emac splitter soft IP node if DWMAC
99+
controller is connected an emac splitter.
100+
101+
altr,f2h_ptp_ref_clk:
102+
$ref: /schemas/types.yaml#/definitions/phandle
103+
description:
104+
Phandle to Precision Time Protocol reference clock. This clock is
105+
common to gmac instances and defaults to osc1.
106+
107+
altr,gmii-to-sgmii-converter:
108+
$ref: /schemas/types.yaml#/definitions/phandle
109+
description:
110+
Should be the phandle to the gmii to sgmii converter soft IP.
111+
112+
altr,sysmgr-syscon:
113+
$ref: /schemas/types.yaml#/definitions/phandle-array
114+
description:
115+
Should be the phandle to the system manager node that encompass
116+
the glue register, the register offset, and the register shift.
117+
On Cyclone5/Arria5, the register shift represents the PHY mode
118+
bits, while on the Arria10/Stratix10/Agilex platforms, the
119+
register shift represents bit for each emac to enable/disable
120+
signals from the FPGA fabric to the EMAC modules.
121+
items:
122+
- items:
123+
- description: phandle to the system manager node
124+
- description: offset of the control register
125+
- description: shift within the control register
126+
127+
patternProperties:
128+
"^mdio[0-9]$":
129+
type: object
130+
131+
required:
132+
- compatible
133+
- clocks
134+
- clock-names
135+
- altr,sysmgr-syscon
136+
137+
allOf:
138+
- $ref: snps,dwmac.yaml#
139+
140+
unevaluatedProperties: false
141+
142+
examples:
143+
144+
- |
145+
#include <dt-bindings/interrupt-controller/arm-gic.h>
146+
#include <dt-bindings/interrupt-controller/irq.h>
147+
soc {
148+
#address-cells = <1>;
149+
#size-cells = <1>;
150+
ethernet@ff700000 {
151+
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a",
152+
"snps,dwmac";
153+
altr,sysmgr-syscon = <&sysmgr 0x60 0>;
154+
reg = <0xff700000 0x2000>;
155+
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
156+
interrupt-names = "macirq";
157+
mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
158+
clocks = <&emac_0_clk>;
159+
clock-names = "stmmaceth";
160+
phy-mode = "sgmii";
161+
};
162+
};

‎Documentation/devicetree/bindings/net/socfpga-dwmac.txt

Lines changed: 0 additions & 57 deletions
This file was deleted.

‎MAINTAINERS

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3262,10 +3262,15 @@ M: Dinh Nguyen <dinguyen@kernel.org>
32623262
S: Maintained
32633263
F: drivers/clk/socfpga/
32643264

3265+
ARM/SOCFPGA DWMAC GLUE LAYER BINDINGS
3266+
M: Matthew Gerlach <matthew.gerlach@altera.com>
3267+
S: Maintained
3268+
F: Documentation/devicetree/bindings/net/altr,gmii-to-sgmii-2.0.yaml
3269+
F: Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
3270+
32653271
ARM/SOCFPGA DWMAC GLUE LAYER
32663272
M: Maxime Chevallier <maxime.chevallier@bootlin.com>
32673273
S: Maintained
3268-
F: Documentation/devicetree/bindings/net/socfpga-dwmac.txt
32693274
F: drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
32703275

32713276
ARM/SOCFPGA EDAC BINDINGS

0 commit comments

Comments
 (0)