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dt-bindings: net: Convert socfpga-dwmac bindings to yaml
Convert the bindings for socfpga-dwmac to yaml. Since the original text contained descriptions for two separate nodes, two separate yaml files were created. Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: NipaLocal <nipa@local>
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‎Documentation/devicetree/bindings/net/altr,gmii-to-sgmii-2.0.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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# Copyright (C) 2025 Altera Corporation
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/altr,gmii-to-sgmii-2.0.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Altera GMII to SGMII Converter
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maintainers:
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- Matthew Gerlach <matthew.gerlach@altera.com>
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description:
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This binding describes the Altera GMII to SGMII converter.
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properties:
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compatible:
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const: altr,gmii-to-sgmii-2.0
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reg:
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items:
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- description: Registers for the emac splitter IP
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- description: Registers for the GMII to SGMII converter.
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- description: Registers for TSE control.
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reg-names:
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items:
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- const: hps_emac_interface_splitter_avalon_slave
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- const: gmii_to_sgmii_adapter_avalon_slave
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- const: eth_tse_control_port
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required:
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- compatible
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- reg
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- reg-names
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unevaluatedProperties: false
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examples:
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- |
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phy@ff000240 {
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compatible = "altr,gmii-to-sgmii-2.0";
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reg = <0xff000240 0x00000008>,
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<0xff000200 0x00000040>,
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<0xff000250 0x00000008>;
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reg-names = "hps_emac_interface_splitter_avalon_slave",
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"gmii_to_sgmii_adapter_avalon_slave",
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"eth_tse_control_port";
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};

‎Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/altr,socfpga-stmmac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Altera SOCFPGA SoC DWMAC controller
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maintainers:
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- Matthew Gerlach <matthew.gerlach@altera.com>
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description:
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This binding describes the Altera SOCFPGA SoC implementation of the
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Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, and Agilex7 families
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of chips.
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# TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
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# does not validate against net/snps,dwmac.yaml.
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select:
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properties:
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compatible:
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contains:
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enum:
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- altr,socfpga-stmmac
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- altr,socfpga-stmmac-a10-s10
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required:
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- compatible
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properties:
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compatible:
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oneOf:
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- items:
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- const: altr,socfpga-stmmac
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- const: snps,dwmac-3.70a
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- const: snps,dwmac
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- items:
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- const: altr,socfpga-stmmac-a10-s10
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- const: snps,dwmac-3.74a
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- const: snps,dwmac
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clocks:
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minItems: 1
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items:
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- description: GMAC main clock
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- description:
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PTP reference clock. This clock is used for programming the
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Timestamp Addend Register. If not passed then the system
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clock will be used and this is fine on some platforms.
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clock-names:
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minItems: 1
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items:
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- const: stmmaceth
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- const: ptp_ref
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iommus:
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maxItems: 1
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phy-mode:
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enum:
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- gmii
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- mii
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- rgmii
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- rgmii-id
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- rgmii-rxid
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- rgmii-txid
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- sgmii
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- 1000base-x
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rxc-skew-ps:
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description: Skew control of RXC pad
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rxd0-skew-ps:
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description: Skew control of RX data 0 pad
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rxd1-skew-ps:
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description: Skew control of RX data 1 pad
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rxd2-skew-ps:
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description: Skew control of RX data 2 pad
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rxd3-skew-ps:
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description: Skew control of RX data 3 pad
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rxdv-skew-ps:
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description: Skew control of RX CTL pad
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txc-skew-ps:
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description: Skew control of TXC pad
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txen-skew-ps:
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description: Skew control of TXC pad
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altr,emac-splitter:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Should be the phandle to the emac splitter soft IP node if DWMAC
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controller is connected an emac splitter.
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altr,f2h_ptp_ref_clk:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to Precision Time Protocol reference clock. This clock is
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common to gmac instances and defaults to osc1.
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altr,gmii-to-sgmii-converter:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Should be the phandle to the gmii to sgmii converter soft IP.
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altr,sysmgr-syscon:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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Should be the phandle to the system manager node that encompass
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the glue register, the register offset, and the register shift.
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On Cyclone5/Arria5, the register shift represents the PHY mode
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bits, while on the Arria10/Stratix10/Agilex platforms, the
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register shift represents bit for each emac to enable/disable
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signals from the FPGA fabric to the EMAC modules.
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items:
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- items:
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- description: phandle to the system manager node
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- description: offset of the control register
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- description: shift within the control register
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patternProperties:
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"^mdio[0-9]$":
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type: object
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required:
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- compatible
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- clocks
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- clock-names
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- altr,sysmgr-syscon
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allOf:
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- $ref: snps,dwmac.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ethernet@ff700000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a",
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"snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x60 0>;
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reg = <0xff700000 0x2000>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
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clocks = <&emac_0_clk>;
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clock-names = "stmmaceth";
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phy-mode = "sgmii";
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};
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};

‎Documentation/devicetree/bindings/net/socfpga-dwmac.txt

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‎MAINTAINERS

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@@ -3262,10 +3262,15 @@ M: Dinh Nguyen <dinguyen@kernel.org>
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S: Maintained
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F: drivers/clk/socfpga/
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ARM/SOCFPGA DWMAC GLUE LAYER BINDINGS
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M: Matthew Gerlach <matthew.gerlach@altera.com>
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S: Maintained
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F: Documentation/devicetree/bindings/net/altr,gmii-to-sgmii-2.0.yaml
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F: Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
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ARM/SOCFPGA DWMAC GLUE LAYER
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M: Maxime Chevallier <maxime.chevallier@bootlin.com>
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S: Maintained
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F: Documentation/devicetree/bindings/net/socfpga-dwmac.txt
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F: drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
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ARM/SOCFPGA EDAC BINDINGS

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