Skip to content

Commit cc0248a

Browse files
randall77randall77
committed
cmd/compile: don't reserve X15 for float sub/div any more
We used to reserve X15 to implement the 3-operand floating-point sub/div ops with the 2-operand sub/div that 386/amd64 gives us. Now that resultInArg0 is implemented, we no longer need to reserve X15 (X7 on 386). Fixes #15584 Change-Id: I978e6c0a35236e89641bfc027538cede66004e82 Reviewed-on: https://go-review.googlesource.com/28272 Run-TryBot: Keith Randall <khr@golang.org> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: David Chase <drchase@google.com>
1 parent 33bb597 commit cc0248a

File tree

3 files changed

+36
-50
lines changed

3 files changed

+36
-50
lines changed

‎src/cmd/compile/internal/ssa/gen/386Ops.go

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,6 @@ func init() {
8888
dx = buildReg("DX")
8989
gp = buildReg("AX CX DX BX BP SI DI")
9090
fp = buildReg("X0 X1 X2 X3 X4 X5 X6 X7")
91-
x7 = buildReg("X7")
9291
gpsp = gp | buildReg("SP")
9392
gpspsb = gpsp | buildReg("SB")
9493
callerSave = gp | fp
@@ -133,10 +132,8 @@ func init() {
133132
gpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, gpsp, 0}}
134133
gpstoreconstidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}}
135134

136-
fp01 = regInfo{inputs: nil, outputs: fponly}
137-
fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: fponly}
138-
fp21x7 = regInfo{inputs: []regMask{fp &^ x7, fp &^ x7},
139-
clobbers: x7, outputs: []regMask{fp &^ x7}}
135+
fp01 = regInfo{inputs: nil, outputs: fponly}
136+
fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: fponly}
140137
fpgp = regInfo{inputs: fponly, outputs: gponly}
141138
gpfp = regInfo{inputs: gponly, outputs: fponly}
142139
fp11 = regInfo{inputs: fponly, outputs: fponly}
@@ -153,12 +150,12 @@ func init() {
153150
// fp ops
154151
{name: "ADDSS", argLength: 2, reg: fp21, asm: "ADDSS", commutative: true, resultInArg0: true}, // fp32 add
155152
{name: "ADDSD", argLength: 2, reg: fp21, asm: "ADDSD", commutative: true, resultInArg0: true}, // fp64 add
156-
{name: "SUBSS", argLength: 2, reg: fp21x7, asm: "SUBSS", resultInArg0: true}, // fp32 sub
157-
{name: "SUBSD", argLength: 2, reg: fp21x7, asm: "SUBSD", resultInArg0: true}, // fp64 sub
153+
{name: "SUBSS", argLength: 2, reg: fp21, asm: "SUBSS", resultInArg0: true}, // fp32 sub
154+
{name: "SUBSD", argLength: 2, reg: fp21, asm: "SUBSD", resultInArg0: true}, // fp64 sub
158155
{name: "MULSS", argLength: 2, reg: fp21, asm: "MULSS", commutative: true, resultInArg0: true}, // fp32 mul
159156
{name: "MULSD", argLength: 2, reg: fp21, asm: "MULSD", commutative: true, resultInArg0: true}, // fp64 mul
160-
{name: "DIVSS", argLength: 2, reg: fp21x7, asm: "DIVSS", resultInArg0: true}, // fp32 div
161-
{name: "DIVSD", argLength: 2, reg: fp21x7, asm: "DIVSD", resultInArg0: true}, // fp64 div
157+
{name: "DIVSS", argLength: 2, reg: fp21, asm: "DIVSS", resultInArg0: true}, // fp32 div
158+
{name: "DIVSD", argLength: 2, reg: fp21, asm: "DIVSD", resultInArg0: true}, // fp64 div
162159

163160
{name: "MOVSSload", argLength: 2, reg: fpload, asm: "MOVSS", aux: "SymOff"}, // fp32 load
164161
{name: "MOVSDload", argLength: 2, reg: fpload, asm: "MOVSD", aux: "SymOff"}, // fp64 load

‎src/cmd/compile/internal/ssa/gen/AMD64Ops.go

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,6 @@ func init() {
9292
ax = buildReg("AX")
9393
cx = buildReg("CX")
9494
dx = buildReg("DX")
95-
x15 = buildReg("X15")
9695
gp = buildReg("AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15")
9796
fp = buildReg("X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15")
9897
gpsp = gp | buildReg("SP")
@@ -137,10 +136,8 @@ func init() {
137136
gpstorexchg = regInfo{inputs: []regMask{gp, gp, 0}, outputs: []regMask{gp}}
138137
cmpxchg = regInfo{inputs: []regMask{gp, ax, gp, 0}, outputs: []regMask{gp, 0}, clobbers: ax}
139138

140-
fp01 = regInfo{inputs: nil, outputs: fponly}
141-
fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: fponly}
142-
fp21x15 = regInfo{inputs: []regMask{fp &^ x15, fp &^ x15},
143-
clobbers: x15, outputs: []regMask{fp &^ x15}}
139+
fp01 = regInfo{inputs: nil, outputs: fponly}
140+
fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: fponly}
144141
fpgp = regInfo{inputs: fponly, outputs: gponly}
145142
gpfp = regInfo{inputs: gponly, outputs: fponly}
146143
fp11 = regInfo{inputs: fponly, outputs: fponly}
@@ -157,12 +154,12 @@ func init() {
157154
// fp ops
158155
{name: "ADDSS", argLength: 2, reg: fp21, asm: "ADDSS", commutative: true, resultInArg0: true}, // fp32 add
159156
{name: "ADDSD", argLength: 2, reg: fp21, asm: "ADDSD", commutative: true, resultInArg0: true}, // fp64 add
160-
{name: "SUBSS", argLength: 2, reg: fp21x15, asm: "SUBSS", resultInArg0: true}, // fp32 sub
161-
{name: "SUBSD", argLength: 2, reg: fp21x15, asm: "SUBSD", resultInArg0: true}, // fp64 sub
157+
{name: "SUBSS", argLength: 2, reg: fp21, asm: "SUBSS", resultInArg0: true}, // fp32 sub
158+
{name: "SUBSD", argLength: 2, reg: fp21, asm: "SUBSD", resultInArg0: true}, // fp64 sub
162159
{name: "MULSS", argLength: 2, reg: fp21, asm: "MULSS", commutative: true, resultInArg0: true}, // fp32 mul
163160
{name: "MULSD", argLength: 2, reg: fp21, asm: "MULSD", commutative: true, resultInArg0: true}, // fp64 mul
164-
{name: "DIVSS", argLength: 2, reg: fp21x15, asm: "DIVSS", resultInArg0: true}, // fp32 div
165-
{name: "DIVSD", argLength: 2, reg: fp21x15, asm: "DIVSD", resultInArg0: true}, // fp64 div
161+
{name: "DIVSS", argLength: 2, reg: fp21, asm: "DIVSS", resultInArg0: true}, // fp32 div
162+
{name: "DIVSD", argLength: 2, reg: fp21, asm: "DIVSD", resultInArg0: true}, // fp64 div
166163

167164
{name: "MOVSSload", argLength: 2, reg: fpload, asm: "MOVSS", aux: "SymOff"}, // fp32 load
168165
{name: "MOVSDload", argLength: 2, reg: fpload, asm: "MOVSD", aux: "SymOff"}, // fp64 load

‎src/cmd/compile/internal/ssa/opGen.go

Lines changed: 24 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -1561,12 +1561,11 @@ var opcodeTable = [...]opInfo{
15611561
asm: x86.ASUBSS,
15621562
reg: regInfo{
15631563
inputs: []inputInfo{
1564-
{0, 32512}, // X0 X1 X2 X3 X4 X5 X6
1565-
{1, 32512}, // X0 X1 X2 X3 X4 X5 X6
1564+
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
1565+
{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
15661566
},
1567-
clobbers: 32768, // X7
15681567
outputs: []outputInfo{
1569-
{0, 32512}, // X0 X1 X2 X3 X4 X5 X6
1568+
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
15701569
},
15711570
},
15721571
},
@@ -1577,12 +1576,11 @@ var opcodeTable = [...]opInfo{
15771576
asm: x86.ASUBSD,
15781577
reg: regInfo{
15791578
inputs: []inputInfo{
1580-
{0, 32512}, // X0 X1 X2 X3 X4 X5 X6
1581-
{1, 32512}, // X0 X1 X2 X3 X4 X5 X6
1579+
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
1580+
{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
15821581
},
1583-
clobbers: 32768, // X7
15841582
outputs: []outputInfo{
1585-
{0, 32512}, // X0 X1 X2 X3 X4 X5 X6
1583+
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
15861584
},
15871585
},
15881586
},
@@ -1625,12 +1623,11 @@ var opcodeTable = [...]opInfo{
16251623
asm: x86.ADIVSS,
16261624
reg: regInfo{
16271625
inputs: []inputInfo{
1628-
{0, 32512}, // X0 X1 X2 X3 X4 X5 X6
1629-
{1, 32512}, // X0 X1 X2 X3 X4 X5 X6
1626+
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
1627+
{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
16301628
},
1631-
clobbers: 32768, // X7
16321629
outputs: []outputInfo{
1633-
{0, 32512}, // X0 X1 X2 X3 X4 X5 X6
1630+
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
16341631
},
16351632
},
16361633
},
@@ -1641,12 +1638,11 @@ var opcodeTable = [...]opInfo{
16411638
asm: x86.ADIVSD,
16421639
reg: regInfo{
16431640
inputs: []inputInfo{
1644-
{0, 32512}, // X0 X1 X2 X3 X4 X5 X6
1645-
{1, 32512}, // X0 X1 X2 X3 X4 X5 X6
1641+
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
1642+
{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
16461643
},
1647-
clobbers: 32768, // X7
16481644
outputs: []outputInfo{
1649-
{0, 32512}, // X0 X1 X2 X3 X4 X5 X6
1645+
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
16501646
},
16511647
},
16521648
},
@@ -3954,12 +3950,11 @@ var opcodeTable = [...]opInfo{
39543950
asm: x86.ASUBSS,
39553951
reg: regInfo{
39563952
inputs: []inputInfo{
3957-
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
3958-
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
3953+
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3954+
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
39593955
},
3960-
clobbers: 2147483648, // X15
39613956
outputs: []outputInfo{
3962-
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
3957+
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
39633958
},
39643959
},
39653960
},
@@ -3970,12 +3965,11 @@ var opcodeTable = [...]opInfo{
39703965
asm: x86.ASUBSD,
39713966
reg: regInfo{
39723967
inputs: []inputInfo{
3973-
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
3974-
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
3968+
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3969+
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
39753970
},
3976-
clobbers: 2147483648, // X15
39773971
outputs: []outputInfo{
3978-
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
3972+
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
39793973
},
39803974
},
39813975
},
@@ -4018,12 +4012,11 @@ var opcodeTable = [...]opInfo{
40184012
asm: x86.ADIVSS,
40194013
reg: regInfo{
40204014
inputs: []inputInfo{
4021-
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
4022-
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
4015+
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
4016+
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
40234017
},
4024-
clobbers: 2147483648, // X15
40254018
outputs: []outputInfo{
4026-
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
4019+
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
40274020
},
40284021
},
40294022
},
@@ -4034,12 +4027,11 @@ var opcodeTable = [...]opInfo{
40344027
asm: x86.ADIVSD,
40354028
reg: regInfo{
40364029
inputs: []inputInfo{
4037-
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
4038-
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
4030+
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
4031+
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
40394032
},
4040-
clobbers: 2147483648, // X15
40414033
outputs: []outputInfo{
4042-
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
4034+
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
40434035
},
40444036
},
40454037
},

0 commit comments

Comments
 (0)