@@ -42,7 +42,7 @@ void ggml_sycl_host_free(void* ptr);
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extern int g_ggml_sycl_debug;
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extern int g_ggml_sycl_disable_optimize;
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- extern int g_ggml_sycl_disable_mmvq ;
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+ extern int g_ggml_sycl_prioritize_dmmv ;
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#define GGML_SYCL_DEBUG (...) \
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do { \
@@ -286,11 +286,25 @@ struct ggml_tensor_extra_gpu {
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void release_extra_gpu (ggml_tensor_extra_gpu * extra, std::vector<queue_ptr> streams={});
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- inline optimize_feature check_gpu_optimize_feature (syclex::architecture &/* arch*/ ) {
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+ inline optimize_feature check_gpu_optimize_feature (syclex::architecture &arch) {
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optimize_feature opt;
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- // TODO: Romain change to Intel vendor?
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- opt.reorder = true ;
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+ opt.reorder =
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+ (arch == syclex::architecture::intel_gpu_dg1 ||
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+ arch == syclex::architecture::intel_gpu_acm_g10 ||
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+ arch == syclex::architecture::intel_gpu_acm_g11 ||
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+ arch == syclex::architecture::intel_gpu_acm_g12 ||
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+ arch == syclex::architecture::intel_gpu_pvc ||
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+ arch == syclex::architecture::intel_gpu_pvc_vg ||
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+ arch == syclex::architecture::intel_gpu_mtl_u ||
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+ arch == syclex::architecture::intel_gpu_mtl_s ||
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+ arch == syclex::architecture::intel_gpu_mtl_h ||
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+ arch == syclex::architecture::intel_gpu_arl_u ||
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+ arch == syclex::architecture::intel_gpu_arl_s ||
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+ arch == syclex::architecture::intel_gpu_arl_h ||
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+ arch == syclex::architecture::intel_gpu_bmg_g21 ||
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+ arch == syclex::architecture::intel_gpu_lnl_m
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+ );
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return opt;
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}
@@ -485,5 +499,4 @@ constexpr size_t ceil_div(const size_t m, const size_t n) {
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}
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bool gpu_has_xmx (sycl::device &dev);
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-
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#endif // GGML_SYCL_COMMON_HPP
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