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lines changed Original file line number Diff line number Diff line change @@ -3689,6 +3689,7 @@ m5stack-core2.upload.tool=esptool_py
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m5stack-core2.upload.maximum_size=6553600
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m5stack-core2.upload.maximum_data_size=4521984
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m5stack-core2.upload.wait_for_upload_port=true
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+ m5stack-core2.upload.flags=
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m5stack-core2.serial.disableDTR=true
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m5stack-core2.serial.disableRTS=true
Original file line number Diff line number Diff line change @@ -51,12 +51,6 @@ bool psramInit(){
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log_w ("PSRAM not supported!" );
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return false;
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}
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- esp_spiram_init_cache ();
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- #elif CONFIG_IDF_TARGET_ESP32S2
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- extern void esp_config_data_cache_mode (void );
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- esp_config_data_cache_mode ();
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- Cache_Enable_DCache (0 );
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- #endif
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if (esp_spiram_init () != ESP_OK ) {
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spiramFailed = true;
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log_w ("PSRAM init failed!" );
@@ -67,6 +61,11 @@ bool psramInit(){
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return false;
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}
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esp_spiram_init_cache ();
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+ #elif CONFIG_IDF_TARGET_ESP32S2
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+ extern void esp_config_data_cache_mode (void );
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+ esp_config_data_cache_mode ();
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+ Cache_Enable_DCache (0 );
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+ #endif
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if (!esp_spiram_test ()) {
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spiramFailed = true;
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log_e ("PSRAM test failed!" );
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