Initial S3 Support

Just so we can compile and test! Some things might/will not work. SPI and UART baud detect need to be looked at.

Author: me-no-dev

boards.txt

@@ -161,6 +161,185 @@ esp32c3.menu.DebugLevel.verbose.build.code_debug=5
 
 ##############################################################
 
+esp32s3.name=ESP32S3 Dev Module
+esp32s3.vid.0=0x303a
+esp32s3.pid.0=0x0002
+
+esp32s3.upload.tool=esptool_py
+esp32s3.upload.maximum_size=1310720
+esp32s3.upload.maximum_data_size=327680
+esp32s3.upload.flags=
+esp32s3.upload.extra_flags=
+esp32s3.upload.use_1200bps_touch=false
+esp32s3.upload.wait_for_upload_port=false
+
+esp32s3.serial.disableDTR=false
+esp32s3.serial.disableRTS=false
+
+esp32s3.build.tarch=xtensa
+esp32s3.build.bootloader_addr=0x1000
+esp32s3.build.target=esp32s3
+esp32s3.build.mcu=esp32s3
+esp32s3.build.core=esp32
+esp32s3.build.variant=esp32s3
+esp32s3.build.board=ESP32S3_DEV
+
+esp32s3.build.cdc_on_boot=0
+esp32s3.build.msc_on_boot=0
+esp32s3.build.dfu_on_boot=0
+esp32s3.build.f_cpu=240000000L
+esp32s3.build.flash_size=4MB
+esp32s3.build.flash_freq=80m
+esp32s3.build.flash_mode=dio
+esp32s3.build.boot=qio
+esp32s3.build.partitions=default
+esp32s3.build.defines=
+esp32s3.build.loop_core=
+esp32s3.build.event_core=
+
+esp32s3.menu.LoopCore.1=Core 1
+esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+esp32s3.menu.LoopCore.0=Core 0
+esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+esp32s3.menu.EventsCore.1=Core 1
+esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+esp32s3.menu.EventsCore.0=Core 0
+esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+esp32s3.menu.CDCOnBoot.default=Disabled
+esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32s3.menu.CDCOnBoot.cdc=Enabled
+esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32s3.menu.MSCOnBoot.default=Disabled
+esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+esp32s3.menu.MSCOnBoot.msc=Enabled
+esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+esp32s3.menu.DFUOnBoot.default=Disabled
+esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+esp32s3.menu.DFUOnBoot.dfu=Enabled
+esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+esp32s3.menu.UploadMode.default=UART0
+esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+esp32s3.menu.UploadMode.cdc=Internal USB
+esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+esp32s3.menu.PSRAM.disabled=Disabled
+esp32s3.menu.PSRAM.disabled.build.defines=
+esp32s3.menu.PSRAM.enabled=Enabled
+esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+
+esp32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32s3.menu.PartitionScheme.default.build.partitions=default
+esp32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32s3.menu.PartitionScheme.default_8MB=8M Flash (3MB APP/1.5MB FAT)
+esp32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
+esp32s3.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS)
+esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+esp32s3.menu.CPUFreq.240=240MHz (WiFi)
+esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L
+esp32s3.menu.CPUFreq.160=160MHz (WiFi)
+esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32s3.menu.CPUFreq.80=80MHz (WiFi)
+esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32s3.menu.CPUFreq.40=40MHz
+esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32s3.menu.CPUFreq.20=20MHz
+esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32s3.menu.CPUFreq.10=10MHz
+esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32s3.menu.FlashMode.qio=QIO
+esp32s3.menu.FlashMode.qio.build.flash_mode=dio
+esp32s3.menu.FlashMode.qio.build.boot=qio
+esp32s3.menu.FlashMode.dio=DIO
+esp32s3.menu.FlashMode.dio.build.flash_mode=dio
+esp32s3.menu.FlashMode.dio.build.boot=dio
+esp32s3.menu.FlashMode.qout=QOUT
+esp32s3.menu.FlashMode.qout.build.flash_mode=dout
+esp32s3.menu.FlashMode.qout.build.boot=qout
+esp32s3.menu.FlashMode.dout=DOUT
+esp32s3.menu.FlashMode.dout.build.flash_mode=dout
+esp32s3.menu.FlashMode.dout.build.boot=dout
+
+esp32s3.menu.FlashFreq.80=80MHz
+esp32s3.menu.FlashFreq.80.build.flash_freq=80m
+esp32s3.menu.FlashFreq.40=40MHz
+esp32s3.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32s3.menu.FlashSize.4M=4MB (32Mb)
+esp32s3.menu.FlashSize.4M.build.flash_size=4MB
+esp32s3.menu.FlashSize.8M=8MB (64Mb)
+esp32s3.menu.FlashSize.8M.build.flash_size=8MB
+esp32s3.menu.FlashSize.8M.build.partitions=default_8MB
+esp32s3.menu.FlashSize.2M=2MB (16Mb)
+esp32s3.menu.FlashSize.2M.build.flash_size=2MB
+esp32s3.menu.FlashSize.2M.build.partitions=minimal
+esp32s3.menu.FlashSize.16M=16MB (128Mb)
+esp32s3.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32s3.menu.UploadSpeed.921600=921600
+esp32s3.menu.UploadSpeed.921600.upload.speed=921600
+esp32s3.menu.UploadSpeed.115200=115200
+esp32s3.menu.UploadSpeed.115200.upload.speed=115200
+esp32s3.menu.UploadSpeed.256000.windows=256000
+esp32s3.menu.UploadSpeed.256000.upload.speed=256000
+esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32s3.menu.UploadSpeed.230400=230400
+esp32s3.menu.UploadSpeed.230400.upload.speed=230400
+esp32s3.menu.UploadSpeed.460800.linux=460800
+esp32s3.menu.UploadSpeed.460800.macosx=460800
+esp32s3.menu.UploadSpeed.460800.upload.speed=460800
+esp32s3.menu.UploadSpeed.512000.windows=512000
+esp32s3.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32s3.menu.DebugLevel.none=None
+esp32s3.menu.DebugLevel.none.build.code_debug=0
+esp32s3.menu.DebugLevel.error=Error
+esp32s3.menu.DebugLevel.error.build.code_debug=1
+esp32s3.menu.DebugLevel.warn=Warn
+esp32s3.menu.DebugLevel.warn.build.code_debug=2
+esp32s3.menu.DebugLevel.info=Info
+esp32s3.menu.DebugLevel.info.build.code_debug=3
+esp32s3.menu.DebugLevel.debug=Debug
+esp32s3.menu.DebugLevel.debug.build.code_debug=4
+esp32s3.menu.DebugLevel.verbose=Verbose
+esp32s3.menu.DebugLevel.verbose.build.code_debug=5
+
+##############################################################
+
 esp32s2.name=ESP32S2 Dev Module
 esp32s2.vid.0=0x303a
 esp32s2.pid.0=0x0002

cores/esp32/Esp.cpp

@@ -40,6 +40,10 @@ extern "C" {
 #include "esp32s2/rom/spi_flash.h"
 #include "soc/efuse_reg.h"
 #define ESP_FLASH_IMAGE_BASE 0x1000
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/spi_flash.h"
+#include "soc/efuse_reg.h"
+#define ESP_FLASH_IMAGE_BASE 0x1000
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rom/spi_flash.h"
 #define ESP_FLASH_IMAGE_BASE 0x0000     // Esp32c3 is located at 0x0000

cores/esp32/HardwareSerial.cpp

@@ -10,7 +10,7 @@
 #ifndef SOC_RX0
 #if CONFIG_IDF_TARGET_ESP32
 #define SOC_RX0 3
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
 #define SOC_RX0 44
 #elif CONFIG_IDF_TARGET_ESP32C3
 #define SOC_RX0 20
@@ -20,7 +20,7 @@
 #ifndef SOC_TX0
 #if CONFIG_IDF_TARGET_ESP32
 #define SOC_TX0 1
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
 #define SOC_TX0 43
 #elif CONFIG_IDF_TARGET_ESP32C3
 #define SOC_TX0 21
@@ -35,7 +35,7 @@ void serialEvent(void) {}
 #ifndef RX1
 #if CONFIG_IDF_TARGET_ESP32
 #define RX1 9
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
 #define RX1 18
 #elif CONFIG_IDF_TARGET_ESP32C3
 #define RX1 18
@@ -45,7 +45,7 @@ void serialEvent(void) {}
 #ifndef TX1
 #if CONFIG_IDF_TARGET_ESP32
 #define TX1 10
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
 #define TX1 17
 #elif CONFIG_IDF_TARGET_ESP32C3
 #define TX1 19
@@ -60,12 +60,16 @@ void serialEvent1(void) {}
 #ifndef RX2
 #if CONFIG_IDF_TARGET_ESP32
 #define RX2 16
+#else
+#define RX2 -1
 #endif
 #endif
 
 #ifndef TX2
 #if CONFIG_IDF_TARGET_ESP32
 #define TX2 17
+#else
+#define TX2 -1
 #endif
 #endif
 

cores/esp32/esp32-hal-adc.c

@@ -35,6 +35,10 @@ static uint8_t __analogVRefPin = 0;
 #include "esp32s2/rom/ets_sys.h"
 #include "soc/sens_reg.h"
 #include "soc/rtc_io_reg.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/ets_sys.h"
+#include "soc/sens_reg.h"
+#include "soc/rtc_io_reg.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rom/ets_sys.h"
 #else

cores/esp32/esp32-hal-cpu.c

@@ -33,6 +33,9 @@
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "freertos/xtensa_timer.h"
 #include "esp32s2/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "freertos/xtensa_timer.h"
+#include "esp32s3/rom/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rom/rtc.h"
 #else 

cores/esp32/esp32-hal-i2c-slave.c

@@ -127,7 +127,7 @@ typedef enum {
 
 static inline i2c_stretch_cause_t i2c_ll_stretch_cause(i2c_dev_t *hw)
 {
-#if CONFIG_IDF_TARGET_ESP32C3
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
     return hw->sr.stretch_cause;
 #elif CONFIG_IDF_TARGET_ESP32S2
     return hw->status_reg.stretch_cause;
@@ -164,7 +164,7 @@ static inline void i2c_ll_stretch_clr(i2c_dev_t *hw)
 
 static inline bool i2c_ll_slave_addressed(i2c_dev_t *hw)
 {
-#if CONFIG_IDF_TARGET_ESP32C3
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
     return hw->sr.slave_addressed;
 #else
     return hw->status_reg.slave_addressed;
@@ -173,7 +173,7 @@ static inline bool i2c_ll_slave_addressed(i2c_dev_t *hw)
 
 static inline bool i2c_ll_slave_rw(i2c_dev_t *hw)//not exposed by hal_ll
 {
-#if CONFIG_IDF_TARGET_ESP32C3
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
     return hw->sr.slave_rw;
 #else
     return hw->status_reg.slave_rw;

cores/esp32/esp32-hal-matrix.c

@@ -21,6 +21,8 @@
 #include "esp32/rom/gpio.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/gpio.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rom/gpio.h"
 #else 

cores/esp32/esp32-hal-misc.c

@@ -41,6 +41,9 @@
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rom/rtc.h"
 #include "driver/temp_sensor.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/rtc.h"
+#include "driver/temp_sensor.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rom/rtc.h"
 #include "driver/temp_sensor.h"