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Update boards.txt
add circuitart_zero_s3 details
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boards.txt

Lines changed: 162 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38845,3 +38845,165 @@ elecrow_crowpanel_7.menu.EraseFlash.all=Enabled
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elecrow_crowpanel_7.menu.EraseFlash.all.upload.erase_cmd=-e
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##############################################################
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circuitart_zero_s3.name=CircuitART Zero S3
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circuitart_zero_s3.vid.0=0x303a
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circuitart_zero_s3.pid.0=0x80DB
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circuitart_zero_s3.bootloader.tool=esptool_py
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circuitart_zero_s3.bootloader.tool.default=esptool_py
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circuitart_zero_s3.upload.tool=esptool_py
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circuitart_zero_s3.upload.tool.default=esptool_py
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circuitart_zero_s3.upload.tool.network=esp_ota
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circuitart_zero_s3.upload.maximum_size=1310720
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circuitart_zero_s3.upload.maximum_data_size=327680
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circuitart_zero_s3.upload.flags=
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circuitart_zero_s3.upload.extra_flags=
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circuitart_zero_s3.upload.use_1200bps_touch=false
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circuitart_zero_s3.upload.wait_for_upload_port=false
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circuitart_zero_s3.serial.disableDTR=false
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circuitart_zero_s3.serial.disableRTS=false
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circuitart_zero_s3.build.tarch=xtensa
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circuitart_zero_s3.build.bootloader_addr=0x0
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circuitart_zero_s3.build.target=esp32s3
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circuitart_zero_s3.build.mcu=esp32s3
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circuitart_zero_s3.build.core=esp32
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circuitart_zero_s3.build.variant=circuitart_zero_s3
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circuitart_zero_s3.build.board=CIRCUITART_ZERO_S3
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circuitart_zero_s3.build.usb_mode=1
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circuitart_zero_s3.build.cdc_on_boot=0
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circuitart_zero_s3.build.msc_on_boot=0
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circuitart_zero_s3.build.dfu_on_boot=0
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circuitart_zero_s3.build.f_cpu=240000000L
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circuitart_zero_s3.build.flash_size=16MB
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circuitart_zero_s3.build.flash_freq=80m
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circuitart_zero_s3.build.flash_mode=dio
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circuitart_zero_s3.build.boot=qio
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circuitart_zero_s3.build.partitions=default
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circuitart_zero_s3.build.defines=
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circuitart_zero_s3.build.loop_core=
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circuitart_zero_s3.build.event_core=
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circuitart_zero_s3.build.flash_type=qio
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circuitart_zero_s3.build.psram_type=qspi
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circuitart_zero_s3.build.memory_type=qio_qspi
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circuitart_zero_s3.menu.LoopCore.1=Core 1
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circuitart_zero_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
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circuitart_zero_s3.menu.LoopCore.0=Core 0
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circuitart_zero_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
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circuitart_zero_s3.menu.EventsCore.1=Core 1
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circuitart_zero_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
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circuitart_zero_s3.menu.EventsCore.0=Core 0
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circuitart_zero_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
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circuitart_zero_s3.menu.USBMode.default=USB-OTG (TinyUSB)
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circuitart_zero_s3.menu.USBMode.default.build.usb_mode=0
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circuitart_zero_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
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circuitart_zero_s3.menu.USBMode.hwcdc.build.usb_mode=1
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circuitart_zero_s3.menu.CDCOnBoot.cdc=Enabled
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circuitart_zero_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
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circuitart_zero_s3.menu.CDCOnBoot.default=Disabled
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circuitart_zero_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
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circuitart_zero_s3.menu.MSCOnBoot.default=Disabled
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circuitart_zero_s3.menu.MSCOnBoot.default.build.msc_on_boot=0
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circuitart_zero_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
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circuitart_zero_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
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circuitart_zero_s3.menu.DFUOnBoot.default=Disabled
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circuitart_zero_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
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circuitart_zero_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
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circuitart_zero_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
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circuitart_zero_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
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circuitart_zero_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
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circuitart_zero_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
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circuitart_zero_s3.menu.UploadMode.default=UART0 / Hardware CDC
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circuitart_zero_s3.menu.UploadMode.default.upload.use_1200bps_touch=false
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circuitart_zero_s3.menu.UploadMode.default.upload.wait_for_upload_port=false
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circuitart_zero_s3.menu.PSRAM.enabled=Enabled
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circuitart_zero_s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
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circuitart_zero_s3.menu.PSRAM.disabled=Disabled
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circuitart_zero_s3.menu.PSRAM.disabled.build.defines=
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circuitart_zero_s3.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS)
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circuitart_zero_s3.menu.PartitionScheme.default_16MB.build.partitions=default_16MB
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circuitart_zero_s3.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600
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circuitart_zero_s3.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/12MB FFAT)
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circuitart_zero_s3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2
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circuitart_zero_s3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2
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circuitart_zero_s3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
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circuitart_zero_s3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
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circuitart_zero_s3.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/6.93MB SPIFFS)
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circuitart_zero_s3.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB
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circuitart_zero_s3.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592
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circuitart_zero_s3.menu.PartitionScheme.app3M_fat9M_16MB=FFAT (3MB APP/9MB FATFS)
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circuitart_zero_s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
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circuitart_zero_s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
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circuitart_zero_s3.menu.PartitionScheme.fatflash=Large FFAT (2MB APP/12.5MB FATFS)
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circuitart_zero_s3.menu.PartitionScheme.fatflash.build.partitions=ffat
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circuitart_zero_s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
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circuitart_zero_s3.menu.CPUFreq.240=240MHz (WiFi)
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circuitart_zero_s3.menu.CPUFreq.240.build.f_cpu=240000000L
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circuitart_zero_s3.menu.CPUFreq.160=160MHz (WiFi)
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circuitart_zero_s3.menu.CPUFreq.160.build.f_cpu=160000000L
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circuitart_zero_s3.menu.CPUFreq.80=80MHz (WiFi)
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circuitart_zero_s3.menu.CPUFreq.80.build.f_cpu=80000000L
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circuitart_zero_s3.menu.CPUFreq.40=40MHz
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circuitart_zero_s3.menu.CPUFreq.40.build.f_cpu=40000000L
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circuitart_zero_s3.menu.CPUFreq.20=20MHz
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circuitart_zero_s3.menu.CPUFreq.20.build.f_cpu=20000000L
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circuitart_zero_s3.menu.CPUFreq.10=10MHz
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circuitart_zero_s3.menu.CPUFreq.10.build.f_cpu=10000000L
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circuitart_zero_s3.menu.FlashMode.qio=QIO
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circuitart_zero_s3.menu.FlashMode.qio.build.flash_mode=dio
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circuitart_zero_s3.menu.FlashMode.qio.build.boot=qio
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circuitart_zero_s3.menu.FlashMode.dio=DIO
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circuitart_zero_s3.menu.FlashMode.dio.build.flash_mode=dio
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circuitart_zero_s3.menu.FlashMode.dio.build.boot=dio
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circuitart_zero_s3.menu.UploadSpeed.921600=921600
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circuitart_zero_s3.menu.UploadSpeed.921600.upload.speed=921600
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circuitart_zero_s3.menu.UploadSpeed.115200=115200
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circuitart_zero_s3.menu.UploadSpeed.115200.upload.speed=115200
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circuitart_zero_s3.menu.UploadSpeed.256000.windows=256000
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circuitart_zero_s3.menu.UploadSpeed.256000.upload.speed=256000
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circuitart_zero_s3.menu.UploadSpeed.230400.windows.upload.speed=256000
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circuitart_zero_s3.menu.UploadSpeed.230400=230400
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circuitart_zero_s3.menu.UploadSpeed.230400.upload.speed=230400
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circuitart_zero_s3.menu.UploadSpeed.460800.linux=460800
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circuitart_zero_s3.menu.UploadSpeed.460800.macosx=460800
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circuitart_zero_s3.menu.UploadSpeed.460800.upload.speed=460800
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circuitart_zero_s3.menu.UploadSpeed.512000.windows=512000
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circuitart_zero_s3.menu.UploadSpeed.512000.upload.speed=512000
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circuitart_zero_s3.menu.DebugLevel.none=None
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circuitart_zero_s3.menu.DebugLevel.none.build.code_debug=0
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circuitart_zero_s3.menu.DebugLevel.error=Error
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circuitart_zero_s3.menu.DebugLevel.error.build.code_debug=1
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circuitart_zero_s3.menu.DebugLevel.warn=Warn
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circuitart_zero_s3.menu.DebugLevel.warn.build.code_debug=2
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circuitart_zero_s3.menu.DebugLevel.info=Info
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circuitart_zero_s3.menu.DebugLevel.info.build.code_debug=3
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circuitart_zero_s3.menu.DebugLevel.debug=Debug
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circuitart_zero_s3.menu.DebugLevel.debug.build.code_debug=4
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circuitart_zero_s3.menu.DebugLevel.verbose=Verbose
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circuitart_zero_s3.menu.DebugLevel.verbose.build.code_debug=5
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circuitart_zero_s3.menu.EraseFlash.none=Disabled
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circuitart_zero_s3.menu.EraseFlash.none.upload.erase_cmd=
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circuitart_zero_s3.menu.EraseFlash.all=Enabled
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circuitart_zero_s3.menu.EraseFlash.all.upload.erase_cmd=-e
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##############################################################
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