diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json index 2687b2471e..8cd9048fc8 100644 --- a/CI/build/conf/cores_config.json +++ b/CI/build/conf/cores_config.json @@ -107,6 +107,7 @@ "DIYMORE_F407VGT", "EEXTR_F030_V1", "ELEKTOR_F072C8", + "ELEKTOR_F072CB", "FEATHER_F405", "FYSETC_S6", "Generic_F103CB", @@ -148,9 +149,9 @@ "pattern": "Firmata[\\\\/]", "applicable": false, "boards": [ - "EEXTR_F030_V1", "ELEKTOR_F072C8", "FYSETC_S6", "Generic_F103ZG", "MALYANM200_F103CB", - "PRNTR_V2", "PX_HER0", "STEVAL_MKSBOX1V1", "VAKE_F446VE", "VCCGND_F103ZET6", - "VCCGND_F103ZET6Mini", "Wraith32_V1" + "EEXTR_F030_V1", "ELEKTOR_F072C8", "ELEKTOR_F072CB", "FYSETC_S6", "Generic_F103ZG", + "MALYANM200_F103CB", "PRNTR_V2", "PX_HER0", "STEVAL_MKSBOX1V1", "VAKE_F446VE", + "VCCGND_F103ZET6", "VCCGND_F103ZET6Mini", "Wraith32_V1" ] }, { diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index bde43514ed..9b1b3c9895 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -364,10 +364,16 @@ #define CMSIS_STARTUP_FILE "startup_stm32l4s9xx.s" #elif defined(STM32MP1xx) #define CMSIS_STARTUP_FILE "startup_stm32mp15xx.s" + #elif defined(STM32WB30xx) + #define CMSIS_STARTUP_FILE "startup_stm32wb30xx_cm4.s" + #elif defined(STM32WB35xx) + #define CMSIS_STARTUP_FILE "startup_stm32wb35xx_cm4.s" #elif defined(STM32WB50xx) #define CMSIS_STARTUP_FILE "startup_stm32wb50xx_cm4.s" #elif defined(STM32WB55xx) #define CMSIS_STARTUP_FILE "startup_stm32wb55xx_cm4.s" + #elif defined(STM32WB5Mxx) + #define CMSIS_STARTUP_FILE "startup_stm32wb5mxx_cm4.s" #else #error UNKNOWN CHIP #endif diff --git a/libraries/Servo/src/stm32/Servo.cpp b/libraries/Servo/src/stm32/Servo.cpp index 9bf4bb047d..41c77c7584 100644 --- a/libraries/Servo/src/stm32/Servo.cpp +++ b/libraries/Servo/src/stm32/Servo.cpp @@ -84,6 +84,7 @@ static void TimerServoInit() TimerServo.setPrescaleFactor(prescaler); TimerServo.setOverflow(REFRESH_INTERVAL); // thanks to prescaler Tick = microsec TimerServo.attachInterrupt(Servo_PeriodElapsedCallback); + TimerServo.setPreloadEnable(false); TimerServo.resume(); } diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2s.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2s.c index dd933a19cc..fb77348cf9 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2s.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2s.c @@ -31,3 +31,6 @@ #ifdef STM32L1xx #include "stm32l1xx_hal_i2s.c" #endif +#ifdef STM32WBxx + #include "stm32wbxx_hal_i2s.c" +#endif diff --git a/system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/generate.bat b/system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/generate.bat new file mode 100644 index 0000000000..9d573ede1d --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/generate.bat @@ -0,0 +1,20 @@ +@color 0B +@echo off + +REM Generate all CMSIS files +REM Active perl must be installed + +set scriptPATH=%CD%\..\..\..\..\..\..\..\__INTERNAL__tools\tools\_CmsisDeviceGenerator\ + +if not exist "%scriptPATH%" ( + echo Input directory does not exist! + pause + exit +) + +cd %scriptPATH% + +perl DeviceGeneration.pl --target STM32F2xx -replace + +pause +:EOF \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h b/system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h index 377491e9aa..b56e1e1550 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h @@ -81,11 +81,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.2.2 + * @brief CMSIS Device version number V2.2.3 */ #define __STM32F2xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */ #define __STM32F2xx_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ -#define __STM32F2xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ +#define __STM32F2xx_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ #define __STM32F2xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F2xx_CMSIS_VERSION ((__STM32F2xx_CMSIS_VERSION_MAIN << 24)\ |(__STM32F2xx_CMSIS_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F2xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32F2xx/Release_Notes.html index 8930a32b60..fa329d2dae 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F2xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32F2xx/Release_Notes.html @@ -82,7 +82,7 @@

Release Notes for STM32F2xx CMSIS

Copyright 2017 STMicroelectronics

-

+

@@ -94,7 +94,9 @@

Update History

-

V2.2.2 / 26-June-2019

+

V2.2.3 / 31-December-2019

+ Main Changes
+

V2.2.2 / 26-June-2019

Main Changes

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32wb35xx + * @{ + */ + +#ifndef __STM32WB35xx_H +#define __STM32WB35xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 1U /*!< Core Revision r0p1 */ +#define __MPU_PRESENT 1U /*!< M4 provides an MPU */ +#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 4U /*!< STM32WBxx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32wb35xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +/*!< Interrupt Number Definition for M4 */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt */ + +/************* STM32WBxx specific Interrupt Numbers on M4 core ************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD and PVM detector */ + TAMP_STAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Interrupt */ + FLASH_IRQn = 4, /*!< FLASH (CFI) global Interrupt */ + RCC_IRQn = 5, /*!< RCC Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line 0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line 1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line 2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line 3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line 4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt (including USB wakeup) */ + C2SEV_PWR_C2H_IRQn = 21, /*!< CPU2 SEV Interrupt */ + COMP_IRQn = 22, /*!< COMP1 and COMP2 Interrupts */ + EXTI9_5_IRQn = 23, /*!< EXTI Lines [9:5] Interrupt */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 global Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Communication and TIM17 global Interrupts */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 Global Interrupt */ + PKA_IRQn = 29, /*!< PKA Interrupt */ + I2C1_EV_IRQn = 30, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 31, /*!< I2C1 Error Interrupt */ + I2C3_EV_IRQn = 32, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 33, /*!< I2C3 Error Interrupt */ + SPI1_IRQn = 34, /*!< SPI1 Interrupt */ + SPI2_IRQn = 35, /*!< SPI2 Interrupt */ + USART1_IRQn = 36, /*!< USART1 Interrupt */ + LPUART1_IRQn = 37, /*!< LPUART1 Interrupt */ + TSC_IRQn = 39, /*!< TSC Interrupt */ + EXTI15_10_IRQn = 40, /*!< EXTI Lines1[15:10 ]Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarms (A and B) Interrupt */ + CRS_IRQn = 42, /*!< CRS interrupt */ + PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQn = 43, /*!< PWR switching on the fly interrupt + PWR end of BLE activity interrupt + PWR end of 802.15.4 (Zigbee) activity interrupt + PWR end of critical radio phase interrupt */ + IPCC_C1_RX_IRQn = 44, /*!< IPCC RX Occupied Interrupt */ + IPCC_C1_TX_IRQn = 45, /*!< IPCC TX Free Interrupt */ + HSEM_IRQn = 46, /*!< HSEM Interrupt */ + LPTIM1_IRQn = 47, /*!< LPTIM1 Interrupt */ + LPTIM2_IRQn = 48, /*!< LPTIM2 Interrupt */ + QUADSPI_IRQn = 50, /*!< QUADSPI Interrupt */ + AES1_IRQn = 51, /*!< AES1 Interrupt */ + AES2_IRQn = 52, /*!< AES2 Interrupt */ + RNG_IRQn = 53, /*!< RNG Interrupt */ + FPU_IRQn = 54, /*!< FPU Interrupt */ + DMA2_Channel1_IRQn = 55, /*!< DMA2 Channel 1 Interrupt */ + DMA2_Channel2_IRQn = 56, /*!< DMA2 Channel 2 Interrupt */ + DMA2_Channel3_IRQn = 57, /*!< DMA2 Channel 3 Interrupt */ + DMA2_Channel4_IRQn = 58, /*!< DMA2 Channel 4 Interrupt */ + DMA2_Channel5_IRQn = 59, /*!< DMA2 Channel 5 Interrupt */ + DMA2_Channel6_IRQn = 60, /*!< DMA2 Channel 6 Interrupt */ + DMA2_Channel7_IRQn = 61, /*!< DMA2 Channel 7 Interrupt */ + DMAMUX1_OVR_IRQn = 62 /*!< DMAMUX1 overrun Interrupt */ +} IRQn_Type; +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32wbxx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */ +} ADC_Common_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x08-0x38 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x3C */ + __IO uint32_t C2APB1FZR1; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x40 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x44 */ + __IO uint32_t C2APB1FZR2; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x48 */ + __IO uint32_t APB2FZR; /*!< Debug MCU CPU1 APB2 freeze register, Address offset: 0x4C */ + __IO uint32_t C2APB2FZR; /*!< Debug MCU CPU2 APB2 freeze register, Address offset: 0x50 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register 0x00 */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register 0x04 */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register 0x08 */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register 0x0C */ + uint32_t RESERVED; /*!< Reserved, 0x10 */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */ + __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank 1 PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank 1 PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank 1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank 1 WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank 1 PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank 1 PCROP area B End address register, Address offset: 0x38 */ + __IO uint32_t IPCCBR; /*!< FLASH IPCC data buffer address, Address offset: 0x3C */ + uint32_t RESERVED2[7]; /*!< Reserved, Address offset: 0x40-0x58 */ + __IO uint32_t C2ACR; /*!< FLASH Core MO+ Access Control Register , Address offset: 0x5C */ + __IO uint32_t C2SR; /*!< FLASH Core MO+ Status Register, Address offset: 0x60 */ + __IO uint32_t C2CR; /*!< FLASH Core MO+ Control register, Address offset: 0x64 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x68-0x7C */ + __IO uint32_t SFR; /*!< FLASH secure start address, Address offset: 0x80 */ + __IO uint32_t SRRVR; /*!< FlASH secure SRAM2 start addr and CPU2 reset vector Address offset: 0x84 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Reset Register, Address offset: 0x18 */ + __IO uint32_t CR5; /*!< PWR Power Control Register 5, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< PWR Pull-Up Control Register of port E, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< PWR Pull-Down Control Register of port E, Address offset: 0x44 */ + uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t PUCRH; /*!< PWR Pull-Up Control Register of port H, Address offset: 0x58 */ + __IO uint32_t PDCRH; /*!< PWR Pull-Down Control Register of port H, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x60-0x7C */ + __IO uint32_t C2CR1; /*!< PWR Power Control Register 1 for CPU2, Address offset: 0x80 */ + __IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset: 0x84 */ + __IO uint32_t EXTSCR; /*!< PWR Power Status Reset Register for CPU2, Address offset: 0x88 */ +} PWR_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ +uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x10-0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t SMPSCR; /*!< RCC SMPS step-down converter control register, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */ +uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable register, Address offset: 0x50 */ +uint32_t RESERVED2; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ +uint32_t RESERVED3; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ +uint32_t RESERVED4; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ +uint32_t RESERVED5; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Clock Configuration Independent Register, Address offset: 0x88 */ +uint32_t RESERVED6; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC Control and Status Register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x98 */ + __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */ +uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */ + __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ +uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ + __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */ + __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */ + __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */ +uint32_t RESERVED9; /*!< Reserved, Address offset: 0x154 */ + __IO uint32_t C2APB1ENR1; /*!< RCC APB1 peripheral CPU2 clocks enable register 1, Address offset: 0x158 */ + __IO uint32_t C2APB1ENR2; /*!< RCC APB1 peripheral CPU2 clocks enable register 2, Address offset: 0x15C */ + __IO uint32_t C2APB2ENR; /*!< RCC APB2 peripheral CPU2 clocks enable register 1, Address offset: 0x160 */ + __IO uint32_t C2APB3ENR; /*!< RCC APB3 peripheral CPU2 clocks enable register 1, Address offset: 0x164 */ + __IO uint32_t C2AHB1SMENR; /*!< RCC AHB1 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x168 */ + __IO uint32_t C2AHB2SMENR; /*!< RCC AHB2 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x16C */ + __IO uint32_t C2AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x170 */ +uint32_t RESERVED10; /*!< Reserved, */ + __IO uint32_t C2APB1SMENR1; /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 1, Address offset: 0x178 */ + __IO uint32_t C2APB1SMENR2; /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 2, Address offset: 0x17C */ + __IO uint32_t C2APB2SMENR; /*!< RCC APB2 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x180 */ + __IO uint32_t C2APB3SMENR; /*!< RCC APB3 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x184 */ +} RCC_TypeDef; + + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + + + + +/** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR1; /*!< SYSCFG SRAM2 write protection register part 1, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ + __IO uint32_t SWPR2; /*!< SYSCFG write protection register part 2, Address offset: 0x28 */ + uint32_t RESERVED1[53]; /*!< Reserved, Address offset: 0x2C-0xFC */ + __IO uint32_t IMR1; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 1, Address offset: 0x100 */ + __IO uint32_t IMR2; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 2, Address offset: 0x104 */ + __IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 1, Address offset: 0x108 */ + __IO uint32_t C2IMR2; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 2, Address offset: 0x10C */ + __IO uint32_t SIPCR; /*!< SYSCFG secure IP control register, Address offset: 0x110 */ + +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ +} AES_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */ +} TSC_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Inter-Processor Communication + */ +typedef struct +{ + __IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, Address offset: 0x000 */ + __IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, Address offset: 0x004 */ + __IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, Address offset: 0x008 */ + __IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status register, Address offset: 0x00C */ + __IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, Address offset: 0x010 */ + __IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, Address offset: 0x014 */ + __IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, Address offset: 0x018 */ + __IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status register, Address offset: 0x01C */ +} IPCC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x000 */ + __IO uint32_t MR; /*!< Mask register, Address offset: 0x004 */ + __IO uint32_t SCR; /*!< Status set clear register, Address offset: 0x008 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x00C */ +} IPCC_CommonTypeDef; + +/** + * @brief Async Interrupts and Events Controller + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI software interrupt event register [31:0], Address offset: 0x08 */ + __IO uint32_t PR1; /*!< EXTI pending register [31:0], Address offset: 0x0C */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x10 - 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI software interrupt event register [31:0], Address offset: 0x28 */ + __IO uint32_t PR2; /*!< EXTI pending register [31:0], Address offset: 0x2C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x30 - 0x3C */ + __IO uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x40 - 0x5C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, Address offset: 0x60 - 0x7C */ + __IO uint32_t IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED8[10]; /*!< Reserved, Address offset: 0x98 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ +}EXTI_TypeDef; + +/** + * @brief Public Key Accelerator (PKA) + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03FC*/ + __IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F4 */ +} PKA_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ +typedef struct +{ + __IO uint32_t R[32]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< HSEM 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM CPU1 interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM CPU1 interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM CPU1 interrupt status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM CPU1 masked interrupt status register , Address offset: 10Ch */ + __IO uint32_t C2IER; /*!< HSEM CPU2 interrupt enable register , Address offset: 110h */ + __IO uint32_t C2ICR; /*!< HSEM CPU2 interrupt clear register , Address offset: 114h */ + __IO uint32_t C2ISR; /*!< HSEM CPU2 interrupt status register , Address offset: 118h */ + __IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 11Ch */ + uint32_t Reserved[8]; /*!< Reserved Address offset: 120h-13Ch*/ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +/*!< Boundary memory map */ +#define FLASH_BASE (0x08000000UL)/*!< FLASH(up to 1 MB) base address */ +#define SRAM_BASE (0x20000000UL)/*!< SRAM(up to 256 KB) base address */ +#define PERIPH_BASE (0x40000000UL)/*!< Peripheral base address */ + +/*!< Memory, OTP and Option bytes */ + +/* Base addresses */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 0x1FFF8FFF) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ + +#define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 32 KB) base address */ +#define SRAM2A_BASE (SRAM_BASE + 0x00008000UL)/*!< SRAM2A(32 KB) base address */ +#define SRAM2B_BASE (SRAM_BASE + 0x00010000UL)/*!< SRAM2B(32 KB) base address */ + +/* Memory Size */ +#define FLASH_SIZE (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U) +#define SRAM1_SIZE 0x00008000UL /*!< SRAM1 default size : 32 kB */ +#define SRAM2A_SIZE 0x00008000UL /*!< SRAM2a default size : 32 kB */ +#define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ + +/* End addresses */ +#define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 0x20007FFF) */ +#define SRAM2A_END_ADDR (0x2000FFFFUL) /*!< SRAM2a (backup) : 32KB (0x20008000 0x2000FFFF) */ +#define SRAM2B_END_ADDR (0x20017FFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20010000 0x20017FFF) */ + +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) +#define AHB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define APB3PERIPH_BASE (PERIPH_BASE + 0x20000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x50000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x00005C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x00006000UL) +#define USB1_BASE (APB1PERIPH_BASE + 0x00006800UL) +#define USB1_PMAADDR (APB1PERIPH_BASE + 0x00006C00UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x00007C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x00008000UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x00009400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x00000200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x00000204UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x00000800UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x0000006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x00000080UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) + +/*!< AHB2 peripherals */ +#define IOPORT_BASE (AHB2PERIPH_BASE + 0x00000000UL) +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOE_BASE (IOPORT_BASE + 0x00001000UL) +#define GPIOH_BASE (IOPORT_BASE + 0x00001C00UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) + +#define AES1_BASE (AHB2PERIPH_BASE + 0x08060000UL) + +/*!< AHB Shared peripherals */ +#define RCC_BASE (AHB4PERIPH_BASE + 0x00000000UL) +#define PWR_BASE (AHB4PERIPH_BASE + 0x00000400UL) +#define EXTI_BASE (AHB4PERIPH_BASE + 0x00000800UL) +#define IPCC_BASE (AHB4PERIPH_BASE + 0x00000C00UL) +#define RNG_BASE (AHB4PERIPH_BASE + 0x00001000UL) +#define HSEM_BASE (AHB4PERIPH_BASE + 0x00001400UL) +#define AES2_BASE (AHB4PERIPH_BASE + 0x00001800UL) +#define PKA_BASE (AHB4PERIPH_BASE + 0x00002000UL) +#define FLASH_REG_BASE (AHB4PERIPH_BASE + 0x00004000UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + + +/*!< AHB3 peripherals */ +#define QUADSPI_BASE (AHB3PERIPH_BASE + 0x00000000UL) /*!< QUADSPI memories accessible over AHB base address */ +#define QUADSPI_R_BASE (AHB3PERIPH_BASE + 0x10001000UL) /*!< QUADSPI control registers base address */ + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE ((uint32_t)0x1FFF7500UL) /*!< Package data register base address */ +#define UID64_BASE ((uint32_t)0x1FFF7580UL) /*!< 64-bit Unique device Identification */ +#define UID_BASE ((uint32_t)0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +/* Peripherals available on APB1 bus */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define USB ((USB_TypeDef *) USB1_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) + +/* Peripherals available on APB2 bus */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) + +/* Peripherals available on AHB1 bus */ +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define TSC ((TSC_TypeDef *) TSC_BASE) + +/* Peripherals available on AHB2 bus */ +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) + +#define AES1 ((AES_TypeDef *) AES1_BASE) + +/* Peripherals available on AHB shared bus */ +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define IPCC ((IPCC_TypeDef *) IPCC_BASE) +#define IPCC_C1 ((IPCC_CommonTypeDef *) IPCC_BASE) +#define IPCC_C2 ((IPCC_CommonTypeDef *) (IPCC_BASE + 0x10U)) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U)) +#define AES2 ((AES_TypeDef *) AES2_BASE) +#define PKA ((PKA_TypeDef *) PKA_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_REG_BASE) + +/* Peripherals available on AHB3 bus */ +#define QUADSPI ((QUADSPI_TypeDef *) QUADSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_ALIGN_Pos (5U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR_EXTSEL_Pos (6U) +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ + +#define ADC_JSQR_JEXTEN_Pos (6U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ + +#define ADC_JSQR_JSQ1_Pos (8U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ + +#define ADC_JSQR_JSQ2_Pos (14U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (20U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ + +#define ADC_JSQR_JSQ4_Pos (26U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003A0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00000100 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00000200 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00000400 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/* Legacy defines */ +#define ADC_CCR_MULTI (ADC_CCR_DUAL) +#define ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0) +#define ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1) +#define ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2) +#define ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3) +#define ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4) + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ***************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ +#define COMP_CSR_PWRMODE_Pos (2U) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */ +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0x7UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INPSEL_Pos (7U) +#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000180 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_WINMODE_Pos (9U) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_BLANKING_Pos (18U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */ +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */ +#define COMP_CSR_INMESEL_Pos (25U) +#define COMP_CSR_INMESEL_Msk (0x3UL << COMP_CSR_INMESEL_Pos) /*!< 0x06000000 */ +#define COMP_CSR_INMESEL COMP_CSR_INMESEL_Msk /*!< Comparator input minus extended selection */ +#define COMP_CSR_INMESEL_0 (0x1UL << COMP_CSR_INMESEL_Pos) /*!< 0x02000000 */ +#define COMP_CSR_INMESEL_1 (0x2UL << COMP_CSR_INMESEL_Pos) /*!< 0x04000000 */ +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1U << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2U << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ + +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1U << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2U << AES_CR_MODE_Pos) /*!< 0x00000010 */ + +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001U << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002U << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800U << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ + +#define AES_CR_CCFC_Pos (7U) +#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ +#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ +#define AES_CR_ERRC_Pos (8U) +#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ +#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ +#define AES_CR_CCFIE_Pos (9U) +#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */ +#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */ +#define AES_CR_ERRIE_Pos (10U) +#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ +#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ + +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1U << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2U << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ + +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ + +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in last payload block */ +#define AES_CR_NPBLB_0 (0x1U << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2U << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4U << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8U << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* DMAMUX Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMAMUX_CxCR register **************/ +#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ +#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ +#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ +#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ +#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ +#define DMAMUX_CxCR_SOIE_Pos (8U) +#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ +#define DMAMUX_CxCR_EGE_Pos (9U) +#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ +#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ +#define DMAMUX_CxCR_SE_Pos (16U) +#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ +#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ +#define DMAMUX_CxCR_SPOL_Pos (17U) +#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ +#define DMAMUX_CxCR_SPOL_0 (0x1U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_CxCR_SPOL_1 (0x2U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_CxCR_NBREQ_Pos (19U) +#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ +#define DMAMUX_CxCR_NBREQ_0 (0x01U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_CxCR_NBREQ_1 (0x02U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_CxCR_NBREQ_2 (0x04U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_CxCR_NBREQ_3 (0x08U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_CxCR_NBREQ_4 (0x10U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ +#define DMAMUX_CxCR_SYNC_ID_Pos (24U) +#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ +#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ +#define DMAMUX_CxCR_SYNC_ID_0 (0x01U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ +#define DMAMUX_CxCR_SYNC_ID_1 (0x02U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ +#define DMAMUX_CxCR_SYNC_ID_2 (0x04U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ +#define DMAMUX_CxCR_SYNC_ID_3 (0x08U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ +#define DMAMUX_CxCR_SYNC_ID_4 (0x10U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ + +/******************* Bits definition for DMAMUX_CSR register **************/ +#define DMAMUX_CSR_SOF0_Pos (0U) +#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ +#define DMAMUX_CSR_SOF1_Pos (1U) +#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ +#define DMAMUX_CSR_SOF2_Pos (2U) +#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ +#define DMAMUX_CSR_SOF3_Pos (3U) +#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */ +#define DMAMUX_CSR_SOF4_Pos (4U) +#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */ +#define DMAMUX_CSR_SOF5_Pos (5U) +#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */ +#define DMAMUX_CSR_SOF6_Pos (6U) +#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */ +#define DMAMUX_CSR_SOF7_Pos (7U) +#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */ +#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Synchronization Overrun Flag 7 */ +#define DMAMUX_CSR_SOF8_Pos (8U) +#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */ +#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Synchronization Overrun Flag 8 */ +#define DMAMUX_CSR_SOF9_Pos (9U) +#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */ +#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Synchronization Overrun Flag 9 */ +#define DMAMUX_CSR_SOF10_Pos (10U) +#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */ +#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Synchronization Overrun Flag 10 */ +#define DMAMUX_CSR_SOF11_Pos (11U) +#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */ +#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Synchronization Overrun Flag 11 */ +#define DMAMUX_CSR_SOF12_Pos (12U) +#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */ +#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Synchronization Overrun Flag 12 */ +#define DMAMUX_CSR_SOF13_Pos (13U) +#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */ +#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Synchronization Overrun Flag 13 */ + +/******************** Bits definition for DMAMUX_CFR register **************/ +#define DMAMUX_CFR_CSOF0_Pos (0U) +#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ +#define DMAMUX_CFR_CSOF1_Pos (1U) +#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ +#define DMAMUX_CFR_CSOF2_Pos (2U) +#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ +#define DMAMUX_CFR_CSOF3_Pos (3U) +#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */ +#define DMAMUX_CFR_CSOF4_Pos (4U) +#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */ +#define DMAMUX_CFR_CSOF5_Pos (5U) +#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */ +#define DMAMUX_CFR_CSOF6_Pos (6U) +#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */ +#define DMAMUX_CFR_CSOF7_Pos (7U) +#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */ +#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Clear Overrun Flag 7 */ +#define DMAMUX_CFR_CSOF8_Pos (8U) +#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */ +#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Clear Overrun Flag 8 */ +#define DMAMUX_CFR_CSOF9_Pos (9U) +#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */ +#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Clear Overrun Flag 9 */ +#define DMAMUX_CFR_CSOF10_Pos (10U) +#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */ +#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Clear Overrun Flag 10 */ +#define DMAMUX_CFR_CSOF11_Pos (11U) +#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */ +#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Clear Overrun Flag 11 */ +#define DMAMUX_CFR_CSOF12_Pos (12U) +#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */ +#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Clear Overrun Flag 12 */ +#define DMAMUX_CFR_CSOF13_Pos (13U) +#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */ +#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Clear Overrun Flag 13 */ + +/******************** Bits definition for DMAMUX_RGxCR register ************/ +#define DMAMUX_RGxCR_SIG_ID_Pos (0U) +#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ +#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ +#define DMAMUX_RGxCR_SIG_ID_0 (0x01U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGxCR_SIG_ID_1 (0x02U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGxCR_SIG_ID_2 (0x04U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGxCR_SIG_ID_3 (0x08U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGxCR_SIG_ID_4 (0x10U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_RGxCR_OIE_Pos (8U) +#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ +#define DMAMUX_RGxCR_GE_Pos (16U) +#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ +#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ +#define DMAMUX_RGxCR_GPOL_Pos (17U) +#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ +#define DMAMUX_RGxCR_GPOL_0 (0x1U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_RGxCR_GPOL_1 (0x2U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_RGxCR_GNBREQ_Pos (19U) +#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ +#define DMAMUX_RGxCR_GNBREQ_0 (0x01U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_RGxCR_GNBREQ_1 (0x02U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_RGxCR_GNBREQ_2 (0x04U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_RGxCR_GNBREQ_3 (0x08U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_RGxCR_GNBREQ_4 (0x10U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for DMAMUX_RGSR register **************/ +#define DMAMUX_RGSR_OF0_Pos (0U) +#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ +#define DMAMUX_RGSR_OF1_Pos (1U) +#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ +#define DMAMUX_RGSR_OF2_Pos (2U) +#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ +#define DMAMUX_RGSR_OF3_Pos (3U) +#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ + +/******************** Bits definition for DMAMUX_RGCFR register **************/ +#define DMAMUX_RGCFR_COF0_Pos (0U) +#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ +#define DMAMUX_RGCFR_COF1_Pos (1U) +#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ +#define DMAMUX_RGCFR_COF2_Pos (2U) +#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ +#define DMAMUX_RGCFR_COF3_Pos (3U) +#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT_Pos (0U) +#define EXTI_RTSR1_RT_Msk (0x803FFFFFUL << EXTI_RTSR1_RT_Pos) /*!< 0x803FFFFF */ +#define EXTI_RTSR1_RT EXTI_RTSR1_RT_Msk /*!< Rising trigger event configuration bit */ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR1_RT17_Pos (17U) +#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR1_RT18_Pos (18U) +#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR1_RT19_Pos (19U) +#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */ +#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR1_RT20_Pos (20U) +#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */ +#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_RTSR1_RT21_Pos (21U) +#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */ +#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_RTSR1_RT31_Pos (31U) +#define EXTI_RTSR1_RT31_Msk (0x1UL << EXTI_RTSR1_RT31_Pos) /*!< 0x80000000 */ +#define EXTI_RTSR1_RT31 EXTI_RTSR1_RT31_Msk /*!< Rising trigger event configuration bit of line 31 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT_Pos (0U) +#define EXTI_FTSR1_FT_Msk (0x803FFFFFUL << EXTI_FTSR1_FT_Pos) /*!< 0x803FFFFF */ +#define EXTI_FTSR1_FT EXTI_FTSR1_FT_Msk /*!< Falling trigger event configuration bit */ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR1_FT17_Pos (17U) +#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR1_FT18_Pos (18U) +#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR1_FT19_Pos (19U) +#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */ +#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR1_FT20_Pos (20U) +#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */ +#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_FTSR1_FT21_Pos (21U) +#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */ +#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ +#define EXTI_FTSR1_FT31_Pos (31U) +#define EXTI_FTSR1_FT31_Msk (0x1UL << EXTI_FTSR1_FT31_Pos) /*!< 0x80000000 */ +#define EXTI_FTSR1_FT31 EXTI_FTSR1_FT31_Msk /*!< Falling trigger event configuration bit of line 31 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI_Pos (0U) +#define EXTI_SWIER1_SWI_Msk (0x803FFFFFUL << EXTI_SWIER1_SWI_Pos) /*!< 0x803FFFFF */ +#define EXTI_SWIER1_SWI EXTI_SWIER1_SWI_Msk /*!< Software interrupt */ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER1_SWI17_Pos (17U) +#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER1_SWI18_Pos (18U) +#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER1_SWI19_Pos (19U) +#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */ +#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER1_SWI20_Pos (20U) +#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */ +#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */ +#define EXTI_SWIER1_SWI21_Pos (21U) +#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */ +#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */ +#define EXTI_SWIER1_SWI31_Pos (31U) +#define EXTI_SWIER1_SWI31_Msk (0x1UL << EXTI_SWIER1_SWI31_Pos) /*!< 0x80000000 */ +#define EXTI_SWIER1_SWI31 EXTI_SWIER1_SWI31_Msk /*!< Software Interrupt on line 31 */ + +/******************* Bit definition for EXTI_PR1 register *******************/ +#define EXTI_PR1_PIF_Pos (0U) +#define EXTI_PR1_PIF_Msk (0x803FFFFFUL << EXTI_PR1_PIF_Pos) /*!< 0x803FFFFF */ +#define EXTI_PR1_PIF EXTI_PR1_PIF_Msk /*!< Pending bit */ +#define EXTI_PR1_PIF0_Pos (0U) +#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */ +#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */ +#define EXTI_PR1_PIF1_Pos (1U) +#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */ +#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */ +#define EXTI_PR1_PIF2_Pos (2U) +#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */ +#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */ +#define EXTI_PR1_PIF3_Pos (3U) +#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */ +#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */ +#define EXTI_PR1_PIF4_Pos (4U) +#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */ +#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */ +#define EXTI_PR1_PIF5_Pos (5U) +#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */ +#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */ +#define EXTI_PR1_PIF6_Pos (6U) +#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */ +#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */ +#define EXTI_PR1_PIF7_Pos (7U) +#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */ +#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */ +#define EXTI_PR1_PIF8_Pos (8U) +#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */ +#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */ +#define EXTI_PR1_PIF9_Pos (9U) +#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */ +#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */ +#define EXTI_PR1_PIF10_Pos (10U) +#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */ +#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */ +#define EXTI_PR1_PIF11_Pos (11U) +#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */ +#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */ +#define EXTI_PR1_PIF12_Pos (12U) +#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */ +#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */ +#define EXTI_PR1_PIF13_Pos (13U) +#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */ +#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */ +#define EXTI_PR1_PIF14_Pos (14U) +#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */ +#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */ +#define EXTI_PR1_PIF15_Pos (15U) +#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */ +#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */ +#define EXTI_PR1_PIF16_Pos (16U) +#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */ +#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */ +#define EXTI_PR1_PIF17_Pos (17U) +#define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */ +#define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */ +#define EXTI_PR1_PIF18_Pos (18U) +#define EXTI_PR1_PIF18_Msk (0x1UL << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */ +#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */ +#define EXTI_PR1_PIF19_Pos (19U) +#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */ +#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */ +#define EXTI_PR1_PIF20_Pos (20U) +#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */ +#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */ +#define EXTI_PR1_PIF21_Pos (21U) +#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */ +#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */ +#define EXTI_PR1_PIF31_Pos (31U) +#define EXTI_PR1_PIF31_Msk (0x1UL << EXTI_PR1_PIF31_Pos) /*!< 0x80000000 */ +#define EXTI_PR1_PIF31 EXTI_PR1_PIF31_Msk /*!< Pending bit for line 31 */ + +/****************** Bit definition for EXTI_RTSR2 register ******************/ +#define EXTI_RTSR2_RT_Pos (0U) +#define EXTI_RTSR2_RT_Msk (0x302UL << EXTI_RTSR2_RT_Pos) /*!< 0x00000302 */ +#define EXTI_RTSR2_RT EXTI_RTSR2_RT_Msk /*!< Rising trigger event configuration bit */ +#define EXTI_RTSR2_RT33_Pos (1U) +#define EXTI_RTSR2_RT33_Msk (0x1UL << EXTI_RTSR2_RT33_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR2_RT33 EXTI_RTSR2_RT33_Msk /*!< Rising trigger event configuration bit of line 33 */ +#define EXTI_RTSR2_RT40_Pos (8U) +#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */ +#define EXTI_RTSR2_RT41_Pos (9U) +#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */ + +/****************** Bit definition for EXTI_FTSR2 register ******************/ +#define EXTI_FTSR2_FT_Pos (0U) +#define EXTI_FTSR2_FT_Msk (0x302UL << EXTI_FTSR2_FT_Pos) /*!< 0x00000302 */ +#define EXTI_FTSR2_FT EXTI_FTSR2_FT_Msk /*!< Falling trigger event configuration bit */ +#define EXTI_FTSR2_FT33_Pos (1U) +#define EXTI_FTSR2_FT33_Msk (0x1UL << EXTI_FTSR2_FT33_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR2_FT33 EXTI_FTSR2_FT33_Msk /*!< Falling trigger event configuration bit of line 33 */ +#define EXTI_FTSR2_FT40_Pos (8U) +#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */ +#define EXTI_FTSR2_FT41_Pos (9U) +#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */ + +/****************** Bit definition for EXTI_SWIER2 register *****************/ +#define EXTI_SWIER2_SWI_Pos (0U) +#define EXTI_SWIER2_SWI_Msk (0x302UL << EXTI_SWIER2_SWI_Pos) /*!< 0x00000302 */ +#define EXTI_SWIER2_SWI EXTI_SWIER2_SWI_Msk /*!< Falling trigger event configuration bit */ +#define EXTI_SWIER2_SWI33_Pos (1U) +#define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */ +#define EXTI_SWIER2_SWI40_Pos (8U) +#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */ +#define EXTI_SWIER2_SWI41_Pos (9U) +#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */ + +/******************* Bit definition for EXTI_PR2 register *******************/ +#define EXTI_PR2_PIF_Pos (0U) +#define EXTI_PR2_PIF_Msk (0x302UL << EXTI_PR2_PIF_Pos) /*!< 0x00000302 */ +#define EXTI_PR2_PIF EXTI_PR2_PIF_Msk /*!< Pending bit */ +#define EXTI_PR2_PIF33_Pos (1U) +#define EXTI_PR2_PIF33_Msk (0x1UL << EXTI_PR2_PIF33_Pos) /*!< 0x00000002 */ +#define EXTI_PR2_PIF33 EXTI_PR2_PIF33_Msk /*!< Pending bit for line 33 */ +#define EXTI_PR2_PIF40_Pos (8U) +#define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */ +#define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */ +#define EXTI_PR2_PIF41_Pos (9U) +#define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */ +#define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */ + +/******************** Bits definition for EXTI_IMR1 register ****************/ +#define EXTI_IMR1_Pos (0U) +#define EXTI_IMR1_Msk (0xFFFFFFFFUL << EXTI_IMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_IMR1_IM EXTI_IMR1_Msk /*!< CPU1 wakeup with interrupt Mask on Event */ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU1 Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU1 Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU1 Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU1 Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU1 Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU1 Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU1 Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU1 Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU1 Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU1 Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU1 Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU1 Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU1 Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU1 Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU1 Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU1 Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU1 Interrupt Mask on line 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU1 Interrupt Mask on line 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU1 Interrupt Mask on line 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU1 Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< CPU1 Interrupt Mask on line 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< CPU1 Interrupt Mask on line 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU1 Interrupt Mask on line 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< CPU1 Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU1 Interrupt Mask on line 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU1 Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU1 Interrupt Mask on line 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU1 Interrupt Mask on line 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU1 Interrupt Mask on line 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< CPU1 Interrupt Mask on line 31 */ + +/******************** Bits definition for EXTI_EMR1 register ****************/ +#define EXTI_EMR1_Pos (0U) +#define EXTI_EMR1_Msk (0x003EFFFFUL << EXTI_EMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_EMR1_EM EXTI_EMR1_Msk /*!< CPU1 Event Mask */ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU1 Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU1 Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU1 Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU1 Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU1 Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU1 Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU1 Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU1 Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU1 Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU1 Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU1 Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU1 Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU1 Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU1 Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU1 Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU1 Event Mask on line 15 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU1 Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< CPU1 Event Mask on line 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU1 Event Mask on line 19 */ +#define EXTI_EMR1_EM20_Pos (20U) +#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< CPU1 Event Mask on line 20 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< CPU1 Event Mask on line 21 */ + +/******************** Bits definition for EXTI_IMR2 register ****************/ +#define EXTI_IMR2_Pos (0U) +#define EXTI_IMR2_Msk (0x0001FFFFUL << EXTI_IMR2_Pos) /*!< 0x0001FFFF */ +#define EXTI_IMR2_IM EXTI_IMR2_Msk /*!< CPU1 Interrupt Mask */ +#define EXTI_IMR2_IM33_Pos (1U) +#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU1 Interrupt Mask on line 33 */ +#define EXTI_IMR2_IM36_Pos (4U) +#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */ +#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< CPU1 Interrupt Mask on line 36 */ +#define EXTI_IMR2_IM37_Pos (5U) +#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */ +#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< CPU1 Interrupt Mask on line 37 */ +#define EXTI_IMR2_IM38_Pos (6U) +#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */ +#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< CPU1 Interrupt Mask on line 38 */ +#define EXTI_IMR2_IM39_Pos (7U) +#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */ +#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< CPU1 Interrupt Mask on line 39 */ +#define EXTI_IMR2_IM40_Pos (8U) +#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */ +#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< CPU1 Interrupt Mask on line 40 */ +#define EXTI_IMR2_IM41_Pos (9U) +#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */ +#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< CPU1 Interrupt Mask on line 41 */ +#define EXTI_IMR2_IM42_Pos (10U) +#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */ +#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< CPU1 Interrupt Mask on line 42 */ +#define EXTI_IMR2_IM44_Pos (12U) +#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */ +#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< CPU1 Interrupt Mask on line 44 */ +#define EXTI_IMR2_IM45_Pos (13U) +#define EXTI_IMR2_IM45_Msk (0x1UL << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */ +#define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< CPU1 Interrupt Mask on line 45 */ +#define EXTI_IMR2_IM46_Pos (14U) +#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */ +#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< CPU1 Interrupt Mask on line 46 */ +#define EXTI_IMR2_IM48_Pos (16U) +#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */ +#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< CPU1 Interrupt Mask on line 48 */ + +/******************** Bits definition for EXTI_EMR2 register ****************/ +#define EXTI_EMR2_Pos (0U) +#define EXTI_EMR2_Msk (0x00000300UL << EXTI_EMR2_Pos) /*!< 0x000003000 */ +#define EXTI_EMR2_EM EXTI_EMR2_Msk /*!< CPU1 Interrupt Mask */ +#define EXTI_EMR2_EM40_Pos (8U) +#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */ +#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< CPU1 Event Mask on line 40 */ +#define EXTI_EMR2_EM41_Pos (9U) +#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */ +#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< CPU1 Event Mask on line 41 */ + +/******************** Bits definition for EXTI_C2IMR1 register **************/ +#define EXTI_C2IMR1_Pos (0U) +#define EXTI_C2IMR1_Msk (0xFFFFFFFFUL << EXTI_C2IMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_C2IMR1_IM EXTI_C2IMR1_Msk /*!< CPU2 wakeup with interrupt Mask on Event */ +#define EXTI_C2IMR1_IM0_Pos (0U) +#define EXTI_C2IMR1_IM0_Msk (0x1UL << EXTI_C2IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_C2IMR1_IM0 EXTI_C2IMR1_IM0_Msk /*!< CPU2 Interrupt Mask on line 0 */ +#define EXTI_C2IMR1_IM1_Pos (1U) +#define EXTI_C2IMR1_IM1_Msk (0x1UL << EXTI_C2IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_C2IMR1_IM1 EXTI_C2IMR1_IM1_Msk /*!< CPU2 Interrupt Mask on line 1 */ +#define EXTI_C2IMR1_IM2_Pos (2U) +#define EXTI_C2IMR1_IM2_Msk (0x1UL << EXTI_C2IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_C2IMR1_IM2 EXTI_C2IMR1_IM2_Msk /*!< CPU2 Interrupt Mask on line 2 */ +#define EXTI_C2IMR1_IM3_Pos (3U) +#define EXTI_C2IMR1_IM3_Msk (0x1UL << EXTI_C2IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_C2IMR1_IM3 EXTI_C2IMR1_IM3_Msk /*!< CPU2 Interrupt Mask on line 3 */ +#define EXTI_C2IMR1_IM4_Pos (4U) +#define EXTI_C2IMR1_IM4_Msk (0x1UL << EXTI_C2IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_C2IMR1_IM4 EXTI_C2IMR1_IM4_Msk /*!< CPU2 Interrupt Mask on line 4 */ +#define EXTI_C2IMR1_IM5_Pos (5U) +#define EXTI_C2IMR1_IM5_Msk (0x1UL << EXTI_C2IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_C2IMR1_IM5 EXTI_C2IMR1_IM5_Msk /*!< CPU2 Interrupt Mask on line 5 */ +#define EXTI_C2IMR1_IM6_Pos (6U) +#define EXTI_C2IMR1_IM6_Msk (0x1UL << EXTI_C2IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_C2IMR1_IM6 EXTI_C2IMR1_IM6_Msk /*!< CPU2 Interrupt Mask on line 6 */ +#define EXTI_C2IMR1_IM7_Pos (7U) +#define EXTI_C2IMR1_IM7_Msk (0x1UL << EXTI_C2IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_C2IMR1_IM7 EXTI_C2IMR1_IM7_Msk /*!< CPU2 Interrupt Mask on line 7 */ +#define EXTI_C2IMR1_IM8_Pos (8U) +#define EXTI_C2IMR1_IM8_Msk (0x1UL << EXTI_C2IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_C2IMR1_IM8 EXTI_C2IMR1_IM8_Msk /*!< CPU2 Interrupt Mask on line 8 */ +#define EXTI_C2IMR1_IM9_Pos (9U) +#define EXTI_C2IMR1_IM9_Msk (0x1UL << EXTI_C2IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_C2IMR1_IM9 EXTI_C2IMR1_IM9_Msk /*!< CPU2 Interrupt Mask on line 9 */ +#define EXTI_C2IMR1_IM10_Pos (10U) +#define EXTI_C2IMR1_IM10_Msk (0x1UL << EXTI_C2IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_C2IMR1_IM10 EXTI_C2IMR1_IM10_Msk /*!< CPU2 Interrupt Mask on line 10 */ +#define EXTI_C2IMR1_IM11_Pos (11U) +#define EXTI_C2IMR1_IM11_Msk (0x1UL << EXTI_C2IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_C2IMR1_IM11 EXTI_C2IMR1_IM11_Msk /*!< CPU2 Interrupt Mask on line 11 */ +#define EXTI_C2IMR1_IM12_Pos (12U) +#define EXTI_C2IMR1_IM12_Msk (0x1UL << EXTI_C2IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_C2IMR1_IM12 EXTI_C2IMR1_IM12_Msk /*!< CPU2 Interrupt Mask on line 12 */ +#define EXTI_C2IMR1_IM13_Pos (13U) +#define EXTI_C2IMR1_IM13_Msk (0x1UL << EXTI_C2IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_C2IMR1_IM13 EXTI_C2IMR1_IM13_Msk /*!< CPU2 Interrupt Mask on line 13 */ +#define EXTI_C2IMR1_IM14_Pos (14U) +#define EXTI_C2IMR1_IM14_Msk (0x1UL << EXTI_C2IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_C2IMR1_IM14 EXTI_C2IMR1_IM14_Msk /*!< CPU2 Interrupt Mask on line 14 */ +#define EXTI_C2IMR1_IM15_Pos (15U) +#define EXTI_C2IMR1_IM15_Msk (0x1UL << EXTI_C2IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_C2IMR1_IM15 EXTI_C2IMR1_IM15_Msk /*!< CPU2 Interrupt Mask on line 15 */ +#define EXTI_C2IMR1_IM16_Pos (16U) +#define EXTI_C2IMR1_IM16_Msk (0x1UL << EXTI_C2IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_C2IMR1_IM16 EXTI_C2IMR1_IM16_Msk /*!< CPU2 Interrupt Mask on line 16 */ +#define EXTI_C2IMR1_IM17_Pos (17U) +#define EXTI_C2IMR1_IM17_Msk (0x1UL << EXTI_C2IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_C2IMR1_IM17 EXTI_C2IMR1_IM17_Msk /*!< CPU2 Interrupt Mask on line 17 */ +#define EXTI_C2IMR1_IM18_Pos (18U) +#define EXTI_C2IMR1_IM18_Msk (0x1UL << EXTI_C2IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_C2IMR1_IM18 EXTI_C2IMR1_IM18_Msk /*!< CPU2 Interrupt Mask on line 18 */ +#define EXTI_C2IMR1_IM19_Pos (19U) +#define EXTI_C2IMR1_IM19_Msk (0x1UL << EXTI_C2IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_C2IMR1_IM19 EXTI_C2IMR1_IM19_Msk /*!< CPU2 Interrupt Mask on line 19 */ +#define EXTI_C2IMR1_IM20_Pos (20U) +#define EXTI_C2IMR1_IM20_Msk (0x1UL << EXTI_C2IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_C2IMR1_IM20 EXTI_C2IMR1_IM20_Msk /*!< CPU2 Interrupt Mask on line 20 */ +#define EXTI_C2IMR1_IM21_Pos (21U) +#define EXTI_C2IMR1_IM21_Msk (0x1UL << EXTI_C2IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_C2IMR1_IM21 EXTI_C2IMR1_IM21_Msk /*!< CPU2 Interrupt Mask on line 21 */ +#define EXTI_C2IMR1_IM22_Pos (22U) +#define EXTI_C2IMR1_IM22_Msk (0x1UL << EXTI_C2IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_C2IMR1_IM22 EXTI_C2IMR1_IM22_Msk /*!< CPU2 Interrupt Mask on line 22 */ +#define EXTI_C2IMR1_IM23_Pos (23U) +#define EXTI_C2IMR1_IM23_Msk (0x1UL << EXTI_C2IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_C2IMR1_IM23 EXTI_C2IMR1_IM23_Msk /*!< CPU2 Interrupt Mask on line 23 */ +#define EXTI_C2IMR1_IM24_Pos (24U) +#define EXTI_C2IMR1_IM24_Msk (0x1UL << EXTI_C2IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_C2IMR1_IM24 EXTI_C2IMR1_IM24_Msk /*!< CPU2 Interrupt Mask on line 24 */ +#define EXTI_C2IMR1_IM25_Pos (25U) +#define EXTI_C2IMR1_IM25_Msk (0x1UL << EXTI_C2IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_C2IMR1_IM25 EXTI_C2IMR1_IM25_Msk /*!< CPU2 Interrupt Mask on line 25 */ +#define EXTI_C2IMR1_IM28_Pos (28U) +#define EXTI_C2IMR1_IM28_Msk (0x1UL << EXTI_C2IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_C2IMR1_IM28 EXTI_C2IMR1_IM28_Msk /*!< CPU2 Interrupt Mask on line 28 */ +#define EXTI_C2IMR1_IM29_Pos (29U) +#define EXTI_C2IMR1_IM29_Msk (0x1UL << EXTI_C2IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_C2IMR1_IM29 EXTI_C2IMR1_IM29_Msk /*!< CPU2 Interrupt Mask on line 29 */ +#define EXTI_C2IMR1_IM30_Pos (30U) +#define EXTI_C2IMR1_IM30_Msk (0x1UL << EXTI_C2IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_C2IMR1_IM30 EXTI_C2IMR1_IM30_Msk /*!< CPU2 Interrupt Mask on line 30 */ +#define EXTI_C2IMR1_IM31_Pos (31U) +#define EXTI_C2IMR1_IM31_Msk (0x1UL << EXTI_C2IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_C2IMR1_IM31 EXTI_C2IMR1_IM31_Msk /*!< CPU2 Interrupt Mask on line 31 */ +/******************** Bits definition for EXTI_C2EMR1 register **************/ +#define EXTI_C2EMR1_Pos (0U) +#define EXTI_C2EMR1_Msk (0x003EFFFFUL << EXTI_C2EMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_C2EMR1_EM EXTI_C2EMR1_Msk /*!< CPU2 Event Mask */ +#define EXTI_C2EMR1_EM0_Pos (0U) +#define EXTI_C2EMR1_EM0_Msk (0x1UL << EXTI_C2EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_C2EMR1_EM0 EXTI_C2EMR1_EM0_Msk /*!< CPU2 Event Mask on line 0 */ +#define EXTI_C2EMR1_EM1_Pos (1U) +#define EXTI_C2EMR1_EM1_Msk (0x1UL << EXTI_C2EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_C2EMR1_EM1 EXTI_C2EMR1_EM1_Msk /*!< CPU2 Event Mask on line 1 */ +#define EXTI_C2EMR1_EM2_Pos (2U) +#define EXTI_C2EMR1_EM2_Msk (0x1UL << EXTI_C2EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_C2EMR1_EM2 EXTI_C2EMR1_EM2_Msk /*!< CPU2 Event Mask on line 2 */ +#define EXTI_C2EMR1_EM3_Pos (3U) +#define EXTI_C2EMR1_EM3_Msk (0x1UL << EXTI_C2EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_C2EMR1_EM3 EXTI_C2EMR1_EM3_Msk /*!< CPU2 Event Mask on line 3 */ +#define EXTI_C2EMR1_EM4_Pos (4U) +#define EXTI_C2EMR1_EM4_Msk (0x1UL << EXTI_C2EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_C2EMR1_EM4 EXTI_C2EMR1_EM4_Msk /*!< CPU2 Event Mask on line 4 */ +#define EXTI_C2EMR1_EM5_Pos (5U) +#define EXTI_C2EMR1_EM5_Msk (0x1UL << EXTI_C2EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_C2EMR1_EM5 EXTI_C2EMR1_EM5_Msk /*!< CPU2 Event Mask on line 5 */ +#define EXTI_C2EMR1_EM6_Pos (6U) +#define EXTI_C2EMR1_EM6_Msk (0x1UL << EXTI_C2EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_C2EMR1_EM6 EXTI_C2EMR1_EM6_Msk /*!< CPU2 Event Mask on line 6 */ +#define EXTI_C2EMR1_EM7_Pos (7U) +#define EXTI_C2EMR1_EM7_Msk (0x1UL << EXTI_C2EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_C2EMR1_EM7 EXTI_C2EMR1_EM7_Msk /*!< CPU2 Event Mask on line 7 */ +#define EXTI_C2EMR1_EM8_Pos (8U) +#define EXTI_C2EMR1_EM8_Msk (0x1UL << EXTI_C2EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_C2EMR1_EM8 EXTI_C2EMR1_EM8_Msk /*!< CPU2 Event Mask on line 8 */ +#define EXTI_C2EMR1_EM9_Pos (9U) +#define EXTI_C2EMR1_EM9_Msk (0x1UL << EXTI_C2EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_C2EMR1_EM9 EXTI_C2EMR1_EM9_Msk /*!< CPU2 Event Mask on line 9 */ +#define EXTI_C2EMR1_EM10_Pos (10U) +#define EXTI_C2EMR1_EM10_Msk (0x1UL << EXTI_C2EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_C2EMR1_EM10 EXTI_C2EMR1_EM10_Msk /*!< CPU2 Event Mask on line 10 */ +#define EXTI_C2EMR1_EM11_Pos (11U) +#define EXTI_C2EMR1_EM11_Msk (0x1UL << EXTI_C2EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_C2EMR1_EM11 EXTI_C2EMR1_EM11_Msk /*!< CPU2 Event Mask on line 11 */ +#define EXTI_C2EMR1_EM12_Pos (12U) +#define EXTI_C2EMR1_EM12_Msk (0x1UL << EXTI_C2EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_C2EMR1_EM12 EXTI_C2EMR1_EM12_Msk /*!< CPU2 Event Mask on line 12 */ +#define EXTI_C2EMR1_EM13_Pos (13U) +#define EXTI_C2EMR1_EM13_Msk (0x1UL << EXTI_C2EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_C2EMR1_EM13 EXTI_C2EMR1_EM13_Msk /*!< CPU2 Event Mask on line 13 */ +#define EXTI_C2EMR1_EM14_Pos (14U) +#define EXTI_C2EMR1_EM14_Msk (0x1UL << EXTI_C2EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_C2EMR1_EM14 EXTI_C2EMR1_EM14_Msk /*!< CPU2 Event Mask on line 14 */ +#define EXTI_C2EMR1_EM15_Pos (15U) +#define EXTI_C2EMR1_EM15_Msk (0x1UL << EXTI_C2EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_C2EMR1_EM15 EXTI_C2EMR1_EM15_Msk /*!< CPU2 Event Mask on line 15 */ +#define EXTI_C2EMR1_EM17_Pos (17U) +#define EXTI_C2EMR1_EM17_Msk (0x1UL << EXTI_C2EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_C2EMR1_EM17 EXTI_C2EMR1_EM17_Msk /*!< CPU2 Event Mask on line 17 */ +#define EXTI_C2EMR1_EM18_Pos (18U) +#define EXTI_C2EMR1_EM18_Msk (0x1UL << EXTI_C2EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_C2EMR1_EM18 EXTI_C2EMR1_EM18_Msk /*!< CPU2 Event Mask on line 18 */ +#define EXTI_C2EMR1_EM19_Pos (19U) +#define EXTI_C2EMR1_EM19_Msk (0x1UL << EXTI_C2EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_C2EMR1_EM19 EXTI_C2EMR1_EM19_Msk /*!< CPU2 Event Mask on line 19 */ +#define EXTI_C2EMR1_EM20_Pos (20U) +#define EXTI_C2EMR1_EM20_Msk (0x1UL << EXTI_C2EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_C2EMR1_EM20 EXTI_C2EMR1_EM20_Msk /*!< CPU2 Event Mask on line 20 */ +#define EXTI_C2EMR1_EM21_Pos (21U) +#define EXTI_C2EMR1_EM21_Msk (0x1UL << EXTI_C2EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_C2EMR1_EM21 EXTI_C2EMR1_EM21_Msk /*!< CPU2 Event Mask on line 21 */ + +/******************** Bits definition for EXTI_C2IMR2 register **************/ +#define EXTI_C2IMR2_Pos (0U) +#define EXTI_C2IMR2_Msk (0x0001FFFFUL << EXTI_C2IMR2_Pos) /*!< 0x0001FFFF */ +#define EXTI_C2IMR2_IM EXTI_C2IMR2_Msk /*!< CPU2 Interrupt Mask */ +#define EXTI_C2IMR2_IM33_Pos (1U) +#define EXTI_C2IMR2_IM33_Msk (0x1UL << EXTI_C2IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_C2IMR2_IM33 EXTI_C2IMR2_IM33_Msk /*!< CPU2 Interrupt Mask on line 33 */ +#define EXTI_C2IMR2_IM36_Pos (4U) +#define EXTI_C2IMR2_IM36_Msk (0x1UL << EXTI_C2IMR2_IM36_Pos) /*!< 0x00000010 */ +#define EXTI_C2IMR2_IM36 EXTI_C2IMR2_IM36_Msk /*!< CPU2 Interrupt Mask on line 36 */ +#define EXTI_C2IMR2_IM37_Pos (5U) +#define EXTI_C2IMR2_IM37_Msk (0x1UL << EXTI_C2IMR2_IM37_Pos) /*!< 0x00000020 */ +#define EXTI_C2IMR2_IM37 EXTI_C2IMR2_IM37_Msk /*!< CPU2 Interrupt Mask on line 37 */ +#define EXTI_C2IMR2_IM38_Pos (6U) +#define EXTI_C2IMR2_IM38_Msk (0x1UL << EXTI_C2IMR2_IM38_Pos) /*!< 0x00000040 */ +#define EXTI_C2IMR2_IM38 EXTI_C2IMR2_IM38_Msk /*!< CPU2 Interrupt Mask on line 38 */ +#define EXTI_C2IMR2_IM39_Pos (7U) +#define EXTI_C2IMR2_IM39_Msk (0x1UL << EXTI_C2IMR2_IM39_Pos) /*!< 0x00000080 */ +#define EXTI_C2IMR2_IM39 EXTI_C2IMR2_IM39_Msk /*!< CPU2 Interrupt Mask on line 39 */ +#define EXTI_C2IMR2_IM40_Pos (8U) +#define EXTI_C2IMR2_IM40_Msk (0x1UL << EXTI_C2IMR2_IM40_Pos) /*!< 0x00000100 */ +#define EXTI_C2IMR2_IM40 EXTI_C2IMR2_IM40_Msk /*!< CPU2 Interrupt Mask on line 40 */ +#define EXTI_C2IMR2_IM41_Pos (9U) +#define EXTI_C2IMR2_IM41_Msk (0x1UL << EXTI_C2IMR2_IM41_Pos) /*!< 0x00000200 */ +#define EXTI_C2IMR2_IM41 EXTI_C2IMR2_IM41_Msk /*!< CPU2 Interrupt Mask on line 41 */ +#define EXTI_C2IMR2_IM42_Pos (10U) +#define EXTI_C2IMR2_IM42_Msk (0x1UL << EXTI_C2IMR2_IM42_Pos) /*!< 0x00000400 */ +#define EXTI_C2IMR2_IM42 EXTI_C2IMR2_IM42_Msk /*!< CPU2 Interrupt Mask on line 42 */ +#define EXTI_C2IMR2_IM44_Pos (12U) +#define EXTI_C2IMR2_IM44_Msk (0x1UL << EXTI_C2IMR2_IM44_Pos) /*!< 0x00001000 */ +#define EXTI_C2IMR2_IM44 EXTI_C2IMR2_IM44_Msk /*!< CPU2 Interrupt Mask on line 44 */ +#define EXTI_C2IMR2_IM45_Pos (13U) +#define EXTI_C2IMR2_IM45_Msk (0x1UL << EXTI_C2IMR2_IM45_Pos) /*!< 0x00002000 */ +#define EXTI_C2IMR2_IM45 EXTI_C2IMR2_IM45_Msk /*!< CPU2 Interrupt Mask on line 45 */ +#define EXTI_C2IMR2_IM46_Pos (14U) +#define EXTI_C2IMR2_IM46_Msk (0x1UL << EXTI_C2IMR2_IM46_Pos) /*!< 0x00004000 */ +#define EXTI_C2IMR2_IM46 EXTI_C2IMR2_IM46_Msk /*!< CPU2 Interrupt Mask on line 46 */ +#define EXTI_C2IMR2_IM48_Pos (16U) +#define EXTI_C2IMR2_IM48_Msk (0x1UL << EXTI_C2IMR2_IM48_Pos) /*!< 0x00010000 */ +#define EXTI_C2IMR2_IM48 EXTI_C2IMR2_IM48_Msk /*!< CPU2 Interrupt Mask on line 48 */ + +/******************** Bits definition for EXTI_C2EMR2 register **************/ +#define EXTI_C2EMR2_Pos (8U) +#define EXTI_C2EMR2_Msk (0x00000300UL << EXTI_C2EMR2_Pos) /*!< 0x000003000 */ +#define EXTI_C2EMR2_EM EXTI_C2EMR2_Msk /*!< CPU2 Interrupt Mask */ +#define EXTI_C2EMR2_EM40_Pos (8U) +#define EXTI_C2EMR2_EM40_Msk (0x1UL << EXTI_C2EMR2_EM40_Pos) /*!< 0x00000100 */ +#define EXTI_C2EMR2_EM40 EXTI_C2EMR2_EM40_Msk /*!< CPU2 Event Mask on line 40 */ +#define EXTI_C2EMR2_EM41_Pos (9U) +#define EXTI_C2EMR2_EM41_Msk (0x1UL << EXTI_C2EMR2_EM41_Pos) /*!< 0x00000200 */ +#define EXTI_C2EMR2_EM41 EXTI_C2EMR2_EM41_Msk /*!< CPU2 Event Mask on line 41 */ + +/******************************************************************************/ +/* */ +/* Public Key Accelerator (PKA) */ +/* */ +/******************************************************************************/ + +/******************* Bits definition for PKA_CR register **************/ +#define PKA_CR_EN_Pos (0U) +#define PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos) /*!< 0x00000001 */ +#define PKA_CR_EN PKA_CR_EN_Msk /*!< PKA enable */ +#define PKA_CR_START_Pos (1U) +#define PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos) /*!< 0x00000002 */ +#define PKA_CR_START PKA_CR_START_Msk /*!< Start operation */ +#define PKA_CR_MODE_Pos (8U) +#define PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos) /*!< 0x00003F00 */ +#define PKA_CR_MODE PKA_CR_MODE_Msk /*!< MODE[5:0] PKA operation code */ +#define PKA_CR_MODE_0 (0x01U << PKA_CR_MODE_Pos) /*!< 0x00000100 */ +#define PKA_CR_MODE_1 (0x02U << PKA_CR_MODE_Pos) /*!< 0x00000200 */ +#define PKA_CR_MODE_2 (0x04U << PKA_CR_MODE_Pos) /*!< 0x00000400 */ +#define PKA_CR_MODE_3 (0x08U << PKA_CR_MODE_Pos) /*!< 0x00000800 */ +#define PKA_CR_MODE_4 (0x10U << PKA_CR_MODE_Pos) /*!< 0x00001000 */ +#define PKA_CR_MODE_5 (0x20U << PKA_CR_MODE_Pos) /*!< 0x00002000 */ +#define PKA_CR_PROCENDIE_Pos (17U) +#define PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos) /*!< 0x00020000 */ +#define PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk /*!< End of operation interrupt enable */ +#define PKA_CR_RAMERRIE_Pos (19U) +#define PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos) /*!< 0x00080000 */ +#define PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk /*!< RAM error interrupt enable */ +#define PKA_CR_ADDRERRIE_Pos (20U) +#define PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos) /*!< 0x00100000 */ +#define PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk /*!< RAM error interrupt enable */ + +/******************* Bits definition for PKA_SR register **************/ +#define PKA_SR_BUSY_Pos (16U) +#define PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos) /*!< 0x00010000 */ +#define PKA_SR_BUSY PKA_SR_BUSY_Msk /*!< PKA operation is in progress */ +#define PKA_SR_PROCENDF_Pos (17U) +#define PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos) /*!< 0x00020000 */ +#define PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk /*!< PKA end of operation flag */ +#define PKA_SR_RAMERRF_Pos (19U) +#define PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos) /*!< 0x00080000 */ +#define PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk /*!< PKA RAM error flag */ +#define PKA_SR_ADDRERRF_Pos (20U) +#define PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos) /*!< 0x00100000 */ +#define PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk /*!< Address error flag */ + +/******************* Bits definition for PKA_CLRFR register **************/ +#define PKA_CLRFR_PROCENDFC_Pos (17U) +#define PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos) /*!< 0x00020000 */ +#define PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk /*!< Clear PKA end of operation flag */ +#define PKA_CLRFR_RAMERRFC_Pos (19U) +#define PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos) /*!< 0x00080000 */ +#define PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk /*!< Clear PKA RAM error flag */ +#define PKA_CLRFR_ADDRERRFC_Pos (20U) +#define PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos) /*!< 0x00100000 */ +#define PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk /*!< Clear address error flag */ + +/******************* Bits definition for PKA RAM *************************/ +#define PKA_RAM_OFFSET 0x400U /*!< PKA RAM address offset */ + +/* Compute Montgomery parameter input data */ +#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 1 */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 2 */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 3 */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Output last double X1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output last double Y1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2) /*!< Output last double Z1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2) /*!< Output check point X2 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2) /*!< Output check point Y2 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2) /*!< Output check point Z2 coordinate */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2) /*!< Output final point kP X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2) /*!< Output final point kP Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic substraction input data */ +#define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic substraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular substraction input data */ +#define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular substraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk /*!< Instruction cache enable */ +#define FLASH_ACR_DCEN_Pos (10U) +#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ +#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk /*!< Data cache enable */ +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk /*!< Instruction cache reset */ +#define FLASH_ACR_DCRST_Pos (12U) +#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk /*!< Data cache reset */ +#define FLASH_ACR_PES_Pos (15U) +#define FLASH_ACR_PES_Msk (0x1UL << FLASH_ACR_PES_Pos) /*!< 0x00008000 */ +#define FLASH_ACR_PES FLASH_ACR_PES_Msk /*!< Program/erase suspend request */ +#define FLASH_ACR_EMPTY_Pos (16U) +#define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Flash use area empty */ + +#define FLASH_ACR_LATENCY_0WS (0x0UL << FLASH_ACR_LATENCY_Pos) /*!< FLASH Zero wait state */ +#define FLASH_ACR_LATENCY_1WS (FLASH_ACR_LATENCY_0 << FLASH_ACR_LATENCY_Pos) /*!< FLASH One wait state */ +#define FLASH_ACR_LATENCY_2WS (FLASH_ACR_LATENCY_1 << FLASH_ACR_LATENCY_Pos) /*!< FLASH Two wait states */ +#define FLASH_ACR_LATENCY_3WS ((FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) << FLASH_ACR_LATENCY_Pos) /*!< FLASH Three wait states */ + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of Operation */ +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Operation error */ +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk /*!< Programming error */ +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */ +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming alignment error */ +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error */ +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk /*!< Fast programming data miss error */ +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk /*!< Fast programming error */ +#define FLASH_SR_OPTNV_Pos (13U) +#define FLASH_SR_OPTNV_Msk (0x1UL << FLASH_SR_OPTNV_Pos) /*!< 0x00002000 */ +#define FLASH_SR_OPTNV FLASH_SR_OPTNV_Msk /*!< User option OPTVAL indication */ +#define FLASH_SR_RDERR_Pos (14U) +#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< PCROP read error */ +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */ +#define FLASH_SR_BSY_Pos (16U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Flash Busy */ +#define FLASH_SR_CFGBSY_Pos (18U) +#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk /*!< Programming or erase configuration busy */ +#define FLASH_SR_PESD_Pos (19U) +#define FLASH_SR_PESD_Msk (0x1UL << FLASH_SR_PESD_Pos) /*!< 0x00080000 */ +#define FLASH_SR_PESD FLASH_SR_PESD_Msk /*!< Programming/erase operation suspended */ + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Flash programming */ +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page erase */ +#define FLASH_CR_MER_Pos (2U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< Page number selection mask */ +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start an erase operation */ +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk /*!< Options modification start */ +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk /*!< Fast programming */ +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error interrupt enable */ +#define FLASH_CR_RDERRIE_Pos (26U) +#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk /*!< PCROP read error interrupt enable */ +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk /*!< Options lock */ +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Flash control register lock */ + +/******************* Bits definition for FLASH_ECCR register ****************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0001FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< double-word address ECC fail */ +#define FLASH_ECCR_SYSF_ECC_Pos (20U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System flash ECC fail */ +#define FLASH_ECCR_ECCCIE_Pos (24U) +#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_CPUID_Pos (26U) +#define FLASH_ECCR_CPUID_Msk (0x7UL << FLASH_ECCR_CPUID_Pos) /*!< 0x1C000000 */ +#define FLASH_ECCR_CPUID FLASH_ECCR_CPUID_Msk /*!< CPU identification */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPTR register ****************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Read protection level */ +#define FLASH_OPTR_ESE_Pos (8U) +#define FLASH_OPTR_ESE_Msk (0x1UL << FLASH_OPTR_ESE_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_ESE FLASH_OPTR_ESE_Msk /*!< Security enable */ +#define FLASH_OPTR_BOR_LEV_Pos (9U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000E00 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset level mask */ +#define FLASH_OPTR_BOR_LEV_0 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000800 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< Reset option in Stop mode */ +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< Reset option in Standby mode */ +#define FLASH_OPTR_nRST_SHDW_Pos (14U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< Reset option in Shutdown mode */ +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter option in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter option in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_nBOOT1_Pos (23U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk /*!< Boot Configuration */ +#define FLASH_OPTR_SRAM2PE_Pos (24U) +#define FLASH_OPTR_SRAM2PE_Msk (0x1UL << FLASH_OPTR_SRAM2PE_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2PE FLASH_OPTR_SRAM2PE_Msk /*!< SRAM2 parity check enable */ +#define FLASH_OPTR_SRAM2RST_Pos (25U) +#define FLASH_OPTR_SRAM2RST_Msk (0x1UL << FLASH_OPTR_SRAM2RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2RST FLASH_OPTR_SRAM2RST_Msk /*!< SRAM2 erase option when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< BOOT0 option bit */ +#define FLASH_OPTR_AGC_TRIM_Pos (29U) +#define FLASH_OPTR_AGC_TRIM_Msk (0x7UL << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0xE0000000 */ +#define FLASH_OPTR_AGC_TRIM FLASH_OPTR_AGC_TRIM_Msk /*!< Automatic Gain Control trimming mask */ +#define FLASH_OPTR_AGC_TRIM_0 (0x1U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_AGC_TRIM_1 (0x2U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_AGC_TRIM_2 (0x4U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for FLASH_PCROP1ASR register ************/ +#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U) +#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0xFFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x000000FF */ +#define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk /*!< PCROP area A start offset */ + +/****************** Bits definition for FLASH_PCROP1AER register ************/ +#define FLASH_PCROP1AER_PCROP1A_END_Pos (0U) +#define FLASH_PCROP1AER_PCROP1A_END_Msk (0xFFUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x000000FF */ +#define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk /*!< PCROP area A end offset */ +#define FLASH_PCROP1AER_PCROP_RDP_Pos (31U) +#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */ +#define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk /*!< PCROP area preserved when RDP level decreased */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk /*!< WRP area A start offset */ +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk /*!< WRP area A end offset */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk /*!< WRP area B start offset */ +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk /*!< WRP area B end offset */ + +/****************** Bits definition for FLASH_PCROP1BSR register ************/ +#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U) +#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0xFFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x000000FF */ +#define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk /*!< PCROP area B start offset */ + +/****************** Bits definition for FLASH_PCROP1BER register ************/ +#define FLASH_PCROP1BER_PCROP1B_END_Pos (0U) +#define FLASH_PCROP1BER_PCROP1B_END_Msk (0xFFUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x000000FF */ +#define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk /*!< PCROP area B end offset */ + +/****************** Bits definition for FLASH_IPCCBR register ************/ +#define FLASH_IPCCBR_IPCCDBA_Pos (0U) +#define FLASH_IPCCBR_IPCCDBA_Msk (0x3FFFUL << FLASH_IPCCBR_IPCCDBA_Pos) /*!< 0x00003FFF */ +#define FLASH_IPCCBR_IPCCDBA FLASH_IPCCBR_IPCCDBA_Msk /*!< IPCC data buffer base address */ + +/****************** Bits definition for FLASH_SFR register ************/ +#define FLASH_SFR_SFSA_Pos (0U) +#define FLASH_SFR_SFSA_Msk (0x7FUL << FLASH_SFR_SFSA_Pos) /*!< 0x0000007F */ +#define FLASH_SFR_SFSA FLASH_SFR_SFSA_Msk /* Secure flash start address */ +#define FLASH_SFR_FSD_Pos (7U) +#define FLASH_SFR_FSD_Msk (0x1UL << FLASH_SFR_FSD_Pos) /*!< 0x00000100 */ +#define FLASH_SFR_FSD FLASH_SFR_FSD_Msk /* Flash mode secure */ +#define FLASH_SFR_DDS_Pos (12U) +#define FLASH_SFR_DDS_Msk (0x1UL << FLASH_SFR_DDS_Pos) /*!< 0x00001000 */ +#define FLASH_SFR_DDS FLASH_SFR_DDS_Msk /* Enabling and disabling CPU2 Debug access */ + +/****************** Bits definition for FLASH_SRRVR register ************/ +#define FLASH_SRRVR_SBRV_Pos (0U) +#define FLASH_SRRVR_SBRV_Msk (0x1FFFFUL << FLASH_SRRVR_SBRV_Pos) /*!< 0x0001FFFF */ +#define FLASH_SRRVR_SBRV FLASH_SRRVR_SBRV_Msk /* SCPU2 boot reset vector memory offset */ + +#define FLASH_SRRVR_SBRSA_Pos (18U) +#define FLASH_SRRVR_SBRSA_Msk (0x1FUL << FLASH_SRRVR_SBRSA_Pos) /*!< 0x007C0000 */ +#define FLASH_SRRVR_SBRSA FLASH_SRRVR_SBRSA_Msk /* Secure backup SRAM2a start address */ +#define FLASH_SRRVR_BRSD_Pos (23U) +#define FLASH_SRRVR_BRSD_Msk (0x1UL << FLASH_SRRVR_BRSD_Pos) /*!< 0x00800000 */ +#define FLASH_SRRVR_BRSD FLASH_SRRVR_BRSD_Msk /* Backup SRAM2A secure mode */ + +#define FLASH_SRRVR_SNBRSA_Pos (25U) +#define FLASH_SRRVR_SNBRSA_Msk (0x1FUL << FLASH_SRRVR_SNBRSA_Pos) /*!< 0x3E000000 */ +#define FLASH_SRRVR_SNBRSA FLASH_SRRVR_SNBRSA_Msk /* Secure non-backup SRAM2b start address */ +#define FLASH_SRRVR_NBRSD_Pos (30U) +#define FLASH_SRRVR_NBRSD_Msk (0x1UL << FLASH_SRRVR_NBRSD_Pos) /*!< 0x40000000 */ +#define FLASH_SRRVR_NBRSD FLASH_SRRVR_NBRSD_Msk /* Non-backup SRAM2B secure mode */ +#define FLASH_SRRVR_C2OPT_Pos (31U) +#define FLASH_SRRVR_C2OPT_Msk (0x1UL << FLASH_SRRVR_C2OPT_Pos) /*!< 0x80000000 */ +#define FLASH_SRRVR_C2OPT FLASH_SRRVR_C2OPT_Msk /* SCPU2 boot reset vector memory selection */ + +/****************** Bits definition for FLASH_C2ACR register ************/ +#define FLASH_C2ACR_PRFTEN_Pos (8U) +#define FLASH_C2ACR_PRFTEN_Msk (0x1UL << FLASH_C2ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_C2ACR_PRFTEN FLASH_C2ACR_PRFTEN_Msk /*!< CPU2 Prefetch enable */ +#define FLASH_C2ACR_ICEN_Pos (9U) +#define FLASH_C2ACR_ICEN_Msk (0x1UL << FLASH_C2ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_C2ACR_ICEN FLASH_C2ACR_ICEN_Msk /*!< CPU2 Instruction cache enable */ +#define FLASH_C2ACR_ICRST_Pos (11U) +#define FLASH_C2ACR_ICRST_Msk (0x1UL << FLASH_C2ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_C2ACR_ICRST FLASH_C2ACR_ICRST_Msk /*!< CPU2 Instruction cache reset */ +#define FLASH_C2ACR_PES_Pos (15U) +#define FLASH_C2ACR_PES_Msk (0x1UL << FLASH_C2ACR_PES_Pos) /*!< 0x00008000 */ +#define FLASH_C2ACR_PES FLASH_C2ACR_PES_Msk /*!< CPU2 Program/erase suspend request */ + +/****************** Bits definition for FLASH_C2SR register ************/ +#define FLASH_C2SR_EOP_Pos (0U) +#define FLASH_C2SR_EOP_Msk (0x1UL << FLASH_C2SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_C2SR_EOP FLASH_C2SR_EOP_Msk /*!< CPU2 End of operation */ +#define FLASH_C2SR_OPERR_Pos (1U) +#define FLASH_C2SR_OPERR_Msk (0x1UL << FLASH_C2SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_C2SR_OPERR FLASH_C2SR_OPERR_Msk /*!< CPU2 Operation error */ +#define FLASH_C2SR_PROGERR_Pos (3U) +#define FLASH_C2SR_PROGERR_Msk (0x1UL << FLASH_C2SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_C2SR_PROGERR FLASH_C2SR_PROGERR_Msk /*!< CPU2 Programming error */ +#define FLASH_C2SR_WRPERR_Pos (4U) +#define FLASH_C2SR_WRPERR_Msk (0x1UL << FLASH_C2SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_C2SR_WRPERR FLASH_C2SR_WRPERR_Msk /*!< CPU2 Write protection error */ +#define FLASH_C2SR_PGAERR_Pos (5U) +#define FLASH_C2SR_PGAERR_Msk (0x1UL << FLASH_C2SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_C2SR_PGAERR FLASH_C2SR_PGAERR_Msk /*!< CPU2 Programming alignment error */ +#define FLASH_C2SR_SIZERR_Pos (6U) +#define FLASH_C2SR_SIZERR_Msk (0x1UL << FLASH_C2SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_C2SR_SIZERR FLASH_C2SR_SIZERR_Msk /*!< CPU2 Size error */ +#define FLASH_C2SR_PGSERR_Pos (7U) +#define FLASH_C2SR_PGSERR_Msk (0x1UL << FLASH_C2SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_C2SR_PGSERR FLASH_C2SR_PGSERR_Msk /*!< CPU2 Programming sequence error */ +#define FLASH_C2SR_MISERR_Pos (8U) +#define FLASH_C2SR_MISERR_Msk (0x1UL << FLASH_C2SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_C2SR_MISERR FLASH_C2SR_MISERR_Msk /*!< CPU2 Fast programming data miss error */ +#define FLASH_C2SR_FASTERR_Pos (9U) +#define FLASH_C2SR_FASTERR_Msk (0x1UL << FLASH_C2SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_C2SR_FASTERR FLASH_C2SR_FASTERR_Msk /*!< CPU2 Fast programming error */ +#define FLASH_C2SR_RDERR_Pos (14U) +#define FLASH_C2SR_RDERR_Msk (0x1UL << FLASH_C2SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_C2SR_RDERR FLASH_C2SR_RDERR_Msk /*!< CPU2 PCROP read error */ +#define FLASH_C2SR_BSY_Pos (16U) +#define FLASH_C2SR_BSY_Msk (0x1UL << FLASH_C2SR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_C2SR_BSY FLASH_C2SR_BSY_Msk /*!< CPU2 Flash busy */ +#define FLASH_C2SR_CFGBSY_Pos (18U) +#define FLASH_C2SR_CFGBSY_Msk (0x1UL << FLASH_C2SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_C2SR_CFGBSY FLASH_C2SR_CFGBSY_Msk /*!< CPU2 Programming or erase configuration busy */ +#define FLASH_C2SR_PESD_Pos (19U) +#define FLASH_C2SR_PESD_Msk (0x1UL << FLASH_C2SR_PESD_Pos) /*!< 0x00080000 */ +#define FLASH_C2SR_PESD FLASH_C2SR_PESD_Msk /*!< CPU2 Programming/erase operation suspended */ + +/****************** Bits definition for FLASH_C2CR register ************/ +#define FLASH_C2CR_PG_Pos (0U) +#define FLASH_C2CR_PG_Msk (0x1UL << FLASH_C2CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_C2CR_PG FLASH_C2CR_PG_Msk /*!< CPU2 Flash programming */ +#define FLASH_C2CR_PER_Pos (1U) +#define FLASH_C2CR_PER_Msk (0x1UL << FLASH_C2CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_C2CR_PER FLASH_C2CR_PER_Msk /*!< CPU2 Page erase */ +#define FLASH_C2CR_MER_Pos (2U) +#define FLASH_C2CR_MER_Msk (0x1UL << FLASH_C2CR_MER_Pos) /*!< 0x00000004 */ +#define FLASH_C2CR_MER FLASH_C2CR_MER_Msk /*!< CPU2 Mass erase */ +#define FLASH_C2CR_PNB_Pos (3U) +#define FLASH_C2CR_PNB_Msk (0x7FUL << FLASH_C2CR_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_C2CR_PNB FLASH_C2CR_PNB_Msk /*!< CPU2 Page number selection mask */ +#define FLASH_C2CR_STRT_Pos (16U) +#define FLASH_C2CR_STRT_Msk (0x1UL << FLASH_C2CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_C2CR_STRT FLASH_C2CR_STRT_Msk /*!< CPU2 Start an erase operation */ +#define FLASH_C2CR_FSTPG_Pos (18U) +#define FLASH_C2CR_FSTPG_Msk (0x1UL << FLASH_C2CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_C2CR_FSTPG FLASH_C2CR_FSTPG_Msk /*!< CPU2 Fast programming */ +#define FLASH_C2CR_EOPIE_Pos (24U) +#define FLASH_C2CR_EOPIE_Msk (0x1UL << FLASH_C2CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_C2CR_EOPIE FLASH_C2CR_EOPIE_Msk /*!< CPU2 End of operation interrupt enable */ +#define FLASH_C2CR_ERRIE_Pos (25U) +#define FLASH_C2CR_ERRIE_Msk (0x1UL << FLASH_C2CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_C2CR_ERRIE FLASH_C2CR_ERRIE_Msk /*!< CPU2 Error interrupt enable */ +#define FLASH_C2CR_RDERRIE_Pos (26U) +#define FLASH_C2CR_RDERRIE_Msk (0x1UL << FLASH_C2CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_C2CR_RDERRIE FLASH_C2CR_RDERRIE_Msk /*!< CPU2 PCROP read error interrupt enable */ + +/******************************************************************************/ +/* */ +/* General Purpose I/O */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/******************************************************************************/ +/* */ +/* HSEM HW Semaphore */ +/* */ +/******************************************************************************/ +/******************** Bit definition for HSEM_R register ********************/ +#define HSEM_R_PROCID_Pos (0U) +#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */ +#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32wb5mxx + * @{ + */ + +#ifndef __STM32WB5Mxx_H +#define __STM32WB5Mxx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 1U /*!< Core Revision r0p1 */ +#define __MPU_PRESENT 1U /*!< M4 provides an MPU */ +#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 4U /*!< STM32WBxx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32wb5mxx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +/*!< Interrupt Number Definition for M4 */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt */ + +/************* STM32WBxx specific Interrupt Numbers on M4 core ************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD and PVM detector */ + TAMP_STAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Interrupt */ + FLASH_IRQn = 4, /*!< FLASH (CFI) global Interrupt */ + RCC_IRQn = 5, /*!< RCC Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line 0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line 1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line 2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line 3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line 4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt (including USB wakeup) */ + C2SEV_PWR_C2H_IRQn = 21, /*!< CPU2 SEV Interrupt */ + COMP_IRQn = 22, /*!< COMP1 and COMP2 Interrupts */ + EXTI9_5_IRQn = 23, /*!< EXTI Lines [9:5] Interrupt */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 global Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Communication and TIM17 global Interrupts */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 Global Interrupt */ + PKA_IRQn = 29, /*!< PKA Interrupt */ + I2C1_EV_IRQn = 30, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 31, /*!< I2C1 Error Interrupt */ + I2C3_EV_IRQn = 32, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 33, /*!< I2C3 Error Interrupt */ + SPI1_IRQn = 34, /*!< SPI1 Interrupt */ + SPI2_IRQn = 35, /*!< SPI2 Interrupt */ + USART1_IRQn = 36, /*!< USART1 Interrupt */ + LPUART1_IRQn = 37, /*!< LPUART1 Interrupt */ + SAI1_IRQn = 38, /*!< SAI1 A and B global interrupt */ + TSC_IRQn = 39, /*!< TSC Interrupt */ + EXTI15_10_IRQn = 40, /*!< EXTI Lines1[15:10 ]Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarms (A and B) Interrupt */ + CRS_IRQn = 42, /*!< CRS interrupt */ + PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQn = 43, /*!< PWR switching on the fly interrupt + PWR end of BLE activity interrupt + PWR end of 802.15.4 (Zigbee) activity interrupt + PWR end of critical radio phase interrupt */ + IPCC_C1_RX_IRQn = 44, /*!< IPCC RX Occupied Interrupt */ + IPCC_C1_TX_IRQn = 45, /*!< IPCC TX Free Interrupt */ + HSEM_IRQn = 46, /*!< HSEM Interrupt */ + LPTIM1_IRQn = 47, /*!< LPTIM1 Interrupt */ + LPTIM2_IRQn = 48, /*!< LPTIM2 Interrupt */ + LCD_IRQn = 49, /*!< LCD Interrupt */ + QUADSPI_IRQn = 50, /*!< QUADSPI Interrupt */ + AES1_IRQn = 51, /*!< AES1 Interrupt */ + AES2_IRQn = 52, /*!< AES2 Interrupt */ + RNG_IRQn = 53, /*!< RNG Interrupt */ + FPU_IRQn = 54, /*!< FPU Interrupt */ + DMA2_Channel1_IRQn = 55, /*!< DMA2 Channel 1 Interrupt */ + DMA2_Channel2_IRQn = 56, /*!< DMA2 Channel 2 Interrupt */ + DMA2_Channel3_IRQn = 57, /*!< DMA2 Channel 3 Interrupt */ + DMA2_Channel4_IRQn = 58, /*!< DMA2 Channel 4 Interrupt */ + DMA2_Channel5_IRQn = 59, /*!< DMA2 Channel 5 Interrupt */ + DMA2_Channel6_IRQn = 60, /*!< DMA2 Channel 6 Interrupt */ + DMA2_Channel7_IRQn = 61, /*!< DMA2 Channel 7 Interrupt */ + DMAMUX1_OVR_IRQn = 62 /*!< DMAMUX1 overrun Interrupt */ +} IRQn_Type; +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32wbxx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */ +} ADC_Common_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x08-0x38 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x3C */ + __IO uint32_t C2APB1FZR1; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x40 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x44 */ + __IO uint32_t C2APB1FZR2; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x48 */ + __IO uint32_t APB2FZR; /*!< Debug MCU CPU1 APB2 freeze register, Address offset: 0x4C */ + __IO uint32_t C2APB2FZR; /*!< Debug MCU CPU2 APB2 freeze register, Address offset: 0x50 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register 0x00 */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register 0x04 */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register 0x08 */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register 0x0C */ + uint32_t RESERVED; /*!< Reserved, 0x10 */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */ + __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank 1 PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank 1 PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank 1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank 1 WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank 1 PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank 1 PCROP area B End address register, Address offset: 0x38 */ + __IO uint32_t IPCCBR; /*!< FLASH IPCC data buffer address, Address offset: 0x3C */ + uint32_t RESERVED2[7]; /*!< Reserved, Address offset: 0x40-0x58 */ + __IO uint32_t C2ACR; /*!< FLASH Core MO+ Access Control Register , Address offset: 0x5C */ + __IO uint32_t C2SR; /*!< FLASH Core MO+ Status Register, Address offset: 0x60 */ + __IO uint32_t C2CR; /*!< FLASH Core MO+ Control register, Address offset: 0x64 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x68-0x7C */ + __IO uint32_t SFR; /*!< FLASH secure start address, Address offset: 0x80 */ + __IO uint32_t SRRVR; /*!< FlASH secure SRAM2 start addr and CPU2 reset vector Address offset: 0x84 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Reset Register, Address offset: 0x18 */ + __IO uint32_t CR5; /*!< PWR Power Control Register 5, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< PWR Pull-Up Control Register of port E, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< PWR Pull-Down Control Register of port E, Address offset: 0x44 */ + uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t PUCRH; /*!< PWR Pull-Up Control Register of port H, Address offset: 0x58 */ + __IO uint32_t PDCRH; /*!< PWR Pull-Down Control Register of port H, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x60-0x7C */ + __IO uint32_t C2CR1; /*!< PWR Power Control Register 1 for CPU2, Address offset: 0x80 */ + __IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset: 0x84 */ + __IO uint32_t EXTSCR; /*!< PWR Power Status Reset Register for CPU2, Address offset: 0x88 */ +} PWR_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ + __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration Register, Address offset: 0x10 */ +uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t SMPSCR; /*!< RCC SMPS step-down converter control register, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */ +uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable register, Address offset: 0x50 */ +uint32_t RESERVED2; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ +uint32_t RESERVED3; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ +uint32_t RESERVED4; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ +uint32_t RESERVED5; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Clock Configuration Independent Register, Address offset: 0x88 */ +uint32_t RESERVED6; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC Control and Status Register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x98 */ + __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */ +uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */ + __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ +uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ + __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */ + __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */ + __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */ +uint32_t RESERVED9; /*!< Reserved, Address offset: 0x154 */ + __IO uint32_t C2APB1ENR1; /*!< RCC APB1 peripheral CPU2 clocks enable register 1, Address offset: 0x158 */ + __IO uint32_t C2APB1ENR2; /*!< RCC APB1 peripheral CPU2 clocks enable register 2, Address offset: 0x15C */ + __IO uint32_t C2APB2ENR; /*!< RCC APB2 peripheral CPU2 clocks enable register 1, Address offset: 0x160 */ + __IO uint32_t C2APB3ENR; /*!< RCC APB3 peripheral CPU2 clocks enable register 1, Address offset: 0x164 */ + __IO uint32_t C2AHB1SMENR; /*!< RCC AHB1 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x168 */ + __IO uint32_t C2AHB2SMENR; /*!< RCC AHB2 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x16C */ + __IO uint32_t C2AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x170 */ +uint32_t RESERVED10; /*!< Reserved, */ + __IO uint32_t C2APB1SMENR1; /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 1, Address offset: 0x178 */ + __IO uint32_t C2APB1SMENR2; /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 2, Address offset: 0x17C */ + __IO uint32_t C2APB2SMENR; /*!< RCC APB2 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x180 */ + __IO uint32_t C2APB3SMENR; /*!< RCC APB3 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x184 */ +} RCC_TypeDef; + + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + + + + +/** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR1; /*!< SYSCFG SRAM2 write protection register part 1, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ + __IO uint32_t SWPR2; /*!< SYSCFG write protection register part 2, Address offset: 0x28 */ + uint32_t RESERVED1[53]; /*!< Reserved, Address offset: 0x2C-0xFC */ + __IO uint32_t IMR1; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 1, Address offset: 0x100 */ + __IO uint32_t IMR2; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 2, Address offset: 0x104 */ + __IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 1, Address offset: 0x108 */ + __IO uint32_t C2IMR2; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 2, Address offset: 0x10C */ + __IO uint32_t SIPCR; /*!< SYSCFG secure IP control register, Address offset: 0x110 */ + +} SYSCFG_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ +} AES_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */ +} TSC_TypeDef; + +/** + * @brief LCD + */ +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Inter-Processor Communication + */ +typedef struct +{ + __IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, Address offset: 0x000 */ + __IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, Address offset: 0x004 */ + __IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, Address offset: 0x008 */ + __IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status register, Address offset: 0x00C */ + __IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, Address offset: 0x010 */ + __IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, Address offset: 0x014 */ + __IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, Address offset: 0x018 */ + __IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status register, Address offset: 0x01C */ +} IPCC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x000 */ + __IO uint32_t MR; /*!< Mask register, Address offset: 0x004 */ + __IO uint32_t SCR; /*!< Status set clear register, Address offset: 0x008 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x00C */ +} IPCC_CommonTypeDef; + +/** + * @brief Async Interrupts and Events Controller + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI software interrupt event register [31:0], Address offset: 0x08 */ + __IO uint32_t PR1; /*!< EXTI pending register [31:0], Address offset: 0x0C */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x10 - 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI software interrupt event register [31:0], Address offset: 0x28 */ + __IO uint32_t PR2; /*!< EXTI pending register [31:0], Address offset: 0x2C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x30 - 0x3C */ + __IO uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x40 - 0x5C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, Address offset: 0x60 - 0x7C */ + __IO uint32_t IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED8[10]; /*!< Reserved, Address offset: 0x98 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ +}EXTI_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Public Key Accelerator (PKA) + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03FC*/ + __IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F4 */ +} PKA_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ +typedef struct +{ + __IO uint32_t R[32]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< HSEM 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM CPU1 interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM CPU1 interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM CPU1 interrupt status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM CPU1 masked interrupt status register , Address offset: 10Ch */ + __IO uint32_t C2IER; /*!< HSEM CPU2 interrupt enable register , Address offset: 110h */ + __IO uint32_t C2ICR; /*!< HSEM CPU2 interrupt clear register , Address offset: 114h */ + __IO uint32_t C2ISR; /*!< HSEM CPU2 interrupt status register , Address offset: 118h */ + __IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 11Ch */ + uint32_t Reserved[8]; /*!< Reserved Address offset: 120h-13Ch*/ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +/*!< Boundary memory map */ +#define FLASH_BASE (0x08000000UL)/*!< FLASH(up to 1 MB) base address */ +#define SRAM_BASE (0x20000000UL)/*!< SRAM(up to 256 KB) base address */ +#define PERIPH_BASE (0x40000000UL)/*!< Peripheral base address */ + +/*!< Memory, OTP and Option bytes */ + +/* Base addresses */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 0x1FFF8FFF) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ + +#define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 192 KB) base address */ +#define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ +#define SRAM2B_BASE (SRAM_BASE + 0x00038000UL)/*!< SRAM2B(32 KB) base address */ + +/* Memory Size */ +#define FLASH_SIZE (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U) +#define SRAM1_SIZE 0x00030000UL /*!< SRAM1 default size : 192 kB */ +#define SRAM2A_SIZE 0x00008000UL /*!< SRAM2a default size : 32 kB */ +#define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ + +/* End addresses */ +#define SRAM1_END_ADDR (0x2002FFFFUL) /*!< SRAM1 : 192KB (0x20000000 0x2002FFFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 0x2003FFFF) */ + +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) +#define AHB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define APB3PERIPH_BASE (PERIPH_BASE + 0x20000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x50000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) +#define LCD_BASE (APB1PERIPH_BASE + 0x00002400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x00005C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x00006000UL) +#define USB1_BASE (APB1PERIPH_BASE + 0x00006800UL) +#define USB1_PMAADDR (APB1PERIPH_BASE + 0x00006C00UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x00007C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x00008000UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x00009400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x00000030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x00000200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x00000204UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x00005400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0000004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0000024UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x00000800UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x0000006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x00000080UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) + +/*!< AHB2 peripherals */ +#define IOPORT_BASE (AHB2PERIPH_BASE + 0x00000000UL) +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOE_BASE (IOPORT_BASE + 0x00001000UL) +#define GPIOH_BASE (IOPORT_BASE + 0x00001C00UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) + +#define AES1_BASE (AHB2PERIPH_BASE + 0x08060000UL) + +/*!< AHB Shared peripherals */ +#define RCC_BASE (AHB4PERIPH_BASE + 0x00000000UL) +#define PWR_BASE (AHB4PERIPH_BASE + 0x00000400UL) +#define EXTI_BASE (AHB4PERIPH_BASE + 0x00000800UL) +#define IPCC_BASE (AHB4PERIPH_BASE + 0x00000C00UL) +#define RNG_BASE (AHB4PERIPH_BASE + 0x00001000UL) +#define HSEM_BASE (AHB4PERIPH_BASE + 0x00001400UL) +#define AES2_BASE (AHB4PERIPH_BASE + 0x00001800UL) +#define PKA_BASE (AHB4PERIPH_BASE + 0x00002000UL) +#define FLASH_REG_BASE (AHB4PERIPH_BASE + 0x00004000UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + + +/*!< AHB3 peripherals */ +#define QUADSPI_BASE (AHB3PERIPH_BASE + 0x00000000UL) /*!< QUADSPI memories accessible over AHB base address */ +#define QUADSPI_R_BASE (AHB3PERIPH_BASE + 0x10001000UL) /*!< QUADSPI control registers base address */ + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE ((uint32_t)0x1FFF7500UL) /*!< Package data register base address */ +#define UID64_BASE ((uint32_t)0x1FFF7580UL) /*!< 64-bit Unique device Identification */ +#define UID_BASE ((uint32_t)0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +/* Peripherals available on APB1 bus */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define USB ((USB_TypeDef *) USB1_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) + +/* Peripherals available on APB2 bus */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) + +/* Peripherals available on AHB1 bus */ +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define TSC ((TSC_TypeDef *) TSC_BASE) + +/* Peripherals available on AHB2 bus */ +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) + +#define AES1 ((AES_TypeDef *) AES1_BASE) + +/* Peripherals available on AHB shared bus */ +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define IPCC ((IPCC_TypeDef *) IPCC_BASE) +#define IPCC_C1 ((IPCC_CommonTypeDef *) IPCC_BASE) +#define IPCC_C2 ((IPCC_CommonTypeDef *) (IPCC_BASE + 0x10U)) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U)) +#define AES2 ((AES_TypeDef *) AES2_BASE) +#define PKA ((PKA_TypeDef *) PKA_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_REG_BASE) + +/* Peripherals available on AHB3 bus */ +#define QUADSPI ((QUADSPI_TypeDef *) QUADSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_ALIGN_Pos (5U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR_EXTSEL_Pos (6U) +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ + +#define ADC_JSQR_JEXTEN_Pos (6U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ + +#define ADC_JSQR_JSQ1_Pos (8U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ + +#define ADC_JSQR_JSQ2_Pos (14U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (20U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ + +#define ADC_JSQR_JSQ4_Pos (26U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003A0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00000100 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00000200 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00000400 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/* Legacy defines */ +#define ADC_CCR_MULTI (ADC_CCR_DUAL) +#define ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0) +#define ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1) +#define ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2) +#define ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3) +#define ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4) + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ***************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ +#define COMP_CSR_PWRMODE_Pos (2U) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */ +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0x7UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INPSEL_Pos (7U) +#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000180 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_WINMODE_Pos (9U) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_BLANKING_Pos (18U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */ +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */ +#define COMP_CSR_INMESEL_Pos (25U) +#define COMP_CSR_INMESEL_Msk (0x3UL << COMP_CSR_INMESEL_Pos) /*!< 0x06000000 */ +#define COMP_CSR_INMESEL COMP_CSR_INMESEL_Msk /*!< Comparator input minus extended selection */ +#define COMP_CSR_INMESEL_0 (0x1UL << COMP_CSR_INMESEL_Pos) /*!< 0x02000000 */ +#define COMP_CSR_INMESEL_1 (0x2UL << COMP_CSR_INMESEL_Pos) /*!< 0x04000000 */ +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1U << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2U << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ + +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1U << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2U << AES_CR_MODE_Pos) /*!< 0x00000010 */ + +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001U << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002U << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800U << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ + +#define AES_CR_CCFC_Pos (7U) +#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ +#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ +#define AES_CR_ERRC_Pos (8U) +#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ +#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ +#define AES_CR_CCFIE_Pos (9U) +#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */ +#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */ +#define AES_CR_ERRIE_Pos (10U) +#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ +#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ + +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1U << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2U << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ + +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ + +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in last payload block */ +#define AES_CR_NPBLB_0 (0x1U << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2U << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4U << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8U << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* DMAMUX Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMAMUX_CxCR register **************/ +#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ +#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ +#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ +#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ +#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ +#define DMAMUX_CxCR_SOIE_Pos (8U) +#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ +#define DMAMUX_CxCR_EGE_Pos (9U) +#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ +#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ +#define DMAMUX_CxCR_SE_Pos (16U) +#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ +#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ +#define DMAMUX_CxCR_SPOL_Pos (17U) +#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ +#define DMAMUX_CxCR_SPOL_0 (0x1U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_CxCR_SPOL_1 (0x2U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_CxCR_NBREQ_Pos (19U) +#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ +#define DMAMUX_CxCR_NBREQ_0 (0x01U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_CxCR_NBREQ_1 (0x02U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_CxCR_NBREQ_2 (0x04U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_CxCR_NBREQ_3 (0x08U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_CxCR_NBREQ_4 (0x10U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ +#define DMAMUX_CxCR_SYNC_ID_Pos (24U) +#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ +#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ +#define DMAMUX_CxCR_SYNC_ID_0 (0x01U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ +#define DMAMUX_CxCR_SYNC_ID_1 (0x02U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ +#define DMAMUX_CxCR_SYNC_ID_2 (0x04U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ +#define DMAMUX_CxCR_SYNC_ID_3 (0x08U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ +#define DMAMUX_CxCR_SYNC_ID_4 (0x10U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ + +/******************* Bits definition for DMAMUX_CSR register **************/ +#define DMAMUX_CSR_SOF0_Pos (0U) +#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ +#define DMAMUX_CSR_SOF1_Pos (1U) +#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ +#define DMAMUX_CSR_SOF2_Pos (2U) +#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ +#define DMAMUX_CSR_SOF3_Pos (3U) +#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */ +#define DMAMUX_CSR_SOF4_Pos (4U) +#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */ +#define DMAMUX_CSR_SOF5_Pos (5U) +#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */ +#define DMAMUX_CSR_SOF6_Pos (6U) +#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */ +#define DMAMUX_CSR_SOF7_Pos (7U) +#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */ +#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Synchronization Overrun Flag 7 */ +#define DMAMUX_CSR_SOF8_Pos (8U) +#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */ +#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Synchronization Overrun Flag 8 */ +#define DMAMUX_CSR_SOF9_Pos (9U) +#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */ +#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Synchronization Overrun Flag 9 */ +#define DMAMUX_CSR_SOF10_Pos (10U) +#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */ +#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Synchronization Overrun Flag 10 */ +#define DMAMUX_CSR_SOF11_Pos (11U) +#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */ +#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Synchronization Overrun Flag 11 */ +#define DMAMUX_CSR_SOF12_Pos (12U) +#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */ +#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Synchronization Overrun Flag 12 */ +#define DMAMUX_CSR_SOF13_Pos (13U) +#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */ +#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Synchronization Overrun Flag 13 */ + +/******************** Bits definition for DMAMUX_CFR register **************/ +#define DMAMUX_CFR_CSOF0_Pos (0U) +#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ +#define DMAMUX_CFR_CSOF1_Pos (1U) +#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ +#define DMAMUX_CFR_CSOF2_Pos (2U) +#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ +#define DMAMUX_CFR_CSOF3_Pos (3U) +#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */ +#define DMAMUX_CFR_CSOF4_Pos (4U) +#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */ +#define DMAMUX_CFR_CSOF5_Pos (5U) +#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */ +#define DMAMUX_CFR_CSOF6_Pos (6U) +#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */ +#define DMAMUX_CFR_CSOF7_Pos (7U) +#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */ +#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Clear Overrun Flag 7 */ +#define DMAMUX_CFR_CSOF8_Pos (8U) +#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */ +#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Clear Overrun Flag 8 */ +#define DMAMUX_CFR_CSOF9_Pos (9U) +#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */ +#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Clear Overrun Flag 9 */ +#define DMAMUX_CFR_CSOF10_Pos (10U) +#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */ +#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Clear Overrun Flag 10 */ +#define DMAMUX_CFR_CSOF11_Pos (11U) +#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */ +#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Clear Overrun Flag 11 */ +#define DMAMUX_CFR_CSOF12_Pos (12U) +#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */ +#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Clear Overrun Flag 12 */ +#define DMAMUX_CFR_CSOF13_Pos (13U) +#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */ +#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Clear Overrun Flag 13 */ + +/******************** Bits definition for DMAMUX_RGxCR register ************/ +#define DMAMUX_RGxCR_SIG_ID_Pos (0U) +#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ +#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ +#define DMAMUX_RGxCR_SIG_ID_0 (0x01U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGxCR_SIG_ID_1 (0x02U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGxCR_SIG_ID_2 (0x04U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGxCR_SIG_ID_3 (0x08U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGxCR_SIG_ID_4 (0x10U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_RGxCR_OIE_Pos (8U) +#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ +#define DMAMUX_RGxCR_GE_Pos (16U) +#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ +#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ +#define DMAMUX_RGxCR_GPOL_Pos (17U) +#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ +#define DMAMUX_RGxCR_GPOL_0 (0x1U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_RGxCR_GPOL_1 (0x2U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_RGxCR_GNBREQ_Pos (19U) +#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ +#define DMAMUX_RGxCR_GNBREQ_0 (0x01U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_RGxCR_GNBREQ_1 (0x02U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_RGxCR_GNBREQ_2 (0x04U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_RGxCR_GNBREQ_3 (0x08U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_RGxCR_GNBREQ_4 (0x10U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for DMAMUX_RGSR register **************/ +#define DMAMUX_RGSR_OF0_Pos (0U) +#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ +#define DMAMUX_RGSR_OF1_Pos (1U) +#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ +#define DMAMUX_RGSR_OF2_Pos (2U) +#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ +#define DMAMUX_RGSR_OF3_Pos (3U) +#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ + +/******************** Bits definition for DMAMUX_RGCFR register **************/ +#define DMAMUX_RGCFR_COF0_Pos (0U) +#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ +#define DMAMUX_RGCFR_COF1_Pos (1U) +#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ +#define DMAMUX_RGCFR_COF2_Pos (2U) +#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ +#define DMAMUX_RGCFR_COF3_Pos (3U) +#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT_Pos (0U) +#define EXTI_RTSR1_RT_Msk (0x803FFFFFUL << EXTI_RTSR1_RT_Pos) /*!< 0x803FFFFF */ +#define EXTI_RTSR1_RT EXTI_RTSR1_RT_Msk /*!< Rising trigger event configuration bit */ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR1_RT17_Pos (17U) +#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR1_RT18_Pos (18U) +#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR1_RT19_Pos (19U) +#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */ +#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR1_RT20_Pos (20U) +#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */ +#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_RTSR1_RT21_Pos (21U) +#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */ +#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_RTSR1_RT31_Pos (31U) +#define EXTI_RTSR1_RT31_Msk (0x1UL << EXTI_RTSR1_RT31_Pos) /*!< 0x80000000 */ +#define EXTI_RTSR1_RT31 EXTI_RTSR1_RT31_Msk /*!< Rising trigger event configuration bit of line 31 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT_Pos (0U) +#define EXTI_FTSR1_FT_Msk (0x803FFFFFUL << EXTI_FTSR1_FT_Pos) /*!< 0x803FFFFF */ +#define EXTI_FTSR1_FT EXTI_FTSR1_FT_Msk /*!< Falling trigger event configuration bit */ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR1_FT17_Pos (17U) +#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR1_FT18_Pos (18U) +#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR1_FT19_Pos (19U) +#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */ +#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR1_FT20_Pos (20U) +#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */ +#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_FTSR1_FT21_Pos (21U) +#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */ +#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ +#define EXTI_FTSR1_FT31_Pos (31U) +#define EXTI_FTSR1_FT31_Msk (0x1UL << EXTI_FTSR1_FT31_Pos) /*!< 0x80000000 */ +#define EXTI_FTSR1_FT31 EXTI_FTSR1_FT31_Msk /*!< Falling trigger event configuration bit of line 31 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI_Pos (0U) +#define EXTI_SWIER1_SWI_Msk (0x803FFFFFUL << EXTI_SWIER1_SWI_Pos) /*!< 0x803FFFFF */ +#define EXTI_SWIER1_SWI EXTI_SWIER1_SWI_Msk /*!< Software interrupt */ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER1_SWI17_Pos (17U) +#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER1_SWI18_Pos (18U) +#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER1_SWI19_Pos (19U) +#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */ +#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER1_SWI20_Pos (20U) +#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */ +#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */ +#define EXTI_SWIER1_SWI21_Pos (21U) +#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */ +#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */ +#define EXTI_SWIER1_SWI31_Pos (31U) +#define EXTI_SWIER1_SWI31_Msk (0x1UL << EXTI_SWIER1_SWI31_Pos) /*!< 0x80000000 */ +#define EXTI_SWIER1_SWI31 EXTI_SWIER1_SWI31_Msk /*!< Software Interrupt on line 31 */ + +/******************* Bit definition for EXTI_PR1 register *******************/ +#define EXTI_PR1_PIF_Pos (0U) +#define EXTI_PR1_PIF_Msk (0x803FFFFFUL << EXTI_PR1_PIF_Pos) /*!< 0x803FFFFF */ +#define EXTI_PR1_PIF EXTI_PR1_PIF_Msk /*!< Pending bit */ +#define EXTI_PR1_PIF0_Pos (0U) +#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */ +#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */ +#define EXTI_PR1_PIF1_Pos (1U) +#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */ +#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */ +#define EXTI_PR1_PIF2_Pos (2U) +#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */ +#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */ +#define EXTI_PR1_PIF3_Pos (3U) +#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */ +#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */ +#define EXTI_PR1_PIF4_Pos (4U) +#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */ +#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */ +#define EXTI_PR1_PIF5_Pos (5U) +#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */ +#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */ +#define EXTI_PR1_PIF6_Pos (6U) +#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */ +#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */ +#define EXTI_PR1_PIF7_Pos (7U) +#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */ +#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */ +#define EXTI_PR1_PIF8_Pos (8U) +#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */ +#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */ +#define EXTI_PR1_PIF9_Pos (9U) +#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */ +#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */ +#define EXTI_PR1_PIF10_Pos (10U) +#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */ +#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */ +#define EXTI_PR1_PIF11_Pos (11U) +#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */ +#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */ +#define EXTI_PR1_PIF12_Pos (12U) +#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */ +#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */ +#define EXTI_PR1_PIF13_Pos (13U) +#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */ +#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */ +#define EXTI_PR1_PIF14_Pos (14U) +#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */ +#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */ +#define EXTI_PR1_PIF15_Pos (15U) +#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */ +#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */ +#define EXTI_PR1_PIF16_Pos (16U) +#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */ +#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */ +#define EXTI_PR1_PIF17_Pos (17U) +#define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */ +#define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */ +#define EXTI_PR1_PIF18_Pos (18U) +#define EXTI_PR1_PIF18_Msk (0x1UL << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */ +#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */ +#define EXTI_PR1_PIF19_Pos (19U) +#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */ +#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */ +#define EXTI_PR1_PIF20_Pos (20U) +#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */ +#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */ +#define EXTI_PR1_PIF21_Pos (21U) +#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */ +#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */ +#define EXTI_PR1_PIF31_Pos (31U) +#define EXTI_PR1_PIF31_Msk (0x1UL << EXTI_PR1_PIF31_Pos) /*!< 0x80000000 */ +#define EXTI_PR1_PIF31 EXTI_PR1_PIF31_Msk /*!< Pending bit for line 31 */ + +/****************** Bit definition for EXTI_RTSR2 register ******************/ +#define EXTI_RTSR2_RT_Pos (0U) +#define EXTI_RTSR2_RT_Msk (0x302UL << EXTI_RTSR2_RT_Pos) /*!< 0x00000302 */ +#define EXTI_RTSR2_RT EXTI_RTSR2_RT_Msk /*!< Rising trigger event configuration bit */ +#define EXTI_RTSR2_RT33_Pos (1U) +#define EXTI_RTSR2_RT33_Msk (0x1UL << EXTI_RTSR2_RT33_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR2_RT33 EXTI_RTSR2_RT33_Msk /*!< Rising trigger event configuration bit of line 33 */ +#define EXTI_RTSR2_RT40_Pos (8U) +#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */ +#define EXTI_RTSR2_RT41_Pos (9U) +#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */ + +/****************** Bit definition for EXTI_FTSR2 register ******************/ +#define EXTI_FTSR2_FT_Pos (0U) +#define EXTI_FTSR2_FT_Msk (0x302UL << EXTI_FTSR2_FT_Pos) /*!< 0x00000302 */ +#define EXTI_FTSR2_FT EXTI_FTSR2_FT_Msk /*!< Falling trigger event configuration bit */ +#define EXTI_FTSR2_FT33_Pos (1U) +#define EXTI_FTSR2_FT33_Msk (0x1UL << EXTI_FTSR2_FT33_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR2_FT33 EXTI_FTSR2_FT33_Msk /*!< Falling trigger event configuration bit of line 33 */ +#define EXTI_FTSR2_FT40_Pos (8U) +#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */ +#define EXTI_FTSR2_FT41_Pos (9U) +#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */ + +/****************** Bit definition for EXTI_SWIER2 register *****************/ +#define EXTI_SWIER2_SWI_Pos (0U) +#define EXTI_SWIER2_SWI_Msk (0x302UL << EXTI_SWIER2_SWI_Pos) /*!< 0x00000302 */ +#define EXTI_SWIER2_SWI EXTI_SWIER2_SWI_Msk /*!< Falling trigger event configuration bit */ +#define EXTI_SWIER2_SWI33_Pos (1U) +#define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */ +#define EXTI_SWIER2_SWI40_Pos (8U) +#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */ +#define EXTI_SWIER2_SWI41_Pos (9U) +#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */ + +/******************* Bit definition for EXTI_PR2 register *******************/ +#define EXTI_PR2_PIF_Pos (0U) +#define EXTI_PR2_PIF_Msk (0x302UL << EXTI_PR2_PIF_Pos) /*!< 0x00000302 */ +#define EXTI_PR2_PIF EXTI_PR2_PIF_Msk /*!< Pending bit */ +#define EXTI_PR2_PIF33_Pos (1U) +#define EXTI_PR2_PIF33_Msk (0x1UL << EXTI_PR2_PIF33_Pos) /*!< 0x00000002 */ +#define EXTI_PR2_PIF33 EXTI_PR2_PIF33_Msk /*!< Pending bit for line 33 */ +#define EXTI_PR2_PIF40_Pos (8U) +#define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */ +#define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */ +#define EXTI_PR2_PIF41_Pos (9U) +#define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */ +#define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */ + +/******************** Bits definition for EXTI_IMR1 register ****************/ +#define EXTI_IMR1_Pos (0U) +#define EXTI_IMR1_Msk (0xFFFFFFFFUL << EXTI_IMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_IMR1_IM EXTI_IMR1_Msk /*!< CPU1 wakeup with interrupt Mask on Event */ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU1 Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU1 Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU1 Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU1 Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU1 Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU1 Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU1 Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU1 Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU1 Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU1 Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU1 Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU1 Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU1 Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU1 Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU1 Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU1 Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU1 Interrupt Mask on line 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU1 Interrupt Mask on line 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU1 Interrupt Mask on line 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU1 Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< CPU1 Interrupt Mask on line 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< CPU1 Interrupt Mask on line 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU1 Interrupt Mask on line 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< CPU1 Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU1 Interrupt Mask on line 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU1 Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU1 Interrupt Mask on line 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU1 Interrupt Mask on line 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU1 Interrupt Mask on line 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< CPU1 Interrupt Mask on line 31 */ + +/******************** Bits definition for EXTI_EMR1 register ****************/ +#define EXTI_EMR1_Pos (0U) +#define EXTI_EMR1_Msk (0x003EFFFFUL << EXTI_EMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_EMR1_EM EXTI_EMR1_Msk /*!< CPU1 Event Mask */ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU1 Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU1 Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU1 Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU1 Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU1 Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU1 Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU1 Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU1 Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU1 Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU1 Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU1 Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU1 Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU1 Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU1 Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU1 Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU1 Event Mask on line 15 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU1 Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< CPU1 Event Mask on line 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU1 Event Mask on line 19 */ +#define EXTI_EMR1_EM20_Pos (20U) +#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< CPU1 Event Mask on line 20 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< CPU1 Event Mask on line 21 */ + +/******************** Bits definition for EXTI_IMR2 register ****************/ +#define EXTI_IMR2_Pos (0U) +#define EXTI_IMR2_Msk (0x0001FFFFUL << EXTI_IMR2_Pos) /*!< 0x0001FFFF */ +#define EXTI_IMR2_IM EXTI_IMR2_Msk /*!< CPU1 Interrupt Mask */ +#define EXTI_IMR2_IM33_Pos (1U) +#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU1 Interrupt Mask on line 33 */ +#define EXTI_IMR2_IM36_Pos (4U) +#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */ +#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< CPU1 Interrupt Mask on line 36 */ +#define EXTI_IMR2_IM37_Pos (5U) +#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */ +#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< CPU1 Interrupt Mask on line 37 */ +#define EXTI_IMR2_IM38_Pos (6U) +#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */ +#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< CPU1 Interrupt Mask on line 38 */ +#define EXTI_IMR2_IM39_Pos (7U) +#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */ +#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< CPU1 Interrupt Mask on line 39 */ +#define EXTI_IMR2_IM40_Pos (8U) +#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */ +#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< CPU1 Interrupt Mask on line 40 */ +#define EXTI_IMR2_IM41_Pos (9U) +#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */ +#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< CPU1 Interrupt Mask on line 41 */ +#define EXTI_IMR2_IM42_Pos (10U) +#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */ +#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< CPU1 Interrupt Mask on line 42 */ +#define EXTI_IMR2_IM43_Pos (11U) +#define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */ +#define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< CPU1 Interrupt Mask on line 43 */ +#define EXTI_IMR2_IM44_Pos (12U) +#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */ +#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< CPU1 Interrupt Mask on line 44 */ +#define EXTI_IMR2_IM45_Pos (13U) +#define EXTI_IMR2_IM45_Msk (0x1UL << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */ +#define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< CPU1 Interrupt Mask on line 45 */ +#define EXTI_IMR2_IM46_Pos (14U) +#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */ +#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< CPU1 Interrupt Mask on line 46 */ +#define EXTI_IMR2_IM48_Pos (16U) +#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */ +#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< CPU1 Interrupt Mask on line 48 */ + +/******************** Bits definition for EXTI_EMR2 register ****************/ +#define EXTI_EMR2_Pos (0U) +#define EXTI_EMR2_Msk (0x00000300UL << EXTI_EMR2_Pos) /*!< 0x000003000 */ +#define EXTI_EMR2_EM EXTI_EMR2_Msk /*!< CPU1 Interrupt Mask */ +#define EXTI_EMR2_EM40_Pos (8U) +#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */ +#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< CPU1 Event Mask on line 40 */ +#define EXTI_EMR2_EM41_Pos (9U) +#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */ +#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< CPU1 Event Mask on line 41 */ + +/******************** Bits definition for EXTI_C2IMR1 register **************/ +#define EXTI_C2IMR1_Pos (0U) +#define EXTI_C2IMR1_Msk (0xFFFFFFFFUL << EXTI_C2IMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_C2IMR1_IM EXTI_C2IMR1_Msk /*!< CPU2 wakeup with interrupt Mask on Event */ +#define EXTI_C2IMR1_IM0_Pos (0U) +#define EXTI_C2IMR1_IM0_Msk (0x1UL << EXTI_C2IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_C2IMR1_IM0 EXTI_C2IMR1_IM0_Msk /*!< CPU2 Interrupt Mask on line 0 */ +#define EXTI_C2IMR1_IM1_Pos (1U) +#define EXTI_C2IMR1_IM1_Msk (0x1UL << EXTI_C2IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_C2IMR1_IM1 EXTI_C2IMR1_IM1_Msk /*!< CPU2 Interrupt Mask on line 1 */ +#define EXTI_C2IMR1_IM2_Pos (2U) +#define EXTI_C2IMR1_IM2_Msk (0x1UL << EXTI_C2IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_C2IMR1_IM2 EXTI_C2IMR1_IM2_Msk /*!< CPU2 Interrupt Mask on line 2 */ +#define EXTI_C2IMR1_IM3_Pos (3U) +#define EXTI_C2IMR1_IM3_Msk (0x1UL << EXTI_C2IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_C2IMR1_IM3 EXTI_C2IMR1_IM3_Msk /*!< CPU2 Interrupt Mask on line 3 */ +#define EXTI_C2IMR1_IM4_Pos (4U) +#define EXTI_C2IMR1_IM4_Msk (0x1UL << EXTI_C2IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_C2IMR1_IM4 EXTI_C2IMR1_IM4_Msk /*!< CPU2 Interrupt Mask on line 4 */ +#define EXTI_C2IMR1_IM5_Pos (5U) +#define EXTI_C2IMR1_IM5_Msk (0x1UL << EXTI_C2IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_C2IMR1_IM5 EXTI_C2IMR1_IM5_Msk /*!< CPU2 Interrupt Mask on line 5 */ +#define EXTI_C2IMR1_IM6_Pos (6U) +#define EXTI_C2IMR1_IM6_Msk (0x1UL << EXTI_C2IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_C2IMR1_IM6 EXTI_C2IMR1_IM6_Msk /*!< CPU2 Interrupt Mask on line 6 */ +#define EXTI_C2IMR1_IM7_Pos (7U) +#define EXTI_C2IMR1_IM7_Msk (0x1UL << EXTI_C2IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_C2IMR1_IM7 EXTI_C2IMR1_IM7_Msk /*!< CPU2 Interrupt Mask on line 7 */ +#define EXTI_C2IMR1_IM8_Pos (8U) +#define EXTI_C2IMR1_IM8_Msk (0x1UL << EXTI_C2IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_C2IMR1_IM8 EXTI_C2IMR1_IM8_Msk /*!< CPU2 Interrupt Mask on line 8 */ +#define EXTI_C2IMR1_IM9_Pos (9U) +#define EXTI_C2IMR1_IM9_Msk (0x1UL << EXTI_C2IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_C2IMR1_IM9 EXTI_C2IMR1_IM9_Msk /*!< CPU2 Interrupt Mask on line 9 */ +#define EXTI_C2IMR1_IM10_Pos (10U) +#define EXTI_C2IMR1_IM10_Msk (0x1UL << EXTI_C2IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_C2IMR1_IM10 EXTI_C2IMR1_IM10_Msk /*!< CPU2 Interrupt Mask on line 10 */ +#define EXTI_C2IMR1_IM11_Pos (11U) +#define EXTI_C2IMR1_IM11_Msk (0x1UL << EXTI_C2IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_C2IMR1_IM11 EXTI_C2IMR1_IM11_Msk /*!< CPU2 Interrupt Mask on line 11 */ +#define EXTI_C2IMR1_IM12_Pos (12U) +#define EXTI_C2IMR1_IM12_Msk (0x1UL << EXTI_C2IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_C2IMR1_IM12 EXTI_C2IMR1_IM12_Msk /*!< CPU2 Interrupt Mask on line 12 */ +#define EXTI_C2IMR1_IM13_Pos (13U) +#define EXTI_C2IMR1_IM13_Msk (0x1UL << EXTI_C2IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_C2IMR1_IM13 EXTI_C2IMR1_IM13_Msk /*!< CPU2 Interrupt Mask on line 13 */ +#define EXTI_C2IMR1_IM14_Pos (14U) +#define EXTI_C2IMR1_IM14_Msk (0x1UL << EXTI_C2IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_C2IMR1_IM14 EXTI_C2IMR1_IM14_Msk /*!< CPU2 Interrupt Mask on line 14 */ +#define EXTI_C2IMR1_IM15_Pos (15U) +#define EXTI_C2IMR1_IM15_Msk (0x1UL << EXTI_C2IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_C2IMR1_IM15 EXTI_C2IMR1_IM15_Msk /*!< CPU2 Interrupt Mask on line 15 */ +#define EXTI_C2IMR1_IM16_Pos (16U) +#define EXTI_C2IMR1_IM16_Msk (0x1UL << EXTI_C2IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_C2IMR1_IM16 EXTI_C2IMR1_IM16_Msk /*!< CPU2 Interrupt Mask on line 16 */ +#define EXTI_C2IMR1_IM17_Pos (17U) +#define EXTI_C2IMR1_IM17_Msk (0x1UL << EXTI_C2IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_C2IMR1_IM17 EXTI_C2IMR1_IM17_Msk /*!< CPU2 Interrupt Mask on line 17 */ +#define EXTI_C2IMR1_IM18_Pos (18U) +#define EXTI_C2IMR1_IM18_Msk (0x1UL << EXTI_C2IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_C2IMR1_IM18 EXTI_C2IMR1_IM18_Msk /*!< CPU2 Interrupt Mask on line 18 */ +#define EXTI_C2IMR1_IM19_Pos (19U) +#define EXTI_C2IMR1_IM19_Msk (0x1UL << EXTI_C2IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_C2IMR1_IM19 EXTI_C2IMR1_IM19_Msk /*!< CPU2 Interrupt Mask on line 19 */ +#define EXTI_C2IMR1_IM20_Pos (20U) +#define EXTI_C2IMR1_IM20_Msk (0x1UL << EXTI_C2IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_C2IMR1_IM20 EXTI_C2IMR1_IM20_Msk /*!< CPU2 Interrupt Mask on line 20 */ +#define EXTI_C2IMR1_IM21_Pos (21U) +#define EXTI_C2IMR1_IM21_Msk (0x1UL << EXTI_C2IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_C2IMR1_IM21 EXTI_C2IMR1_IM21_Msk /*!< CPU2 Interrupt Mask on line 21 */ +#define EXTI_C2IMR1_IM22_Pos (22U) +#define EXTI_C2IMR1_IM22_Msk (0x1UL << EXTI_C2IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_C2IMR1_IM22 EXTI_C2IMR1_IM22_Msk /*!< CPU2 Interrupt Mask on line 22 */ +#define EXTI_C2IMR1_IM23_Pos (23U) +#define EXTI_C2IMR1_IM23_Msk (0x1UL << EXTI_C2IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_C2IMR1_IM23 EXTI_C2IMR1_IM23_Msk /*!< CPU2 Interrupt Mask on line 23 */ +#define EXTI_C2IMR1_IM24_Pos (24U) +#define EXTI_C2IMR1_IM24_Msk (0x1UL << EXTI_C2IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_C2IMR1_IM24 EXTI_C2IMR1_IM24_Msk /*!< CPU2 Interrupt Mask on line 24 */ +#define EXTI_C2IMR1_IM25_Pos (25U) +#define EXTI_C2IMR1_IM25_Msk (0x1UL << EXTI_C2IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_C2IMR1_IM25 EXTI_C2IMR1_IM25_Msk /*!< CPU2 Interrupt Mask on line 25 */ +#define EXTI_C2IMR1_IM28_Pos (28U) +#define EXTI_C2IMR1_IM28_Msk (0x1UL << EXTI_C2IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_C2IMR1_IM28 EXTI_C2IMR1_IM28_Msk /*!< CPU2 Interrupt Mask on line 28 */ +#define EXTI_C2IMR1_IM29_Pos (29U) +#define EXTI_C2IMR1_IM29_Msk (0x1UL << EXTI_C2IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_C2IMR1_IM29 EXTI_C2IMR1_IM29_Msk /*!< CPU2 Interrupt Mask on line 29 */ +#define EXTI_C2IMR1_IM30_Pos (30U) +#define EXTI_C2IMR1_IM30_Msk (0x1UL << EXTI_C2IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_C2IMR1_IM30 EXTI_C2IMR1_IM30_Msk /*!< CPU2 Interrupt Mask on line 30 */ +#define EXTI_C2IMR1_IM31_Pos (31U) +#define EXTI_C2IMR1_IM31_Msk (0x1UL << EXTI_C2IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_C2IMR1_IM31 EXTI_C2IMR1_IM31_Msk /*!< CPU2 Interrupt Mask on line 31 */ +/******************** Bits definition for EXTI_C2EMR1 register **************/ +#define EXTI_C2EMR1_Pos (0U) +#define EXTI_C2EMR1_Msk (0x003EFFFFUL << EXTI_C2EMR1_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_C2EMR1_EM EXTI_C2EMR1_Msk /*!< CPU2 Event Mask */ +#define EXTI_C2EMR1_EM0_Pos (0U) +#define EXTI_C2EMR1_EM0_Msk (0x1UL << EXTI_C2EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_C2EMR1_EM0 EXTI_C2EMR1_EM0_Msk /*!< CPU2 Event Mask on line 0 */ +#define EXTI_C2EMR1_EM1_Pos (1U) +#define EXTI_C2EMR1_EM1_Msk (0x1UL << EXTI_C2EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_C2EMR1_EM1 EXTI_C2EMR1_EM1_Msk /*!< CPU2 Event Mask on line 1 */ +#define EXTI_C2EMR1_EM2_Pos (2U) +#define EXTI_C2EMR1_EM2_Msk (0x1UL << EXTI_C2EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_C2EMR1_EM2 EXTI_C2EMR1_EM2_Msk /*!< CPU2 Event Mask on line 2 */ +#define EXTI_C2EMR1_EM3_Pos (3U) +#define EXTI_C2EMR1_EM3_Msk (0x1UL << EXTI_C2EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_C2EMR1_EM3 EXTI_C2EMR1_EM3_Msk /*!< CPU2 Event Mask on line 3 */ +#define EXTI_C2EMR1_EM4_Pos (4U) +#define EXTI_C2EMR1_EM4_Msk (0x1UL << EXTI_C2EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_C2EMR1_EM4 EXTI_C2EMR1_EM4_Msk /*!< CPU2 Event Mask on line 4 */ +#define EXTI_C2EMR1_EM5_Pos (5U) +#define EXTI_C2EMR1_EM5_Msk (0x1UL << EXTI_C2EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_C2EMR1_EM5 EXTI_C2EMR1_EM5_Msk /*!< CPU2 Event Mask on line 5 */ +#define EXTI_C2EMR1_EM6_Pos (6U) +#define EXTI_C2EMR1_EM6_Msk (0x1UL << EXTI_C2EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_C2EMR1_EM6 EXTI_C2EMR1_EM6_Msk /*!< CPU2 Event Mask on line 6 */ +#define EXTI_C2EMR1_EM7_Pos (7U) +#define EXTI_C2EMR1_EM7_Msk (0x1UL << EXTI_C2EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_C2EMR1_EM7 EXTI_C2EMR1_EM7_Msk /*!< CPU2 Event Mask on line 7 */ +#define EXTI_C2EMR1_EM8_Pos (8U) +#define EXTI_C2EMR1_EM8_Msk (0x1UL << EXTI_C2EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_C2EMR1_EM8 EXTI_C2EMR1_EM8_Msk /*!< CPU2 Event Mask on line 8 */ +#define EXTI_C2EMR1_EM9_Pos (9U) +#define EXTI_C2EMR1_EM9_Msk (0x1UL << EXTI_C2EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_C2EMR1_EM9 EXTI_C2EMR1_EM9_Msk /*!< CPU2 Event Mask on line 9 */ +#define EXTI_C2EMR1_EM10_Pos (10U) +#define EXTI_C2EMR1_EM10_Msk (0x1UL << EXTI_C2EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_C2EMR1_EM10 EXTI_C2EMR1_EM10_Msk /*!< CPU2 Event Mask on line 10 */ +#define EXTI_C2EMR1_EM11_Pos (11U) +#define EXTI_C2EMR1_EM11_Msk (0x1UL << EXTI_C2EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_C2EMR1_EM11 EXTI_C2EMR1_EM11_Msk /*!< CPU2 Event Mask on line 11 */ +#define EXTI_C2EMR1_EM12_Pos (12U) +#define EXTI_C2EMR1_EM12_Msk (0x1UL << EXTI_C2EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_C2EMR1_EM12 EXTI_C2EMR1_EM12_Msk /*!< CPU2 Event Mask on line 12 */ +#define EXTI_C2EMR1_EM13_Pos (13U) +#define EXTI_C2EMR1_EM13_Msk (0x1UL << EXTI_C2EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_C2EMR1_EM13 EXTI_C2EMR1_EM13_Msk /*!< CPU2 Event Mask on line 13 */ +#define EXTI_C2EMR1_EM14_Pos (14U) +#define EXTI_C2EMR1_EM14_Msk (0x1UL << EXTI_C2EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_C2EMR1_EM14 EXTI_C2EMR1_EM14_Msk /*!< CPU2 Event Mask on line 14 */ +#define EXTI_C2EMR1_EM15_Pos (15U) +#define EXTI_C2EMR1_EM15_Msk (0x1UL << EXTI_C2EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_C2EMR1_EM15 EXTI_C2EMR1_EM15_Msk /*!< CPU2 Event Mask on line 15 */ +#define EXTI_C2EMR1_EM17_Pos (17U) +#define EXTI_C2EMR1_EM17_Msk (0x1UL << EXTI_C2EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_C2EMR1_EM17 EXTI_C2EMR1_EM17_Msk /*!< CPU2 Event Mask on line 17 */ +#define EXTI_C2EMR1_EM18_Pos (18U) +#define EXTI_C2EMR1_EM18_Msk (0x1UL << EXTI_C2EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_C2EMR1_EM18 EXTI_C2EMR1_EM18_Msk /*!< CPU2 Event Mask on line 18 */ +#define EXTI_C2EMR1_EM19_Pos (19U) +#define EXTI_C2EMR1_EM19_Msk (0x1UL << EXTI_C2EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_C2EMR1_EM19 EXTI_C2EMR1_EM19_Msk /*!< CPU2 Event Mask on line 19 */ +#define EXTI_C2EMR1_EM20_Pos (20U) +#define EXTI_C2EMR1_EM20_Msk (0x1UL << EXTI_C2EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_C2EMR1_EM20 EXTI_C2EMR1_EM20_Msk /*!< CPU2 Event Mask on line 20 */ +#define EXTI_C2EMR1_EM21_Pos (21U) +#define EXTI_C2EMR1_EM21_Msk (0x1UL << EXTI_C2EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_C2EMR1_EM21 EXTI_C2EMR1_EM21_Msk /*!< CPU2 Event Mask on line 21 */ + +/******************** Bits definition for EXTI_C2IMR2 register **************/ +#define EXTI_C2IMR2_Pos (0U) +#define EXTI_C2IMR2_Msk (0x0001FFFFUL << EXTI_C2IMR2_Pos) /*!< 0x0001FFFF */ +#define EXTI_C2IMR2_IM EXTI_C2IMR2_Msk /*!< CPU2 Interrupt Mask */ +#define EXTI_C2IMR2_IM33_Pos (1U) +#define EXTI_C2IMR2_IM33_Msk (0x1UL << EXTI_C2IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_C2IMR2_IM33 EXTI_C2IMR2_IM33_Msk /*!< CPU2 Interrupt Mask on line 33 */ +#define EXTI_C2IMR2_IM36_Pos (4U) +#define EXTI_C2IMR2_IM36_Msk (0x1UL << EXTI_C2IMR2_IM36_Pos) /*!< 0x00000010 */ +#define EXTI_C2IMR2_IM36 EXTI_C2IMR2_IM36_Msk /*!< CPU2 Interrupt Mask on line 36 */ +#define EXTI_C2IMR2_IM37_Pos (5U) +#define EXTI_C2IMR2_IM37_Msk (0x1UL << EXTI_C2IMR2_IM37_Pos) /*!< 0x00000020 */ +#define EXTI_C2IMR2_IM37 EXTI_C2IMR2_IM37_Msk /*!< CPU2 Interrupt Mask on line 37 */ +#define EXTI_C2IMR2_IM38_Pos (6U) +#define EXTI_C2IMR2_IM38_Msk (0x1UL << EXTI_C2IMR2_IM38_Pos) /*!< 0x00000040 */ +#define EXTI_C2IMR2_IM38 EXTI_C2IMR2_IM38_Msk /*!< CPU2 Interrupt Mask on line 38 */ +#define EXTI_C2IMR2_IM39_Pos (7U) +#define EXTI_C2IMR2_IM39_Msk (0x1UL << EXTI_C2IMR2_IM39_Pos) /*!< 0x00000080 */ +#define EXTI_C2IMR2_IM39 EXTI_C2IMR2_IM39_Msk /*!< CPU2 Interrupt Mask on line 39 */ +#define EXTI_C2IMR2_IM40_Pos (8U) +#define EXTI_C2IMR2_IM40_Msk (0x1UL << EXTI_C2IMR2_IM40_Pos) /*!< 0x00000100 */ +#define EXTI_C2IMR2_IM40 EXTI_C2IMR2_IM40_Msk /*!< CPU2 Interrupt Mask on line 40 */ +#define EXTI_C2IMR2_IM41_Pos (9U) +#define EXTI_C2IMR2_IM41_Msk (0x1UL << EXTI_C2IMR2_IM41_Pos) /*!< 0x00000200 */ +#define EXTI_C2IMR2_IM41 EXTI_C2IMR2_IM41_Msk /*!< CPU2 Interrupt Mask on line 41 */ +#define EXTI_C2IMR2_IM42_Pos (10U) +#define EXTI_C2IMR2_IM42_Msk (0x1UL << EXTI_C2IMR2_IM42_Pos) /*!< 0x00000400 */ +#define EXTI_C2IMR2_IM42 EXTI_C2IMR2_IM42_Msk /*!< CPU2 Interrupt Mask on line 42 */ +#define EXTI_C2IMR2_IM43_Pos (11U) +#define EXTI_C2IMR2_IM43_Msk (0x1UL << EXTI_C2IMR2_IM43_Pos) /*!< 0x00000800 */ +#define EXTI_C2IMR2_IM43 EXTI_C2IMR2_IM43_Msk /*!< CPU2 Interrupt Mask on line 43 */ +#define EXTI_C2IMR2_IM44_Pos (12U) +#define EXTI_C2IMR2_IM44_Msk (0x1UL << EXTI_C2IMR2_IM44_Pos) /*!< 0x00001000 */ +#define EXTI_C2IMR2_IM44 EXTI_C2IMR2_IM44_Msk /*!< CPU2 Interrupt Mask on line 44 */ +#define EXTI_C2IMR2_IM45_Pos (13U) +#define EXTI_C2IMR2_IM45_Msk (0x1UL << EXTI_C2IMR2_IM45_Pos) /*!< 0x00002000 */ +#define EXTI_C2IMR2_IM45 EXTI_C2IMR2_IM45_Msk /*!< CPU2 Interrupt Mask on line 45 */ +#define EXTI_C2IMR2_IM46_Pos (14U) +#define EXTI_C2IMR2_IM46_Msk (0x1UL << EXTI_C2IMR2_IM46_Pos) /*!< 0x00004000 */ +#define EXTI_C2IMR2_IM46 EXTI_C2IMR2_IM46_Msk /*!< CPU2 Interrupt Mask on line 46 */ +#define EXTI_C2IMR2_IM48_Pos (16U) +#define EXTI_C2IMR2_IM48_Msk (0x1UL << EXTI_C2IMR2_IM48_Pos) /*!< 0x00010000 */ +#define EXTI_C2IMR2_IM48 EXTI_C2IMR2_IM48_Msk /*!< CPU2 Interrupt Mask on line 48 */ + +/******************** Bits definition for EXTI_C2EMR2 register **************/ +#define EXTI_C2EMR2_Pos (8U) +#define EXTI_C2EMR2_Msk (0x00000300UL << EXTI_C2EMR2_Pos) /*!< 0x000003000 */ +#define EXTI_C2EMR2_EM EXTI_C2EMR2_Msk /*!< CPU2 Interrupt Mask */ +#define EXTI_C2EMR2_EM40_Pos (8U) +#define EXTI_C2EMR2_EM40_Msk (0x1UL << EXTI_C2EMR2_EM40_Pos) /*!< 0x00000100 */ +#define EXTI_C2EMR2_EM40 EXTI_C2EMR2_EM40_Msk /*!< CPU2 Event Mask on line 40 */ +#define EXTI_C2EMR2_EM41_Pos (9U) +#define EXTI_C2EMR2_EM41_Msk (0x1UL << EXTI_C2EMR2_EM41_Pos) /*!< 0x00000200 */ +#define EXTI_C2EMR2_EM41 EXTI_C2EMR2_EM41_Msk /*!< CPU2 Event Mask on line 41 */ + +/******************************************************************************/ +/* */ +/* Public Key Accelerator (PKA) */ +/* */ +/******************************************************************************/ + +/******************* Bits definition for PKA_CR register **************/ +#define PKA_CR_EN_Pos (0U) +#define PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos) /*!< 0x00000001 */ +#define PKA_CR_EN PKA_CR_EN_Msk /*!< PKA enable */ +#define PKA_CR_START_Pos (1U) +#define PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos) /*!< 0x00000002 */ +#define PKA_CR_START PKA_CR_START_Msk /*!< Start operation */ +#define PKA_CR_MODE_Pos (8U) +#define PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos) /*!< 0x00003F00 */ +#define PKA_CR_MODE PKA_CR_MODE_Msk /*!< MODE[5:0] PKA operation code */ +#define PKA_CR_MODE_0 (0x01U << PKA_CR_MODE_Pos) /*!< 0x00000100 */ +#define PKA_CR_MODE_1 (0x02U << PKA_CR_MODE_Pos) /*!< 0x00000200 */ +#define PKA_CR_MODE_2 (0x04U << PKA_CR_MODE_Pos) /*!< 0x00000400 */ +#define PKA_CR_MODE_3 (0x08U << PKA_CR_MODE_Pos) /*!< 0x00000800 */ +#define PKA_CR_MODE_4 (0x10U << PKA_CR_MODE_Pos) /*!< 0x00001000 */ +#define PKA_CR_MODE_5 (0x20U << PKA_CR_MODE_Pos) /*!< 0x00002000 */ +#define PKA_CR_PROCENDIE_Pos (17U) +#define PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos) /*!< 0x00020000 */ +#define PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk /*!< End of operation interrupt enable */ +#define PKA_CR_RAMERRIE_Pos (19U) +#define PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos) /*!< 0x00080000 */ +#define PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk /*!< RAM error interrupt enable */ +#define PKA_CR_ADDRERRIE_Pos (20U) +#define PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos) /*!< 0x00100000 */ +#define PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk /*!< RAM error interrupt enable */ + +/******************* Bits definition for PKA_SR register **************/ +#define PKA_SR_BUSY_Pos (16U) +#define PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos) /*!< 0x00010000 */ +#define PKA_SR_BUSY PKA_SR_BUSY_Msk /*!< PKA operation is in progress */ +#define PKA_SR_PROCENDF_Pos (17U) +#define PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos) /*!< 0x00020000 */ +#define PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk /*!< PKA end of operation flag */ +#define PKA_SR_RAMERRF_Pos (19U) +#define PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos) /*!< 0x00080000 */ +#define PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk /*!< PKA RAM error flag */ +#define PKA_SR_ADDRERRF_Pos (20U) +#define PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos) /*!< 0x00100000 */ +#define PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk /*!< Address error flag */ + +/******************* Bits definition for PKA_CLRFR register **************/ +#define PKA_CLRFR_PROCENDFC_Pos (17U) +#define PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos) /*!< 0x00020000 */ +#define PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk /*!< Clear PKA end of operation flag */ +#define PKA_CLRFR_RAMERRFC_Pos (19U) +#define PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos) /*!< 0x00080000 */ +#define PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk /*!< Clear PKA RAM error flag */ +#define PKA_CLRFR_ADDRERRFC_Pos (20U) +#define PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos) /*!< 0x00100000 */ +#define PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk /*!< Clear address error flag */ + +/******************* Bits definition for PKA RAM *************************/ +#define PKA_RAM_OFFSET 0x400U /*!< PKA RAM address offset */ + +/* Compute Montgomery parameter input data */ +#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 1 */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 2 */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 3 */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Output last double X1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output last double Y1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2) /*!< Output last double Z1 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2) /*!< Output check point X2 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2) /*!< Output check point Y2 coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2) /*!< Output check point Z2 coordinate */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2) /*!< Output final point kP X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2) /*!< Output final point kP Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic substraction input data */ +#define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic substraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular substraction input data */ +#define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular substraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk /*!< Instruction cache enable */ +#define FLASH_ACR_DCEN_Pos (10U) +#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ +#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk /*!< Data cache enable */ +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk /*!< Instruction cache reset */ +#define FLASH_ACR_DCRST_Pos (12U) +#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk /*!< Data cache reset */ +#define FLASH_ACR_PES_Pos (15U) +#define FLASH_ACR_PES_Msk (0x1UL << FLASH_ACR_PES_Pos) /*!< 0x00008000 */ +#define FLASH_ACR_PES FLASH_ACR_PES_Msk /*!< Program/erase suspend request */ +#define FLASH_ACR_EMPTY_Pos (16U) +#define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Flash use area empty */ + +#define FLASH_ACR_LATENCY_0WS (0x0UL << FLASH_ACR_LATENCY_Pos) /*!< FLASH Zero wait state */ +#define FLASH_ACR_LATENCY_1WS (FLASH_ACR_LATENCY_0 << FLASH_ACR_LATENCY_Pos) /*!< FLASH One wait state */ +#define FLASH_ACR_LATENCY_2WS (FLASH_ACR_LATENCY_1 << FLASH_ACR_LATENCY_Pos) /*!< FLASH Two wait states */ +#define FLASH_ACR_LATENCY_3WS ((FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) << FLASH_ACR_LATENCY_Pos) /*!< FLASH Three wait states */ + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of Operation */ +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Operation error */ +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk /*!< Programming error */ +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */ +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming alignment error */ +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error */ +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk /*!< Fast programming data miss error */ +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk /*!< Fast programming error */ +#define FLASH_SR_OPTNV_Pos (13U) +#define FLASH_SR_OPTNV_Msk (0x1UL << FLASH_SR_OPTNV_Pos) /*!< 0x00002000 */ +#define FLASH_SR_OPTNV FLASH_SR_OPTNV_Msk /*!< User option OPTVAL indication */ +#define FLASH_SR_RDERR_Pos (14U) +#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< PCROP read error */ +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */ +#define FLASH_SR_BSY_Pos (16U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Flash Busy */ +#define FLASH_SR_CFGBSY_Pos (18U) +#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk /*!< Programming or erase configuration busy */ +#define FLASH_SR_PESD_Pos (19U) +#define FLASH_SR_PESD_Msk (0x1UL << FLASH_SR_PESD_Pos) /*!< 0x00080000 */ +#define FLASH_SR_PESD FLASH_SR_PESD_Msk /*!< Programming/erase operation suspended */ + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Flash programming */ +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page erase */ +#define FLASH_CR_MER_Pos (2U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0xFFUL << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< Page number selection mask */ +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start an erase operation */ +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk /*!< Options modification start */ +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk /*!< Fast programming */ +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error interrupt enable */ +#define FLASH_CR_RDERRIE_Pos (26U) +#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk /*!< PCROP read error interrupt enable */ +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk /*!< Options lock */ +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Flash control register lock */ + +/******************* Bits definition for FLASH_ECCR register ****************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0001FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< double-word address ECC fail */ +#define FLASH_ECCR_SYSF_ECC_Pos (20U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System flash ECC fail */ +#define FLASH_ECCR_ECCCIE_Pos (24U) +#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_CPUID_Pos (26U) +#define FLASH_ECCR_CPUID_Msk (0x7UL << FLASH_ECCR_CPUID_Pos) /*!< 0x1C000000 */ +#define FLASH_ECCR_CPUID FLASH_ECCR_CPUID_Msk /*!< CPU identification */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPTR register ****************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Read protection level */ +#define FLASH_OPTR_ESE_Pos (8U) +#define FLASH_OPTR_ESE_Msk (0x1UL << FLASH_OPTR_ESE_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_ESE FLASH_OPTR_ESE_Msk /*!< Security enable */ +#define FLASH_OPTR_BOR_LEV_Pos (9U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000E00 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset level mask */ +#define FLASH_OPTR_BOR_LEV_0 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000800 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< Reset option in Stop mode */ +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< Reset option in Standby mode */ +#define FLASH_OPTR_nRST_SHDW_Pos (14U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< Reset option in Shutdown mode */ +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter option in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter option in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_nBOOT1_Pos (23U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk /*!< Boot Configuration */ +#define FLASH_OPTR_SRAM2PE_Pos (24U) +#define FLASH_OPTR_SRAM2PE_Msk (0x1UL << FLASH_OPTR_SRAM2PE_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2PE FLASH_OPTR_SRAM2PE_Msk /*!< SRAM2 parity check enable */ +#define FLASH_OPTR_SRAM2RST_Pos (25U) +#define FLASH_OPTR_SRAM2RST_Msk (0x1UL << FLASH_OPTR_SRAM2RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2RST FLASH_OPTR_SRAM2RST_Msk /*!< SRAM2 erase option when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< BOOT0 option bit */ +#define FLASH_OPTR_AGC_TRIM_Pos (29U) +#define FLASH_OPTR_AGC_TRIM_Msk (0x7UL << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0xE0000000 */ +#define FLASH_OPTR_AGC_TRIM FLASH_OPTR_AGC_TRIM_Msk /*!< Automatic Gain Control trimming mask */ +#define FLASH_OPTR_AGC_TRIM_0 (0x1U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_AGC_TRIM_1 (0x2U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_AGC_TRIM_2 (0x4U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for FLASH_PCROP1ASR register ************/ +#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U) +#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x1FFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x000001FF */ +#define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk /*!< PCROP area A start offset */ + +/****************** Bits definition for FLASH_PCROP1AER register ************/ +#define FLASH_PCROP1AER_PCROP1A_END_Pos (0U) +#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x1FFUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x000001FF */ +#define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk /*!< PCROP area A end offset */ +#define FLASH_PCROP1AER_PCROP_RDP_Pos (31U) +#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */ +#define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk /*!< PCROP area preserved when RDP level decreased */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk /*!< WRP area A start offset */ +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk /*!< WRP area A end offset */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk /*!< WRP area B start offset */ +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk /*!< WRP area B end offset */ + +/****************** Bits definition for FLASH_PCROP1BSR register ************/ +#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U) +#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x1FFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x000001FF */ +#define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk /*!< PCROP area B start offset */ + +/****************** Bits definition for FLASH_PCROP1BER register ************/ +#define FLASH_PCROP1BER_PCROP1B_END_Pos (0U) +#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x1FFUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x000001FF */ +#define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk /*!< PCROP area B end offset */ + +/****************** Bits definition for FLASH_IPCCBR register ************/ +#define FLASH_IPCCBR_IPCCDBA_Pos (0U) +#define FLASH_IPCCBR_IPCCDBA_Msk (0x3FFFUL << FLASH_IPCCBR_IPCCDBA_Pos) /*!< 0x00003FFF */ +#define FLASH_IPCCBR_IPCCDBA FLASH_IPCCBR_IPCCDBA_Msk /*!< IPCC data buffer base address */ + +/****************** Bits definition for FLASH_SFR register ************/ +#define FLASH_SFR_SFSA_Pos (0U) +#define FLASH_SFR_SFSA_Msk (0xFFUL << FLASH_SFR_SFSA_Pos) /*!< 0x000000FF */ +#define FLASH_SFR_SFSA FLASH_SFR_SFSA_Msk /* Secure flash start address */ +#define FLASH_SFR_FSD_Pos (8U) +#define FLASH_SFR_FSD_Msk (0x1UL << FLASH_SFR_FSD_Pos) /*!< 0x00000100 */ +#define FLASH_SFR_FSD FLASH_SFR_FSD_Msk /* Flash mode secure */ +#define FLASH_SFR_DDS_Pos (12U) +#define FLASH_SFR_DDS_Msk (0x1UL << FLASH_SFR_DDS_Pos) /*!< 0x00001000 */ +#define FLASH_SFR_DDS FLASH_SFR_DDS_Msk /* Enabling and disabling CPU2 Debug access */ + +/****************** Bits definition for FLASH_SRRVR register ************/ +#define FLASH_SRRVR_SBRV_Pos (0U) +#define FLASH_SRRVR_SBRV_Msk (0x3FFFFUL << FLASH_SRRVR_SBRV_Pos) /*!< 0x0003FFFF */ +#define FLASH_SRRVR_SBRV FLASH_SRRVR_SBRV_Msk /* SCPU2 boot reset vector memory offset */ + +#define FLASH_SRRVR_SBRSA_Pos (18U) +#define FLASH_SRRVR_SBRSA_Msk (0x1FUL << FLASH_SRRVR_SBRSA_Pos) /*!< 0x007C0000 */ +#define FLASH_SRRVR_SBRSA FLASH_SRRVR_SBRSA_Msk /* Secure backup SRAM2a start address */ +#define FLASH_SRRVR_BRSD_Pos (23U) +#define FLASH_SRRVR_BRSD_Msk (0x1UL << FLASH_SRRVR_BRSD_Pos) /*!< 0x00800000 */ +#define FLASH_SRRVR_BRSD FLASH_SRRVR_BRSD_Msk /* Backup SRAM2A secure mode */ + +#define FLASH_SRRVR_SNBRSA_Pos (25U) +#define FLASH_SRRVR_SNBRSA_Msk (0x1FUL << FLASH_SRRVR_SNBRSA_Pos) /*!< 0x3E000000 */ +#define FLASH_SRRVR_SNBRSA FLASH_SRRVR_SNBRSA_Msk /* Secure non-backup SRAM2b start address */ +#define FLASH_SRRVR_NBRSD_Pos (30U) +#define FLASH_SRRVR_NBRSD_Msk (0x1UL << FLASH_SRRVR_NBRSD_Pos) /*!< 0x40000000 */ +#define FLASH_SRRVR_NBRSD FLASH_SRRVR_NBRSD_Msk /* Non-backup SRAM2B secure mode */ +#define FLASH_SRRVR_C2OPT_Pos (31U) +#define FLASH_SRRVR_C2OPT_Msk (0x1UL << FLASH_SRRVR_C2OPT_Pos) /*!< 0x80000000 */ +#define FLASH_SRRVR_C2OPT FLASH_SRRVR_C2OPT_Msk /* SCPU2 boot reset vector memory selection */ + +/****************** Bits definition for FLASH_C2ACR register ************/ +#define FLASH_C2ACR_PRFTEN_Pos (8U) +#define FLASH_C2ACR_PRFTEN_Msk (0x1UL << FLASH_C2ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_C2ACR_PRFTEN FLASH_C2ACR_PRFTEN_Msk /*!< CPU2 Prefetch enable */ +#define FLASH_C2ACR_ICEN_Pos (9U) +#define FLASH_C2ACR_ICEN_Msk (0x1UL << FLASH_C2ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_C2ACR_ICEN FLASH_C2ACR_ICEN_Msk /*!< CPU2 Instruction cache enable */ +#define FLASH_C2ACR_ICRST_Pos (11U) +#define FLASH_C2ACR_ICRST_Msk (0x1UL << FLASH_C2ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_C2ACR_ICRST FLASH_C2ACR_ICRST_Msk /*!< CPU2 Instruction cache reset */ +#define FLASH_C2ACR_PES_Pos (15U) +#define FLASH_C2ACR_PES_Msk (0x1UL << FLASH_C2ACR_PES_Pos) /*!< 0x00008000 */ +#define FLASH_C2ACR_PES FLASH_C2ACR_PES_Msk /*!< CPU2 Program/erase suspend request */ + +/****************** Bits definition for FLASH_C2SR register ************/ +#define FLASH_C2SR_EOP_Pos (0U) +#define FLASH_C2SR_EOP_Msk (0x1UL << FLASH_C2SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_C2SR_EOP FLASH_C2SR_EOP_Msk /*!< CPU2 End of operation */ +#define FLASH_C2SR_OPERR_Pos (1U) +#define FLASH_C2SR_OPERR_Msk (0x1UL << FLASH_C2SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_C2SR_OPERR FLASH_C2SR_OPERR_Msk /*!< CPU2 Operation error */ +#define FLASH_C2SR_PROGERR_Pos (3U) +#define FLASH_C2SR_PROGERR_Msk (0x1UL << FLASH_C2SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_C2SR_PROGERR FLASH_C2SR_PROGERR_Msk /*!< CPU2 Programming error */ +#define FLASH_C2SR_WRPERR_Pos (4U) +#define FLASH_C2SR_WRPERR_Msk (0x1UL << FLASH_C2SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_C2SR_WRPERR FLASH_C2SR_WRPERR_Msk /*!< CPU2 Write protection error */ +#define FLASH_C2SR_PGAERR_Pos (5U) +#define FLASH_C2SR_PGAERR_Msk (0x1UL << FLASH_C2SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_C2SR_PGAERR FLASH_C2SR_PGAERR_Msk /*!< CPU2 Programming alignment error */ +#define FLASH_C2SR_SIZERR_Pos (6U) +#define FLASH_C2SR_SIZERR_Msk (0x1UL << FLASH_C2SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_C2SR_SIZERR FLASH_C2SR_SIZERR_Msk /*!< CPU2 Size error */ +#define FLASH_C2SR_PGSERR_Pos (7U) +#define FLASH_C2SR_PGSERR_Msk (0x1UL << FLASH_C2SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_C2SR_PGSERR FLASH_C2SR_PGSERR_Msk /*!< CPU2 Programming sequence error */ +#define FLASH_C2SR_MISERR_Pos (8U) +#define FLASH_C2SR_MISERR_Msk (0x1UL << FLASH_C2SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_C2SR_MISERR FLASH_C2SR_MISERR_Msk /*!< CPU2 Fast programming data miss error */ +#define FLASH_C2SR_FASTERR_Pos (9U) +#define FLASH_C2SR_FASTERR_Msk (0x1UL << FLASH_C2SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_C2SR_FASTERR FLASH_C2SR_FASTERR_Msk /*!< CPU2 Fast programming error */ +#define FLASH_C2SR_RDERR_Pos (14U) +#define FLASH_C2SR_RDERR_Msk (0x1UL << FLASH_C2SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_C2SR_RDERR FLASH_C2SR_RDERR_Msk /*!< CPU2 PCROP read error */ +#define FLASH_C2SR_BSY_Pos (16U) +#define FLASH_C2SR_BSY_Msk (0x1UL << FLASH_C2SR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_C2SR_BSY FLASH_C2SR_BSY_Msk /*!< CPU2 Flash busy */ +#define FLASH_C2SR_CFGBSY_Pos (18U) +#define FLASH_C2SR_CFGBSY_Msk (0x1UL << FLASH_C2SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_C2SR_CFGBSY FLASH_C2SR_CFGBSY_Msk /*!< CPU2 Programming or erase configuration busy */ +#define FLASH_C2SR_PESD_Pos (19U) +#define FLASH_C2SR_PESD_Msk (0x1UL << FLASH_C2SR_PESD_Pos) /*!< 0x00080000 */ +#define FLASH_C2SR_PESD FLASH_C2SR_PESD_Msk /*!< CPU2 Programming/erase operation suspended */ + +/****************** Bits definition for FLASH_C2CR register ************/ +#define FLASH_C2CR_PG_Pos (0U) +#define FLASH_C2CR_PG_Msk (0x1UL << FLASH_C2CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_C2CR_PG FLASH_C2CR_PG_Msk /*!< CPU2 Flash programming */ +#define FLASH_C2CR_PER_Pos (1U) +#define FLASH_C2CR_PER_Msk (0x1UL << FLASH_C2CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_C2CR_PER FLASH_C2CR_PER_Msk /*!< CPU2 Page erase */ +#define FLASH_C2CR_MER_Pos (2U) +#define FLASH_C2CR_MER_Msk (0x1UL << FLASH_C2CR_MER_Pos) /*!< 0x00000004 */ +#define FLASH_C2CR_MER FLASH_C2CR_MER_Msk /*!< CPU2 Mass erase */ +#define FLASH_C2CR_PNB_Pos (3U) +#define FLASH_C2CR_PNB_Msk (0xFFUL << FLASH_C2CR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_C2CR_PNB FLASH_C2CR_PNB_Msk /*!< CPU2 Page number selection mask */ +#define FLASH_C2CR_STRT_Pos (16U) +#define FLASH_C2CR_STRT_Msk (0x1UL << FLASH_C2CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_C2CR_STRT FLASH_C2CR_STRT_Msk /*!< CPU2 Start an erase operation */ +#define FLASH_C2CR_FSTPG_Pos (18U) +#define FLASH_C2CR_FSTPG_Msk (0x1UL << FLASH_C2CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_C2CR_FSTPG FLASH_C2CR_FSTPG_Msk /*!< CPU2 Fast programming */ +#define FLASH_C2CR_EOPIE_Pos (24U) +#define FLASH_C2CR_EOPIE_Msk (0x1UL << FLASH_C2CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_C2CR_EOPIE FLASH_C2CR_EOPIE_Msk /*!< CPU2 End of operation interrupt enable */ +#define FLASH_C2CR_ERRIE_Pos (25U) +#define FLASH_C2CR_ERRIE_Msk (0x1UL << FLASH_C2CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_C2CR_ERRIE FLASH_C2CR_ERRIE_Msk /*!< CPU2 Error interrupt enable */ +#define FLASH_C2CR_RDERRIE_Pos (26U) +#define FLASH_C2CR_RDERRIE_Msk (0x1UL << FLASH_C2CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_C2CR_RDERRIE FLASH_C2CR_RDERRIE_Msk /*!< CPU2 PCROP read error interrupt enable */ + +/******************************************************************************/ +/* */ +/* General Purpose I/O */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/******************************************************************************/ +/* */ +/* HSEM HW Semaphore */ +/* */ +/******************************************************************************/ +/******************** Bit definition for HSEM_R register ********************/ +#define HSEM_R_PROCID_Pos (0U) +#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */ +#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!Purpose

This driver provides the CMSIS device for the stm32wbxx products. This covers

  • STM32WB55xx devices
    • +
  • STM32WB5Mxx devices
  • STM32WB50xx devices
    • +
  • STM32WB35xx devices
    • +
  • STM32WB30xx devices

This driver is composed of the descriptions of the registers under “Include” directory.

Various template file are provided to easily build an application. They can be adapted to fit applications requirements.

@@ -45,13 +48,68 @@

Purpose

  • Startup files are provided as example for IAR©, KEIL© and SW4STM32©.
  • Linker files are provided as example for IAR©, KEIL© and SW4STM32©.
    • +

    Specific consideration for available FLASH size inside linker file

    +

    The available flash size depends on the wireless binary used inside the STM32WB device.

    +

    The linker files templates for IAR, KEIL and GCC provide example of implementation which can be tuned.

    +

    You can refer to the below chapters to optimize the usage of the flash on your device.

    +

    STM32WB55xx, STM32WB50xx and STM32WB5M

    +

    The default linker file provided in “/Drivers/CMSIS/DeviceST/STM32WBxx/Source/Templates” allows the application to use 512KB of flash.

    +

    The maximum flash memory that can be used by the application is up to the Secure Flash Start Address (SFSA) that can be read from the option byte.

    +

    The __ICFEDIT_region_ROM_end__ in the linker can be modified with a value up to : (0x08000000 + (SFSA << 12)) - 1.

    +

    Example:

    +
      +
    • When the SFSA option byte is set to 0xA0, the maximum value to be used for __ICFEDIT_region_ROM_end is 0x0809FFFF which is 640KB of flash.
      • +
    +

    Note:

    +
      +
    • The SFSA option byte can only be set by the CPU2. The user cannot modify that value.
      • +
    +

    STM32WB35xx and STM32WB30xx

    +

    The default linker file provided in "/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates allows the application to use 120KB of flash.

    +

    The maximum flash memory that can be used by the application is up to the Secure Flash Start Address (SFSA) that can be read from the option byte.

    +

    The __ICFEDIT_region_ROM_end__ in the linker can be modified with a value up to : (0x08000000 + (SFSA << 12)) - 1.

    +

    Example:

    +
      +
    • When the SFSA option byte is set to 0x32, the maximum value to be used for __ICFEDIT_region_ROM_end is 0x08031FFF – which is 200KB of flash
      • +
    +

    Note:

    +
      +
    • The SFSA option byte can only be set by the CPU2. The user cannot modify that value.
      • +

    Update History

    - +

    Main Changes

    +

    Introduction of STM32WB35xx, STM32WB30xx and STM32WB5Mxx product

    +

    This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.

    +

    Added features:

    +
      +
    • Templates/system_stm32wbxx.c contains the initialization code referred as SystemInit.
      • +
    • Startup files are provided as example for IAR©, KEIL© and SW4STM32©.
      • +
    • Linker files are provided as example for IAR©, KEIL© and SW4STM32©.
      • +
    • The product STM32WB5Mxx is supported by enabling inside your project the define “STM32WB5Mxx”.
      • +
    • The product STM32WB35xx is supported by enabling inside your project the define “STM32WB35xx”.
      • +
    • The product STM32WB30xx is supported by enabling inside your project the define “STM32WB30xx”.
      • +
    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • +
    • System Workbench STM32 (SW4STM32) toolchain V2.7
      • +
    +

    Supported Devices and boards

    +
      +
    • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx and STM32WB30xx devices.
      • +
    +
    +
    +
    + +
    +

    Main Changes

    Maintenance release for STM32WBxx devices (stm32wb55xx and stm32wb50xx devices)

    @@ -74,13 +132,13 @@

    Main Changes

    -

    Development Toolchains and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • System Workbench STM32 (SW4STM32) toolchain V2.7
    -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx, STM32WB50xx devices
    @@ -89,18 +147,18 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Introduction of STM32WB50xx device

    First release for STM32WBxx CMSIS introducing stm32wb50xx devices.

    Contents

    CMSIS devices files for stm32wb55xx, stm32wb50xx devices.

    -

    Development Toolchains and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • System Workbench STM32 (SW4STM32) toolchain V2.7
    -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx and STM32WB50xx devices
    @@ -109,7 +167,7 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Maintenance release

    Maintenance release for STM32WBxx devices (stm32wb55xx devices)

    @@ -133,7 +191,7 @@

    Maintenance release

    -

    Main Changes

    +

    Main Changes

    First release

    Add support of STM32WB55xx.

    diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb30xx_flash_cm4.ld b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb30xx_flash_cm4.ld new file mode 100644 index 0000000000..4d0a213397 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb30xx_flash_cm4.ld @@ -0,0 +1,185 @@ +/** +***************************************************************************** +** +** File : stm32wb30xx_flash_cm4.ld +** +** Abstract : System Workbench Minimal System calls file +** +** For more information about which c-functions +** need which of these lowlevel functions +** please consult the Newlib libc-manual +** +** Environment : System Workbench for MCU +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** +**

    © COPYRIGHT(c) 2019 Ac6

    +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of Ac6 nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20008000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K +RAM1 (xrw) : ORIGIN = 0x20000004, LENGTH = 0x7FFC +RAM_SHARED (xrw) : ORIGIN = 0x20008000, LENGTH = 10K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM1 AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM1 + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM1 + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED + MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED + MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb35xx_flash_cm4.ld b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb35xx_flash_cm4.ld new file mode 100644 index 0000000000..f7891e17fe --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb35xx_flash_cm4.ld @@ -0,0 +1,185 @@ +/** +***************************************************************************** +** +** File : stm32wb35xx_flash_cm4.ld +** +** Abstract : System Workbench Minimal System calls file +** +** For more information about which c-functions +** need which of these lowlevel functions +** please consult the Newlib libc-manual +** +** Environment : System Workbench for MCU +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** +**

    © COPYRIGHT(c) 2019 Ac6

    +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of Ac6 nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20008000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K +RAM1 (xrw) : ORIGIN = 0x20000004, LENGTH = 0x7FFC +RAM_SHARED (xrw) : ORIGIN = 0x20008000, LENGTH = 10K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM1 AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM1 + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM1 + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED + MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED + MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb5mxx_flash_cm4.ld b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb5mxx_flash_cm4.ld new file mode 100644 index 0000000000..a34b2ad8a5 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb5mxx_flash_cm4.ld @@ -0,0 +1,185 @@ +/** +***************************************************************************** +** +** File : stm32wb5mxx_flash_cm4.ld +** +** Abstract : System Workbench Minimal System calls file +** +** For more information about which c-functions +** need which of these lowlevel functions +** please consult the Newlib libc-manual +** +** Environment : System Workbench for MCU +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** +**

    © COPYRIGHT(c) 2019 Ac6

    +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of Ac6 nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20030000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K +RAM1 (xrw) : ORIGIN = 0x20000004, LENGTH = 0x2FFFC +RAM_SHARED (xrw) : ORIGIN = 0x20030000, LENGTH = 10K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM1 AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM1 + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM1 + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED + MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED + MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb30xx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb30xx_cm4.s new file mode 100644 index 0000000000..602dd8896c --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb30xx_cm4.s @@ -0,0 +1,388 @@ +/** + ****************************************************************************** + * @file startup_stm32wb30xx_cm4.s + * @author MCD Application Team + * @brief STM32WB30xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* start address for the .MB_MEM2 section. defined in linker script */ +.word _sMB_MEM2 +/* end address for the .MB_MEM2 section. defined in linker script */ +.word _eMB_MEM2 + +/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */ +.macro INIT_BSS start, end + ldr r0, =\start + ldr r1, =\end + movs r3, #0 + bl LoopFillZerobss +.endm + +/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */ +.macro INIT_DATA start, end, src + ldr r0, =\start + ldr r1, =\end + ldr r2, =\src + movs r3, #0 + bl LoopCopyDataInit +.endm + +.section .text.data_initializers +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + bx lr + +FillZerobss: + str r3, [r0] + adds r0, r0, #4 + +LoopFillZerobss: + cmp r0, r1 + bcc FillZerobss + bx lr + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + INIT_DATA _sdata, _edata, _sidata + +/* Zero fill the bss segments. */ + INIT_BSS _sbss, _ebss + INIT_BSS _sMB_MEM2, _eMB_MEM2 + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application s entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_LSECSS_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word C2SEV_PWR_C2H_IRQHandler + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word PKA_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word 0 + .word 0 + .word TSC_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word 0 + .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + .word IPCC_C1_RX_IRQHandler + .word IPCC_C1_TX_IRQHandler + .word HSEM_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word 0 + .word 0 + .word 0 + .word AES2_IRQHandler + .word RNG_IRQHandler + .word FPU_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word DMAMUX1_OVR_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_LSECSS_IRQHandler + .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak C2SEV_PWR_C2H_IRQHandler + .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler + + .weak IPCC_C1_RX_IRQHandler + .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler + + .weak IPCC_C1_TX_IRQHandler + .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler + + .weak HSEM_IRQHandler + .thumb_set HSEM_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak AES2_IRQHandler + .thumb_set AES2_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb35xx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb35xx_cm4.s new file mode 100644 index 0000000000..d4c2ba32c5 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb35xx_cm4.s @@ -0,0 +1,439 @@ +/** + ****************************************************************************** + * @file startup_stm32wb35xx_cm4.s + * @author MCD Application Team + * @brief STM32WB35xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* start address for the .MB_MEM2 section. defined in linker script */ +.word _sMB_MEM2 +/* end address for the .MB_MEM2 section. defined in linker script */ +.word _eMB_MEM2 + +/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */ +.macro INIT_BSS start, end + ldr r0, =\start + ldr r1, =\end + movs r3, #0 + bl LoopFillZerobss +.endm + +/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */ +.macro INIT_DATA start, end, src + ldr r0, =\start + ldr r1, =\end + ldr r2, =\src + movs r3, #0 + bl LoopCopyDataInit +.endm + +.section .text.data_initializers +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + bx lr + +FillZerobss: + str r3, [r0] + adds r0, r0, #4 + +LoopFillZerobss: + cmp r0, r1 + bcc FillZerobss + bx lr + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + INIT_DATA _sdata, _edata, _sidata + +/* Zero fill the bss segments. */ + INIT_BSS _sbss, _ebss + INIT_BSS _sMB_MEM2, _eMB_MEM2 + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application s entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_LSECSS_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word C2SEV_PWR_C2H_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word PKA_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word LPUART1_IRQHandler + .word 0 + .word TSC_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word CRS_IRQHandler + .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + .word IPCC_C1_RX_IRQHandler + .word IPCC_C1_TX_IRQHandler + .word HSEM_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word 0 + .word QUADSPI_IRQHandler + .word AES1_IRQHandler + .word AES2_IRQHandler + .word RNG_IRQHandler + .word FPU_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word DMAMUX1_OVR_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_LSECSS_IRQHandler + .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak C2SEV_PWR_C2H_IRQHandler + .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler + + .weak IPCC_C1_RX_IRQHandler + .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler + + .weak IPCC_C1_TX_IRQHandler + .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler + + .weak HSEM_IRQHandler + .thumb_set HSEM_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak AES1_IRQHandler + .thumb_set AES1_IRQHandler,Default_Handler + + .weak AES2_IRQHandler + .thumb_set AES2_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s new file mode 100644 index 0000000000..c25d69eb0a --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s @@ -0,0 +1,445 @@ +/** + ****************************************************************************** + * @file startup_stm32wb5mxx_cm4.s + * @author MCD Application Team + * @brief STM32WB5Mxx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* start address for the .MB_MEM2 section. defined in linker script */ +.word _sMB_MEM2 +/* end address for the .MB_MEM2 section. defined in linker script */ +.word _eMB_MEM2 + +/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */ +.macro INIT_BSS start, end + ldr r0, =\start + ldr r1, =\end + movs r3, #0 + bl LoopFillZerobss +.endm + +/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */ +.macro INIT_DATA start, end, src + ldr r0, =\start + ldr r1, =\end + ldr r2, =\src + movs r3, #0 + bl LoopCopyDataInit +.endm + +.section .text.data_initializers +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + bx lr + +FillZerobss: + str r3, [r0] + adds r0, r0, #4 + +LoopFillZerobss: + cmp r0, r1 + bcc FillZerobss + bx lr + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + INIT_DATA _sdata, _edata, _sidata + +/* Zero fill the bss segments. */ + INIT_BSS _sbss, _ebss + INIT_BSS _sMB_MEM2, _eMB_MEM2 + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application s entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_LSECSS_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word C2SEV_PWR_C2H_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word PKA_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word LPUART1_IRQHandler + .word SAI1_IRQHandler + .word TSC_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word CRS_IRQHandler + .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + .word IPCC_C1_RX_IRQHandler + .word IPCC_C1_TX_IRQHandler + .word HSEM_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word LCD_IRQHandler + .word QUADSPI_IRQHandler + .word AES1_IRQHandler + .word AES2_IRQHandler + .word RNG_IRQHandler + .word FPU_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word DMAMUX1_OVR_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_LSECSS_IRQHandler + .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak C2SEV_PWR_C2H_IRQHandler + .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler + .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler + + .weak IPCC_C1_RX_IRQHandler + .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler + + .weak IPCC_C1_TX_IRQHandler + .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler + + .weak HSEM_IRQHandler + .thumb_set HSEM_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak AES1_IRQHandler + .thumb_set AES1_IRQHandler,Default_Handler + + .weak AES2_IRQHandler + .thumb_set AES2_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/system_stm32wbxx.c b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/system_stm32wbxx.c index 7594093689..4cb9e0e423 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/system_stm32wbxx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/system_stm32wbxx.c @@ -161,7 +161,7 @@ const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \ 4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */ -#if defined(STM32WB55xx) +#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \ {2UL,6UL,4UL,3UL,2UL,4UL}, \ {4UL,12UL,8UL,6UL,4UL,8UL}, \ @@ -223,7 +223,7 @@ void SystemInit(void) /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x22041000U; -#if defined(STM32WB55xx) +#if defined(STM32WB55xx) || defined(STM32WB5Mxx) /* Reset PLLSAI1CFGR register */ RCC->PLLSAI1CFGR = 0x22041000U; #endif diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 6cee0847ce..4a1fb5935c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -2,18 +2,18 @@ * STM32F0: 2.3.4 * STM32F1: 4.3.1 - * STM32F2: 2.2.2 + * STM32F2: 2.2.3 * STM32F3: 2.3.4 * STM32F4: 2.6.4 * STM32F7: 1.2.4 * STM32G0: 1.3.0 * STM32G4: 1.1.1 - * STM32H7: 1.7.0 + * STM32H7: 1.8.0 * STM32L0: 1.9.0 * STM32L1: 2.3.0 - * STM32L4: 1.6.0 + * STM32L4: 1.6.1 * STM32MP1: 1.2.0 - * STM32WB: 1.3.0 + * STM32WB: 1.4.0 Release notes of each STM32YYxx CMSIS available here: diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32F2xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 52c9d6c5ed..90767ed33b 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32F2xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -236,12 +236,12 @@ #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) -#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH) -#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH) +#if defined(STM32G4) || defined(STM32H7) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -306,8 +306,17 @@ #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + #endif /* STM32L4 */ +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#endif + #if defined(STM32H7) #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 @@ -365,6 +374,9 @@ #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + #endif /* STM32H7 */ /** @@ -460,7 +472,9 @@ #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 -#endif +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ /** * @} @@ -564,7 +578,14 @@ #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 -#endif + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 @@ -735,6 +756,66 @@ #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 #endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the events that can be selected to configure the + * set/reset crossbar of a timer output + */ +#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) +#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) +#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) +#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) +#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) +#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) +#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) +#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) +#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) + +#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) +#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) +#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) +#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) +#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) +#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) +#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) +#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) +#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) + +/** @brief Constants defining the event filtering applied to external events + * by a timer + */ +#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + +#endif /* STM32F3 */ /** * @} */ @@ -874,7 +955,7 @@ #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif @@ -965,6 +1046,16 @@ #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT + +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL +#endif /* STM32H7 */ + /** * @} */ @@ -1358,6 +1449,30 @@ #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ @@ -1380,6 +1495,13 @@ #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + /** * @} */ @@ -1409,16 +1531,18 @@ #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */ +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ #if defined(STM32F4) #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT @@ -1437,6 +1561,13 @@ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown @@ -1509,14 +1640,14 @@ #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4) +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA -#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */ +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ /** * @} */ @@ -3114,7 +3245,7 @@ #if defined(STM32L4) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) +#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -3242,7 +3373,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3365,7 +3496,7 @@ #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif -#if defined(STM32H7) +#if defined(STM32H7) || defined(STM32L5) #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback @@ -3606,12 +3737,12 @@ * @{ */ #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) -#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT -#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA -#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart -#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT -#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA -#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop #endif /** * @} @@ -3620,9 +3751,9 @@ /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32L4) +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE -#endif +#endif /* STM32L4 || STM32F4 || STM32F7 */ /** * @} */ diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2c.h b/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2c.h index 4aeed36a45..e1f83fb65c 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2c.h +++ b/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2c.h @@ -170,6 +170,7 @@ typedef enum #define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */ #define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */ #define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */ +#define HAL_I2C_WRONG_START 0x00000200U /*!< Wrong start Error */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) #define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */ #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_irda.h b/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_irda.h index 0737aad25f..4529d2488d 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_irda.h +++ b/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_irda.h @@ -646,7 +646,7 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); #define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U) -#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U) +#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) ((((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U) /* UART BRR = mantissa + overflow + fraction = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_smartcard.h b/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_smartcard.h index f2cdfb84bf..25cd0abe6e 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_smartcard.h +++ b/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_smartcard.h @@ -720,7 +720,7 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc); #define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25U)/(4U*(__BAUD__))) #define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100U) -#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U + 50U) / 100U) +#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) ((((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U) + 50U) / 100U) /* SMARTCARD BRR = mantissa + overflow + fraction = (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */ #define SMARTCARD_BRR(__PCLK__, __BAUD__) (((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4U) + \ diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_uart.h b/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_uart.h index 6b723a7fd0..306dacc65c 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_uart.h +++ b/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_uart.h @@ -535,7 +535,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) -/** @brief Checks whether the specified UART interrupt has occurred or not. +/** @brief Checks whether the specified UART interrupt source is enabled or not. * @param __HANDLE__ specifies the UART Handle. * UART Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). @@ -800,7 +800,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); #define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_))) #define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U) -#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U) +#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U) /* UART BRR = mantissa + overflow + fraction = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ #define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \ @@ -809,7 +809,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); #define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_))) #define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U) -#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U) +#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U) /* UART BRR = mantissa + overflow + fraction = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ #define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \ diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_usart.h b/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_usart.h index a2d21ee498..2d046e4d5f 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_usart.h +++ b/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_usart.h @@ -607,7 +607,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); #define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U) -#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U) +#define USART_DIVFRAQ(_PCLK_, _BAUD_) ((((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U) /* UART BRR = mantissa + overflow + fraction = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_usart.h b/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_usart.h index 8dbf5eeaa2..864d8a3c2a 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_usart.h +++ b/system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_usart.h @@ -375,7 +375,7 @@ typedef struct */ #define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__))) #define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100) -#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100) +#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16) + 50) / 100) /* USART BRR = mantissa + overflow + fraction = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */ #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F2xx_HAL_Driver/Release_Notes.html index 6517a83ca3..eec31af60c 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F2xx_HAL_Driver/Release_Notes.html @@ -25,7 +25,7 @@

    Release Notes for STM32F2xx HAL Drivers

    Copyright © 2017 STMicroelectronics

    - +
    @@ -38,15 +38,82 @@

    License

    Update History

    - +

    Main Changes

    • General updates to fix known defects and enhancements implementation
      • -
    • Add support of HAL callback registration feature
      • -
    • Add new HAL EXTI driver
      • +
    • HAL/LL GPIO update +
        +
      • Update GPIO initialization sequence to avoid unwanted pulse on GPIO Pin’s
        • +
      • +
    • HAL I2C update +
        +
      • Update HAL_I2C_EV_IRQHandler() API to fix I2C send break issue +
          +
        • Add additional check on hi2c->hdmatx, hdmatx->XferCpltCallback, hi2c->hdmarx, hdmarx->XferCpltCallback in I2C_Master_SB() API to avoid enabling DMA request when IT mode is used.
          • +
        • +
      • Update HAL_I2C_ER_IRQHandler() API to fix acknowledge failure issue with I2C memory IT processes +
          +
        • Add stop condition generation when NACK occurs.
          • +
        • +
      • Update HAL_I2C_Init() API to force software reset before setting new I2C configuration.
        • +
      • Update HAL I2C processes to report ErrorCode when wrong I2C start condition occurs +
          +
        • Add new ErrorCode define: HAL_I2C_WRONG_START
          • +
        • Set ErrorCode parameter in I2C handle to HAL_I2C_WRONG_START
          • +
        • +
      • Update I2C_DMAXferCplt(), I2C_DMAError() and I2C_DMAAbort() APIs to fix hardfault issue when hdmatx and hdmarx parameters in i2c handle aren’t initialized (NULL pointer). +
          +
        • Add additional check on hi2c->hdmtx and hi2c->hdmarx before resetting DMA Tx/Rx complete callbacks.
          • +
        • +
      • +
    • HAL IRDA update +
        +
      • Update IRDA interruption handler to manage correctly the overrun interrupt +
          +
        • Add in the HAL_IRDA_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
          • +
        • +
      • +
    • HAL SMARTCARD update +
        +
      • Update SMARTCARD interruption handler to manage correctly the overrun interrupt. +
          +
        • Add in the HAL_SMARTCARD_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
          • +
        • +
      • +
    • HAL UART update +
        +
      • Update UART polling processes to handle efficiently the Lock mechanism +
          +
        • Move the process unlock at the top of the HAL_UART_Receive() and HAL_UART_Transmit() API.
          • +
        • +
      • Update UART interruption handler to manage correctly the overrun interrupt +
          +
        • Add in the HAL_UART_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
          • +
        • +
      • +
    • HAL USART update +
        +
      • Update USART interruption handler to manage correctly the overrun interrupt +
          +
        • Add in the HAL_USART_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
          • +
        • +
      • +
    +
    +
    +
    + +
    +

    Main Changes

    +
      +
    • General updates to fix known defects and enhancements implementation
      • +
    • HAL drivers clean up: remove double casting ‘uint32_t’ and ‘U’
    • General updates to fix CodeSonar compilation warnings
    • General updates to fix the user manual .chm files
      • +
    • Add support of HAL callback registration feature
      • +
    • Add new HAL EXTI driver
    • The following changes done on the HAL drivers require an update on the application code based on older HAL versions
      • HAL/LL Generic update @@ -96,7 +163,7 @@

        Main Changes

      • HAL_IS_BIT_SET()/HAL_IS_BIT_CLR() macros implementation update
      • “stdio.h” include updated with “stddef.h”
      • -
    • Add HAL_GetUIDw0(), HAL_GetUIDw1() and HAL_GetUIDw2() API in order to return the unique device identifier
      • +
    • Add HAL_GetUIDw0(), HAL_GetUIDw1() and HAL_GetUIDw2() API in order to returns the unique device identifier
  • HAL CAN update
      @@ -104,25 +171,47 @@

      Main Changes

      • SJW to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to TransmitFifoPriority
      +
    • Rename CAN_FilterConfTypeDef structure to CAN_FilterTypeDef and update some fields: +
        +
      • FilterNumber to FilterBank
        • +
      • BankNumber to SlaveStartFilterBank
        • +
      • +
    • Rename CanTxMsgTypeDef structure to CAN_TxHeaderTypeDef and update some fields: +
        +
      • Data to TransmitGlobalTime
        • +
      • +
    • Rename CanRxMsgTypeDef structure to CAN_RxHeaderTypeDef and update some fields: +
        +
      • Data to Timestamp
        • +
      • FMI to FilterMatchIndex
        • +
    • Update possible values list for FilterActivation parameter in CAN_FilterTypeDef structure
      • CAN_FILTER_ENABLE instead of ENABLE
      • CAN_FILTER_DISABLE instead of DISABLE
      • -
    • HAL_CAN_Init() is split into HAL_CAN_Init() and HAL_CAN_Start() APIs
      • +
    • HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start() API’s
    • HAL_CAN_Transmit() is replaced by HAL_CAN_AddTxMessage() to place Tx Request, then HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion.
      • -
    • HAL_CAN_Transmit_IT() is replaced by HAL_CAN_ActivateNotification() to enable transmit IT, then HAL_CAN_AddTxMessage() to place Tx request.
      • -
    • HAL_CAN_Receive() is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until reception, then HAL_CAN_GetRxMessage() to get Rx message.
      • -
    • HAL_CAN_Receive_IT() is replaced by HAL_CAN_ActivateNotification() to enable receive IT, then HAL_CAN_GetRxMessage() in the receive callback to get Rx message
      • +
    • HAL_CAN_Transmit_IT() is replaced by HAL_CAN_ActivateNotification() to enable transmit IT, then HAL_CAN_AddTxMessage() for place Tx request.
      • +
    • HAL_CAN_Receive() is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until reception, then HAL_CAN_GetRxMessage()
      • +
    • to get Rx message.
      • +
    • HAL_CAN_Receive_IT() is replaced by HAL_CAN_ActivateNotification() to enable receive IT, then HAL_CAN_GetRxMessage()
      • +
    • in the receive callback to get Rx message
    • HAL_CAN_Slepp() is renamed as HAL_CAN_RequestSleep()
    • HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), HAL_CAN_TxMailbox1CompleteCallback() and HAL_CAN_TxMailbox2CompleteCallback().
    • HAL_CAN_RxCpltCallback is split into HAL_CAN_RxFifo0MsgPendingCallback() and HAL_CAN_RxFifo1MsgPendingCallback().
    • More complete “How to use the new driver” is detailed in the driver header section itself.
      • +
    • Refer to the following example to identify the changes
  • HAL CRC update
      -
    • Update HAL_CRC_DeInit() API to be more safe
      • -
    • Remove lock mechanism on the followings API’s: +
    • Update __HAL_CRC_DR_RESET() macro
      • +
    • Update HAL_CRC_DeInit() API to +
        +
      • Be able to return HAL status when CRC is is already busy
        • +
      • DeInit the low level hardware after reset IDR register content
        • +
      • +
    • Remove extra call to HAL_LOCK/HAL_UNLOCK from the followings API’s:
      • HAL_CRC_Accumulate()
      • HAL_CRC_Calculate()
        • @@ -130,7 +219,8 @@

        Main Changes

    • HAL CRYP update
        -
      • The CRYP_InitTypeDef is no more supported, changed by CRYP_ConfigTypedef to allow parameters change using HAL_CRYP_setConfig() API without reinitializing the CRYP IP using the HAL_CRYP_Init() API
        • +
      • The CRYP_InitTypeDef is no more supported, changed by CRYP_ConfigTypedef to allow changing parameters
        • +
      • Using HAL_CRYP_setConfig() API without reinitialize the CRYP IP using the HAL_CRYP_Init() API
      • New parameters added in the CRYP_ConfigTypeDef structure: B0 and DataWidthUnit
      • Input data size and error code parameters are added in the CRYP_HandleTypeDef structure
      • Add new APIs to manage the CRYP configuration: @@ -147,32 +237,49 @@

        Main Changes

      • HAL_CRYP_Encypt_DMA()
      • HAL_CRYP_Decypt_DMA()
      • +
    • More complete “How to use the new driver” is detailed in the driver header section itself.
      • +
    • Refer to the following example to identify the changes
  • HAL DAC update
      -
    • General updates for more efficiency implementation
      • -
    • Update HAL_DAC_IRQHandler() to manage DAC Under-run error only once DAC DMAUDR interrupt is enabled
      • +
    • Overall rework of the driver for a more efficient implementation +
        +
      • Update HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA() and HAL_DAC_ConfigChannel() API to +
          +
        • Update lock mechanism for DAC process
          • +
        • Optimize code by using direct register read
          • +
        • +
      • Update HAL_DAC_IRQHandler() function to +
          +
        • Add error management in case DMA errors through HAL_DAC_DMAUnderrunCallbackCh1() and HAL_DACEx_DMAUnderrunCallbackCh2()
          • +
        • Optimize code by using direct register read
          • +
        • +
  • HAL DCMI update
      +
    • Update HAL_DCMI_Start_DMA() function to Enable the DCMI peripheral
    • Add new timeout implementation based on cpu cycles for DCMI stop
      • -
    • Update HAL_DCMI_IRQHandler() API to clear the End of Frame flag in case of Frame error
      • -
    • The extension files stm32f2xx_hal_dcmi_ex.c/.h is added and kept empty for compatibility reason with other STM32 series
      • +
    • Update lock mechanism for DCMI process
      • +
    • Update HAL_DCMI_IRQHandler() function to: +
        +
      • Optimize code by using direct register read
        • +
      • +
    • The extension files stm32f2xx_hal_dcmi_ex.c/.h is added and kept empty for projects compatibility reason
    • Add DCMI_SyncUnmaskTypeDef structure and HAL_DCMI_ConfigSyncUnmask() API to manage embedded synchronization delimiters unmasks
    • HAL DCMI driver clean-up: remove non referenced callback APIs: HAL_DCMI_VsyncCallback() and HAL_DCMI_HsyncCallback()
  • HAL DMA update
      -
    • HAL_DMA_DeInit() API: Add clean of DMA handler callbacks
      • -
    • HAL_DMA_Start_IT API: Remove FIFO error management +
    • Add clean of callbacks in HAL_DMA_DeInit() API
      • +
    • Remove FIFO error enabling in “HAL_DMA_Start_IT”
        -
      • when FIFO error monitoring is requested in IT mode, the macro __HAL_DMA_ENABLE_IT can be used to enable the FIFO error IT in user application
        • +
      • when FIFO error monitoring is requested in IT model, the macro __HAL_DMA_ENABLE_IT can be used to enable the FIFO error IT at the user Msp functio
  • HAL FLASH update
      -
    • HAL_FLASH_Unlock() update to return state error when flash is still locked.
      • -
    • FLASH_Program_DoubleWord() updated to fix Program DoubleWord fails (PGAERR) when using STRD assembly instruction.
      • +
    • HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked
  • HAL GPIO update
      @@ -183,6 +290,7 @@

      Main Changes

      • Overall rework of the driver for a more efficient implementation
          +
        • HASH API changes for MISRA-C 2012 compliance
        • Update HASH_Start_DMA() to add check on HASH_CR_MDMAT bit before checking input buffer length in case of multi-buffer processing
        • Fill-up empty statement in HAL_HASH_DMAFeed_ProcessSuspend() to correct CodeSonar warning
        • @@ -210,62 +318,17 @@

        Main Changes

    • Fix I2C send break issue in IT processes
        -
      • Add additional check on hi2c->hdmatx and hi2c->hdmarx to avoid the DMA request enable when ITmode is used.
        • -
      • +
    • Add additional check on hi2c->hdmatxand hi2c->hdmarx to avoid the DMA request enable when ITmode is used.
    • -
  • HAL IRDA driver -
      -
    • Align HAL IRDA driver with latest updates and enhancements
      • -
    • Add callback registration feature -
        -
      • Add HAL_IRDA_RegisterCallback() and HAL_IRDA_UnRegisterCallback() APIs
        • -
      • Add callback identifiers in HAL_IRDA_CallbackIDTypeDef enumerated typedef
      • -
    • Review IRDA state machine to avoid cases where IRDA state is overwritten by IRDA IRQ
      • -
    • Implement new APIs for HAL IRDA Abort management: +
    • HAL UART/USART/IrDA/SMARTCARD update
        -
      • HAL_IRDA_Abort(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortReceive(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_AbortReceive_IT()
        • -
      • -
    • Optimize WaitOnFlag management in IRDA_Transmit() function
      • -
    • Optimize all HAL IRQ Handler routines
      • -
    • Optimize HAL IRDA to avoid using macros as argument of function calls
      • -
    • -
  • HAL SMARTCARD driver -
      -
    • Align HAL SMARTCARD driver with latest updates and enhancements
      • -
    • Add callback registration feature -
        -
      • Add HAL_SMARTCARD_RegisterCallback() and HAL_SMARTCARD_UnRegisterCallback() APIs
        • -
      • Add callback identifiers in HAL_SMARTCARD_CallbackIDTypeDef enumerated typedef
        • -
      • -
    • Review SMARTCARD state machine to avoid cases where SMARTCARD state is overwritten by SMARTCARD IRQ
      • -
    • Implement new APIs for HAL SMARTCARD Abort management: -
        -
      • HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_AbortReceive_IT()
        • -
      • -
    • Optimize WaitOnFlag management in SMARTCARD_Transmit() function
      • -
    • Optimize all HAL IRQ Handler routines
      • -
    • Optimize HAL SMARTCARD to avoid using macros as argument of function calls
      • -
    • -
  • HAL UART/USART driver -
      -
    • Align HAL UART/USART driver with latest updates and enhancements
      • -
    • Add callback registration feature -
        -
      • Add HAL_UART/USART_RegisterCallback() and HAL_UART/USART_UnRegisterCallback() APIs
        • -
      • Add callback identifiers in HAL_UART/USART_CallbackIDTypeDef enumerated typedef
        • -
      • -
    • Add missing __IO in UART/USART_HandleTypeDef definition (for TxXferCount and RxXferCount)
      • -
    • Review UART/USART state machine to avoid cases where UART/USART state is overwritten by UART/USART IRQ
      • -
    • Implement new APIs for HAL UART/USART Abort management: +
    • Overall rework of the driver for a more efficient implementation
        -
      • HAL_UART/USART_Abort(), HAL_UART/USART_AbortTransmit(), HAL_UART/USART_AbortReceive(), HAL_UART/USART_Abort_IT(), HAL_UART/USART_AbortTransmit_IT(), HAL_UART/USART_AbortReceive_IT()
        • +
      • Improve I/O operation functions: separate transfer process and PPP state management
        • +
      • Update the HAL_PPP_IRQHandler function by optimizing the management of interrupt errors
        • +
      • Align driver with the Reference Manual regarding registers and bit definition naming
      • -
    • Optimize WaitOnFlag management in UART/USART_Transmit() function
      • -
    • Optimize all HAL IRQ Handler routines
      • -
    • Align __HAL_UART_GET_IT and __HAL_UART_GET_IT_SOURCE with other series
      • -
    • Optimize HAL UART/USART to avoid using macros as argument of function calls
      • -
    • Update USART BRR calculation
  • LL IWDG update
      @@ -273,12 +336,9 @@

      Main Changes

  • HAL RNG update
      -
    • Update to manage RNG error: -
      • Add ErrorCode parameter in HAL RNG Handler structure
      • Add HAL_RNG_GetError() API
        • -
      • -
    • Remove lock mechanism from HAL_RNG_GenerateRandomNumber_IT() API
      • +
    • HAL Lock/Unlock mecanism update
  • HAL/LL RTC update
      @@ -293,39 +353,37 @@

      Main Changes

    • Update HAL_RCC_DeInit() and LL_RCC_DeInit() APIs to
      • Be able to return HAL/LL status
        • -
      • Add checks on HSI, PLL and PLLI2S ready flags before modifying RCC CFGR registers
        • -
      • Clear all RCC interrupt flags
        • +
      • Add checks for HSI, PLL and PLLI2S ready before modifying RCC CFGR registers
        • +
      • Clear all interrupt flags
      • Initialize systick interrupt period
  • HAL SDMMC update
      -
    • Align HAL SDMMC driver with latest updates and enhancements
      • -
    • Due to limitation SDIO hardware flow control indicated in Errata Sheet : -
        -
      • In 4-bits bus wide mode, do not use the HAL_SD_WriteBlocks_IT() or HAL_SD_WriteBlocks() APIs otherwise underrun will occur and there is not possibility to activate the flow control
        • -
      • Use DMA mode when using 4-bits bus wide mode or decrease the frequency
        • -
      • -
    • Add callback registration feature -
        -
      • Add HAL_SD_RegisterCallback(),HAL_SD_UnRegisterCallback(), HAL_SD_RegisterTransceiverCallback() and HAL_SD_UnRegisterTransceiverCallback APIs
        • -
      • Add callback identifiers in HAL_SD_CallbackIDTypeDef enumerated typedef
        • -
      • +
    • Add API HAL_SD_ConfigSpeedBusOperation() to configure the SD card speed bus mode
      • +
    • Fix and improve state and error management
      • +
    • Fix preprocessing compilation issue with SDIO STA STBITERR interrupt
      • +
    • Align driver with the Reference Manual regarding registers and bit definition naming
  • HAL SPI update
      -
    • Align HAL/LL SPI driver with latest updates and enhancements
      • -
    • Fix issue in HAL_SPI_Transmit() and HAL_SPI_TransmitReceive() functions
      • -
    • Add SPI Abort transfer API’s: +
    • Overall rework of the driver for a more efficient implementation
        -
      • HAL_SPI_Abort()
        • -
      • HAL_SPI_Abort_IT()
        • +
      • Add the following new macros: +
          +
        • SPI_CHECK_FLAG()
          • +
        • SPI_CHECK_IT_SOURCE()
        • -
      • Update HAL/LL SPI driver to manage TI mode not supported by all STM32F2xx devices
        • -
      • Add callback registration feature +
      • Update HAL_SPI_StateTypeDef structure to add new state: HAL_SPI_STATE_ABORT
        • +
      • Add HAL_SPI_Abort() to manage abort issue in SPI TX or Rx mode only
        • +
      • Update HAL_SPI_Transmit()/HAL_SPI_Receive() API’s to fix memory overflow issue.
        • +
      • Update HAL_SPI_Transmit_DMA : checking hmdtx instead of hdmrx.
        • +
      • Update HAL_SPI_IRQHandler() function to
          -
        • Add HAL_SPI_RegisterCallback() and HAL_SPI_UnRegisterCallback() APIs
          • -
        • Add callback identifiers in HAL_SPI_CallbackIDTypeDef enumerated typedef
          • +
        • Add error management in case DMA errors through HAL_DMA_Abort_IT() and ErrorCallback()
          • +
        • Optimize code by using direct register read
          • +
        • +
      • Align driver with the Reference Manual regarding registers and bit definition naming
  • HAL I2S update @@ -357,7 +415,7 @@

    Main Changes

  • HAL/LL TIM update
      -
    • Move the following TIM structures from stm32f2xx_hal_tim_ex.h into stm32f2xx_hal_tim.h +
    • Move the following TIM structures from stm32f4xx_hal_tim_ex.h into stm32f4xx_hal_tim.h
      • TIM_MasterConfigTypeDef()
      • TIM_BreakDeadTimeConfigTypeDef()
        • @@ -384,11 +442,11 @@

        Main Changes

      • HAL/LL USB update
        • Rework USB interrupt handler and improve HS DMA support in Device mode
          • -
        • Fix BCD handling of OTG instance in device mode
          • +
        • Fix BCD handling for OTG instance in device mode
        • cleanup reference to low speed in device mode
          • -
        • Allow writing TX FIFO when transfer length is equal to available space in the TX FIFO
          • +
        • Allow writing TX FIFO in case of transfer length is equal to available space in the TX FIFO
        • Fix Toggle OUT interrupt channel in host mode
          • -
        • Add new callback to be used to handle the usb device connection/disconnection +
        • Add new callback to be used to handle usb device connection/disconnection
          • HAL_HCD_PortEnabled_Callback()
          • HAL_HCD_PortDisabled_Callback()
            • @@ -396,10 +454,10 @@

            Main Changes

          • Update to prevent reactivate host interrupt channel
          • Updated USB_WritePacket(), USB_ReadPacket()APIs to prevent compilation warning with GCC GNU v8.2.0
          • Rework USB_EPStartXfer() API to enable theUSB endpoint before unmasking the TX FiFo empty interrupt in case DMA is not used
            • -
          • Update USB HAL_HCD_Init() and HAL_PCD_Init() APIs to avoid enabling USB DMA feature for OTG FS instance, USB DMAfeature is available only on OTG HS Instance
            • +
          • USB HAL_HCD_Init() and HAL_PCD_Init() APIsupdated to avoid enabling USB DMA feature for OTG FS instance, USB DMAfeature is available only on OTG HS Instance
          • Remove duplicated line in hal_hcd.c header file comment section
            • -
          • Rework USB HAL driver to use instancePCD_SPEED_xxx, HCD_SPEED_xx instead of OTG register Core speed definition during the instance initialization
            • -
          • Software Quality improvement with a fix of CodeSonar warnings on PCD_Port_IRQHandler() and HCD_Port_IRQHandler()interrupt handlers
            • +
          • Rework USB HAL driver to use instancePCD_SPEED_xxx, HCD_SPEED_xx speeds instead of OTG register Core speed definition during the instance initialization
            • +
          • Software Quality improvement with a fix ofCodeSonar warning on PCD_Port_IRQHandler() and HCD_Port_IRQHandler()interrupt handlers
        • HAL UTILS update
            @@ -411,7 +469,7 @@

            Main Changes

            -

            Main Changes

            +

            Main Changes

            • General updates to fix known defects and enhancements implementation
            • Fix compilation warning with GCC compiler
              • @@ -477,7 +535,7 @@

              Main Changes

              -

              Main Changes

              +

              Main Changes

              • General updates to fix known defects and enhancements implementation
              • HAL CONF Template update @@ -498,7 +556,7 @@

                Main Changes

                -

                Main Changes

                +

                Main Changes

                • Add Low Layer drivers allowing performance and footprint optimization
                    @@ -616,7 +674,7 @@

                    Main Changes

                    -

                    Main Changes

                    +

                    Main Changes

                    • General updates to fix known defects and enhancements implementation
                    • Enhance HAL delay and time base implementation: @@ -970,7 +1028,7 @@

                      Main Changes

                      -

                      Main Changes

                      +

                      Main Changes

                      • HAL RCC update
                          @@ -986,7 +1044,7 @@

                          Main Changes

                          -

                          Main Changes

                          +

                          Main Changes

                          • General updates to fix known defects and enhancements implementation
                          • One change done on the HAL CRYP requires an update on the application code based on HAL V1.1.0 @@ -1049,7 +1107,7 @@

                            Main Changes

                            -

                            Main Changes

                            +

                            Main Changes

                            • Maintenance release to fix known defects and enhancements implementation
                            • Macros and literals renaming to ensure compatibles across STM32 series, backward compatibility maintained thanks to new added file stm32_hal_legacy.h under /Inc/Legacy
                              • @@ -1879,7 +1937,7 @@

                              Main Changes

                              -

                              Main Changes

                              +

                              Main Changes

                              • Patch release : moved macros related to RNG from hal_rcc_ex.h to hal_rcc.h as RNG is present in all versions of the STM32F2
                              @@ -1888,7 +1946,7 @@

                              Main Changes

                              -

                              Main Changes

                              +

                              Main Changes

                              • First official release
                              diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal.c b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal.c index dd6e4d1cbb..767b393306 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal.c +++ b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal.c @@ -50,11 +50,11 @@ * @{ */ /** - * @brief STM32F2xx HAL Driver version number V1.2.3 + * @brief STM32F2xx HAL Driver version number V1.2.4 */ #define __STM32F2xx_HAL_VERSION_MAIN 0x01U /*!< [31:24] main version */ #define __STM32F2xx_HAL_VERSION_SUB1 0x02U /*!< [23:16] sub1 version */ -#define __STM32F2xx_HAL_VERSION_SUB2 0x03U /*!< [15:8] sub2 version */ +#define __STM32F2xx_HAL_VERSION_SUB2 0x04U /*!< [15:8] sub2 version */ #define __STM32F2xx_HAL_VERSION_RC 0x00U /*!< [7:0] release candidate */ #define __STM32F2xx_HAL_VERSION ((__STM32F2xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F2xx_HAL_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_adc_ex.c b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_adc_ex.c index 30cc2f6474..e2ded61a8f 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_adc_ex.c +++ b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_adc_ex.c @@ -5,7 +5,7 @@ * @brief This file provides firmware functions to manage the following * functionalities of the ADC extension peripheral: * + Extended features functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -15,8 +15,8 @@ (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() (##) ADC pins configuration (+++) Enable the clock for the ADC GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE() - (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() + __HAL_RCC_GPIOx_CLK_ENABLE() + (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() @@ -32,54 +32,43 @@ priority than the input stream. (#) Configure the ADC Prescaler, conversion resolution and data alignment using the HAL_ADC_Init() function. - + (#) Configure the ADC Injected channels group features, use HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions. - - (#) Three operation modes are available within this driver : - + + (#) Three operation modes are available within this driver: + *** Polling mode IO operation *** ================================= - [..] - (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart() + [..] + (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart() (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage - user can specify the value of timeout according to his end application + user can specify the value of timeout according to his end application (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function. (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop() - - *** Interrupt mode IO operation *** + + *** Interrupt mode IO operation *** =================================== - [..] - (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT() + [..] + (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT() (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine - (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback - (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can + (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback + (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT() - - - *** DMA mode IO operation *** - ============================== - [..] - (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length - of data to be transferred at each end of conversion - (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback - (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback - (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA() - + + *** Multi mode ADCs Regular channels configuration *** ====================================================== - [..] - (+) Select the Multi mode ADC regular channels features (dual or triple mode) - and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions. - (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length - of data to be transferred at each end of conversion + [..] + (+) Select the Multi mode ADC regular channels features (dual or triple mode) + and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions. + (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length + of data to be transferred at each end of conversion (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function. - - + + @endverbatim ****************************************************************************** * @attention diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_gpio.c b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_gpio.c index cf8caaf3ee..4f80e5dc81 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_gpio.c +++ b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_gpio.c @@ -194,27 +194,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) if (iocurrent != 0x00u) { - /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Alternate function mode selection */ - if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Alternate function parameters */ - assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3u]; - temp &= ~(0xFu << ((position & 0x07u) * 4u)); - temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); - GPIOx->AFR[position >> 3u] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); - GPIOx->MODER = temp; - /* In case of Output or Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) @@ -240,6 +219,27 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp |= ((GPIO_Init->Pull) << (position * 2u)); GPIOx->PUPDR = temp; + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3u]; + temp &= ~(0xFu << ((position & 0x07u) * 4u)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + GPIOx->AFR[position >> 3u] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + GPIOx->MODER = temp; + /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) @@ -327,7 +327,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Clear EXTI line configuration */ EXTI->IMR &= ~((uint32_t)iocurrent); EXTI->EMR &= ~((uint32_t)iocurrent); - + /* Clear Rising Falling edge configuration */ EXTI->RTSR &= ~((uint32_t)iocurrent); EXTI->FTSR &= ~((uint32_t)iocurrent); @@ -342,16 +342,16 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u)); /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)) ; + GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)); - /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); /* Configure the default value IO Output Type */ - GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position); - /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); } position++; diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_i2c.c b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_i2c.c index 9fdb4a9801..b2d3559cac 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_i2c.c +++ b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_i2c.c @@ -378,6 +378,8 @@ static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags); static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c); +static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c); + /* Private function to Convert Specific options */ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); /** @@ -486,6 +488,10 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); + /*Reset I2C*/ + hi2c->Instance->CR1 |= I2C_CR1_SWRST; + hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; + /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); @@ -3303,7 +3309,11 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + if (hi2c->Instance->CR1 & I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; } /* Send slave address */ @@ -4803,6 +4813,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); uint32_t itsources = READ_REG(hi2c->Instance->CR2); uint32_t error = HAL_I2C_ERROR_NONE; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; /* I2C Bus error interrupt occurred ----------------------------------------*/ if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) @@ -4825,7 +4836,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) /* I2C Acknowledge failure error interrupt occurred ------------------------*/ if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) { - tmp1 = hi2c->Mode; + tmp1 = CurrentMode; tmp2 = hi2c->XferCount; tmp3 = hi2c->State; tmp4 = hi2c->PreviousState; @@ -4843,7 +4854,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) error |= HAL_I2C_ERROR_AF; /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ - if (hi2c->Mode == HAL_I2C_MODE_MASTER) + if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) { /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); @@ -5168,59 +5179,7 @@ static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) { if (hi2c->Mode == HAL_I2C_MODE_MEM) { - if (hi2c->EventCount == 0U) - { - /* If Memory address size is 8Bit */ - if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); - - hi2c->EventCount += 2U; - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); - - hi2c->EventCount++; - } - } - else if (hi2c->EventCount == 1U) - { - /* Send LSB of Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); - - hi2c->EventCount++; - } - else if (hi2c->EventCount == 2U) - { - if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - /* Generate Restart */ - hi2c->Instance->CR1 |= I2C_CR1_START; - } - else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - /* Write data to DR */ - hi2c->Instance->DR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - /* Update counter */ - hi2c->XferCount--; - } - else - { - /* Do nothing */ - } - } - else - { - /* Do nothing */ - } + I2C_MemoryTransmit_TXE_BTF(hi2c); } else { @@ -5315,6 +5274,77 @@ static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) } } } + else if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + I2C_MemoryTransmit_TXE_BTF(hi2c); + } + else + { + /* Do nothing */ + } +} + +/** + * @brief Handle TXE and BTF flag for Memory transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->EventCount == 0U) + { + /* If Memory address size is 8Bit */ + if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount += 2U; + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + } + else if (hi2c->EventCount == 1U) + { + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + else if (hi2c->EventCount == 2U) + { + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } } /** @@ -5558,13 +5588,11 @@ static void I2C_Master_SB(I2C_HandleTypeDef *hi2c) hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); } - if ((hi2c->hdmatx != NULL) || (hi2c->hdmarx != NULL)) + if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) + || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) { - if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL)) - { - /* Enable DMA Request */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - } + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); } } else @@ -6174,6 +6202,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c) { /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ HAL_I2C_StateTypeDef CurrentState = hi2c->State; + uint32_t CurrentError; if ((hi2c->Mode == HAL_I2C_MODE_MASTER) && (CurrentState == HAL_I2C_STATE_BUSY_RX)) { @@ -6293,15 +6322,24 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c) HAL_I2C_ErrorCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } - /* STOP Flag is not set after a NACK reception */ + + /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */ + CurrentError = hi2c->ErrorCode; + + if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \ + ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \ + ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \ + ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR)) + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + /* So may inform upper layer that listen phase is stopped */ /* during NACK error treatment */ CurrentState = hi2c->State; if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN)) { - /* Disable EVT, BUF and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->PreviousState = I2C_STATE_NONE; hi2c->State = HAL_I2C_STATE_READY; @@ -6349,7 +6387,11 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_ /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + if (hi2c->Instance->CR1 & I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; } if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) @@ -6418,7 +6460,11 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + if (hi2c->Instance->CR1 & I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; } if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) @@ -6455,7 +6501,11 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + if (hi2c->Instance->CR1 & I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; } /* Send header of slave address */ @@ -6491,7 +6541,11 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + if (hi2c->Instance->CR1 & I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; } /* Send slave address */ @@ -6570,7 +6624,11 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + if (hi2c->Instance->CR1 & I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; } /* Send slave address */ @@ -6640,7 +6698,11 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Wait until SB flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + if (hi2c->Instance->CR1 & I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; } /* Send slave address */ @@ -6673,8 +6735,14 @@ static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); /* Clear Complete callback */ - hi2c->hdmatx->XferCpltCallback = NULL; - hi2c->hdmarx->XferCpltCallback = NULL; + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferCpltCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferCpltCallback = NULL; + } if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) { @@ -6797,8 +6865,14 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ /* Clear Complete callback */ - hi2c->hdmatx->XferCpltCallback = NULL; - hi2c->hdmarx->XferCpltCallback = NULL; + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferCpltCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferCpltCallback = NULL; + } /* Ignore DMA FIFO error */ if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) @@ -6835,8 +6909,14 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) HAL_I2C_StateTypeDef CurrentState = hi2c->State; /* Clear Complete callback */ - hi2c->hdmatx->XferCpltCallback = NULL; - hi2c->hdmarx->XferCpltCallback = NULL; + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferCpltCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferCpltCallback = NULL; + } /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); @@ -6844,8 +6924,14 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) hi2c->XferCount = 0U; /* Reset XferAbortCallback */ - hi2c->hdmatx->XferAbortCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferAbortCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferAbortCallback = NULL; + } /* Disable I2C peripheral to prevent dummy data in buffer */ __HAL_I2C_DISABLE(hi2c); diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_irda.c b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_irda.c index c31e6978d1..bfcc32d7ab 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_irda.c +++ b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_irda.c @@ -1763,7 +1763,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } /* IRDA Over-Run interrupt occurred -----------------------------------*/ - if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) { hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; } diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_smartcard.c b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_smartcard.c index 3e0e015e6c..70718b5c34 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_smartcard.c +++ b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_smartcard.c @@ -1566,7 +1566,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) } /* SMARTCARD Over-Run interrupt occurred -------------------------------*/ - if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) { hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; } diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_uart.c b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_uart.c index d064c6f2e2..51bc8a3988 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_uart.c +++ b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_uart.c @@ -1039,6 +1039,10 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u huart->TxXferSize = Size; huart->TxXferCount = Size; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + while (huart->TxXferCount > 0U) { huart->TxXferCount--; @@ -1077,9 +1081,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } else @@ -1125,6 +1126,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui huart->RxXferSize = Size; huart->RxXferCount = Size; + /* Process Unlocked */ + __HAL_UNLOCK(huart); + /* Check the remain data to be received */ while (huart->RxXferCount > 0U) { @@ -1169,9 +1173,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } else @@ -2051,7 +2052,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* UART Over-Run interrupt occurred --------------------------------------*/ - if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) { huart->ErrorCode |= HAL_UART_ERROR_ORE; } diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_usart.c b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_usart.c index ac5b65b1c3..81ca14571c 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_usart.c +++ b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_usart.c @@ -1788,7 +1788,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) } /* USART Over-Run interrupt occurred -----------------------------------*/ - if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) { husart->ErrorCode |= HAL_USART_ERROR_ORE; } diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_adc.c b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_adc.c index c95d2dcc2c..eaa0724d9d 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_adc.c +++ b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_adc.c @@ -264,7 +264,9 @@ #endif /* ADC_MULTIMODE_SUPPORT */ +#ifndef UNUSED #define UNUSED(x) ((void)(x)) +#endif /** * @} diff --git a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_gpio.c b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_gpio.c index 553f2185a8..b5ae92f75d 100644 --- a/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_gpio.c +++ b/system/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_gpio.c @@ -223,9 +223,6 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru if (currentpin != 0x00u) { - /* Pin Mode configuration */ - LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) { /* Check Speed mode parameters */ @@ -233,6 +230,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru /* Speed mode configuration */ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); } /* Pull-up Pull down resistor configuration*/ @@ -253,19 +256,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); } } + + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); } pinpos++; } - - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) - { - /* Check Output mode parameters */ - assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); - - /* Output mode configuration*/ - LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); - - } return (SUCCESS); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 78c8d9c2dd..4d27330cbd 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -241,7 +241,7 @@ #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -313,8 +313,8 @@ #endif /* STM32L4 */ #if defined(STM32G0) -#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 -#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 #endif #if defined(STM32H7) @@ -955,7 +955,7 @@ #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif @@ -1450,7 +1450,7 @@ #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY -#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End @@ -1472,7 +1472,7 @@ #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT -#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */ +#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ @@ -1563,10 +1563,10 @@ */ #if defined(STM32G0) -#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD -#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD -#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD -#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler #endif #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg @@ -3243,9 +3243,8 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -3373,7 +3372,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3481,9 +3480,9 @@ #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND /* alias CMSIS for compatibilities */ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler @@ -3751,9 +3750,9 @@ /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32L4) +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE -#endif +#endif /* STM32L4 || STM32F4 || STM32F7 */ /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h index cdc9722c1e..52f8ecddc1 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h @@ -296,8 +296,8 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); * @{ */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ - (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h index 1e70a710c0..933a4c5876 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h @@ -303,7 +303,6 @@ extern "C" { #define GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */ #endif /* PSSI */ #define GPIO_AF13_TIM1 ((uint8_t)0x0D) /* TIM1 Alternate Function mapping */ -#define GPIO_AF13_TIM8 ((uint8_t)0x0D) /* TIM8 Alternate Function mapping : available on STM32H74xxx/STM32H75xxx */ /** * @brief AF 14 selection @@ -364,7 +363,7 @@ extern "C" { #define GPIOI_PIN_AVAILABLE GPIO_PIN_All #define GPIOJ_PIN_AVAILABLE GPIO_PIN_All #define GPIOH_PIN_AVAILABLE GPIO_PIN_All -#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \ +#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \ GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h index e727bc5b42..c2be7a50a2 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h @@ -654,11 +654,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @{ * @brief Constants defining timer high-resolution clock prescaler ratio. */ -#define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */ -#define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */ -#define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */ -#define HRTIM_PRESCALERRATIO_MUL4 (0x00000003U) /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */ -#define HRTIM_PRESCALERRATIO_MUL2 (0x00000004U) /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */ #define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */ #define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */ #define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */ @@ -2083,12 +2078,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< ((FAULT) == HRTIM_FAULT_5)) #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ + (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) @@ -3117,11 +3107,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg 0x0 to 0x4 for timers A to E * @param __PRESCALER__ specifies the clock prescaler new value. * This parameter can be one of the following values: - * @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) - * @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) - * @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) - * @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) - * @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) * @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) * @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) * @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h index ce956fb15a..ccf984c4ea 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h @@ -271,33 +271,33 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); /** @defgroup NAND_Private_Constants NAND Private Constants * @{ */ -#define NAND_DEVICE ((uint32_t)0x80000000U) -#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U) - -#define CMD_AREA ((uint32_t)(1UL<<16U)) /* A16 = CLE high */ -#define ADDR_AREA ((uint32_t)(1UL<<17U)) /* A17 = ALE high */ - -#define NAND_CMD_AREA_A ((uint8_t)0x00U) -#define NAND_CMD_AREA_B ((uint8_t)0x01U) -#define NAND_CMD_AREA_C ((uint8_t)0x50U) -#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U) - -#define NAND_CMD_WRITE0 ((uint8_t)0x80U) -#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U) -#define NAND_CMD_ERASE0 ((uint8_t)0x60U) -#define NAND_CMD_ERASE1 ((uint8_t)0xD0U) -#define NAND_CMD_READID ((uint8_t)0x90U) -#define NAND_CMD_STATUS ((uint8_t)0x70U) -#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU) -#define NAND_CMD_RESET ((uint8_t)0xFFU) +#define NAND_DEVICE 0x80000000UL +#define NAND_WRITE_TIMEOUT 0x01000000UL + +#define CMD_AREA (1UL<<16U) /* A16 = CLE high */ +#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ + +#define NAND_CMD_AREA_A 0x00U +#define NAND_CMD_AREA_B 0x01U +#define NAND_CMD_AREA_C 0x50U +#define NAND_CMD_AREA_TRUE1 0x30U + +#define NAND_CMD_WRITE0 0x80U +#define NAND_CMD_WRITE_TRUE1 0x10U +#define NAND_CMD_ERASE0 0x60U +#define NAND_CMD_ERASE1 0xD0U +#define NAND_CMD_READID 0x90U +#define NAND_CMD_STATUS 0x70U +#define NAND_CMD_LOCK_STATUS 0x7AU +#define NAND_CMD_RESET 0xFFU /* NAND memory status */ -#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U) -#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U) -#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U) -#define NAND_BUSY ((uint32_t)0x00000000U) -#define NAND_ERROR ((uint32_t)0x00000001U) -#define NAND_READY ((uint32_t)0x00000040U) +#define NAND_VALID_ADDRESS 0x00000100UL +#define NAND_INVALID_ADDRESS 0x00000200UL +#define NAND_TIMEOUT_ERROR 0x00000400UL +#define NAND_BUSY 0x00000000UL +#define NAND_ERROR 0x00000001UL +#define NAND_READY 0x00000040UL /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nor.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nor.h index d767cf5039..04a3800716 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nor.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nor.h @@ -245,29 +245,29 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres * @{ */ /* NOR device IDs addresses */ -#define MC_ADDRESS ((uint16_t)0x0000U) -#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U) -#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU) -#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU) +#define MC_ADDRESS ((uint16_t)0x0000) +#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) +#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) +#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) /* NOR CFI IDs addresses */ -#define CFI1_ADDRESS ((uint16_t)0x61U) -#define CFI2_ADDRESS ((uint16_t)0x62U) -#define CFI3_ADDRESS ((uint16_t)0x63U) -#define CFI4_ADDRESS ((uint16_t)0x64U) +#define CFI1_ADDRESS ((uint16_t)0x61) +#define CFI2_ADDRESS ((uint16_t)0x62) +#define CFI3_ADDRESS ((uint16_t)0x63) +#define CFI4_ADDRESS ((uint16_t)0x64) /* NOR operation wait timeout */ -#define NOR_TMEOUT ((uint16_t)0xFFFFU) +#define NOR_TMEOUT ((uint16_t)0xFFFF) /* NOR memory data width */ -#define NOR_MEMORY_8B ((uint8_t)0x0U) -#define NOR_MEMORY_16B ((uint8_t)0x1U) +#define NOR_MEMORY_8B ((uint8_t)0x0) +#define NOR_MEMORY_16B ((uint8_t)0x1) /* NOR memory device read/write start address */ -#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U) -#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U) -#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U) -#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U) +#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000) +#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000) +#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000) +#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000) /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ospi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ospi.h index d2ee43c355..0262589bd6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ospi.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ospi.h @@ -259,6 +259,9 @@ typedef struct This parameter can be a value of @ref OSPIM_IOPort */ uint32_t IOHighPort; /* It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins. This parameter can be a value of @ref OSPIM_IOPort */ + uint32_t Req2AckTime; /* It indicates the minimum switching duration (in number of clock cycles) expected + if some signals are multiplexed in the OSPI IO Manager with the other OSPI. + This parameter can be a value between 1 and 256 */ }OSPIM_CfgTypeDef; #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) @@ -683,7 +686,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); * @{ */ /** @brief Reset OSPI handle state. - * @param __HANDLE__: OSPI handle. + * @param __HANDLE__ specifies the OSPI Handle. * @retval None */ #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) @@ -697,20 +700,20 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); #endif /** @brief Enable the OSPI peripheral. - * @param __HANDLE__: specifies the OSPI Handle. + * @param __HANDLE__ specifies the OSPI Handle. * @retval None */ #define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) /** @brief Disable the OSPI peripheral. - * @param __HANDLE__: specifies the OSPI Handle. + * @param __HANDLE__ specifies the OSPI Handle. * @retval None */ #define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) /** @brief Enable the specified OSPI interrupt. - * @param __HANDLE__: specifies the OSPI Handle. - * @param __INTERRUPT__: specifies the OSPI interrupt source to enable. + * @param __HANDLE__ specifies the OSPI Handle. + * @param __INTERRUPT__ specifies the OSPI interrupt source to enable. * This parameter can be one of the following values: * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt @@ -723,8 +726,8 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); /** @brief Disable the specified OSPI interrupt. - * @param __HANDLE__: specifies the OSPI Handle. - * @param __INTERRUPT__: specifies the OSPI interrupt source to disable. + * @param __HANDLE__ specifies the OSPI Handle. + * @param __INTERRUPT__ specifies the OSPI interrupt source to disable. * This parameter can be one of the following values: * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt @@ -736,8 +739,8 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); #define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** @brief Check whether the specified OSPI interrupt source is enabled or not. - * @param __HANDLE__: specifies the OSPI Handle. - * @param __INTERRUPT__: specifies the OSPI interrupt source to check. + * @param __HANDLE__ specifies the OSPI Handle. + * @param __INTERRUPT__ specifies the OSPI interrupt source to check. * This parameter can be one of the following values: * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt @@ -750,8 +753,8 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); /** * @brief Check whether the selected OSPI flag is set or not. - * @param __HANDLE__: specifies the OSPI Handle. - * @param __FLAG__: specifies the OSPI flag to check. + * @param __HANDLE__ specifies the OSPI Handle. + * @param __FLAG__ specifies the OSPI flag to check. * This parameter can be one of the following values: * @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag @@ -764,8 +767,8 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); #define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) /** @brief Clears the specified OSPI's flag status. - * @param __HANDLE__: specifies the OSPI Handle. - * @param __FLAG__: specifies the OSPI clear register flag that needs to be set + * @param __HANDLE__ specifies the OSPI Handle. + * @param __FLAG__ specifies the OSPI clear register flag that needs to be set * This parameter can be one of the following values: * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag @@ -1046,6 +1049,8 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, ((PORT) == HAL_OSPIM_IOPORT_7_HIGH) || \ ((PORT) == HAL_OSPIM_IOPORT_8_LOW) || \ ((PORT) == HAL_OSPIM_IOPORT_8_HIGH)) + +#define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U)) /** @endcond */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pssi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pssi.h index 8b33335bf5..922fafa95c 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pssi.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pssi.h @@ -239,6 +239,9 @@ typedef enum #define PSSI_FLAG_RTT1B PSSI_SR_RTT1B /*!< 1 Byte Fifo Flag*/ #define PSSI_FLAG_RTT4B PSSI_SR_RTT4B /*!< 4 Bytes Fifo Flag*/ + + + /** * @} */ @@ -253,6 +256,9 @@ typedef enum /** * @} */ + + + /** * @} */ @@ -403,6 +409,7 @@ typedef enum * @} */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup PSSI_Exported_Functions * @{ @@ -411,6 +418,7 @@ typedef enum /** @addtogroup PSSI_Exported_Functions_Group1 * @{ */ + /* Initialization and de-initialization functions *******************************/ HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi); HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi); @@ -420,6 +428,8 @@ void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi); HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID); + + /** * @} */ @@ -427,6 +437,7 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS /** @addtogroup PSSI_Exported_Functions_Group2 * @{ */ + /* IO operation functions *******************************************************/ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout); @@ -434,6 +445,7 @@ HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDa HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size); HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi); void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi); + /** * @} */ @@ -441,10 +453,13 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi); /** @addtogroup PSSI_Exported_Functions_Group3 * @{ */ + void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi); void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi); void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi); void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi); + + /** * @} */ @@ -452,9 +467,11 @@ void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi); /** @addtogroup PSSI_Exported_Functions_Group4 * @{ */ + /* Peripheral State functions ***************************************************/ HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi); -uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi); +uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi); + /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h index b67222dbc0..4379cbe39d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h @@ -12,7 +12,7 @@ * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -25,11 +25,11 @@ extern "C" { #endif -#if defined(QUADSPI) - /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal_def.h" +#if defined(QUADSPI) + /** @addtogroup STM32H7xx_HAL_Driver * @{ */ @@ -46,35 +46,27 @@ /** * @brief QSPI Init structure definition */ - typedef struct { uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. This parameter can be a number between 0 and 255 */ - uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) This parameter can be a value between 1 and 32 */ - uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) This parameter can be a value of @ref QSPI_SampleShifting */ - uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits required to address the flash memory. The flash capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB This parameter can be a number between 0 and 31 */ - uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number of clock cycles which the chip select must remain high between commands. This parameter can be a value of @ref QSPI_ChipSelectHighTime */ - uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. This parameter can be a value of @ref QSPI_ClockMode */ - uint32_t FlashID; /* Specifies the Flash which will be used, This parameter can be a value of @ref QSPI_Flash_Select */ - uint32_t DualFlash; /* Specifies the Dual Flash Mode State This parameter can be a value of @ref QSPI_DualFlash_Mode */ }QSPI_InitTypeDef; @@ -102,7 +94,7 @@ typedef enum typedef struct __QSPI_HandleTypeDef #else typedef struct -#endif/* USE_HAL_QSPI_REGISTER_CALLBACKS */ +#endif { QUADSPI_TypeDef *Instance; /* QSPI registers base address */ QSPI_InitTypeDef Init; /* QSPI communication parameters */ @@ -112,7 +104,7 @@ typedef struct uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ - MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */ + MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */ __IO HAL_LockTypeDef Lock; /* Locking object */ __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ __IO uint32_t ErrorCode; /* QSPI Error code */ @@ -157,13 +149,13 @@ typedef struct This parameter can be a value of @ref QSPI_AlternateBytesMode */ uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) This parameter can be a value of @ref QSPI_DataMode */ - uint32_t NbData; /* Specifies the number of data to transfer. + uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length until end of memory)*/ uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase This parameter can be a value of @ref QSPI_DdrMode */ - uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of - system clock in DDR mode. + uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data + output by one half of system clock in DDR mode. This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ uint32_t SIOOMode; /* Specifies the send instruction only once mode This parameter can be a value of @ref QSPI_SIOOMode */ @@ -195,7 +187,7 @@ typedef struct { uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. This parameter can be any value between 0 and 0xFFFF */ - uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select. + uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. This parameter can be a value of @ref QSPI_TimeOutActivation */ }QSPI_MemoryMappedTypeDef; @@ -235,11 +227,11 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @defgroup QSPI_ErrorCode QSPI Error Code * @{ */ -#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ -#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ -#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ -#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ +#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ +#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ +#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ +#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ #endif @@ -250,7 +242,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @defgroup QSPI_SampleShifting QSPI Sample Shifting * @{ */ -#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!Instance->CR, QUADSPI_CR_EN) /** @brief Disable the QSPI peripheral. - * @param __HANDLE__: specifies the QSPI Handle. + * @param __HANDLE__ : specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Enable the specified QSPI interrupt. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to enable. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -501,8 +493,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @brief Disable the specified QSPI interrupt. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to disable. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -514,8 +506,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** @brief Check whether the specified QSPI interrupt source is enabled or not. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to check. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to check. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -528,8 +520,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** * @brief Check whether the selected QSPI flag is set or not. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __FLAG__: specifies the QSPI flag to check. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __FLAG__ : specifies the QSPI flag to check. * This parameter can be one of the following values: * @arg QSPI_FLAG_BUSY: QSPI Busy flag * @arg QSPI_FLAG_TO: QSPI Timeout flag @@ -542,8 +534,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) /** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __FLAG__: specifies the QSPI clear register flag that needs to be set + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set * This parameter can be one of the following values: * @arg QSPI_FLAG_TO: QSPI Timeout flag * @arg QSPI_FLAG_SM: QSPI Status match flag @@ -560,12 +552,22 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @addtogroup QSPI_Exported_Functions * @{ */ + +/** @addtogroup QSPI_Exported_Functions_Group1 + * @{ + */ /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); +/** + * @} + */ +/** @addtogroup QSPI_Exported_Functions_Group2 + * @{ + */ /* IO operation functions *****************************************************/ /* QSPI IRQ handler method */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); @@ -628,12 +630,15 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint3 * @} */ +/** + * @} + */ /* End of exported functions -------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup QSPI_Private_Macros QSPI Private Macros -* @{ -*/ + * @{ + */ #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) @@ -655,7 +660,6 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint3 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ ((CLKMODE) == QSPI_CLOCK_MODE_3)) - #define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ ((FLASH_ID) == QSPI_FLASH_ID_2)) @@ -732,11 +736,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint3 * @} */ -/** - * @} - */ - -#endif /* QUADSPI */ +#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h index b51161a631..eb02e9e97a 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h @@ -294,10 +294,10 @@ typedef struct /** @defgroup RCC_PLL1_VCI_Range RCC PLL1 VCI Range * @{ */ -#define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0 -#define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1 -#define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2 -#define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3 +#define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0 /*!< Clock range frequency between 1 and 2 MHz */ +#define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1 /*!< Clock range frequency between 2 and 4 MHz */ +#define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2 /*!< Clock range frequency between 4 and 8 MHz */ +#define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3 /*!< Clock range frequency between 8 and 16 MHz */ /** @@ -1176,6 +1176,7 @@ typedef struct } while(0) #endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ @@ -1183,7 +1184,9 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ UNUSED(tmpreg); \ } while(0) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ @@ -1191,6 +1194,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ UNUSED(tmpreg); \ } while(0) +#endif /* HASH */ #define __HAL_RCC_RNG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1280,8 +1284,12 @@ typedef struct #else #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) #endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) +#endif /* HASH */ #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) #if defined(RCC_AHB2ENR_D2SRAM1EN) @@ -1316,8 +1324,12 @@ typedef struct #else #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U) #endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U) +#endif /* HASH */ #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U) #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U) #if defined(RCC_AHB2ENR_D2SRAM1EN) @@ -1346,8 +1358,12 @@ typedef struct #else #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U) #endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U) +#endif /* HASH */ #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U) #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U) #if defined(RCC_AHB2ENR_D2SRAM1EN) @@ -2711,7 +2727,7 @@ typedef struct tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ UNUSED(tmpreg); \ } while(0) - +#if defined(CRYP) #define __HAL_RCC_C1_CRYP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ @@ -2719,7 +2735,9 @@ typedef struct tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ UNUSED(tmpreg); \ } while(0) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_C1_HASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\ @@ -2727,6 +2745,7 @@ typedef struct tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\ UNUSED(tmpreg); \ } while(0) +#endif /* HASH */ #define __HAL_RCC_C1_RNG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -2769,8 +2788,12 @@ typedef struct } while(0) #define __HAL_RCC_C1_DCMI_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) +#if defined(CRYP) #define __HAL_RCC_C1_CRYP_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_C1_HASH_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) +#endif /* HASH */ #define __HAL_RCC_C1_RNG_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) #define __HAL_RCC_C1_SDMMC2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) #define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) @@ -3734,6 +3757,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(CRYP) #define __HAL_RCC_C2_CRYP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ @@ -3741,7 +3765,9 @@ typedef struct tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ UNUSED(tmpreg); \ } while(0) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_C2_HASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\ @@ -3749,6 +3775,7 @@ typedef struct tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\ UNUSED(tmpreg); \ } while(0) +#endif /* HASH */ #define __HAL_RCC_C2_RNG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -3791,8 +3818,12 @@ typedef struct } while(0) #define __HAL_RCC_C2_DCMI_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) +#if defined(CRYP) #define __HAL_RCC_C2_CRYP_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_C2_HASH_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) +#endif /* HASH */ #define __HAL_RCC_C2_RNG_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) #define __HAL_RCC_C2_SDMMC2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) #define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) @@ -4528,7 +4559,7 @@ typedef struct /** @brief Enable or disable the AHB3 peripheral reset. */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x7FFFFFFFU) #define __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST)) #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST)) #if defined(JPEG) @@ -4637,8 +4668,12 @@ typedef struct #else #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) #endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) +#endif /* HASH */ #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST)) #if defined(RCC_AHB2RSTR_HSEMRST) @@ -4655,8 +4690,12 @@ typedef struct #else #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST)) #endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST)) +#endif /* HASH */ #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST)) #if defined(RCC_AHB2RSTR_HSEMRST) @@ -5240,8 +5279,12 @@ typedef struct #else #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) #endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) #if defined(RCC_AHB2LPENR_DFSDMDMALPEN) @@ -5267,8 +5310,12 @@ typedef struct #else #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) #endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) #if defined(RCC_AHB2LPENR_DFSDMDMALPEN) @@ -5301,8 +5348,12 @@ typedef struct #else #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U) #endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U) +#endif /* HASH */ #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U) #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U) #if defined(RCC_AHB2LPENR_DFSDMDMALPEN) @@ -5328,8 +5379,12 @@ typedef struct #else #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U) #endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U) +#endif /* HASH */ #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U) #if defined(RCC_AHB2LPENR_DFSDMDMALPEN) #define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U) @@ -6010,8 +6065,12 @@ typedef struct */ #define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) #define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ #define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) #define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) @@ -6019,8 +6078,12 @@ typedef struct #define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) #define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) #define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ #define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) #define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) @@ -6298,8 +6361,12 @@ typedef struct */ #define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) #define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ #define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) #define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) @@ -6307,8 +6374,12 @@ typedef struct #define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) #define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) #define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ #define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) #define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h index 07e4c9547a..5e4a8aec2e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h @@ -461,10 +461,10 @@ typedef struct /** @defgroup RCC_PLL2_VCI_Range RCC PLL2 VCI Range * @{ */ -#define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0 -#define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1 -#define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2 -#define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3 +#define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0 /*!< Clock range frequency between 1 and 2 MHz */ +#define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1 /*!< Clock range frequency between 2 and 4 MHz */ +#define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2 /*!< Clock range frequency between 4 and 8 MHz */ +#define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3 /*!< Clock range frequency between 8 and 16 MHz */ /** * @} @@ -484,10 +484,10 @@ typedef struct /** @defgroup RCC_PLL3_VCI_Range RCC PLL3 VCI Range * @{ */ -#define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0 -#define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1 -#define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2 -#define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3 +#define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0 /*!< Clock range frequency between 1 and 2 MHz */ +#define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1 /*!< Clock range frequency between 2 and 4 MHz */ +#define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2 /*!< Clock range frequency between 4 and 8 MHz */ +#define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3 /*!< Clock range frequency between 8 and 16 MHz */ /** * @} @@ -1511,6 +1511,14 @@ typedef struct #endif /*DUAL_CORE*/ +/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line + * @{ + */ +#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ +/** + * @} + */ + /** @defgroup RCCEx_CRS_Status RCCEx CRS Status * @{ */ @@ -3403,6 +3411,134 @@ typedef struct /** * @} */ + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Line. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Line. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Event Line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Event Line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) + +#if defined(DUAL_CORE) +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Line for CM4. + * @retval None + */ +#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Line for CM4. + * @retval None + */ +#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Event Line for CM4. + * @retval None. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Event Line for CM4. + * @retval None. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS) +#endif /* DUAL_CORE */ + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. + * @retval EXTI RCC LSE CSS Line Status. + */ +#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) + +/** + * @brief Clear the RCC LSE CSS EXTI flag. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) + +#if defined(DUAL_CORE) +/** + * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not for CM4. + * @retval EXTI RCC LSE CSS Line Status. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) + +/** + * @brief Clear the RCC LSE CSS EXTI flag or not for CM4. + * @retval None. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) +#endif /* DUAL_CORE */ +/** + * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) + /** * @brief Enable the specified CRS interrupts. * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. @@ -3583,6 +3719,9 @@ void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); void HAL_RCCEx_EnableLSECSS(void); void HAL_RCCEx_DisableLSECSS(void); +void HAL_RCCEx_EnableLSECSS_IT(void); +void HAL_RCCEx_LSECSS_IRQHandler(void); +void HAL_RCCEx_LSECSS_Callback(void); #if defined(DUAL_CORE) void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx); #endif /*DUAL_CORE*/ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h index c794031a63..15b610e812 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h @@ -228,6 +228,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) #define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +#define HAL_USART_ERROR_RTO ((uint32_t)0x00000080U) /*!< Receiver Timeout error */ /** * @} */ @@ -352,6 +353,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin #define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */ #define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */ #define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */ +#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */ #define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ #define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */ #define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */ @@ -406,6 +408,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin #define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ #define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */ #define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */ +#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */ /** * @} */ @@ -462,6 +465,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_FLAG_TC Transmission Complete flag * @arg @ref USART_FLAG_RXNE Receive data register not empty flag * @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag + * @arg @ref USART_FLAG_RTOF Receiver Timeout flag * @arg @ref USART_FLAG_IDLE Idle Line detection flag * @arg @ref USART_FLAG_ORE OverRun Error flag * @arg @ref USART_FLAG_NE Noise Error flag @@ -482,6 +486,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag * @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag * @retval None */ @@ -632,6 +637,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag * @retval None diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart_ex.h index 8b6fe98ef8..b6987263df 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart_ex.h @@ -46,7 +46,7 @@ extern "C" { * @{ */ #define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ #define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} @@ -169,7 +169,6 @@ extern "C" { } \ } while(0U) - /** * @brief Ensure that USART frame length is valid. * @param __LENGTH__ USART frame length. diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h index 639565bb46..095202d500 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h @@ -969,6 +969,50 @@ __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL)); } +/** + * @brief Enable DMA stream bufferable transfer. + * @rmtoll CR TRBUFF LL_DMA_EnableBufferableTransfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + register uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF); +} + +/** + * @brief Disable DMA stream bufferable transfer. + * @rmtoll CR TRBUFF LL_DMA_DisableBufferableTransfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + register uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF); +} + /** * @brief Set Number of data to transfer. * @rmtoll NDTR NDT LL_DMA_SetDataLength diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h index 6354b763a6..185a7dc138 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h @@ -457,10 +457,10 @@ typedef struct /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank * @{ */ -#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U) -#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U) -#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U) -#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U) +#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) +#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) +#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) +#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) /** * @} */ @@ -468,8 +468,8 @@ typedef struct /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing * @{ */ -#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U) -#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U) +#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) +#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002) /** * @} */ @@ -477,9 +477,9 @@ typedef struct /** @defgroup FMC_Memory_Type FMC Memory Type * @{ */ -#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U) -#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U) -#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U) +#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) +#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004) +#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008) /** * @} */ @@ -487,9 +487,9 @@ typedef struct /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width * @{ */ -#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) -#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) -#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) +#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) +#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) /** * @} */ @@ -497,8 +497,8 @@ typedef struct /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access * @{ */ -#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U) -#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U) +#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040) +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) /** * @} */ @@ -506,8 +506,8 @@ typedef struct /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode * @{ */ -#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U) -#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U) +#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) +#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100) /** * @} */ @@ -515,8 +515,8 @@ typedef struct /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity * @{ */ -#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U) -#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U) +#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) +#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200) /** * @} */ @@ -524,8 +524,8 @@ typedef struct /** @defgroup FMC_Wait_Timing FMC Wait Timing * @{ */ -#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U) -#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U) +#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) +#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800) /** * @} */ @@ -533,8 +533,8 @@ typedef struct /** @defgroup FMC_Write_Operation FMC Write Operation * @{ */ -#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U) -#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U) +#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) +#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000) /** * @} */ @@ -542,8 +542,8 @@ typedef struct /** @defgroup FMC_Wait_Signal FMC Wait Signal * @{ */ -#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U) -#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U) +#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) +#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000) /** * @} */ @@ -551,8 +551,8 @@ typedef struct /** @defgroup FMC_Extended_Mode FMC Extended Mode * @{ */ -#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U) -#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U) +#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) +#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000) /** * @} */ @@ -560,8 +560,8 @@ typedef struct /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait * @{ */ -#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U) -#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U) +#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) +#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000) /** * @} */ @@ -569,7 +569,7 @@ typedef struct /** @defgroup FMC_Page_Size FMC Page Size * @{ */ -#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U) +#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0) #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1) #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1)) @@ -581,8 +581,8 @@ typedef struct /** @defgroup FMC_Write_Burst FMC Write Burst * @{ */ -#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U) -#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U) +#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) +#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000) /** * @} */ @@ -590,8 +590,8 @@ typedef struct /** @defgroup FMC_Continous_Clock FMC Continuous Clock * @{ */ -#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U) -#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U) +#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) +#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000) /** * @} */ @@ -600,7 +600,7 @@ typedef struct * @{ */ #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS) -#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U) +#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000) /** * @} */ @@ -608,10 +608,10 @@ typedef struct /** @defgroup FMC_Access_Mode FMC Access Mode * @{ */ -#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U) -#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U) -#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U) -#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U) +#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000) +#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000) +#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000) +#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000) /** * @} */ @@ -627,7 +627,7 @@ typedef struct /** @defgroup FMC_NAND_Bank FMC NAND Bank * @{ */ -#define FMC_NAND_BANK3 ((uint32_t)0x00000100U) +#define FMC_NAND_BANK3 ((uint32_t)0x00000100) /** * @} */ @@ -635,8 +635,8 @@ typedef struct /** @defgroup FMC_Wait_feature FMC Wait feature * @{ */ -#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U) -#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U) +#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) +#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002) /** * @} */ @@ -644,7 +644,7 @@ typedef struct /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type * @{ */ -#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U) +#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008) /** * @} */ @@ -652,8 +652,8 @@ typedef struct /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width * @{ */ -#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) -#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) +#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) +#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) /** * @} */ @@ -661,8 +661,8 @@ typedef struct /** @defgroup FMC_ECC FMC ECC * @{ */ -#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U) -#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U) +#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) +#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040) /** * @} */ @@ -670,12 +670,12 @@ typedef struct /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size * @{ */ -#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U) -#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U) -#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U) -#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U) -#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U) -#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U) +#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) +#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000) +#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000) +#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000) +#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000) +#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000) /** * @} */ @@ -690,8 +690,8 @@ typedef struct /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank * @{ */ -#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U) -#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U) +#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000) +#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001) /** * @} */ @@ -699,10 +699,10 @@ typedef struct /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number * @{ */ -#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U) -#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U) -#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U) -#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U) +#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000) +#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001) +#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002) +#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003) /** * @} */ @@ -710,9 +710,9 @@ typedef struct /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number * @{ */ -#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U) -#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U) -#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U) +#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000) +#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004) +#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008) /** * @} */ @@ -720,9 +720,9 @@ typedef struct /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width * @{ */ -#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) -#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) -#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) +#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) +#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) +#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) /** * @} */ @@ -730,8 +730,8 @@ typedef struct /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number * @{ */ -#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U) -#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U) +#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000) +#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040) /** * @} */ @@ -739,9 +739,9 @@ typedef struct /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency * @{ */ -#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U) -#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U) -#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180U) +#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080) +#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100) +#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180) /** * @} */ @@ -749,8 +749,8 @@ typedef struct /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection * @{ */ -#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U) -#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U) +#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000) +#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200) /** * @} */ @@ -758,9 +758,9 @@ typedef struct /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period * @{ */ -#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U) -#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U) -#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00U) +#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000) +#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800) +#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00) /** * @} */ @@ -768,8 +768,8 @@ typedef struct /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst * @{ */ -#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U) -#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U) +#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000) +#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000) /** * @} */ @@ -777,9 +777,9 @@ typedef struct /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay * @{ */ -#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U) -#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U) -#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U) +#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000) +#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000) +#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000) /** * @} */ @@ -787,13 +787,13 @@ typedef struct /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode * @{ */ -#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U) -#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U) -#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U) -#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U) -#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U) -#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U) -#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U) +#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000) +#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001) +#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002) +#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003) +#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004) +#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005) +#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006) /** * @} */ @@ -803,7 +803,7 @@ typedef struct */ #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 -#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U) +#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018) /** * @} */ @@ -811,7 +811,7 @@ typedef struct /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status * @{ */ -#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U) +#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000) #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 /** @@ -826,10 +826,10 @@ typedef struct /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition * @{ */ -#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U) -#define FMC_IT_LEVEL ((uint32_t)0x00000010U) -#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U) -#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U) +#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008) +#define FMC_IT_LEVEL ((uint32_t)0x00000010) +#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020) +#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000) /** * @} */ @@ -837,10 +837,10 @@ typedef struct /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition * @{ */ -#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U) -#define FMC_FLAG_LEVEL ((uint32_t)0x00000002U) -#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U) -#define FMC_FLAG_FEMPT ((uint32_t)0x00000040U) +#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001) +#define FMC_FLAG_LEVEL ((uint32_t)0x00000002) +#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004) +#define FMC_FLAG_FEMPT ((uint32_t)0x00000040) #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h index c24b53c568..a16dd28126 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h @@ -608,11 +608,6 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] = * @{ * @brief Constants defining timer high-resolution clock prescaler ratio. */ -#define LL_HRTIM_PRESCALERRATIO_MUL32 0x00000000U /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */ -#define LL_HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U) /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */ -#define LL_HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U) /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */ -#define LL_HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U) /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */ -#define LL_HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U) /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */ #define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */ #define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */ #define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */ @@ -2568,11 +2563,6 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, ui * @arg @ref LL_HRTIM_TIMER_D * @arg @ref LL_HRTIM_TIMER_E * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32 - * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16 - * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8 - * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4 - * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4 @@ -2598,11 +2588,6 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_TIMER_D * @arg @ref LL_HRTIM_TIMER_E * @retval Prescaler Returned value can be one of the following values: - * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32 - * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16 - * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8 - * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4 - * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4 diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lptim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lptim.h index d5a4fc9c06..2529003767 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lptim.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lptim.h @@ -375,7 +375,7 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); } /** @@ -428,7 +428,7 @@ __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL)); } /** @@ -772,7 +772,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); } /** @@ -1063,7 +1063,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); } /** @@ -1093,7 +1093,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL)); } /** @@ -1115,7 +1115,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); } /** @@ -1137,7 +1137,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); } /** @@ -1159,7 +1159,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL)); } /** @@ -1181,7 +1181,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); } /** @@ -1203,7 +1203,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); } /** @@ -1225,7 +1225,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); } /** @@ -1266,7 +1266,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL)); } /** @@ -1299,7 +1299,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL)); } /** @@ -1332,7 +1332,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL)); } /** @@ -1365,7 +1365,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL)); } /** @@ -1394,11 +1394,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). + * @retval State of bit(1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL)); } /** @@ -1427,11 +1427,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). + * @retval State of bit(1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL)); } /** @@ -1460,11 +1460,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). + * @retval State of bit(1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) { - return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL); + return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL); } /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h index f6a85519b4..e2ccb71ded 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h @@ -1419,9 +1419,9 @@ typedef struct * @retval SYSCLK clock frequency (in Hz) */ #if defined(RCC_D1CFGR_D1CPRE) -#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) +#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU)) #else -#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) +#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU)) #endif /* RCC_D1CFGR_D1CPRE */ /** @@ -1440,9 +1440,9 @@ typedef struct * @retval HCLK clock frequency (in Hz) */ #if defined(RCC_D1CFGR_HPRE) -#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) +#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)) #else -#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) +#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)) #endif /* RCC_D1CFGR_HPRE */ /** @@ -1457,9 +1457,9 @@ typedef struct * @retval PCLK1 clock frequency (in Hz) */ #if defined(RCC_D2CFGR_D2PPRE1) -#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) +#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)) #else -#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) +#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)) #endif /* RCC_D2CFGR_D2PPRE1 */ /** @@ -1474,9 +1474,9 @@ typedef struct * @retval PCLK2 clock frequency (in Hz) */ #if defined(RCC_D2CFGR_D2PPRE2) -#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) +#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)) #else -#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) +#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)) #endif /* RCC_D2CFGR_D2PPRE2 */ /** @@ -1491,9 +1491,9 @@ typedef struct * @retval PCLK1 clock frequency (in Hz) */ #if defined(RCC_D1CFGR_D1PPRE) -#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos]) +#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU)) #else -#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) +#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) & 0x1FU)) #endif /* RCC_D1CFGR_D1PPRE */ /** @@ -1508,9 +1508,9 @@ typedef struct * @retval PCLK1 clock frequency (in Hz) */ #if defined(RCC_D3CFGR_D3PPRE) -#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos]) +#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU)) #else -#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos]) +#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos]) & 0x1FU)) #endif /* RCC_D3CFGR_D3PPRE */ /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h index 5b729e72af..2c3c51342d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h @@ -220,13 +220,14 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ - uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ } LL_TIM_InitTypeDef; @@ -1734,7 +1735,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) * whether or not a timer instance supports a repetition counter. * @rmtoll RCR REP LL_TIM_SetRepetitionCounter * @param TIMx Timer instance - * @param RepetitionCounter between Min_Data=0 and Max_Data=255 + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. * @retval None */ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h index 8e2e154cf5..e090a1ed0b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h @@ -2651,7 +2651,8 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) { /* In Asynchronous mode, the following bits must be kept cleared: - LINEN, CLKEN bits in the USART_CR2 register, - - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); } @@ -2687,7 +2688,8 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) { /* In Synchronous mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register, - - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); /* set the UART/USART in Synchronous mode */ @@ -2727,7 +2729,8 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) { /* In LIN mode, the following bits must be kept cleared: - STOP and CLKEN bits in the USART_CR2 register, - - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); /* Set the UART/USART in LIN mode */ @@ -2765,7 +2768,8 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) { /* In Half Duplex mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ + - SCEN and IREN bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); /* set the UART/USART in Half Duplex mode */ @@ -2805,7 +2809,8 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) { /* In Smartcard mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register, - - IREN and HDSEL bits in the USART_CR3 register.*/ + - IREN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); /* Configure Stop bits to 1.5 bits */ @@ -2848,7 +2853,8 @@ __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) { /* In IRDA mode, the following bits must be kept cleared: - LINEN, STOP and CLKEN bits in the USART_CR2 register, - - SCEN and HDSEL bits in the USART_CR3 register.*/ + - SCEN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); /* set the UART/USART in IRDA mode */ @@ -2886,7 +2892,8 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) { /* In Multi Processor mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h index 63912648df..3dc60e7899 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h @@ -121,13 +121,13 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_RCC_PLL1_SetFRACN(). */ - uint32_t VCO_Input; /*!< Fractional part of the multiplication factor for PLL VCO. + uint32_t VCO_Input; /*!< PLL clock Input range. This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE This feature can be modified afterwards using unitary function @ref LL_RCC_PLL1_SetVCOInputRange(). */ - uint32_t VCO_Output; /*!< Fractional part of the multiplication factor for PLL VCO. + uint32_t VCO_Output; /*!< PLL clock Output range. This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE This feature can be modified afterwards using unitary function @@ -213,11 +213,11 @@ typedef struct #define LL_UTILS_PACKAGETYPE_LQFP144 0x00000005UL /*!< LQFP144 package type */ #define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x00000006UL /*!< LQFP144 with SMPS package type */ #define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007UL /*!< UFBGA169 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 0x00000010UL /*!< UFBGA176 or LQFP176 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x00000011UL /*!< LQFP176 with SMPS package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x00000012UL /*!< UFBGA176 with SMPS package type */ -#define LL_UTILS_PACKAGETYPE_TFBGA216 0x00000014UL /*!< TFBGA216 package type */ -#define LL_UTILS_PACKAGETYPE_TFBGA225 0x00000016UL /*!< TFBGA225 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 0x00000008UL /*!< UFBGA176 or LQFP176 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x00000009UL /*!< LQFP176 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000AUL /*!< UFBGA176 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA216 0x0000000CUL /*!< TFBGA216 package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA225 0x0000000EUL /*!< TFBGA225 package type */ #endif /* SYSCFG_PKGR_PKG */ /** * @} @@ -355,6 +355,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html index bc59796291..37472cbb4f 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html @@ -38,10 +38,249 @@

                              License

                              Update History

                              - +

                              Main Changes

                                +
                              • General updates to fix known defects and implementation enhancements
                                • +
                              • HAL: generic +
                                  +
                                • stm32h7xx_hal.c: +
                                    +
                                  • Update HAL_Init implementation to reflect the current core clock in SystemCoreClock global variable (Corex-M7 or Corext-M4 clock depending of the current context in case of Dual Core)
                                    • +
                                  • Update HAL_InitTick implementation to use SystemCoreClock global variable as it reflect now the current core clock (simplifying the implementation)
                                    • +
                                  • +
                                • +
                              • HAL DAC: +
                                  +
                                • stm32h7xx_hal_dac.c: +
                                    +
                                  • Update HAL_DAC_ConfigChannel function implemenation to fix the “DAC_ConnectOnChipPeripheral” check and settings
                                    • +
                                  • +
                                • +
                              • HAL/LL GPIO: +
                                  +
                                • stm32h7xx_hal_gpio.h +
                                    +
                                  • Update IS_GPIO_PIN macro implementation with an explicit cast to avoid compilation warning on EWARM 8.30
                                    • +
                                  • +
                                • stm32h7xx_hal_gpio_ex.h +
                                    +
                                  • Remove useless GPIO_AF13_TIM8 define
                                    • +
                                  • Update GPIOK_PIN_AVAILABLE define to consider missed GPIO Pin 2
                                    • +
                                  • +
                                • stm32h7xx_hal_gpio.c: +
                                    +
                                  • Update HAL_GPIO_Init and HAL_GPIO_DeInit functions implementation to avoid a glitch during GPIO initialization/de-initialization
                                    • +
                                  • +
                                • stm32h7xx_ll_gpio.c: +
                                    +
                                  • Update LL_GPIO_Init function implementation to avoid a glitch during GPIO initialization
                                    • +
                                  • +
                                • +
                              • HAL/LL HRTIM: +
                                  +
                                • stm32h7xx_hal_hrtim.h +
                                    +
                                  • Remove HRTIM_PRESCALERRATIO_MUL2 to HRTIM_PRESCALERRATIO_MUL32 definition that are not supported on STM32H7 devices
                                    • +
                                  • +
                                • stm32h7xx_ll_hrtim.h +
                                    +
                                  • Remove LL_HRTIM_PRESCALERRATIO_MUL2 to LL_HRTIM_PRESCALERRATIO_MUL32 definition that are not supported on STM32H7 devices
                                    • +
                                  • +
                                • Note: Only Prescaler ratios 1/2/4 are supported for HRTIM on STM32H7 devices
                                  • +
                                • +
                              • HAL I2C: +
                                  +
                                • stm32h7xx_hal_i2c.h +
                                    +
                                  • Updates to fix incorrectly enable interrupts in I2C_Enable_IRQ routine when InterruptRequest = I2C_XFER_CPLT_IT
                                    • +
                                  • Updates to avoid HardFault in I2C_DMAAbort when DMA is not used for Tx or/and Rx
                                    • +
                                  • +
                                • +
                              • HAL JPEG: +
                                  +
                                • stm32h7xx_hal_jpeg.h: Minor update for STM32 coding rules compliance (one line per variable declaration, local variables naming …)
                                  • +
                                • +
                              • HAL/LL LPTIM: +
                                  +
                                • stm32h7xx_hal_lptim.c: +
                                    +
                                  • Update HAL_LPTIM_Init implementation to configure digital filter for external clock when LPTIM is clocked by an internal clock source
                                    • +
                                  • +
                                • +
                              • HAL MMC: +
                                  +
                                • stm32h7xx_hal_mmc.c: +
                                    +
                                  • Update implementation to avoid setting the block size during every MMC card transaction (block size is set once in HAL_MMC_InitCard )
                                    • +
                                  • +
                                • +
                              • HAL NAND: +
                                  +
                                • stm32h7xx_hal_nand.h: Minor update to use UL/U suffix respectively instead of uint32_t/uint8_t cast
                                  • +
                                • +
                              • HAL NOR: +
                                  +
                                • stm32h7xx_hal_nor.h: Minor update to remove useless U suffix following uint32_t/uint16_t/uint8_t cast
                                  • +
                                • +
                              • HAL OSPI: Add support of multiplexed mode feature +
                                  +
                                • stm32h7xx_hal_ospi.h: +
                                    +
                                  • Update “OSPIM_CfgTypeDef” structure definition to add “Req2AckTime” allowing to set the “minimum switching duration” clock cycles when OSPI signals are multiplexed in the OSPI IO Manager
                                    • +
                                  • Add IS_OSPIM_REQ2ACKTIME macro useful when the HAL assert is enabled and allowing to check the “Req2AckTime” value validity
                                    +
                                    • +
                                  • +
                                • stm32h7xx_hal_ospi.c: +
                                    +
                                  • Update “HAL_OSPIM_Config” implementation to support OSPI signals Mux using the OSPI IO Manager
                                    • +
                                  • +
                                • +
                              • HAL PSSI: +
                                  +
                                • stm32h7xx_hal_pssi.c: +
                                    +
                                  • Update HAL_PSSI_Transmit/HAL_PSSI_Receive implementation to fix warning on GCC compiler
                                    • +
                                  • +
                                • +
                              • HAL QSPI: +
                                  +
                                • stm32h7xx_hal_qspi.h: +
                                    +
                                  • Rename HAL_QPSI_TIMEOUT_DEFAULT_VALUE define to HAL_QSPI_TIMEOUT_DEFAULT_VALUE (typo fix). backward compatibility ensured through stm32_hal_legacy.h header file
                                    +
                                    • +
                                  • +
                                • stm32h7xx_hal_qspi.c: +
                                    +
                                  • Update HAL_QSPI_Init/HAL_QSPI_DeInit implementation to remove useless lock/unlock
                                    • +
                                  • Update HAL_QSPI_IRQHandler implementation to optimize flags check
                                    • +
                                  • Update HAL_QSPI_Transmit_DMA to: +
                                      +
                                    • Fix performance issue at high frequency by fixing wrong activation of TC interrupt
                                      • +
                                    • Enabling QUADSPI_CR_DMAEN bit field: used only by the HAL_QSPI_IRQHandler to check if current Transmit is using DMA when IT occurs
                                      • +
                                    • +
                                  • Update HAL_QSPI_Receive_DMA to enable QUADSPI_CR_DMAEN bit field: used only by the HAL_QSPI_IRQHandler to check if current Receive is using DMA when IT occurs
                                    • +
                                  • Update HAL_QSPI_Abort to reset functional mode configuration to indirect write mode by default
                                    +
                                    • +
                                  • Update HAL_QSPI_Abort_IT to call Abort Complete callback
                                    • +
                                  • +
                                • +
                              • HAL/LL RCC: +
                                  +
                                • stm32h7xx_hal_rcc.h: +
                                    +
                                  • Delimit CRYP and HASH Clock enable/disable/reset/sleep macros with conditional define on respectively CRYP/HASH availability (through CMSIS device header files)
                                    • +
                                  • Update __HAL_RCC_AHB3_FORCE_RESET macro implementation to avoid altering reserved bit 31.
                                    • +
                                  • +
                                • stm32h7xx_hal_rcc_ex.h: +
                                    +
                                  • Add definition of RCC_EXTI_LINE_LSECSS (EXTI IMR1 EXTI line 18)
                                    • +
                                  • Add macros __HAL_RCC_LSECSS_EXTI_ENABLE_IT, __HAL_RCC_LSECSS_EXTI_DISABLE_IT, __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT and __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT
                                    • +
                                  • Add macros __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT, __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT, __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT, __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT: for Dual Core lines allowing to control LSECSS EXTI Line for Coretx-M4.
                                    • +
                                  • Add macros __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE, __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE, __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE, __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE, __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE, __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE, __HAL_RCC_LSECSS_EXTI_GET_FLAG and __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG.
                                    • +
                                  • Add macros __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG and __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG for Dual Core lines allowing to get/clear LSECSS EXTI line on Coretx-M4.
                                    • +
                                  • Add macro __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT
                                    • +
                                  • Add prototypes for new APIs HAL_RCCEx_EnableLSECSS_IT, HAL_RCCEx_LSECSS_IRQHandler and HAL_RCCEx_LSECSS_Callback.
                                    • +
                                  • +
                                • stm32h7xx_ll_rcc.h: +
                                    +
                                  • Update LL_RCC_CALC_SYSCLK_FREQ, LL_RCC_CALC_HCLK_FREQ, LL_RCC_CALC_PCLK1_FREQ, LL_RCC_CALC_PCLK2_FREQ, LL_RCC_CALC_PCLK3_FREQ and LL_RCC_CALC_PCLK4_FREQ macros implementation to avoid overflow (MISRA-C 2012 compliant)
                                    +
                                    • +
                                  • +
                                • stm32h7xx_hal_rcc.c: +
                                    +
                                  • Update HAL_RCC_DeInit, HAL_RCC_ClockConfig, HAL_RCC_GetHCLKFreq and HAL_RCC_GetPCLK1Freq to reflect the current core clock in SystemCoreClock global variable (Corex-M7 or Corext-M4 clock depending of the current context in case of Dual Core)
                                    • +
                                  • +
                                • stm32h7xx_hal_rcc_ex.c: +
                                    +
                                  • Update HAL_RCCEx_GetD1SysClockFreq to reflect the current core clock in SystemCoreClock global variable (Corex-M7 or Corext-M4 clock depending of the current context in case of Dual Core).
                                    • +
                                  • Add HAL_RCCEx_EnableLSECSS_IT, HAL_RCCEx_LSECSS_IRQHandler and HAL_RCCEx_LSECSS_Callback APIs: allowing to handle LSECSS interrupt.
                                    • +
                                  • +
                                • +
                              • HAL SD: +
                                  +
                                • stm32h7xx_hal_sd.c: +
                                    +
                                  • Update HAL_SD_InitCard implementation to fix compilation issue when USE_SD_TRANSCEIVER is disabled and USE_SD_DIRPOL enabled
                                    • +
                                  • Update implementation to avoid setting the block size during every SD card transaction (block size is set once in HAL_SD_InitCard, HAL_SD_GetCardStatus, HAL_SD_ConfigWideBusOperation)
                                    • +
                                  • +
                                • stm32h7xx_hal_sd_ex.c: +
                                    +
                                  • Update HAL_SDEx_ReadBlocksDMAMultiBuffer and HAL_SDEx_WriteBlocksDMAMultiBuffer to avoid setting the block size during every SD card transaction
                                    • +
                                  • +
                                • +
                              • HAL/LL TIM: +
                                  +
                                • stm32h7xx_hal_tim.c: Minor fixes with the assert parameters checks
                                  • +
                                • +
                              • HAL/LL USART: Add RTO (Receive Time Out) flag support +
                                  +
                                • stm32h7xx_hal_usart.h +
                                    +
                                  • Add HAL_USART_ERROR_RTO define to USART Error Definition section
                                    • +
                                  • Add USART_FLAG_RTOF define to USART Flags section
                                    • +
                                  • Add USART_CLEAR_RTOF define to USART Interruption Clear Flags section
                                    • +
                                  • +
                                • stm32h7xx_hal_usart.c: Update HAL_USART_IRQHandler to handle USART_ISR_RTOF flag and IT
                                  • +
                                • stm32h7xx_hal_usart_ex.c: Update HAL_USARTEx_DisableSlaveMode to fix typo in disabling salve mode
                                  • +
                                • +
                              • HAL/LL DMA: Add support for DMA_SxCR_TRBUFF +
                                  +
                                • stm32h7xx_ll_dma.h +
                                    +
                                  • Add API “LL_DMA_EnableBufferableTransfer” allowing to enable bufferable transfer
                                    +
                                    • +
                                  • Add API “LL_DMA_DisableBufferableTransfer” allowing to disable bufferable transfer
                                    • +
                                  • +
                                • stm32h7xx_hal_dma.c: +
                                    +
                                  • Add workaround to fix Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be lock when transferring data to/from USART/UART +
                                      +
                                    • Enabling the DMA bufferable transfer when the request is from a UART/USART(DMA_SxCR_TRBUFF bit field)
                                      • +
                                    • +
                                  • +
                                • +
                              • HAL/LL TIM: +
                                  +
                                • stm32h7xx_ll_tim.h +
                                    +
                                  • Parameter “RepetitionCounter” of “LL_TIM_InitTypeDef” is now of type “uint32_t” with possible values from 0 to 0xFFFF for advanced timers
                                    • +
                                  • +
                                • +
                              • LL FMC: (Core LL driver for HAL NAND, NOR, SDRAM, SRAM, not user LL driver) +
                                  +
                                • stm32h7xx_ll_fmc.h: Minor update to remove useless U suffix following uint32_t cast
                                  • +
                                • stm32h7xx_ll_fmc.c: +
                                    +
                                  • Update FMC_NORSRAM_Init implemenation to fix compilation issue with MS Visual 2017
                                    • +
                                  • Update FMC_NAND_CommonSpace_Timing_Init, FMC_NAND_AttributeSpace_Timing_Init, FMC_NAND_ECC_Enable, FMC_NAND_ECC_Disable and FMC_NAND_GetECC to fix GCC compiler warning due to unused parameter
                                    • +
                                  • +
                                • +
                              • LL UTIL: +
                                  +
                                • stm32h7xx_ll_utils.h +
                                    +
                                  • Update numerical value of LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 to LL_UTILS_PACKAGETYPE_TFBGA225 definition to align with the Reference Manual
                                    • +
                                  • Add LL_SetFlashLatency API.
                                    • +
                                  • +
                                • stm32h7xx_ll_utils.c +
                                    +
                                  • Add implementation of LL_SetFlashLatency API (static functions UTILS_CalculateFlashLatency and UTILS_SetFlashLatency removed and repalced by the user API LL_SetFlashLatency)
                                    • +
                                  • Update LL_SetSystemCoreClock to keep only setting SystemCoreClock according to the current Core frequency (Corex-M7 or Coretx-M4 in case of Dual Core line). +
                                      +
                                    • SystemD2Clock reflecting the D2 domain frequency is now set within UTILS_EnablePLLAndSwitchSystem
                                      • +
                                    • +
                                  • +
                                • +
                              +
                              +
                              +
                              + +
                              +

                              Main Changes

                              +
                              • Official release with support of STM32H7A3/B3xx/B0xx new devices
                              • General updates to fix known defects and implementation enhancements
                                • @@ -633,7 +872,7 @@

                                Backward compatibility

                                -

                                Main Changes

                                +

                                Main Changes

                                • General updates to fix known defects and implementation enhancements
                                • HAL: generic @@ -930,7 +1169,7 @@

                                  Backward compatibility

                                  -

                                  Main Changes

                                  +

                                  Main Changes

                                  • General updates to fix known defects and implementation enhancements
                                  • Add support for VOS0 power regulator voltage scaling with 480MHz over clock
                                    • @@ -1466,7 +1705,7 @@

                                    Backward compatibility

                                    -

                                    Main Changes

                                    +

                                    Main Changes

                                    • General updates to fix known defects and implementation enhancements
                                    • Add LL drivers : LL_ADC, LL_BDMA, LL_BUS, LL_COMP, LL_CORTEX, LL_CRC, LL_DAC, LL_DMA, LL_DMA2D, LL_DMAMUX, LL_EXTI, LL_GPIO, LL_HRTIM, LL_HSEM, LL_I2C, LL_IWDG, LL_LPTIM, LL_LPUART, LL_MDMA, LL_OPAMP,LL_PWR, LL_RCC, LL_RNG, LL_RTC, LL_SPI, LL_SWPMI, LL_SYSTEM, LL_TIM, LL_USART, LL_UTILS, LL_WWDG
                                      • @@ -1783,7 +2022,7 @@

                                      Backward compatibility

                                      -

                                      Main Changes

                                      +

                                      Main Changes

                                      • Updates to fix known defects on HAL Cortex, HAL RCC and HAL SDMMC drivers
                                      • HAL Cortex: Driver update to support 16 MPU regions instead of 8. User can now select an MPU regions from MPU_REGION_NUMBER0 to MPU_REGION_NUMBER15
                                        • @@ -1795,7 +2034,7 @@

                                        Main Changes

                                        -

                                        Main Changes

                                        +

                                        Main Changes

                                        • General updates to fix known defects and enhancements implementation
                                        • HAL SPI: Driver reworked to fix critical issues
                                          • @@ -1806,7 +2045,7 @@

                                          Main Changes

                                          -

                                          Main Changes

                                          +

                                          Main Changes

                                          • General updates to fix known defects and enhancements implementation
                                          • HAL FLASH: Add Mass Erase for both banks
                                            • @@ -1821,7 +2060,7 @@

                                            Main Changes

                                            -

                                            Main Changes

                                            +

                                            Main Changes

                                            • First official release for STM32H743xx/753xx devices
                                            diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c index c52df22d8f..861bf403b9 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c @@ -47,10 +47,10 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** - * @brief STM32H7xx HAL Driver version number V1.7.0 + * @brief STM32H7xx HAL Driver version number V1.8.0 */ #define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ -#define __STM32H7xx_HAL_VERSION_SUB1 (0x07UL) /*!< [23:16] sub1 version */ +#define __STM32H7xx_HAL_VERSION_SUB1 (0x08UL) /*!< [23:16] sub1 version */ #define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */ #define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\ @@ -134,6 +134,8 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ HAL_StatusTypeDef HAL_Init(void) { +uint32_t common_system_clock; + #if defined(DUAL_CORE) && defined(CORE_CM4) /* Configure Cortex-M4 Instruction cache through ART accelerator */ __HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */ @@ -146,18 +148,24 @@ HAL_StatusTypeDef HAL_Init(void) /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); #else - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) - SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); #else - SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); #endif +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { @@ -259,32 +267,11 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) return HAL_ERROR; } -#if defined(DUAL_CORE) - if (HAL_GetCurrentCPUID() == CM7_CPUID) - { - /* Cortex-M7 detected */ - /* Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) - { - return HAL_ERROR; - } - } - else - { - /* Cortex-M4 detected */ - /* Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000UL / (uint32_t)uwTickFreq)) > 0U) - { - return HAL_ERROR; - } - } -#else /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) { return HAL_ERROR; } -#endif /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c index a9437eb650..89fbd803ea 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c @@ -1112,15 +1112,15 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ - if ((sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_EXTERNAL) == DAC_CHIPCONNECT_EXTERNAL) + if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) { connectOnChip = 0x00000000UL; } - else if ((sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_INTERNAL) == DAC_CHIPCONNECT_INTERNAL) + else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) { connectOnChip = DAC_MCR_MODE1_0; } - else /* (sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_BOTH) == DAC_CHIPCONNECT_BOTH */ + else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ { if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) { diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c index 399ae0e0b8..aeabc95a27 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c @@ -146,6 +146,19 @@ typedef struct #define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U) +#if defined(UART9) +#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_UART9_RX) && ((__REQUEST__) <= DMA_REQUEST_USART10_TX ))) +#else +#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX ))) + +#endif /** * @} */ @@ -278,6 +291,20 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; } + /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be + lock when transfering data to/from USART/UART */ +#if (STM32H7_DEV_ID == 0x450UL) + if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) + { +#endif /* STM32H7_DEV_ID == 0x450UL */ + if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) + { + registerValue |= DMA_SxCR_TRBUFF; + } +#if (STM32H7_DEV_ID == 0x450UL) + } +#endif /* STM32H7_DEV_ID == 0x450UL */ + /* Write to DMA Stream CR register */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c index 641c7e9342..25a19dea36 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c @@ -198,26 +198,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) if (iocurrent != 0x00U) { /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Alternate function parameters */ - assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3U]; - temp &= ~(0xFU << ((position & 0x07U) * 4U)); - temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); - GPIOx->AFR[position >> 3U] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); - GPIOx->MODER = temp; - /* In case of Output or Alternate function mode selection */ if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) @@ -243,6 +223,26 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp |= ((GPIO_Init->Pull) << (position * 2U)); GPIOx->PUPDR = temp; + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + temp &= ~(0xFU << ((position & 0x07U) * 4U)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3U] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + GPIOx->MODER = temp; + /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) @@ -333,9 +333,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) tmp &= (0x0FUL << (4U * (position & 0x03U))); if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) { - tmp = 0x0FUL << (4U * (position & 0x03U)); - SYSCFG->EXTICR[position >> 2U] &= ~tmp; - /* Clear EXTI line configuration for Current CPU */ EXTI_CurrentCPU->IMR1 &= ~(iocurrent); EXTI_CurrentCPU->EMR1 &= ~(iocurrent); @@ -343,6 +340,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Clear Rising Falling edge configuration */ EXTI->RTSR1 &= ~(iocurrent); EXTI->FTSR1 &= ~(iocurrent); + + tmp = 0x0FUL << (4U * (position & 0x03U)); + SYSCFG->EXTICR[position >> 2U] &= ~tmp; } /*------------------------- GPIO Mode Configuration --------------------*/ @@ -352,14 +352,14 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Configure the default Alternate Function in current IO */ GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ; - /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; - /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); } position++; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c index 1b8c17920e..a9e7408ce6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c @@ -351,13 +351,13 @@ /* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (0x00000001U) -#define I2C_XFER_RX_IT (0x00000002U) -#define I2C_XFER_LISTEN_IT (0x00000004U) +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */ -#define I2C_XFER_ERROR_IT (0x00000011U) -#define I2C_XFER_CPLT_IT (0x00000012U) -#define I2C_XFER_RELOAD_IT (0x00000012U) +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */ /* Private define Sequential Transfer Options default/reset value */ #define I2C_NO_OPTION_FRAME (0xFFFF0000U) @@ -410,6 +410,9 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + /* Private function to flush TXDR register */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); @@ -4251,9 +4254,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Locked */ __HAL_LOCK(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Set State at HAL_I2C_STATE_ABORT */ hi2c->State = HAL_I2C_STATE_ABORT; @@ -5001,6 +5016,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { uint32_t tmpoptions = hi2c->XferOptions; uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; /* Process locked */ __HAL_LOCK(hi2c); @@ -5079,8 +5095,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } @@ -5369,9 +5401,27 @@ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) */ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ @@ -5426,19 +5476,36 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + uint32_t tmp; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); /* Reset handle parameters */ - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -5447,12 +5514,18 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmp = (uint8_t)hi2c->Instance->RXDR; + + UNUSED(tmp); + } + /* Flush TX register */ I2C_Flush_TXDR(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); - /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; @@ -5466,6 +5539,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5500,6 +5574,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5546,12 +5621,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -5565,6 +5654,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if (hi2c->hdmatx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); @@ -5572,6 +5664,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if (hi2c->hdmarx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); @@ -5608,7 +5703,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -5631,6 +5725,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5646,6 +5741,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5660,6 +5756,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5733,6 +5830,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { HAL_I2C_StateTypeDef tmpstate = hi2c->State; + uint32_t tmppreviousstate; /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; @@ -5752,7 +5850,6 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* keep HAL_I2C_STATE_LISTEN if set */ hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = I2C_Slave_ISR_IT; } else @@ -5767,16 +5864,19 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; } /* Abort DMA TX transfer if any */ - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } - if (hi2c->hdmatx != NULL) + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5792,13 +5892,20 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } /* Abort DMA RX transfer if any */ - else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } - if (hi2c->hdmarx != NULL) + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5814,10 +5921,28 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } - else if (hi2c->State == HAL_I2C_STATE_ABORT) + else + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5831,6 +5956,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } else { + hi2c->PreviousState = I2C_STATE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -6062,30 +6189,16 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Reset AbortCpltCallback */ - hi2c->hdmatx->XferAbortCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Check if come from abort from user */ - if (hi2c->State == HAL_I2C_STATE_ABORT) + if (hi2c->hdmatx != NULL) { - hi2c->State = HAL_I2C_STATE_READY; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AbortCpltCallback(hi2c); -#else - HAL_I2C_AbortCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmatx->XferAbortCallback = NULL; } - else + if (hi2c->hdmarx != NULL) { - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->ErrorCallback(hi2c); -#else - HAL_I2C_ErrorCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmarx->XferAbortCallback = NULL; } + + I2C_TreatErrorCallback(hi2c); } /** @@ -6362,19 +6475,19 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -6400,7 +6513,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; @@ -6454,19 +6567,19 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c index d60bdd05ee..223574f42e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c @@ -1100,7 +1100,11 @@ HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf) { uint32_t error; - uint32_t numberMCU, hfactor, vfactor, hMCU, vMCU; + uint32_t numberMCU; + uint32_t hfactor; + uint32_t vfactor; + uint32_t hMCU; + uint32_t vMCU; /* Check the JPEG handle allocation */ if ((hjpeg == NULL) || (pConf == NULL)) @@ -1285,7 +1289,9 @@ HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTy */ HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo) { - uint32_t yblockNb, cBblockNb, cRblockNb; + uint32_t yblockNb; + uint32_t cBblockNb; + uint32_t cRblockNb; /* Check the JPEG handle allocation */ if ((hjpeg == NULL) || (pInfo == NULL)) @@ -2192,7 +2198,8 @@ void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputB */ HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg) { - uint32_t tickstart, tmpContext; + uint32_t tickstart; + uint32_t tmpContext; tmpContext = hjpeg->Context; /*Reset the Context operation and method*/ @@ -2522,7 +2529,11 @@ uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg) */ static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK) { - uint32_t i, p, l, code, si; + uint32_t i; + uint32_t p; + uint32_t l; + uint32_t code; + uint32_t si; /* Figure C.1: Generation of table of Huffman code sizes */ p = 0; @@ -2688,7 +2699,9 @@ static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCH { HAL_StatusTypeDef error; JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable; - uint32_t i, lsb, msb; + uint32_t i; + uint32_t lsb; + uint32_t msb; __IO uint32_t *address, *addressDef; if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC0)) @@ -3053,7 +3066,11 @@ static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg) static uint32_t JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, __IO uint32_t *QTableAddress) { - uint32_t i, j, quantRow, quantVal, ScaleFactor; + uint32_t i; + uint32_t j; + uint32_t quantRow; + uint32_t quantVal; + uint32_t ScaleFactor; __IO uint32_t *tableAddress; tableAddress = QTableAddress; @@ -3455,7 +3472,10 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) */ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords) { - uint32_t index, nBwords, nbBytes, dataword; + uint32_t index; + uint32_t nb_words; + uint32_t nb_bytes; + uint32_t dataword; if (hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords * 4UL))) { @@ -3482,8 +3502,8 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor } else if (hjpeg->OutDataLength > hjpeg->JpegOutCount) { - nBwords = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL; - for (index = 0; index < nBwords; index++) + nb_words = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL; + for (index = 0; index < nb_words; index++) { /*Transfer 32 bits from the JPEG output FIFO*/ dataword = hjpeg->Instance->DOR; @@ -3505,9 +3525,9 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor } else { - nbBytes = hjpeg->OutDataLength - hjpeg->JpegOutCount; + nb_bytes = hjpeg->OutDataLength - hjpeg->JpegOutCount; dataword = hjpeg->Instance->DOR; - for (index = 0; index < nbBytes; index++) + for (index = 0; index < nb_bytes; index++) { hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * (index & 0x3UL))) & 0xFFUL); hjpeg->JpegOutCount++; @@ -3521,8 +3541,8 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor hjpeg->JpegOutCount = 0; - nbBytes = 4UL - nbBytes; - for (index = nbBytes; index < 4UL; index++) + nb_bytes = 4UL - nb_bytes; + for (index = nb_bytes; index < 4UL; index++) { hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * index)) & 0xFFUL); hjpeg->JpegOutCount++; @@ -3546,7 +3566,11 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor */ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords) { - uint32_t nbBytes = 0, nBwords, index, Dataword, inputCount; + uint32_t nb_bytes = 0; + uint32_t nb_words; + uint32_t index; + uint32_t dataword; + uint32_t input_count; if ((hjpeg->InDataLength == 0UL) || (nbRequestWords == 0UL)) { @@ -3555,7 +3579,7 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord } else if (hjpeg->InDataLength > hjpeg->JpegInCount) { - nbBytes = hjpeg->InDataLength - hjpeg->JpegInCount; + nb_bytes = hjpeg->InDataLength - hjpeg->JpegInCount; } else if (hjpeg->InDataLength == hjpeg->JpegInCount) { @@ -3571,39 +3595,39 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL); } hjpeg->JpegInCount = 0; - nbBytes = hjpeg->InDataLength; + nb_bytes = hjpeg->InDataLength; } else { /* Nothing to do */ } - if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nbBytes > 0UL)) + if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nb_bytes > 0UL)) { - nBwords = nbBytes / 4UL; - if (nBwords >= nbRequestWords) + nb_words = nb_bytes / 4UL; + if (nb_words >= nbRequestWords) { for (index = 0; index < nbRequestWords; index++) { - inputCount = hjpeg->JpegInCount; - hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1UL])) << 8) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2UL])) << 16) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3UL])) << 24)); + input_count = hjpeg->JpegInCount; + hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24)); hjpeg->JpegInCount += 4UL; } } - else /*nBwords < nbRequestWords*/ + else /*nb_words < nbRequestWords*/ { - if (nBwords > 0UL) + if (nb_words > 0UL) { - for (index = 0; index < nBwords; index++) + for (index = 0; index < nb_words; index++) { - inputCount = hjpeg->JpegInCount; - hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1UL])) << 8) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2UL])) << 16) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3UL])) << 24)); + input_count = hjpeg->JpegInCount; + hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24)); hjpeg->JpegInCount += 4UL; } @@ -3611,13 +3635,13 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord else { /* end of file*/ - Dataword = 0; - for (index = 0; index < nbBytes; index++) + dataword = 0; + for (index = 0; index < nb_bytes; index++) { - Dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL)); + dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL)); hjpeg->JpegInCount++; } - hjpeg->Instance->DIR = Dataword; + hjpeg->Instance->DIR = dataword; } } } @@ -3850,7 +3874,9 @@ static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg) */ static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg) { - uint32_t tmpContext, count, dataOut; + uint32_t tmpContext; + uint32_t count; + uint32_t dataOut; for (count = JPEG_FIFO_SIZE; count > 0UL; count--) { diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c index b11c521a7a..0a579dcec7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c @@ -174,7 +174,6 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ /** @addtogroup LPTIM_Private_Constants * @{ */ @@ -183,6 +182,7 @@ * @} */ +/* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) @@ -235,17 +235,20 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); - if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); - assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { - assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); } + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) + { + assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); + assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); + } assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); @@ -278,13 +281,17 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; - if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL)) + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL)); } - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) + { + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL)); + } + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT)); } /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ @@ -298,25 +305,35 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) hlptim->Init.UpdateMode | hlptim->Init.CounterSource); - if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL)) + /* Glitch filters for internal triggers and external inputs are configured + * only if an internal clock source is provided to the LPTIM + */ + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) { - tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + tmpcfgr |= (hlptim->Init.Trigger.SampleTime | hlptim->Init.UltraLowPowerClock.SampleTime); } - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + /* Configure the active edge or edges used by the counter only if LPTIM is + * clocked by an external clock source + */ + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + { + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity); + } + + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable External trigger and set the trigger source */ - tmpcfgr |= (hlptim->Init.Trigger.Source | - hlptim->Init.Trigger.ActiveEdge | - hlptim->Init.Trigger.SampleTime); + tmpcfgr |= (hlptim->Init.Trigger.Source | + hlptim->Init.Trigger.ActiveEdge); } /* Write to LPTIMx CFGR */ hlptim->Instance->CFGR = tmpcfgr; /* Configure LPTIM input sources */ - if ((hlptim->Instance == LPTIM1)||(hlptim->Instance == LPTIM2)) + if ((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2)) { /* Check LPTIM Input1 and Input2 sources */ assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); @@ -327,7 +344,7 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) } else { - if(hlptim->Instance == LPTIM3) + if (hlptim->Instance == LPTIM3) { /* Check LPTIM3 Input1 source */ assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); @@ -2307,17 +2324,17 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t { HAL_StatusTypeDef result = HAL_OK; uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL); - do + do + { + count--; + if (count == 0UL) { - count--; - if (count == 0UL) - { - result = HAL_TIMEOUT; - } + result = HAL_TIMEOUT; } - while((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); + } + while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); - return result; + return result; } /** @@ -2344,29 +2361,29 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /* Save LPTIM source clock */ switch ((uint32_t)hlptim->Instance) { - case LPTIM1_BASE: - tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE(); - break; - case LPTIM2_BASE: - tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE(); - break; + case LPTIM1_BASE: + tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE(); + break; + case LPTIM2_BASE: + tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE(); + break; #if defined(LPTIM3) - case LPTIM3_BASE: - tmpclksource = __HAL_RCC_GET_LPTIM3_SOURCE(); - break; + case LPTIM3_BASE: + tmpclksource = __HAL_RCC_GET_LPTIM3_SOURCE(); + break; #endif /* LPTIM3 */ #if defined(LPTIM4) - case LPTIM4_BASE: - tmpclksource = __HAL_RCC_GET_LPTIM4_SOURCE(); - break; + case LPTIM4_BASE: + tmpclksource = __HAL_RCC_GET_LPTIM4_SOURCE(); + break; #endif /* LPTIM4 */ #if defined(LPTIM5) - case LPTIM5_BASE: - tmpclksource = __HAL_RCC_GET_LPTIM5_SOURCE(); - break; + case LPTIM5_BASE: + tmpclksource = __HAL_RCC_GET_LPTIM5_SOURCE(); + break; #endif /* LPTIM5 */ - default: - break; + default: + break; } /* Save LPTIM configuration registers */ @@ -2379,34 +2396,34 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /*********** Reset LPTIM ***********/ switch ((uint32_t)hlptim->Instance) { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_FORCE_RESET(); - __HAL_RCC_LPTIM1_RELEASE_RESET(); - break; - case LPTIM2_BASE: - __HAL_RCC_LPTIM2_FORCE_RESET(); - __HAL_RCC_LPTIM2_RELEASE_RESET(); - break; + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_FORCE_RESET(); + __HAL_RCC_LPTIM1_RELEASE_RESET(); + break; + case LPTIM2_BASE: + __HAL_RCC_LPTIM2_FORCE_RESET(); + __HAL_RCC_LPTIM2_RELEASE_RESET(); + break; #if defined(LPTIM3) - case LPTIM3_BASE: - __HAL_RCC_LPTIM3_FORCE_RESET(); - __HAL_RCC_LPTIM3_RELEASE_RESET(); - break; + case LPTIM3_BASE: + __HAL_RCC_LPTIM3_FORCE_RESET(); + __HAL_RCC_LPTIM3_RELEASE_RESET(); + break; #endif /* LPTIM3 */ #if defined(LPTIM4) - case LPTIM4_BASE: - __HAL_RCC_LPTIM4_FORCE_RESET(); - __HAL_RCC_LPTIM4_RELEASE_RESET(); - break; + case LPTIM4_BASE: + __HAL_RCC_LPTIM4_FORCE_RESET(); + __HAL_RCC_LPTIM4_RELEASE_RESET(); + break; #endif /* LPTIM4 */ #if defined(LPTIM5) - case LPTIM5_BASE: - __HAL_RCC_LPTIM5_FORCE_RESET(); - __HAL_RCC_LPTIM5_RELEASE_RESET(); - break; + case LPTIM5_BASE: + __HAL_RCC_LPTIM5_FORCE_RESET(); + __HAL_RCC_LPTIM5_RELEASE_RESET(); + break; #endif /* LPTIM5 */ - default: - break; + default: + break; } /*********** Restore LPTIM Config ***********/ @@ -2415,29 +2432,29 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /* Force LPTIM source kernel clock from APB */ switch ((uint32_t)hlptim->Instance) { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_D2PCLK1); - break; - case LPTIM2_BASE: - __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_D3PCLK1); - break; + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_D2PCLK1); + break; + case LPTIM2_BASE: + __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_D3PCLK1); + break; #if defined(LPTIM3) - case LPTIM3_BASE: - __HAL_RCC_LPTIM3_CONFIG(RCC_LPTIM3CLKSOURCE_D3PCLK1); - break; + case LPTIM3_BASE: + __HAL_RCC_LPTIM3_CONFIG(RCC_LPTIM3CLKSOURCE_D3PCLK1); + break; #endif /* LPTIM3 */ #if defined(LPTIM4) - case LPTIM4_BASE: - __HAL_RCC_LPTIM4_CONFIG(RCC_LPTIM4CLKSOURCE_D3PCLK1); - break; + case LPTIM4_BASE: + __HAL_RCC_LPTIM4_CONFIG(RCC_LPTIM4CLKSOURCE_D3PCLK1); + break; #endif /* LPTIM4 */ #if defined(LPTIM5) - case LPTIM5_BASE: - __HAL_RCC_LPTIM5_CONFIG(RCC_LPTIM5CLKSOURCE_D3PCLK1); - break; + case LPTIM5_BASE: + __HAL_RCC_LPTIM5_CONFIG(RCC_LPTIM5CLKSOURCE_D3PCLK1); + break; #endif /* LPTIM5 */ - default: - break; + default: + break; } if (tmpCMP != 0UL) @@ -2472,29 +2489,29 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /* Restore LPTIM source kernel clock */ switch ((uint32_t)hlptim->Instance) { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_CONFIG(tmpclksource); - break; - case LPTIM2_BASE: - __HAL_RCC_LPTIM2_CONFIG(tmpclksource); - break; + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_CONFIG(tmpclksource); + break; + case LPTIM2_BASE: + __HAL_RCC_LPTIM2_CONFIG(tmpclksource); + break; #if defined(LPTIM3) - case LPTIM3_BASE: - __HAL_RCC_LPTIM3_CONFIG(tmpclksource); - break; + case LPTIM3_BASE: + __HAL_RCC_LPTIM3_CONFIG(tmpclksource); + break; #endif /* LPTIM3 */ #if defined(LPTIM4) - case LPTIM4_BASE: - __HAL_RCC_LPTIM4_CONFIG(tmpclksource); - break; + case LPTIM4_BASE: + __HAL_RCC_LPTIM4_CONFIG(tmpclksource); + break; #endif /* LPTIM4 */ #if defined(LPTIM5) - case LPTIM5_BASE: - __HAL_RCC_LPTIM5_CONFIG(tmpclksource); - break; + case LPTIM5_BASE: + __HAL_RCC_LPTIM5_CONFIG(tmpclksource); + break; #endif /* LPTIM5 */ - default: - break; + default: + break; } } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c index 36e0325faf..29f5f6077b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c @@ -387,7 +387,6 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) { uint32_t errorstate; MMC_InitTypeDef Init; - HAL_StatusTypeDef status; /* Default SDMMC peripheral configuration for MMC card initialization */ Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; @@ -397,18 +396,10 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) Init.ClockDiv = SDMMC_INIT_CLK_DIV; /* Initialize SDMMC peripheral interface with default configuration */ - status = SDMMC_Init(hmmc->Instance, Init); - if(status == HAL_ERROR) - { - return HAL_ERROR; - } + (void)SDMMC_Init(hmmc->Instance, Init); /* Set Power State to ON */ - status = SDMMC_PowerState_ON(hmmc->Instance); - if(status == HAL_ERROR) - { - return HAL_ERROR; - } + (void)SDMMC_PowerState_ON(hmmc->Instance); /* Identify card operating voltage */ errorstate = MMC_PowerON(hmmc); @@ -428,6 +419,17 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) return HAL_ERROR; } + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + return HAL_OK; } @@ -568,20 +570,6 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui add *= 512U; } - if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) - { - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - } - /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; @@ -755,20 +743,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u add *= 512U; } - if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) - { - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - } - /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; @@ -943,20 +917,6 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, add *= 512U; } - if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) - { - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - } - /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; @@ -1050,20 +1010,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData add *= 512U; } - if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) - { - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - } - /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; @@ -1158,20 +1104,6 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData add *= 512U; } - if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) - { - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode = errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - } - /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; @@ -1268,20 +1200,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat add *= 512U; } - if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) - { - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - } - /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; @@ -2755,29 +2673,6 @@ HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, /* Initialize data control register */ hmmc->Instance->DCTRL = 0; - /* Configure the MMC DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 0; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_DISABLE; - (void)SDMMC_ConfigData(hmmc->Instance, &config); - - if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) - { - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - } - /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = 512; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c index d1f70d3268..978ac175c6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c @@ -377,11 +377,8 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) #endif /* Configure the default timeout for the OSPI memory access */ - status = HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE); - } + (void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE); - if (status == HAL_OK) - { /* Configure memory type, device size, chip select high time, clocked chip select high time, delay block bypass, free running clock, clock mode */ MODIFY_REG(hospi->Instance->DCR1, (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_CKCSHT | @@ -408,33 +405,33 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) if (status == HAL_OK) { - /* Configure clock prescaler */ - MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos)); - - /* Configure Dual Quad mode */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad); - - /* Configure sample shifting and delay hold quarter cycle */ - MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle)); - - /* Enable OctoSPI */ - __HAL_OSPI_ENABLE(hospi); - - /* Enable free running clock if needed : must be done after OSPI enable */ - if (hospi->Init.FreeRunningClock == HAL_OSPI_FREERUNCLK_ENABLE) - { - SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); - } - - /* Initialize the OSPI state */ - if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) - { - hospi->State = HAL_OSPI_STATE_HYPERBUS_INIT; - } - else - { - hospi->State = HAL_OSPI_STATE_READY; - } + /* Configure clock prescaler */ + MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos)); + + /* Configure Dual Quad mode */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad); + + /* Configure sample shifting and delay hold quarter cycle */ + MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle)); + + /* Enable OctoSPI */ + __HAL_OSPI_ENABLE(hospi); + + /* Enable free running clock if needed : must be done after OSPI enable */ + if (hospi->Init.FreeRunningClock == HAL_OSPI_FREERUNCLK_ENABLE) + { + SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); + } + + /* Initialize the OSPI state */ + if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) + { + hospi->State = HAL_OSPI_STATE_HYPERBUS_INIT; + } + else + { + hospi->State = HAL_OSPI_STATE_READY; + } } } } @@ -2457,6 +2454,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * assert_param(IS_OSPIM_PORT(cfg->NCSPort)); assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort)); assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort)); + assert_param(IS_OSPIM_REQ2ACKTIME(cfg->Req2AckTime)); if (hospi->Instance == OCTOSPI1) { @@ -2494,13 +2492,29 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * } /***************** Deactivation of previous configuration *****************/ - if (IOM_cfg[instance].ClkPort != 0U) + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN); + if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U) { - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN); + /* De-multiplexing should be performed */ + CLEAR_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN); + + if (other_instance == 1U) + { + SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKSRC); + SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSSRC); + SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLSRC_1); + SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHSRC_1); + } + } + else + { + if (IOM_cfg[instance].ClkPort != 0U) + { + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN); + } } /********************* Deactivation of other instance *********************/ @@ -2508,38 +2522,79 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) { - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN); + if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && + (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) && (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) + { + /* Multiplexing should be performed */ + SET_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN); + } + else + { + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN); + } } /******************** Activation of new configuration *********************/ - MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos))); - MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos))); MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort-1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos))); - if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U) + if ((cfg->Req2AckTime - 1U) > ((OCTOSPIM->CR & OCTOSPIM_CR_REQ2ACK_TIME) >> OCTOSPIM_CR_REQ2ACK_TIME_Pos)) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), - (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U)))); - } - else - { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), - (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U)))); + MODIFY_REG(OCTOSPIM->CR, OCTOSPIM_CR_REQ2ACK_TIME, ((cfg->Req2AckTime - 1U) << OCTOSPIM_CR_REQ2ACK_TIME_Pos)); } - if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U) + if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), - (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U)))); + MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), OCTOSPIM_PCR_CLKEN); + MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN); + + if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U) + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN); + } + else + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN); + } + + if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U) + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0)); + } + else + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0)); + } } else { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), - (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U)))); + MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos))); + MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos))); + + if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U) + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), + (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U)))); + } + else + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), + (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U)))); + } + + if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U) + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), + (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U)))); + } + else + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), + (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U)))); + } } /******* Re-enable both OctoSPI after configure OctoSPI IO Manager ********/ @@ -2905,7 +2960,14 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef * if (instance_nb == 2U) { - value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1); + if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U) + { + value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1); + } + else + { + value = OCTOSPIM_PCR_NCSSRC; + } } /* Get the information about the instance */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c index 5db2fc8c92..19f0a69362 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c @@ -185,6 +185,7 @@ void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); void PSSI_DMAError(DMA_HandleTypeDef *hdma); void PSSI_DMAAbort(DMA_HandleTypeDef *hdma); + /* Private functions to handle IT transfer */ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode); @@ -613,6 +614,10 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u uint32_t tickstart; uint32_t transfer_size = Size; +#if defined (__GNUC__) + __IO uint16_t *pdr_16bits = (__IO uint16_t *)(&(hpssi->Instance->DR)); +#endif /* __GNUC__ */ + if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) || ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size%2U) != 0U)) || ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size%4U) != 0U))) @@ -682,7 +687,11 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u return HAL_ERROR; } /* Write data to DR */ +#if defined (__GNUC__) + *pdr_16bits = *pbuffer; +#else *(__IO uint16_t *)((uint32_t)(&hpssi->Instance->DR)) = *pbuffer; +#endif /* __GNUC__ */ /* Increment Buffer pointer */ pbuffer++; @@ -763,6 +772,9 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui { uint32_t tickstart; uint32_t transfer_size = Size; +#if defined (__GNUC__) + __IO uint16_t *pdr_16bits = (__IO uint16_t *)(&(hpssi->Instance->DR)); +#endif /* __GNUC__ */ if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) || ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size%2U) != 0U)) || @@ -833,7 +845,12 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui } /* Read data from DR */ +#if defined (__GNUC__) + *pbuffer = *pdr_16bits; +#else *pbuffer = *(__IO uint16_t *)((uint32_t)&hpssi->Instance->DR); +#endif /* __GNUC__ */ + pbuffer++; transfer_size -= 2U; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c index 7b41ec24d8..74505b35b9 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c @@ -24,7 +24,7 @@ [..] (#) As prerequisite, fill in the HAL_QSPI_MspInit() : (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE(). - (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET(). + (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET(). (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init(). (++) If interrupt mode is used, enable and configure QuadSPI global @@ -64,7 +64,7 @@ (++) In polling mode, the output of the function is done when the transfer is complete. (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. - (++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. + (++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. *** Auto-polling functional mode *** ==================================== @@ -137,7 +137,7 @@ (++) In polling mode, the output of the function is done when the transfer complete bit is set and the busy bit cleared. (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when - the transfer complete bi is set. + the transfer complete bit is set. *** Control functions *** ========================= @@ -146,6 +146,7 @@ (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver. (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP. (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed. *** Callback registration *** ============================================= @@ -218,7 +219,7 @@ * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -226,18 +227,17 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal.h" +#if defined(QUADSPI) + /** @addtogroup STM32H7xx_HAL_Driver * @{ */ -#ifdef HAL_QSPI_MODULE_ENABLED - -#if defined(QUADSPI) - /** @defgroup QSPI QSPI * @brief QSPI HAL module driver * @{ */ +#ifdef HAL_QSPI_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -245,7 +245,7 @@ /** @defgroup QSPI_Private_Constants QSPI Private Constants * @{ */ -#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!Init.FlashID)); } - /* Process locked */ - __HAL_LOCK(hqspi); - if(hqspi->State == HAL_QSPI_STATE_RESET) { - /* Allocate lock resource and initialize it */ - hqspi->Lock = HAL_UNLOCKED; #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */ @@ -359,8 +354,9 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) /* Init the low level hardware : GPIO, CLOCK */ HAL_QSPI_MspInit(hqspi); #endif + /* Configure the default timeout for the QSPI memory access */ - HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE); + HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE); } /* Configure QSPI FIFO Threshold */ @@ -392,16 +388,13 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) hqspi->State = HAL_QSPI_STATE_READY; } - /* Release Lock */ - __HAL_UNLOCK(hqspi); - /* Return function status */ return status; } /** * @brief De-Initialize the QSPI peripheral. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) @@ -412,9 +405,6 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hqspi); - /* Disable the QSPI Peripheral Clock */ __HAL_QSPI_DISABLE(hqspi); @@ -437,15 +427,12 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /* Initialize the QSPI state */ hqspi->State = HAL_QSPI_STATE_RESET; - /* Release Lock */ - __HAL_UNLOCK(hqspi); - return HAL_OK; } /** * @brief Initialize the QSPI MSP. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) @@ -460,7 +447,7 @@ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) /** * @brief DeInitialize the QSPI MSP. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) @@ -499,7 +486,7 @@ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Handle QSPI interrupt request. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) @@ -509,7 +496,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) uint32_t itsource = READ_REG(hqspi->Instance->CR); /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/ - if(((flag & QSPI_FLAG_FT) == QSPI_FLAG_FT) && ((itsource & QSPI_IT_FT) == QSPI_IT_FT)) + if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U)) { data_reg = &hqspi->Instance->DR; @@ -521,7 +508,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) if (hqspi->TxXferCount > 0U) { /* Fill the FIFO until the threshold is reached */ - *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr; + *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; hqspi->pTxBuffPtr++; hqspi->TxXferCount--; } @@ -542,7 +529,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) if (hqspi->RxXferCount > 0U) { /* Read the FIFO until the threshold is reached */ - *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg; + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } @@ -559,6 +546,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) { /* Nothing to do */ } + /* FIFO Threshold callback */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) hqspi->FifoThresholdCallback(hqspi); @@ -568,7 +556,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Transfer Complete interrupt occurred -------------------------------*/ - else if(((flag & QSPI_FLAG_TC) == QSPI_FLAG_TC) && ((itsource & QSPI_IT_TC) == QSPI_IT_TC)) + else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); @@ -579,7 +567,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Transfer complete callback */ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) { - if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -588,6 +576,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) __HAL_MDMA_DISABLE(hqspi->hmdma); } + /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; @@ -600,7 +589,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) { - if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -616,7 +605,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) if (hqspi->RxXferCount > 0U) { /* Read the last data received in the FIFO until it is empty */ - *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg; + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } @@ -628,6 +617,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } } + /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; @@ -688,7 +678,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Status Match interrupt occurred ------------------------------------*/ - else if(((flag & QSPI_FLAG_SM)== QSPI_FLAG_SM) && ((itsource & QSPI_IT_SM) == QSPI_IT_SM)) + else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); @@ -712,7 +702,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Transfer Error interrupt occurred ----------------------------------*/ - else if(((flag & QSPI_FLAG_TE) == QSPI_FLAG_TE) && ((itsource & QSPI_IT_TE) == QSPI_IT_TE)) + else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); @@ -723,7 +713,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Set error code */ hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; - if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -761,7 +751,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Timeout interrupt occurred -----------------------------------------*/ - else if(((flag & QSPI_FLAG_TO) == QSPI_FLAG_TO) && ((itsource & QSPI_IT_TO) == QSPI_IT_TO)) + else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); @@ -773,6 +763,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) HAL_QSPI_TimeOutCallback(hqspi); #endif } + else { /* Nothing to do */ @@ -781,7 +772,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /** * @brief Set the command configuration. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information * @param Timeout : Timeout duration * @note This function is used only in Indirect Read or Write Modes @@ -849,7 +840,6 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /* Update QSPI state */ hqspi->State = HAL_QSPI_STATE_READY; } - } else { @@ -872,7 +862,7 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /** * @brief Set the command configuration in interrupt mode. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes * @retval HAL status @@ -971,10 +961,11 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp /** * @brief Transmit an amount of data in blocking mode. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @param Timeout : Timeout duration * @note This function is used only in Indirect Write Mode + * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) @@ -1013,7 +1004,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u break; } - *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr; + *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; hqspi->pTxBuffPtr++; hqspi->TxXferCount--; } @@ -1054,8 +1045,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @param Timeout : Timeout duration * @note This function is used only in Indirect Read Mode * @retval HAL status @@ -1100,7 +1091,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui break; } - *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg; + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } @@ -1114,6 +1105,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui { /* Clear Transfer Complete bit */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + } } @@ -1139,8 +1131,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /** * @brief Send an amount of data in non-blocking mode with interrupt. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1199,8 +1191,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Receive an amount of data in non-blocking mode with interrupt. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1263,18 +1255,15 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) /** * @brief Send an amount of data in non-blocking mode with DMA. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Write Mode - * @note If MDMA peripheral access is configured as halfword, the number - * of data and the fifo threshold should be aligned on halfword - * @note If MDMA peripheral access is configured as word, the number - * of data and the fifo threshold should be aligned on word * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; + uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); /* Process locked */ __HAL_LOCK(hqspi); @@ -1286,64 +1275,75 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat if(pData != NULL ) { + /* Configure counters of the handle */ + hqspi->TxXferCount = data_size; - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; + /* Update state */ + hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); - /* Configure counters and size of the handle */ - hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; - hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; - hqspi->pTxBuffPtr = pData; + /* Configure size and pointer of the handle */ + hqspi->TxXferSize = hqspi->TxXferCount; + hqspi->pTxBuffPtr = pData; - /* Configure QSPI: CCR register with functional mode as indirect write */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + /* Configure QSPI: CCR register with functional mode as indirect write */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - /* Set the QSPI MDMA transfer complete callback */ - hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt; + /* Set the QSPI MDMA transfer complete callback */ + hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt; - /* Set the MDMA error callback */ - hqspi->hmdma->XferErrorCallback = QSPI_DMAError; + /* Set the MDMA error callback */ + hqspi->hmdma->XferErrorCallback = QSPI_DMAError; - /* Clear the MDMA abort callback */ - hqspi->hmdma->XferAbortCallback = NULL; + /* Clear the MDMA abort callback */ + hqspi->hmdma->XferAbortCallback = NULL; - /* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destination Increment to disable */ - MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE); + /* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destination Increment to disable */ + MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE); - /* Update MDMA configuration with the correct SourceInc field for Write operation */ - if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE) - { - MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE); - } - else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD) - { - MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD); - } - else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD) - { - MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD); - } - else - { - /* in case of incorrect source data size */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; - status = HAL_ERROR; - } + /* Update MDMA configuration with the correct SourceInc field for Write operation */ + if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE) + { + MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE); + } + else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD) + { + MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD); + } + else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD) + { + MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD); + } + else + { + /* in case of incorrect source data size */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + status = HAL_ERROR; + } - /* Enable the QSPI transfer error and complete Interrupts : Workaround for QSPI low kernel clock frequency */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE |QSPI_IT_TC); + /* Enable the QSPI transmit MDMA */ + if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK) + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); - /* Enable the QSPI transmit MDMA */ - if(HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK) - { - /* Process unlocked */ - __HAL_UNLOCK(hqspi); + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/ - } + /* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->State = HAL_QSPI_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } } else { @@ -1367,8 +1367,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer. + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer. * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1376,6 +1376,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData { HAL_StatusTypeDef status = HAL_OK; uint32_t addr_reg = READ_REG(hqspi->Instance->AR); + uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); /* Process locked */ __HAL_LOCK(hqspi); @@ -1387,35 +1388,26 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData if(pData != NULL ) { + /* Configure counters of the handle */ + hqspi->RxXferCount = data_size; + /* Update state */ + hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); - - /* Configure counters and size of the handle */ - hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; - hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; - hqspi->pRxBuffPtr = pData; - - /* Set the QSPI DMA transfer complete callback */ - hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt; + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); - /* Set the MDMA error callback */ - hqspi->hmdma->XferErrorCallback = QSPI_DMAError; + /* Configure size and pointer of the handle */ + hqspi->RxXferSize = hqspi->RxXferCount; + hqspi->pRxBuffPtr = pData; - /* Clear the MDMA abort callback */ - hqspi->hmdma->XferAbortCallback = NULL; + /* Set the QSPI MDMA transfer complete callback */ + hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt; + /* Set the MDMA error callback */ + hqspi->hmdma->XferErrorCallback = QSPI_DMAError; - /* QSPI need to be configured to indirect mode before starting - the MDMA to avoid primatury triggering for the MDMA transfert */ - /* Configure QSPI: CCR register with functional as indirect read */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - - /* Start the transfer by re-writing the address in AR register */ - WRITE_REG(hqspi->Instance->AR, addr_reg); + /* Clear the MDMA abort callback */ + hqspi->hmdma->XferAbortCallback = NULL; /* In Receive mode , the MDMA source is the QSPI DR register : Force the MDMA Source Increment to disable */ MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE); @@ -1439,21 +1431,37 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; status = HAL_ERROR; } + /* Configure QSPI: CCR register with functional as indirect read */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - /* Enable the MDMA */ - if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK) - { - /* Process unlocked */ - __HAL_UNLOCK(hqspi); + /* Start the transfer by re-writing the address in AR register */ + WRITE_REG(hqspi->Instance->AR, addr_reg); + + /* Enable the MDMA */ + if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK) + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/ - } + /* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->State = HAL_QSPI_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } } else { + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; /* Process unlocked */ @@ -1473,9 +1481,9 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Configure the QSPI Automatic Polling Mode in blocking mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the polling configuration information. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the polling configuration information. * @param Timeout : Timeout duration * @note This function is used only in Automatic Polling Mode * @retval HAL status @@ -1574,9 +1582,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy /** * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the polling configuration information. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the polling configuration information. * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1678,9 +1686,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /** * @brief Configure the Memory Mapped mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the memory mapped configuration information. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode * @retval HAL status */ @@ -1733,9 +1741,9 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT if (status == HAL_OK) { /* Configure QSPI: CR register with timeout counter enable */ - MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); - if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE) + if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE) { assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); @@ -1767,7 +1775,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT /** * @brief Transfer Error callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) @@ -1782,7 +1790,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Abort completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1797,7 +1805,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Command completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1812,7 +1820,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Transfer completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1827,10 +1835,10 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Transfer completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); @@ -1843,7 +1851,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief FIFO Threshold callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) @@ -1858,7 +1866,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Status Match callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) @@ -1873,7 +1881,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Timeout callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) @@ -2115,7 +2123,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS /** * @brief Return the QSPI handle state. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval HAL state */ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) @@ -2126,7 +2134,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) /** * @brief Return the QSPI error code. -* @param hqspi: QSPI handle +* @param hqspi : QSPI handle * @retval QSPI Error Code */ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) @@ -2136,7 +2144,7 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission. -* @param hqspi: QSPI handle +* @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) @@ -2150,7 +2158,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /* Process unlocked */ __HAL_UNLOCK(hqspi); - if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -2169,7 +2177,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /* Wait until TC flag is set to go back in idle state */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - if(status == HAL_OK) + if (status == HAL_OK) { __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); @@ -2179,6 +2187,9 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) if (status == HAL_OK) { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + /* Update state */ hqspi->State = HAL_QSPI_STATE_READY; } @@ -2189,7 +2200,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission (non-blocking function) -* @param hqspi: QSPI handle +* @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) @@ -2208,7 +2219,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) /* Disable all interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); - if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -2217,10 +2228,15 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt; if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK) { - /* Set error code to DMA */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; - status = HAL_ERROR; + /* Abort Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->AbortCpltCallback(hqspi); +#else + HAL_QSPI_AbortCpltCallback(hqspi); +#endif } } else @@ -2239,8 +2255,8 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) } /** @brief Set QSPI timeout. - * @param hqspi: QSPI handle. - * @param Timeout: Timeout for the QSPI memory access. + * @param hqspi : QSPI handle. + * @param Timeout : Timeout for the QSPI memory access. * @retval None */ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) @@ -2249,8 +2265,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) } /** @brief Set QSPI Fifo threshold. - * @param hqspi: QSPI handle. - * @param Threshold: Threshold of the Fifo (value between 1 and 16). + * @param hqspi : QSPI handle. + * @param Threshold : Threshold of the Fifo (value between 1 and 16). * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) @@ -2282,7 +2298,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t } /** @brief Get QSPI Fifo threshold. - * @param hqspi: QSPI handle. + * @param hqspi : QSPI handle. * @retval Fifo threshold (value between 1 and 16) */ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) @@ -2331,14 +2347,22 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashI * @} */ +/** + * @} + */ + +/** @defgroup QSPI_Private_Functions QSPI Private Functions + * @{ + */ + /** * @brief DMA QSPI receive process complete callback. - * @param hmdma: MDMA handle + * @param hmdma : MDMA handle * @retval None */ static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent; + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent); hqspi->RxXferCount = 0U; /* Enable the QSPI transfer complete Interrupt */ @@ -2347,12 +2371,12 @@ static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma) /** * @brief DMA QSPI transmit process complete callback. - * @param hmdma: MDMA handle + * @param hmdma : MDMA handle * @retval None */ static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent; + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent); hqspi->TxXferCount = 0U; /* Enable the QSPI transfer complete Interrupt */ @@ -2361,12 +2385,12 @@ static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma) /** * @brief DMA QSPI communication error callback. - * @param hmdma: MDMA handle + * @param hmdma : MDMA handle * @retval None */ static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent; + QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent); hqspi->RxXferCount = 0U; hqspi->TxXferCount = 0U; @@ -2382,12 +2406,12 @@ static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma) /** * @brief MDMA QSPI abort complete callback. - * @param hmdma: MDMA handle + * @param hmdma : MDMA handle * @retval None */ static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent; + QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent); hqspi->RxXferCount = 0U; hqspi->TxXferCount = 0U; @@ -2418,13 +2442,14 @@ static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma) #endif } } + /** * @brief Wait for a flag state until timeout. - * @param hqspi: QSPI handle - * @param Flag: Flag checked - * @param State: Value of the flag expected - * @param Tickstart: Tick start value - * @param Timeout: Duration of the timeout + * @param hqspi : QSPI handle + * @param Flag : Flag checked + * @param State : Value of the flag expected + * @param Tickstart : Tick start value + * @param Timeout : Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, @@ -2450,9 +2475,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp /** * @brief Configure the communication registers. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information - * @param FunctionalMode: functional mode to configured + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information + * @param FunctionalMode : functional mode to configured * This parameter can be one of the following values: * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode @@ -2606,16 +2631,15 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin * @} */ +#endif /* HAL_QSPI_MODULE_ENABLED */ /** * @} */ -#endif /* QUADSPI */ - -#endif /* HAL_QSPI_MODULE_ENABLED */ - /** * @} */ +#endif /* defined(QUADSPI) */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c index 5be9eb10fc..17c241b8d6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c @@ -228,8 +228,9 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); - /* Update the SystemCoreClock global variable */ + /* Update the SystemCoreClock and SystemD2Clock global variables */ SystemCoreClock = HSI_VALUE; + SystemD2Clock = HSI_VALUE; /* Adapt Systick interrupt period */ if(HAL_InitTick(uwTickPrio) != HAL_OK) @@ -859,7 +860,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc * contains the configuration information for the RCC peripheral. * @param FLatency: FLASH Latency, this parameter depend on device selected * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * @note The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency * and updated by HAL_InitTick() function called within this function * * @note The HSI is used (enabled by hardware) as system clock source after @@ -882,6 +883,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui { HAL_StatusTypeDef halstatus; uint32_t tickstart; + uint32_t common_system_clock; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) @@ -1174,10 +1176,23 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); +#endif + +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); #else - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); #endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick (uwTickPrio); @@ -1429,11 +1444,26 @@ uint32_t HAL_RCC_GetSysClockFreq(void) */ uint32_t HAL_RCC_GetHCLKFreq(void) { +uint32_t common_system_clock; + +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); +#endif + #if defined(RCC_D1CFGR_HPRE) - SystemD2Clock = (HAL_RCCEx_GetD1SysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); #else - SystemD2Clock = (HAL_RCCEx_GetD1SysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); #endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + return SystemD2Clock; } @@ -1451,7 +1481,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); #else /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> POSITION_VAL(RCC_CDCFGR2_CDPPRE1_0)]); + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); #endif } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c index e8cfbf23d2..22c9e940ca 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c @@ -2635,21 +2635,37 @@ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks) } /** - * @brief Returns the main Core frequency - * @note Each time core clock changes, this function must be called to update the - * right system core clock value. Otherwise, any configuration based on this function will be incorrect. - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * @brief Returns the main System frequency + * @note Each time System clock changes, this function must be called to update the + * right core clock value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCCEx_GetD1SysClockFreq(void) { +uint32_t common_system_clock; + #if defined(RCC_D1CFGR_D1CPRE) - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); #else - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif - return SystemCoreClock; + + /* Update the SystemD2Clock global variable */ +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + + return common_system_clock; } /** * @} @@ -2683,6 +2699,28 @@ void HAL_RCCEx_DisableLSECSS(void) __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); } +/** + * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. + * @note LSE Clock Security System Interrupt is mapped on EXTI line 18 + * @retval None + */ +void HAL_RCCEx_EnableLSECSS_IT(void) +{ + /* Enable LSE CSS */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + + /* Enable LSE CSS IT */ + __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); + + /* Enable IT on EXTI Line 18 */ +#if defined(DUAL_CORE) && defined(CORE_CM4) + __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT(); +#else + __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); +#endif /* DUAL_CORE && CORE_CM4 */ + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); +} + /** * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock * @param WakeUpClk: Wakeup clock @@ -3351,6 +3389,38 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t D return status; } +/** + * @brief Handle the RCC LSE Clock Security System interrupt request. + * @retval None + */ +void HAL_RCCEx_LSECSS_IRQHandler(void) +{ + /* Check RCC LSE CSSF flag */ + if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) + { + + /* Clear RCC LSE CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); + + /* RCC LSE Clock Security System interrupt user callback */ + HAL_RCCEx_LSECSS_Callback(); + + } +} + +/** + * @brief RCCEx LSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_LSECSS_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file + */ +} + + + /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c index 9ef4e90ce8..02aaa0231c 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c @@ -464,7 +464,6 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) { uint32_t errorstate; - HAL_StatusTypeDef status; SD_InitTypeDef Init; uint32_t sdmmc_clk; @@ -475,27 +474,22 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; Init.ClockDiv = SDMMC_INIT_CLK_DIV; -#if (USE_SD_TRANSCEIVER != 0U) || defined (USE_SD_DIRPOL) +#if (USE_SD_TRANSCEIVER != 0U) if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) { /* Set Transceiver polarity */ hsd->Instance->POWER |= SDMMC_POWER_DIRPOL; } +#elif defined (USE_SD_DIRPOL) + /* Set Transceiver polarity */ + hsd->Instance->POWER |= SDMMC_POWER_DIRPOL; #endif /* USE_SD_TRANSCEIVER */ /* Initialize SDMMC peripheral interface with default configuration */ - status = SDMMC_Init(hsd->Instance, Init); - if(status != HAL_OK) - { - return HAL_ERROR; - } + (void)SDMMC_Init(hsd->Instance, Init); /* Set Power State to ON */ - status = SDMMC_PowerState_ON(hsd->Instance); - if(status != HAL_OK) - { - return HAL_ERROR; - } + (void)SDMMC_PowerState_ON(hsd->Instance); /* wait 74 Cycles: required power up waiting time before starting the SD initialization sequence */ @@ -528,6 +522,17 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) return HAL_ERROR; } + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + return HAL_OK; } @@ -684,17 +689,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = NumberOfBlocks * BLOCKSIZE; @@ -877,17 +871,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = NumberOfBlocks * BLOCKSIZE; @@ -1071,17 +1054,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = BLOCKSIZE * NumberOfBlocks; @@ -1175,17 +1147,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = BLOCKSIZE * NumberOfBlocks; @@ -1281,17 +1242,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = BLOCKSIZE * NumberOfBlocks; @@ -1390,16 +1340,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = BLOCKSIZE * NumberOfBlocks; @@ -2342,6 +2282,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT { uint32_t sd_status[16]; uint32_t errorstate; + HAL_StatusTypeDef status = HAL_OK; errorstate = SD_SendSDStatus(hsd, sd_status); if(errorstate != HAL_SD_ERROR_NONE) @@ -2350,7 +2291,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; + status = HAL_ERROR; } else { @@ -2380,7 +2321,18 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT pStatus->VideoSpeedClass = (uint8_t)((sd_status[4] & 0xFF000000U) >> 24U); } - return HAL_OK; + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode = errorstate; + hsd->State = HAL_SD_STATE_READY; + status = HAL_ERROR; + } + + return status; } /** @@ -2419,6 +2371,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t { SDMMC_InitTypeDef Init; uint32_t errorstate; + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_SDMMC_BUS_WIDE(WideMode)); @@ -2460,8 +2413,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; + status = HAL_ERROR; } else { @@ -2495,10 +2447,20 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t (void)SDMMC_Init(hsd->Instance, Init); } + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + status = HAL_ERROR; + } + /* Change State */ hsd->State = HAL_SD_STATE_READY; - return HAL_OK; + return status; } /** @@ -2516,6 +2478,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode) { uint32_t tickstart; + uint32_t errorstate; HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ @@ -2743,6 +2706,16 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } } + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + status = HAL_ERROR; + } + /* Change State */ hsd->State = HAL_SD_STATE_READY; return status; @@ -3548,7 +3521,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) { /* Initialize the Data control register */ hsd->Instance->DCTRL = 0; - errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64); + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); if (errorstate != HAL_SD_ERROR_NONE) { @@ -3557,16 +3530,13 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) /* Configure the SD DPSM (Data Path State Machine) */ sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = 64; + sdmmc_datainitstructure.DataLength = 64U; sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ; sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK) - { - return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); - } + (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure); errorstate = SDMMC_CmdSwitch(hsd->Instance,SDMMC_SDR25_SWITCH_PATTERN); @@ -3662,7 +3632,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) { /* Initialize the Data control register */ hsd->Instance->DCTRL = 0; - errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64); + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); if (errorstate != HAL_SD_ERROR_NONE) { @@ -3671,7 +3641,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) /* Configure the SD DPSM (Data Path State Machine) */ sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = 64; + sdmmc_datainitstructure.DataLength = 64U; sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ; sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; @@ -3790,7 +3760,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) { /* Initialize the Data control register */ hsd->Instance->DCTRL = 0; - errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64); + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); if (errorstate != HAL_SD_ERROR_NONE) { @@ -3799,7 +3769,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) /* Configure the SD DPSM (Data Path State Machine) */ sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = 64; + sdmmc_datainitstructure.DataLength = 64U; sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ; sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c index cc7844774d..7c4da99d30 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c @@ -139,17 +139,6 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = BLOCKSIZE * NumberOfBlocks; @@ -231,17 +220,6 @@ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = BLOCKSIZE * NumberOfBlocks; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c index 0b2bcb493b..38731139df 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c @@ -2617,10 +2617,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini } /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); @@ -2783,7 +2783,7 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Enable the encoder interface channels */ switch (Channel) @@ -2827,7 +2827,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -2873,7 +2873,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Enable the encoder interface channels */ /* Enable the capture compare Interrupts 1 and/or 2 */ @@ -2923,7 +2923,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -2978,7 +2978,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch uint32_t *pData2, uint16_t Length) { /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); if (htim->State == HAL_TIM_STATE_BUSY) { @@ -3112,7 +3112,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c index 0458da47f7..8f9d2b629d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c @@ -317,7 +317,8 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) /* In Synchronous mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ + - HDSEL, SCEN and IREN bits in the USART_CR3 register. + */ husart->Instance->CR2 &= ~USART_CR2_LINEN; husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); @@ -2091,7 +2092,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) uint32_t errorcode; /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR)); + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | USART_ISR_UDR)); if (errorflags == 0U) { /* USART in mode Receiver ---------------------------------------------------*/ @@ -2146,6 +2147,14 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) husart->ErrorCode |= HAL_USART_ERROR_ORE; } + /* USART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(husart, UART_CLEAR_RTOF); + + husart->ErrorCode |= HAL_USART_ERROR_RTO; + } + /* USART SPI slave underrun error interrupt occurred -------------------------*/ if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c index 5a2f54ef8f..f38b03d203 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c @@ -57,10 +57,10 @@ /** @defgroup USARTEx_Private_Constants USARTEx Private Constants * @{ */ -/* UART RX FIFO depth */ +/* USART RX FIFO depth */ #define RX_FIFO_DEPTH 8U -/* UART TX FIFO depth */ +/* USART TX FIFO depth */ #define TX_FIFO_DEPTH 8U /** * @} @@ -243,7 +243,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart) /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); - husart->SlaveMode = USART_SLAVEMODE_ENABLE; + husart->SlaveMode = USART_SLAVEMODE_DISABLE; husart->State = HAL_USART_STATE_READY; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c index 6e223901f9..52d1d8008d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c @@ -194,6 +194,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init) { uint32_t flashaccess; + uint32_t btcr_reg; + uint32_t mask; /* Check the parameters */ assert_param(IS_FMC_NORSRAM_DEVICE(Device)); @@ -226,38 +228,42 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE; } - MODIFY_REG(Device->BTCR[Init->NSBank], - (FMC_BCRx_MBKEN | - FMC_BCRx_MUXEN | - FMC_BCRx_MTYP | - FMC_BCRx_MWID | - FMC_BCRx_FACCEN | - FMC_BCRx_BURSTEN | - FMC_BCRx_WAITPOL | - FMC_BCRx_WAITCFG | - FMC_BCRx_WREN | - FMC_BCRx_WAITEN | - FMC_BCRx_EXTMOD | - FMC_BCRx_ASYNCWAIT | - FMC_BCRx_CBURSTRW | - FMC_BCR1_CCLKEN | - FMC_BCR1_WFDIS | - FMC_BCRx_CPSIZE), - (flashaccess | - Init->DataAddressMux | - Init->MemoryType | - Init->MemoryDataWidth | - Init->BurstAccessMode | - Init->WaitSignalPolarity | - Init->WaitSignalActive | - Init->WriteOperation | - Init->WaitSignal | - Init->ExtendedMode | - Init->AsynchronousWait | - Init->WriteBurst | - Init->ContinuousClock | - Init->WriteFifo | - Init->PageSize)); + btcr_reg = (flashaccess | \ + Init->DataAddressMux | \ + Init->MemoryType | \ + Init->MemoryDataWidth | \ + Init->BurstAccessMode | \ + Init->WaitSignalPolarity | \ + Init->WaitSignalActive | \ + Init->WriteOperation | \ + Init->WaitSignal | \ + Init->ExtendedMode | \ + Init->AsynchronousWait | \ + Init->WriteBurst); + + btcr_reg |= Init->ContinuousClock; + btcr_reg |= Init->WriteFifo; + btcr_reg |= Init->PageSize; + + mask = (FMC_BCRx_MBKEN | + FMC_BCRx_MUXEN | + FMC_BCRx_MTYP | + FMC_BCRx_MWID | + FMC_BCRx_FACCEN | + FMC_BCRx_BURSTEN | + FMC_BCRx_WAITPOL | + FMC_BCRx_WAITCFG | + FMC_BCRx_WREN | + FMC_BCRx_WAITEN | + FMC_BCRx_EXTMOD | + FMC_BCRx_ASYNCWAIT | + FMC_BCRx_CBURSTRW); + + mask |= FMC_BCR1_CCLKEN; + mask |= FMC_BCR1_WFDIS; + mask |= FMC_BCRx_CPSIZE; + + MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) @@ -556,6 +562,9 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); assert_param(IS_FMC_NAND_BANK(Bank)); + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + /* NAND bank 3 registers configuration */ MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | @@ -583,6 +592,9 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); assert_param(IS_FMC_NAND_BANK(Bank)); + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + /* NAND bank 3 registers configuration */ MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | @@ -608,6 +620,9 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) __FMC_NAND_DISABLE(Device, Bank); /* De-initialize the NAND Bank */ + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + /* Set the FMC_NAND_BANK3 registers to their reset values */ WRITE_REG(Device->PCR, 0x00000018U); WRITE_REG(Device->SR, 0x00000040U); @@ -650,6 +665,9 @@ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) assert_param(IS_FMC_NAND_BANK(Bank)); /* Enable ECC feature */ + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + SET_BIT(Device->PCR, FMC_PCR_ECCEN); return HAL_OK; @@ -669,6 +687,9 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) assert_param(IS_FMC_NAND_BANK(Bank)); /* Disable ECC feature */ + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); return HAL_OK; @@ -706,6 +727,9 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui } } + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + /* Get the ECCR register value */ *ECCval = (uint32_t)Device->ECCR; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c index 30f8662a28..773ee0a68e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c @@ -220,8 +220,6 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru if (currentpin != 0x00000000U) { - /* Pin Mode configuration */ - LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) { @@ -230,6 +228,13 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru /* Speed mode configuration */ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); + } /* Pull-up Pull down resistor configuration*/ @@ -240,7 +245,7 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru /* Check Alternate parameter */ assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); - /* Speed mode configuration */ + /* Alternate function configuration */ if (currentpin < LL_GPIO_PIN_8) { LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); @@ -250,19 +255,13 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); } } + + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); } pinpos++; } - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) - { - /* Check Output mode parameters */ - assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); - - /* Output mode configuration*/ - LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); - - } return (SUCCESS); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c index 139764c54e..ff1ee656cc 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c @@ -226,25 +226,25 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) /* Save LPTIM source clock */ switch ((uint32_t)LPTIMx) { - case LPTIM1_BASE: - tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); - break; - case LPTIM2_BASE: - tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE); - break; + case LPTIM1_BASE: + tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); + break; + case LPTIM2_BASE: + tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE); + break; #if defined(LPTIM3)&&defined(LPTIM4)&&defined(LPTIM5) - case LPTIM3_BASE: - case LPTIM4_BASE: - case LPTIM5_BASE: - tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE); - break; + case LPTIM3_BASE: + case LPTIM4_BASE: + case LPTIM5_BASE: + tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE); + break; #elif defined(LPTIM3) - case LPTIM3_BASE: - tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE); - break; + case LPTIM3_BASE: + tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE); + break; #endif /* LPTIM3 && LPTIM4 && LPTIM5 */ - default: - break; + default: + break; } /* Save LPTIM configuration registers */ @@ -265,25 +265,25 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) /* Force LPTIM source kernel clock from APB */ switch ((uint32_t)LPTIMx) { - case LPTIM1_BASE: - LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1); - break; - case LPTIM2_BASE: - LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK4); - break; + case LPTIM1_BASE: + LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1); + break; + case LPTIM2_BASE: + LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK4); + break; #if defined(LPTIM3)&&defined(LPTIM4)&&defined(LPTIM5) - case LPTIM3_BASE: - case LPTIM4_BASE: - case LPTIM5_BASE: - LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE_PCLK4); - break; + case LPTIM3_BASE: + case LPTIM4_BASE: + case LPTIM5_BASE: + LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE_PCLK4); + break; #elif defined(LPTIM3) - case LPTIM3_BASE: - LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE_PCLK4); - break; + case LPTIM3_BASE: + LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE_PCLK4); + break; #endif /* LPTIM3 && LPTIM4 && LPTIM5*/ - default: - break; + default: + break; } if (tmpCMP != 0UL) @@ -296,7 +296,8 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } + while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_CMPOK(LPTIMx); } @@ -311,7 +312,8 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } + while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_ARROK(LPTIMx); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c index 30e3be71a7..a11ca8368a 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c @@ -338,7 +338,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; TIM_InitStruct->Autoreload = 0xFFFFFFFFU; TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; - TIM_InitStruct->RepetitionCounter = (uint8_t)0x00; + TIM_InitStruct->RepetitionCounter = 0x00000000U; } /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c index a4836fd994..a039e79811 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c @@ -224,8 +224,6 @@ * @{ */ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); -static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t *latency); -static ErrorStatus UTILS_SetFlashLatency(uint32_t latency); static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); static ErrorStatus UTILS_IsPLLsReady(void); /** @@ -341,7 +339,7 @@ void LL_mDelay(uint32_t Delay) (++) +----------------------------------------------------------------------------+ #else - (+) The maximum frequency of the SYSCLK is 280 MHz and HCLK is 140 MHz. + (+) The maximum frequency of the SYSCLK is 280 MHz and HCLK is 280 MHz. (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 140 MHz. @endverbatim @internal @@ -399,14 +397,6 @@ void LL_SetSystemCoreClock(uint32_t CPU_Frequency) { /* HCLK clock frequency */ SystemCoreClock = CPU_Frequency; - - /* Update the SystemD2Clock global variable */ -#if defined(RCC_D1CFGR_HPRE) - SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); -#else - SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); -#endif - } /** @@ -505,7 +495,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS * @note Function is based on the following formula: * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP) * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM) - * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz (PLLVCO_output = PLLVCO_input * PLLN) + * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(*) (PLLVCO_output = PLLVCO_input * PLLN) * - PLLP: ensure that max frequency at 400000000 Hz or 280000000 Hz(*) is reached (PLLVCO_output / PLLP) * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000 * @param HSEBypass This parameter can be one of the following values: @@ -609,36 +599,24 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa */ /** - * @} - */ - -/** @addtogroup UTILS_LL_Private_Functions - * @{ - */ - -/** - * @brief Calculate and check the Flash wait states number according to the - new HCLK frequency and current voltage range. + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. * @param HCLK_Frequency HCLK frequency - * @param latency This parameter can be one of the following values: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - * @arg @ref LL_FLASH_LATENCY_2 - * @arg @ref LL_FLASH_LATENCY_3 - * @arg @ref LL_FLASH_LATENCY_4 - * @arg @ref LL_FLASH_LATENCY_5 - * @arg @ref LL_FLASH_LATENCY_6 - * @arg @ref LL_FLASH_LATENCY_7 * @retval An ErrorStatus enumeration value: * - SUCCESS: Latency has been modified * - ERROR: Latency cannot be modified */ -static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t *latency) +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) { ErrorStatus status = SUCCESS; + uint32_t timeout; + uint32_t getlatency; + uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + + /* Frequency cannot be equal to 0 */ - if(HCLK_Frequency == 0U) + if (HCLK_Frequency == 0U) { status = ERROR; } @@ -650,37 +628,36 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t if((HCLK_Frequency > UTILS_SCALE0_LATENCY5_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY6_FREQ)) { /* 264 < HCLK <= 280 => 6WS (7 CPU cycles) */ - *latency = LL_FLASH_LATENCY_6; + latency = LL_FLASH_LATENCY_6; } else if((HCLK_Frequency > UTILS_SCALE0_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY5_FREQ)) { /* 220 < HCLK <= 264 => 5WS (6 CPU cycles) */ - *latency = LL_FLASH_LATENCY_5; + latency = LL_FLASH_LATENCY_5; } else if((HCLK_Frequency > UTILS_SCALE0_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY4_FREQ)) { /* 176 < HCLK <= 220 => 4WS (5 CPU cycles) */ - *latency = LL_FLASH_LATENCY_4; + latency = LL_FLASH_LATENCY_4; } else if((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ)) { /* 132 < HCLK <= 176 => 3WS (4 CPU cycles) */ - *latency = LL_FLASH_LATENCY_3; + latency = LL_FLASH_LATENCY_3; } else if((HCLK_Frequency > UTILS_SCALE0_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY2_FREQ)) { /* 88 < HCLK <= 132 => 2WS (3 CPU cycles) */ - *latency = LL_FLASH_LATENCY_2; + latency = LL_FLASH_LATENCY_2; } else if((HCLK_Frequency > UTILS_SCALE0_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY1_FREQ)) { /* 44 < HCLK <= 88 => 1WS (2 CPU cycles) */ - *latency = LL_FLASH_LATENCY_1; + latency = LL_FLASH_LATENCY_1; } else if(HCLK_Frequency <= UTILS_SCALE0_LATENCY0_FREQ) { - /* HCLK <= 44 => 0WS (1 CPU cycles) */ - *latency = LL_FLASH_LATENCY_0; + /* HCLK <= 44 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */ } else { @@ -692,17 +669,17 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY5_FREQ)) { /* 210 < HCLK <= 225 => 5WS (6 CPU cycles) */ - *latency = LL_FLASH_LATENCY_5; + latency = LL_FLASH_LATENCY_5; } else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ)) { /* 168 < HCLK <= 210 => 4WS (5 CPU cycles) */ - *latency = LL_FLASH_LATENCY_4; + latency = LL_FLASH_LATENCY_4; } else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ)) { /* 126 < HCLK <= 168 => 3WS (4 CPU cycles) */ - *latency = LL_FLASH_LATENCY_3; + latency = LL_FLASH_LATENCY_3; } else if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ)) #else @@ -712,17 +689,16 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t #endif /*POWER_DOMAINS_NUMBER == 2U*/ { /* 140 < HCLK <= 210 => 2WS (3 CPU cycles) */ - *latency = LL_FLASH_LATENCY_2; + latency = LL_FLASH_LATENCY_2; } else if((HCLK_Frequency > UTILS_SCALE1_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ)) { /* 70 < HCLK <= 140 => 1WS (2 CPU cycles) */ - *latency = LL_FLASH_LATENCY_1; + latency = LL_FLASH_LATENCY_1; } else if(HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ) { - /* HCLK <= 70 => 0WS (1 CPU cycles) */ - *latency = LL_FLASH_LATENCY_0; + /* HCLK <= 70 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */ } else { @@ -735,7 +711,7 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY4_FREQ)) { /* 136 < HCLK <= 160 => 4WS (5 CPU cycles) */ - *latency = LL_FLASH_LATENCY_4; + latency = LL_FLASH_LATENCY_4; } else if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ)) #else @@ -743,22 +719,21 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t #endif /*POWER_DOMAINS_NUMBER == 2U*/ { /* 165 < HCLK <= 220 => 3WS (4 CPU cycles) */ - *latency = LL_FLASH_LATENCY_3; + latency = LL_FLASH_LATENCY_3; } else if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ)) { /* 110 < HCLK <= 165 => 2WS (3 CPU cycles) */ - *latency = LL_FLASH_LATENCY_2; + latency = LL_FLASH_LATENCY_2; } else if((HCLK_Frequency > UTILS_SCALE2_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ)) { /* 55 < HCLK <= 110 => 1WS (2 CPU cycles) */ - *latency = LL_FLASH_LATENCY_1; + latency = LL_FLASH_LATENCY_1; } else if(HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ) { - /* HCLK <= 55 => 0WS (1 CPU cycles) */ - *latency = LL_FLASH_LATENCY_0; + /* HCLK <= 55 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */ } else { @@ -771,7 +746,7 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY4_FREQ)) { /* 180 < HCLK <= 225 => 4WS (5 CPU cycles) */ - *latency = LL_FLASH_LATENCY_4; + latency = LL_FLASH_LATENCY_4; } else if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ)) #else @@ -779,55 +754,62 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t #endif /*POWER_DOMAINS_NUMBER == 3U*/ { /* 135 < HCLK <= 180 => 3WS (4 CPU cycles) */ - *latency = LL_FLASH_LATENCY_3; + latency = LL_FLASH_LATENCY_3; } else if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ)) { /* 90 < HCLK <= 135 => 2WS (3 CPU cycles) */ - *latency = LL_FLASH_LATENCY_2; + latency = LL_FLASH_LATENCY_2; } else if((HCLK_Frequency > UTILS_SCALE3_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ)) { /* 45 < HCLK <= 90 => 1WS (2 CPU cycles) */ - *latency = LL_FLASH_LATENCY_1; + latency = LL_FLASH_LATENCY_1; } else if(HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ) { - /* HCLK <= 45 => 0WS (1 CPU cycles) */ - *latency = LL_FLASH_LATENCY_0; + /* HCLK <= 45 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */ } else { status = ERROR; } } + + if(status == SUCCESS) + { + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + timeout = 2; + do + { + /* Wait for Flash latency to be updated */ + getlatency = LL_FLASH_GetLatency(); + timeout--; + } while ((getlatency != latency) && (timeout > 0U)); + + if(getlatency != latency) + { + status = ERROR; + } + } + } return status; } + /** - * @brief Update number of Flash wait states - * @param latency Flash Latency - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Latency has been modified - * - ERROR: Latency cannot be modified + * @} */ -static ErrorStatus UTILS_SetFlashLatency(uint32_t latency) -{ - ErrorStatus status = SUCCESS; - LL_FLASH_SetLatency(latency); +/** @addtogroup UTILS_LL_Private_Functions + * @{ + */ - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(LL_FLASH_GetLatency() != latency) - { - status = ERROR; - } - - return status; -} /** * @brief Function to check that PLL can be modified @@ -896,8 +878,8 @@ static ErrorStatus UTILS_IsPLLsReady(void) */ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { - ErrorStatus status; - uint32_t new_hclk_frequency, new_latency; + ErrorStatus status = SUCCESS; + uint32_t new_hclk_frequency; assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->SYSCLKDivider)); assert_param(IS_LL_UTILS_AHB_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); @@ -909,63 +891,72 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ /* Calculate the new HCLK frequency */ new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); - /* Calculate the new FLASH latency according to the new HCLK frequency */ - status = UTILS_CalculateFlashLatency(new_hclk_frequency, &new_latency); + /* Increasing the number of wait states because of higher CPU frequency */ + if (SystemD2Clock < new_hclk_frequency) + { + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(new_hclk_frequency); + } + /* Update system clock configuration */ if(status == SUCCESS) { - /* Increasing the number of wait states because of higher CPU frequency */ - if(LL_FLASH_GetLatency() < new_latency) + /* Enable PLL */ + LL_RCC_PLL1_Enable(); + while (LL_RCC_PLL1_IsReady() != 1U) { - status = UTILS_SetFlashLatency(new_latency); + /* Wait for PLL ready */ } - /* Update system clock configuration */ - if(status == SUCCESS) - { - /* Enable PLL */ - LL_RCC_PLL1_Enable(); - while (LL_RCC_PLL1_IsReady() != 1U) - { - /* Wait for PLL ready */ - } - - /* Set All APBxPrescaler to the Highest Divider */ - LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16); - LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16); - LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16); - LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16); - - /* Set SYS prescaler*/ - LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider); - - /* Set AHB prescaler*/ - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + /* Set All APBxPrescaler to the Highest Divider */ + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16); + LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16); + LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16); + LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16); - /* Sysclk activation on the main PLL */ - LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1); - while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) - { - /* Wait for system clock switch to PLL */ - } + /* Set SYS prescaler*/ + LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider); - /* Set APBn prescaler*/ - LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); - LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); - LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider); - LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider); + /* Set AHB prescaler*/ + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); - /* Update SystemCoreClock variable */ - LL_SetSystemCoreClock(SYSCLK_Frequency); + /* Sysclk activation on the main PLL */ + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1); + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) + { + /* Wait for system clock switch to PLL */ } + /* Set APBn prescaler*/ + LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); + LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); + LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider); + LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider); + /* Decreasing the number of wait states because of lower CPU frequency */ - if(LL_FLASH_GetLatency() > new_latency) + if (SystemD2Clock > new_hclk_frequency) { - status = UTILS_SetFlashLatency(new_latency); + /* Set FLASH latency to lowest latency */ + status = LL_SetFlashLatency(new_hclk_frequency); } + + /* Update the SystemD2Clock global variable */ +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + + /* Update SystemCoreClock variable */ +#if defined(DUAL_CORE) && defined(CORE_CM4) + LL_SetSystemCoreClock(SystemD2Clock); +#else + LL_SetSystemCoreClock(SYSCLK_Frequency); +#endif /* DUAL_CORE && CORE_CM4 */ + } + return status; } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h index 785cf797ee..7dc071f58e 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

                                            © COPYRIGHT(c) 2016 STMicroelectronics

                                            + *

                                            © Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

                                            * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h index 9123bf2cbd..171a4bf812 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h @@ -1594,7 +1594,6 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupReg /** @defgroup RTCEx_Private_Constants RTCEx Private Constants * @{ */ -//#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM18 /*!< External interrupt line 18 Connected to the RTC Alarm event */ #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) #define RTC_EXTI_LINE_SSRU_EVENT EXTI_IMR1_IM18 /*!< External interrupt line 18 Connected to the RTC SSR Underflow event */ #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h index 9871c85dfa..66fad3a30f 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h @@ -132,7 +132,11 @@ typedef struct * @brief SMBUS handle Structure definition * @{ */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) typedef struct __SMBUS_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ { I2C_TypeDef *Instance; /*!< SMBUS registers base address */ @@ -326,6 +330,7 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE)) #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) @@ -582,11 +587,12 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t ((REQUEST) == SMBUS_NO_STARTSTOP)) -#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ +#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ ((REQUEST) == SMBUS_FIRST_FRAME) || \ ((REQUEST) == SMBUS_NEXT_FRAME) || \ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h index 0a84990b59..2cb0a8891c 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h @@ -21,29 +21,13 @@ ****************************************************************************** * @attention * - *

                                            © COPYRIGHT(c) 2016 STMicroelectronics

                                            + *

                                            © Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

                                            * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h index 5db2e3a84b..bb0f3b8690 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h @@ -297,6 +297,7 @@ void LL_mDelay(uint32_t Delay); */ void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency); ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html index 31e2183283..bc56f54779 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html @@ -46,10 +46,57 @@

                                            Purpose

                                            Update History

                                            - +

                                            Main Changes

                                              +
                                            • Patch release of HAL and Low Layer drivers to include latest corrections
                                              • +
                                            +

                                            Contents

                                            +

                                            HAL drivers changes

                                            +
                                              +
                                            • HAL GPIO driver +
                                                +
                                              • Update HAL_GPIO_Init() initialization sequence to modify the order of GPIO registers update
                                                • +
                                              • +
                                            • HAL I2C driver +
                                                +
                                              • Update I2C_Enable_IRQ() function to remove incorrect interrupts enable when InterruptRequest = I2C_XFER_CPLT_IT
                                                • +
                                              • Update I2C_DMAXferCplt(), I2C_DMAError() and I2C_DMAAbort() functions to avoid null pointer exceptions
                                                • +
                                              • Update HAL_I2C_Master_Seq_Transmit/Receive_IT/DMA() functions to set correct condition range
                                                • +
                                              • Update I2C_ITMasterCplt() to remove C++ compilation warning due to unused variable
                                                • +
                                              • +
                                            • HAL RTC driver +
                                                +
                                              • Correct MISRA C:2012-Rule-3.1 warning in RTC driver
                                                • +
                                              • +
                                            • HAL SDMMC driver +
                                                +
                                              • Update MMC_InitCard() function to add missing correction for eMMC card size computation issue
                                                • +
                                              • Update SD_UltraHighSpeed() and SD_DDR_Mode() functions to remove useless assignment
                                                • +
                                              • Correct MISRA C:2012 warnings in SDMMC driver (rules 10.4_a, 10.7, 13.5, 15.7, 2.2_c)
                                                • +
                                              • +
                                            • HAL SMBUS driver +
                                                +
                                              • Update IS_SMBUS_TRANSFER_OPTIONS_REQUEST macro definition to include transfers with PEC
                                                • +
                                              • Correct MISRA C:2012-Rule-2.4 warning in structure __SMBUS_HandleTypeDef definition
                                                • +
                                              • +
                                            +

                                            LL drivers changes

                                            +
                                              +
                                            • LL UTILS driver +
                                                +
                                              • Change private UTILS_SetFlashLatency() function into LL_SetFlashLatency() public function
                                                • +
                                              • Update LL_PLL_ConfigSystemClock_MSI/HSI/HSE() functions to set expected AHB prescaler value
                                                • +
                                              • +
                                            +
                                            +
                                            +
                                            + +
                                            +

                                            Main Changes

                                            +
                                            • Release of HAL and Low Layer drivers to add support of STM32L4P5xx/STM32L4Q5xx devices
                                              • New PKA and PSSI peripherals supported in new HAL/LL PKA and HAL PSSI drivers
                                                • @@ -58,6 +105,7 @@

                                                Main Changes

                                              • Correction of several issues applicable to other devices
                                              +

                                              Contents

                                              HAL drivers changes

                                              • HAL driver @@ -397,10 +445,11 @@

                                                Main Changes

                                                -

                                                Main Changes

                                                +

                                                Main Changes

                                                • Delivery of the new HAL MMC driver
                                                +

                                                Contents

                                                HAL drivers changes

                                                • HAL ADC driver @@ -688,12 +737,13 @@

                                                  Main Changes

                                                  -

                                                  Main Changes

                                                  +

                                                  Main Changes

                                                  • Release of HAL and Low Layer drivers to add support of STM32L412xx/STM32L422xx
                                                  • Superset features device STM32L422xx API User Manual available (STM32L422xx_User_Manual.chm)  
                                                  • MISRA C:2012 corrections
                                                  +

                                                  Contents

                                                  HAL drivers changes

                                                  MISRA C:2012 corrections listed hereafter are applicable to LL driver as well.

                                                    @@ -879,7 +929,7 @@

                                                    Main Changes

                                                    -

                                                    Main Changes

                                                    +

                                                    Main Changes

                                                    Maintenance Release of HAL and Low Layer drivers

                                                    Add support of HAL callback registration feature

                                                      @@ -889,6 +939,7 @@

                                                      Main Changes

                                                    • Once enabled, the user application may resort to HAL_PPP_RegisterCallback() to register specific callback function(s) and unregister it(them) with HAL_PPP_UnRegisterCallback().

                                                    MISRAC-2012 corrections

                                                    +

                                                    Contents

                                                    HAL drivers changes

                                                    • HAL generic driver

                                                      @@ -1236,10 +1287,11 @@

                                                      Main Changes

                                                      -

                                                      Main Changes

                                                      +

                                                      Main Changes

                                                      • Maintenance Release of HAL and Low Layer drivers
                                                      +

                                                      Contents

                                                      HAL drivers changes

                                                      • HAL CAN driver
                                                        • @@ -1317,10 +1369,11 @@

                                                        Main Changes

                                                        -

                                                        Main Changes

                                                        +

                                                        Main Changes

                                                        • Maintenance Release of HAL and Low Layer drivers
                                                        +

                                                        Contents

                                                        HAL drivers changes

                                                        • HAL generic driver

                                                          @@ -1398,13 +1451,14 @@

                                                          Main Changes

                                                          -

                                                          Main Changes

                                                          +

                                                          Main Changes

                                                          • Release of HAL and Low Layer drivers to add support of STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx devices

                                                          • New OctoSPI, DSI, LTDC, GFXMMU peripherals supported in new HAL OSPI, HAL DSI, HAL LTDC and HAL GFXMMU drivers

                                                          • Superset features device STM32L4S9xx API User Manual available (STM32L4S9xx_User_Manual.chm)  

                                                          -

                                                              HAL drivers changes

                                                          +

                                                              ## Contents

                                                          +

                                                          HAL drivers changes

                                                          • HAL DSI driver (NEW): stm32l4xx_hal_dsi.h/.c files
                                                          • HAL GFXMMU driver (NEW):stm32l4xx_hal_gfxmmu.h/.c files
                                                            • @@ -1654,10 +1708,11 @@

                                                            Main Changes

                                                            -

                                                            Main Changes

                                                            +

                                                            Main Changes

                                                            • Maintenance Release of HAL and Low Layer drivers
                                                            +

                                                            Contents

                                                            HAL drivers changes

                                                            • HAL CAN driver

                                                              @@ -1709,10 +1764,11 @@

                                                              Main Changes

                                                              -

                                                              Main Changes

                                                              +

                                                              Main Changes

                                                              • Maintenance Release of HAL and Low Layer drivers
                                                              +

                                                              Contents

                                                              HAL drivers changes

                                                              • HAL generic driver

                                                                @@ -1752,7 +1808,7 @@

                                                                Main Changes

                                                                -

                                                                Main Changes

                                                                +

                                                                Main Changes

                                                                • Release of HAL and Low Layer drivers to add support of STM32L496xx/STM32L4A6xx devices
                                                                • New DCMI, DMA2D, HASH peripherals supported in new HAL DCMI, HAL & LL DMA2D and HAL HASH drivers
                                                                  • @@ -1761,6 +1817,7 @@

                                                                  Main Changes

                                                                • Superset features device STM32L4A6xx API User Manual available (STM32L4A6xx_User_Manual.chm) 
                                                                +

                                                                Contents

                                                                HAL drivers changes

                                                                • HAL DCMI driver (NEW): stm32l4xx_hal_dcmi.h/.c files
                                                                  • @@ -1860,11 +1917,12 @@

                                                                  Main Changes

                                                                  -

                                                                  Main Changes

                                                                  +

                                                                  Main Changes

                                                                  • Release of HAL and Low Layer drivers to add support of STM32L451xx/STM32L452xx/STM32L462xx devices
                                                                  • Superset features device STM32L462xx API User Manual available (STM32L462xx_User_Manual.chm)
                                                                  +

                                                                  Contents

                                                                  HAL drivers changes

                                                                  • HAL CRYP driver

                                                                    @@ -1924,6 +1982,7 @@

                                                                    Main Changes

                                                                    +

                                                                    Contents

                                                                    HAL drivers changes

                                                                    • HAL ADC driver

                                                                      @@ -2015,6 +2074,7 @@

                                                                      Main Changes

                                                                      +

                                                                      Contents

                                                                      HAL drivers changes

                                                                      • HAL ADC driver

                                                                        @@ -2042,10 +2102,11 @@

                                                                        Main Changes

                                                                        -

                                                                        Main Changes

                                                                        +

                                                                        Main Changes

                                                                        • Maintenance Release of HAL and Low Layer drivers
                                                                        +

                                                                        Contents

                                                                        HAL drivers changes

                                                                        Enhance HAL delay and timebase implementation

                                                                          @@ -2225,7 +2286,7 @@

                                                                          Main Changes

                                                                        • Update initialization sequence in voltage class B
                                                                      -

                                                                      HAL drivers changes

                                                                      +

                                                                      LL drivers changes

                                                                      • LL ADC driver
                                                                          @@ -2291,7 +2352,7 @@

                                                                          Main Changes

                                                                          -

                                                                          Main Changes

                                                                          +

                                                                          Main Changes

                                                                          • Release of HAL and Low Layer drivers to add support of STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx devices
                                                                          • Low Layer driver initialization/de-initialization APIs applicable to all STM32L4xx devices
                                                                            • @@ -2299,6 +2360,7 @@

                                                                            Main Changes

                                                                          • Superset features device STM32L443xx API User Manual available (STM32L443xx_User_Manual.chm) 
                                                                          +

                                                                          Contents

                                                                          HAL drivers changes

                                                                          • HAL generic update

                                                                            @@ -2315,9 +2377,11 @@

                                                                            Main Changes

                                                                        LL drivers changes

                                                                        -

                                                                        New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs

                                                                          -

                                                                        • stm32l4xx_ll_crs.c

                                                                          • +
                                                                        • New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs +
                                                                            +
                                                                          • stm32l4xx_ll_crs.c
                                                                            • +
                                                                        • LL BUS update
                                                                          • Add read-back register on clock enable functions to take into account any delay on bus
                                                                            • @@ -2360,15 +2424,20 @@

                                                                            Main Changes

                                                                            -

                                                                            Main Changes

                                                                            -

                                                                            New Low Layer driver initialization/de-initialization APIs

                                                                            -

                                                                            Naming rule is LL_PPP_Init(), LL_PPP_StructInit(), LL_PPP_DeInit() and more initialization APIs when applicable for peripheral PPP: ADC, COMP, CRC, DAC, DMA, EXTI, GPIO, I2C, LPTIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, SWPMI, TIM and USART. 

                                                                            -

                                                                            New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs

                                                                            +

                                                                            Main Changes

                                                                            +
                                                                              +
                                                                            • New Low Layer driver initialization/de-initialization APIs +
                                                                                +
                                                                              • Naming rule is LL_PPP_Init(), LL_PPP_StructInit(), LL_PPP_DeInit() and more initialization APIs when applicable for peripheral PPP: ADC, COMP, CRC, DAC, DMA, EXTI, GPIO, I2C, LPTIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, SWPMI, TIM and USART. 
                                                                                • +
                                                                              • +
                                                                            • New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs
                                                                              • stm32l4xx_ll_adc.c, stm32l4xx_ll_comp.c, stm32l4xx_ll_crc.c, stm32l4xx_ll_dac.c, stm32l4xx_ll_dma.c, stm32l4xx_ll_exti.c, stm32l4xx_ll_gpio.c, stm32l4xx_ll_i2c.c, stm32l4xx_ll_lptim.c, stm32l4xx_ll_lpuart.c, stm32l4xx_ll_opamp.c, stm32l4xx_ll_pwr.c, stm32l4xx_ll_rcc.c, stm32l4xx_ll_rng.c, stm32l4xx_ll_rtc.c, stm32l4xx_ll_spi.c, stm32l4xx_ll_swpmi.c, stm32l4xx_ll_tim.c and stm32l4xx_ll_usart.c
                                                                              • stm32l4xx_ll_utils.c contains some Low Layer utilities for SysTick, Flash latency and clock configuration. 
                                                                                • +
                                                                              • +
                                                                            • Fix "parameter unused" GCC compilation warnings on __weak functions
                                                                            -

                                                                            Fix "parameter unused" GCC compilation warnings on __weak functions

                                                                            +

                                                                            Contents

                                                                            HAL drivers changes

                                                                            • HAL generic update

                                                                              @@ -2516,7 +2585,7 @@

                                                                              Main Changes

                                                                              -

                                                                              Main Changes

                                                                              +

                                                                              Main Changes

                                                                              • HAL generic update
                                                                                  @@ -2573,7 +2642,7 @@

                                                                                  Main Changes

                                                                                  -

                                                                                  Main Changes

                                                                                  +

                                                                                  Main Changes

                                                                                  • HAL generic update

                                                                                      @@ -2603,13 +2672,16 @@

                                                                                      Main Changes

                                                                                      -

                                                                                      Main Changes

                                                                                      +

                                                                                      Main Changes

                                                                                      Add Low Layer drivers allowing performance and footprint optimization

                                                                                      • Low Layer drivers APIs provide register level programming: they require deep knowledge of peripherals described in STM32L4x6 Reference Manual

                                                                                      • Low Layer drivers are available for: ADC, COMP, Cortex, CRC, DAC, DMA, EXTI, GPIO, I2C, IWDG, LPYIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, SWPMI, TIM, USART, WWDG peripherals and additionnal Low Level Bus, System and Utilities APIs.

                                                                                      • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32l4xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32l4xx_ll_ppp.h file must be included in user code.

                                                                                        • +
                                                                                      +

                                                                                      Contents

                                                                                      +

                                                                                      • HAL ADC update

                                                                                        • Channel 5 is not usable for ADC3
                                                                                          • @@ -2673,7 +2745,7 @@

                                                                                          Main Changes

                                                                                          -

                                                                                          Main Changes

                                                                                          +

                                                                                          Main Changes

                                                                                          • First official release of STM32L4xx HAL Drivers for STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx and STM32L486xx devices
                                                                                          diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c index 5ff687dc9c..e9e30ae8fe 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c @@ -53,7 +53,7 @@ */ #define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define STM32L4XX_HAL_VERSION_SUB1 (0x0BU) /*!< [23:16] sub1 version */ -#define STM32L4XX_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define STM32L4XX_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\ |(STM32L4XX_HAL_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c index b63d4f7a80..967a247f70 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c @@ -90,29 +90,13 @@ ****************************************************************************** * @attention * - *

                                                                                          © COPYRIGHT(c) 2016 STMicroelectronics

                                                                                          + *

                                                                                          © Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

                                                                                          * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -161,7 +145,7 @@ /** * @brief Set the priority grouping field (pre-emption priority and subpriority) * using the required unlock sequence. - * @param PriorityGroup The priority grouping bits length. + * @param PriorityGroup: The priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, * 4 bits for subpriority @@ -188,13 +172,13 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) /** * @brief Set the priority of an interrupt. - * @param IRQn External interrupt number. + * @param IRQn: External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @param PreemptPriority The pre-emption priority for the IRQn channel. + * @param PreemptPriority: The pre-emption priority for the IRQn channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority - * @param SubPriority the subpriority level for the IRQ channel. + * @param SubPriority: the subpriority level for the IRQ channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None @@ -259,7 +243,7 @@ void HAL_NVIC_SystemReset(void) /** * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ @@ -299,7 +283,7 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void) /** * @brief Get the priority of an interrupt. - * @param IRQn External interrupt number. + * @param IRQn: External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) * @param PriorityGroup: the priority grouping bits length. @@ -314,8 +298,8 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void) * 1 bit for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, * 0 bit for subpriority - * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority Pointer on the Subpriority value (starting from 0). + * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority: Pointer on the Subpriority value (starting from 0). * @retval None */ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) @@ -392,7 +376,7 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) /** * @brief Configure the SysTick clock source. - * @param CLKSource specifies the SysTick clock source. + * @param CLKSource: specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. @@ -435,7 +419,7 @@ __weak void HAL_SYSTICK_Callback(void) #if (__MPU_PRESENT == 1) /** * @brief Enable the MPU. - * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, * NMI, FAULTMASK and privileged accessto the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE @@ -471,7 +455,7 @@ void HAL_MPU_Disable(void) /** * @brief Initialize and configure the Region and the memory to be protected. - * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c index 412be3d444..7454bec27e 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c @@ -190,26 +190,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) if (iocurrent != 0x00u) { /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Alternate function mode selection */ - if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Alternate function parameters */ - assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3u]; - temp &= ~(0xFu << ((position & 0x07u) * 4u)); - temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); - GPIOx->AFR[position >> 3u] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); - GPIOx->MODER = temp; - /* In case of Output or Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) @@ -249,6 +229,26 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp |= ((GPIO_Init->Pull) << (position * 2u)); GPIOx->PUPDR = temp; + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3u]; + temp &= ~(0xFu << ((position & 0x07u) * 4u)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + GPIOx->AFR[position >> 3u] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + GPIOx->MODER = temp; + /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c index 40afa7f956..5ea8fd3a48 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c @@ -351,13 +351,13 @@ /* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (0x00000001U) -#define I2C_XFER_RX_IT (0x00000002U) -#define I2C_XFER_LISTEN_IT (0x00000004U) +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */ -#define I2C_XFER_ERROR_IT (0x00000011U) -#define I2C_XFER_CPLT_IT (0x00000012U) -#define I2C_XFER_RELOAD_IT (0x00000012U) +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */ /* Private define Sequential Transfer Options default/reset value */ #define I2C_NO_OPTION_FRAME (0xFFFF0000U) @@ -410,6 +410,9 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + /* Private function to flush TXDR register */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); @@ -3200,7 +3203,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3285,7 +3288,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3446,7 +3449,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3531,7 +3534,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -4251,9 +4254,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Locked */ __HAL_LOCK(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Set State at HAL_I2C_STATE_ABORT */ hi2c->State = HAL_I2C_STATE_ABORT; @@ -5001,6 +5016,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { uint32_t tmpoptions = hi2c->XferOptions; uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; /* Process locked */ __HAL_LOCK(hi2c); @@ -5079,8 +5095,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } @@ -5369,9 +5401,27 @@ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) */ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ @@ -5426,19 +5476,36 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); /* Reset handle parameters */ - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -5447,12 +5514,17 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + /* Flush TX register */ I2C_Flush_TXDR(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); - /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; @@ -5466,6 +5538,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5500,6 +5573,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5546,12 +5620,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -5565,6 +5653,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if (hi2c->hdmatx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); @@ -5572,6 +5663,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if (hi2c->hdmarx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); @@ -5608,7 +5702,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -5631,6 +5724,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5646,6 +5740,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5660,6 +5755,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5733,6 +5829,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { HAL_I2C_StateTypeDef tmpstate = hi2c->State; + uint32_t tmppreviousstate; /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; @@ -5752,7 +5849,6 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* keep HAL_I2C_STATE_LISTEN if set */ hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = I2C_Slave_ISR_IT; } else @@ -5767,16 +5863,19 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; } /* Abort DMA TX transfer if any */ - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } - if (hi2c->hdmatx != NULL) + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5792,13 +5891,20 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } /* Abort DMA RX transfer if any */ - else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } - if (hi2c->hdmarx != NULL) + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5814,10 +5920,28 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } - else if (hi2c->State == HAL_I2C_STATE_ABORT) + else + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5831,6 +5955,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } else { + hi2c->PreviousState = I2C_STATE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -6041,30 +6167,16 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Reset AbortCpltCallback */ - hi2c->hdmatx->XferAbortCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Check if come from abort from user */ - if (hi2c->State == HAL_I2C_STATE_ABORT) + if (hi2c->hdmatx != NULL) { - hi2c->State = HAL_I2C_STATE_READY; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AbortCpltCallback(hi2c); -#else - HAL_I2C_AbortCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmatx->XferAbortCallback = NULL; } - else + if (hi2c->hdmarx != NULL) { - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->ErrorCallback(hi2c); -#else - HAL_I2C_ErrorCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmarx->XferAbortCallback = NULL; } + + I2C_TreatErrorCallback(hi2c); } /** @@ -6341,19 +6453,19 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -6379,7 +6491,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; @@ -6433,19 +6545,19 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_mmc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_mmc.c index 2085432aec..d52f6db8ea 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_mmc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_mmc.c @@ -2532,7 +2532,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 { case SDMMC_SPEED_MODE_AUTO: { - if (((device_type & 0x04U) != 0U) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U)) + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U)) { /* High Speed DDR mode allowed */ errorstate = MMC_HighSpeed(hmmc, ENABLE); @@ -2558,11 +2558,15 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 hmmc->ErrorCode |= errorstate; } } + else + { + /* Nothing to do : keep current speed */ + } break; } case SDMMC_SPEED_MODE_DDR: { - if (((device_type & 0x04U) != 0U) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U)) + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U)) { /* High Speed DDR mode allowed */ errorstate = MMC_HighSpeed(hmmc, ENABLE); @@ -3022,9 +3026,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) HAL_MMC_CardCSDTypeDef CSD; uint32_t errorstate; uint16_t mmc_rca = 1U; -#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) MMC_InitTypeDef Init; -#endif /* Check the power State */ if(SDMMC_GetPowerState(hmmc->Instance) == 0U) @@ -3077,23 +3079,6 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Get the Card Class */ hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U); -#if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) - /* Get CSD parameters */ - if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK) - { - return hmmc->ErrorCode; - } - - /* Select the Card */ - errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) - { - return errorstate; - } - - /* Configure SDMMC peripheral interface */ - (void)SDMMC_Init(hmmc->Instance, hmmc->Init); -#else /* Select the Card */ errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); if(errorstate != HAL_MMC_ERROR_NONE) @@ -3121,7 +3106,6 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl; Init.ClockDiv = hmmc->Init.ClockDiv; (void)SDMMC_Init(hmmc->Instance, Init); -#endif /* All cards are initialized */ return HAL_MMC_ERROR_NONE; @@ -3274,7 +3258,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel tmp_data = SDMMC_ReadFIFO(hmmc->Instance); /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */ /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */ - if ((i + count) == (FieldIndex/4)) + if ((i + count) == ((uint32_t)FieldIndex/4U)) { *pFieldData = tmp_data; } @@ -3395,16 +3379,16 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) { uint32_t errorstate = HAL_MMC_ERROR_NONE; - uint32_t response = 0U, count = 0U; + uint32_t response, count; SDMMC_InitTypeDef Init; - if ((state == DISABLE) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U)) + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE)) { /* Index : 185 - Value : 0 */ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U); } - if ((state != DISABLE) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U)) + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE)) { /* Index : 185 - Value : 1 */ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U); @@ -3479,9 +3463,9 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state) { uint32_t errorstate = HAL_MMC_ERROR_NONE; - uint32_t response = 0U, count = 0U; + uint32_t response, count; - if ((state == DISABLE) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U)) + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) && (state == DISABLE)) { if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U) { @@ -3495,7 +3479,7 @@ static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state) } } - if ((state != DISABLE) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)) + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) && (state != DISABLE)) { if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U) { diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c index 37ef756b24..2a00821593 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c @@ -3556,8 +3556,6 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* Clean Status flags */ hsd->Instance->ICR = 0xFFFFFFFFU; } - - hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; } } #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ @@ -3732,7 +3730,7 @@ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) */ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) { - uint32_t scr[2U] = {0U, 0U}; + uint32_t scr[2U] = {0UL, 0UL}; uint32_t errorstate; if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) @@ -3779,7 +3777,7 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) */ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) { - uint32_t scr[2U] = {0U, 0U}; + uint32_t scr[2U] = {0UL, 0UL}; uint32_t errorstate; if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) @@ -3832,7 +3830,7 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); uint32_t index = 0U; - uint32_t tempscr[2U] = {0U, 0U}; + uint32_t tempscr[2U] = {0UL, 0UL}; uint32_t *scr = pSCR; /* Set Block Size To 8 Bytes */ @@ -4086,8 +4084,6 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - errorstate = 0; - return errorstate; } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) @@ -4201,8 +4197,6 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - errorstate = 0; - return errorstate; } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) @@ -4332,8 +4326,6 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - errorstate = 0; - return errorstate; } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c index 29618a0974..fa269e9beb 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c @@ -203,18 +203,18 @@ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions * @{ */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); -static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); -static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); /** * @} */ @@ -1801,7 +1801,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) * @param StatusFlags Value of Interrupt Flags. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) { uint16_t DevAddress; @@ -2085,7 +2085,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, * @param StatusFlags Value of Interrupt Flags. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) { uint8_t TransferDirection; uint16_t SlaveAddrCode; @@ -2341,7 +2341,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, u * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) { uint32_t tmpisr = 0UL; @@ -2381,7 +2381,7 @@ static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Inte * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) { uint32_t tmpisr = 0UL; uint32_t tmpstate = hsmbus->State; @@ -2453,7 +2453,7 @@ static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Int * @param hsmbus SMBUS handle. * @retval None */ -static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus) +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) { uint32_t itflags = READ_REG(hsmbus->Instance->ISR); uint32_t itsources = READ_REG(hsmbus->Instance->CR1); @@ -2554,7 +2554,7 @@ static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -2603,7 +2603,7 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeD * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); @@ -2620,7 +2620,7 @@ static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t * @param hsmbus SMBUS handle. * @retval None */ -static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus) +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) { /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */ /* it request implicitly to generate a restart condition */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c index 0f1999b45d..b1dd002362 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c @@ -41,7 +41,8 @@ /** @addtogroup UTILS_LL_Private_Constants * @{ */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define UTILS_MAX_FREQUENCY_SCALE1 120000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ #define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ #else @@ -60,7 +61,8 @@ #define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */ /* Defines used for FLASH latency according to HCLK Frequency */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define UTILS_SCALE1_LATENCY1_FREQ 20000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ #define UTILS_SCALE1_LATENCY2_FREQ 40000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ #define UTILS_SCALE1_LATENCY3_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ @@ -143,7 +145,6 @@ */ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); -static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency); static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); static ErrorStatus UTILS_PLL_IsBusy(void); /** @@ -227,7 +228,7 @@ void LL_mDelay(uint32_t Delay) Depending on the device voltage range, the maximum frequency should be adapted accordingly: - (++) Table 1. HCLK clock frequency for STM32L4Rx/STM32L4Sx devices + (++) Table 1. HCLK clock frequency for STM32L4+ Series devices (++) +--------------------------------------------------------+ (++) | Latency | HCLK clock frequency (MHz) | (++) | |--------------------------------------| @@ -247,7 +248,7 @@ void LL_mDelay(uint32_t Delay) (++) |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 | (++) +--------------------------------------------------------+ - (++) Table 2. HCLK clock frequency for other STM32L4 devices + (++) Table 2. HCLK clock frequency for STM32L4 Series devices (++) +-------------------------------------------------------+ (++) | Latency | HCLK clock frequency (MHz) | (++) | |-------------------------------------| @@ -281,6 +282,150 @@ void LL_SetSystemCoreClock(uint32_t HCLKFrequency) SystemCoreClock = HCLKFrequency; } +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @param HCLKFrequency HCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency) +{ + ErrorStatus status = SUCCESS; + + uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + + /* Frequency cannot be equal to 0 or greater than max clock */ + if ((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_MAX_FREQUENCY_SCALE1)) + { + status = ERROR; + } + else + { + if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) + { +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(HCLKFrequency > UTILS_SCALE1_LATENCY5_FREQ) + { + /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */ + latency = LL_FLASH_LATENCY_5; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ) + { + /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ) + { + /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ) + { + /* 40 < HCLK <= 20 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ) + { + /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLKFrequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ + } +#else + if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ) + { + /* 64 < HCLK <= 80 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ) + { + /* 48 < HCLK <= 64 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ) + { + /* 32 < HCLK <= 48 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ) + { + /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLKFrequency <= 16MHz default LL_FLASH_LATENCY_0 0WS */ + } +#endif + } + else /* SCALE2 */ + { +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(HCLKFrequency > UTILS_MAX_FREQUENCY_SCALE2) + { + /* Unexpected HCLK > 26 */ + status = ERROR; + } + else if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ) + { + /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ) + { + /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLKFrequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */ + } +#else + if(HCLKFrequency > UTILS_MAX_FREQUENCY_SCALE2) + { + /* Unexpected HCLK > 26 */ + status = ERROR; + } + else if(HCLKFrequency > UTILS_SCALE2_LATENCY3_FREQ) + { + /* 18 < HCLK <= 26 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ) + { + /* 12 < HCLK <= 18 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ) + { + /* 6 < HCLK <= 12 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLKFrequency <= 6MHz default LL_FLASH_LATENCY_0 0WS */ + } +#endif + } + + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(LL_FLASH_GetLatency() != latency) + { + status = ERROR; + } + } + return status; +} + /** * @brief This function configures system clock with MSI as clock source of the PLL * @note The application needs to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled. @@ -302,7 +447,8 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS { ErrorStatus status = SUCCESS; uint32_t pllfreq, msi_range; -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) uint32_t hpre = 0U; /* Set default value */ #endif @@ -374,26 +520,34 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->PLLR); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ if(pllfreq > 80000000U) { - hpre = UTILS_ClkInitStruct->AHBCLKDivider; - if(hpre == LL_RCC_SYSCLK_DIV_1) + if(UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1) { UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + hpre = LL_RCC_SYSCLK_DIV_2; } } #endif /* Enable PLL and switch system clock to PLL */ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Apply definitive AHB prescaler value if necessary */ - if((status == SUCCESS) && (hpre != 0U)) + if((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1)) { - UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(pllfreq); + if(status == SUCCESS) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_SetSystemCoreClock(pllfreq); + } } #endif } @@ -428,8 +582,9 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS { ErrorStatus status; uint32_t pllfreq; -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t hpre = 0U; /* Set default value */ +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t hpre = LL_RCC_SYSCLK_DIV_1; /* Set default value */ #endif /* Check if one of the PLL is enabled */ @@ -452,26 +607,34 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->PLLR); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ if(pllfreq > 80000000U) { - hpre = UTILS_ClkInitStruct->AHBCLKDivider; - if(hpre == LL_RCC_SYSCLK_DIV_1) + if(UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1) { UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + hpre = LL_RCC_SYSCLK_DIV_2; } } #endif /* Enable PLL and switch system clock to PLL */ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Apply definitive AHB prescaler value if necessary */ - if((status == SUCCESS) && (hpre != 0U)) + if((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1)) { - UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(pllfreq); + if(status == SUCCESS) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_SetSystemCoreClock(pllfreq); + } } #endif } @@ -509,7 +672,8 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa { ErrorStatus status; uint32_t pllfreq; -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) uint32_t hpre = 0U; /* Set default value */ #endif @@ -548,26 +712,34 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->PLLR); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ if(pllfreq > 80000000U) { - hpre = UTILS_ClkInitStruct->AHBCLKDivider; - if(hpre == LL_RCC_SYSCLK_DIV_1) + if(UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1) { UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + hpre = LL_RCC_SYSCLK_DIV_2; } } #endif /* Enable PLL and switch system clock to PLL */ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Apply definitive AHB prescaler value if necessary */ - if((status == SUCCESS) && (hpre != 0U)) + if((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1)) { - UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(pllfreq); + if(status == SUCCESS) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_SetSystemCoreClock(pllfreq); + } } #endif } @@ -591,138 +763,6 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa /** @addtogroup UTILS_LL_Private_Functions * @{ */ -/** - * @brief Update number of Flash wait states in line with new frequency and current - voltage range. - * @param HCLK_Frequency HCLK frequency - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Latency has been modified - * - ERROR: Latency cannot be modified - */ -static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) -{ - ErrorStatus status = SUCCESS; - - uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ - - /* Frequency cannot be equal to 0 */ - if(HCLK_Frequency == 0U) - { - status = ERROR; - } - else - { - if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) - { -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - if(HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) - { - /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */ - latency = LL_FLASH_LATENCY_5; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) - { - /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */ - latency = LL_FLASH_LATENCY_4; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) - { - /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) - { - /* 40 < HCLK <= 20 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) - { - /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ - } -#else - if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) - { - /* 64 < HCLK <= 80 => 4WS (5 CPU cycles) */ - latency = LL_FLASH_LATENCY_4; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) - { - /* 48 < HCLK <= 64 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) - { - /* 32 < HCLK <= 48 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) - { - /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency <= 16MHz default LL_FLASH_LATENCY_0 0WS */ - } -#endif - } - else /* SCALE2 */ - { -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) - { - /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) - { - /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */ - } -#else - if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) - { - /* 18 < HCLK <= 26 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) - { - /* 12 < HCLK <= 18 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) - { - /* 6 < HCLK <= 12 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency <= 6MHz default LL_FLASH_LATENCY_0 0WS */ - } -#endif - } - - LL_FLASH_SetLatency(latency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(LL_FLASH_GetLatency() != latency) - { - status = ERROR; - } - } - return status; -} - /** * @brief Function to check that PLL can be modified * @param PLL_InputFrequency PLL input frequency (in Hz) @@ -818,7 +858,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ if(SystemCoreClock < hclk_frequency) { /* Set FLASH latency to highest latency */ - status = UTILS_SetFlashLatency(hclk_frequency); + status = LL_SetFlashLatency(hclk_frequency); } /* Update system clock configuration */ @@ -849,7 +889,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ if(SystemCoreClock > hclk_frequency) { /* Set FLASH latency to lowest latency */ - status = UTILS_SetFlashLatency(hclk_frequency); + status = LL_SetFlashLatency(hclk_frequency); } /* Update SystemCoreClock variable */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index e6635d118f..f0face3725 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -241,7 +241,7 @@ #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32H7) || defined(STM32F4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -313,8 +313,8 @@ #endif /* STM32L4 */ #if defined(STM32G0) -#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 -#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 #endif #if defined(STM32H7) @@ -579,8 +579,7 @@ #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 -#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) \ - || defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS @@ -955,7 +954,7 @@ #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) || defined(STM32H7) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif @@ -1449,6 +1448,30 @@ #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ @@ -1507,13 +1530,13 @@ #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA @@ -1539,10 +1562,10 @@ */ #if defined(STM32G0) -#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD -#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD -#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD -#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler #endif #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg @@ -3219,9 +3242,8 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -3349,7 +3371,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined STM32G4 +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined STM32WL #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3457,9 +3479,9 @@ #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND /* alias CMSIS for compatibilities */ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler @@ -3472,7 +3494,7 @@ #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif -#if defined(STM32H7) +#if defined(STM32H7) || defined(STM32L5) #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback @@ -3727,9 +3749,9 @@ /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32L4) +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE -#endif +#endif /* STM32L4 || STM32F4 || STM32F7 */ /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h index b69544f384..4e130d4a5f 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h @@ -38,23 +38,26 @@ * @{ */ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup HAL_Exported_Constants HAL Exported Constants - * @{ - */ - /** @defgroup HAL_TICK_FREQ Tick Frequency * @{ */ -#define HAL_TICK_FREQ_10HZ 100U -#define HAL_TICK_FREQ_100HZ 10U -#define HAL_TICK_FREQ_1KHZ 1U -#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; /** * @} */ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants * @{ */ @@ -594,8 +597,8 @@ void HAL_IncTick(void); void HAL_Delay(uint32_t Delay); uint32_t HAL_GetTick(void); uint32_t HAL_GetTickPrio(void); -HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq); -uint32_t HAL_GetTickFreq(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); void HAL_SuspendTick(void); void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); @@ -630,7 +633,7 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void); */ extern __IO uint32_t uwTick; extern uint32_t uwTickPrio; -extern uint32_t uwTickFreq; +extern HAL_TickFreqTypeDef uwTickFreq; /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc.h index 51790fca22..0968ba9891 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_adc.h @@ -125,8 +125,8 @@ typedef struct This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. - Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag - to free the IRQ vector sequencer. + Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). + Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_exti.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_exti.h index e16979617b..a122369a10 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_exti.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_exti.h @@ -105,18 +105,39 @@ typedef struct #define EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x11u) #define EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x12u) #define EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x13u) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x14u) #define EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x15u) +#else +#define EXTI_LINE_20 (EXTI_RESERVED | EXTI_REG1 | 0x14u) +#define EXTI_LINE_21 (EXTI_RESERVED | EXTI_REG1 | 0x15u) +#endif #define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u) +#else +#define EXTI_LINE_23 (EXTI_RESERVED | EXTI_REG1 | 0x17u) +#endif #define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u) +#else +#define EXTI_LINE_25 (EXTI_RESERVED | EXTI_REG1 | 0x19u) +#endif #define EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au) #define EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu) +#else +#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu) +#endif #define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du) #define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu) +#else +#define EXTI_LINE_31 (EXTI_RESERVED | EXTI_REG1 | 0x1Fu) +#endif #define EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00u) #define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u) #define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u) @@ -128,7 +149,7 @@ typedef struct #define EXTI_LINE_40 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x08u) #define EXTI_LINE_41 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x09u) #define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au) -#if defined (STM32WB55xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) #define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu) #else #define EXTI_LINE_43 (EXTI_RESERVED | EXTI_REG2 | 0x0Bu) @@ -170,7 +191,7 @@ typedef struct #define EXTI_GPIOA 0x00000000u #define EXTI_GPIOB 0x00000001u #define EXTI_GPIOC 0x00000002u -#if defined (STM32WB55xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) #define EXTI_GPIOD 0x00000003u #endif #define EXTI_GPIOE 0x00000004u @@ -261,7 +282,7 @@ typedef struct #define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) -#if defined (STM32WB55xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ ((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOC) || \ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h index 548518ffbe..683e0f2a1b 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h @@ -46,7 +46,7 @@ extern "C" { */ typedef struct { - uint32_t TypeErase; /*!< Mass erase or page erase. + uint32_t TypeErase; /*!< Page erase. This parameter can be a value of @ref FLASH_TYPE_ERASE */ uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */ @@ -222,7 +222,6 @@ typedef struct * @{ */ #define FLASH_TYPEERASE_PAGES FLASH_CR_PER /*!< Pages erase only*/ -#define FLASH_TYPEERASE_MASSERASE FLASH_CR_MER /*!< Flash mass erase activation*/ /** * @} */ @@ -853,8 +852,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define IS_ADDR_ALIGNED_64BITS(__VALUE__) (((__VALUE__) & 0x7U) == (0x00UL)) -#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \ - ((__VALUE__) == FLASH_TYPEERASE_MASSERASE)) +#define IS_FLASH_TYPEERASE(__VALUE__) ((__VALUE__) == FLASH_TYPEERASE_PAGES) #define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ ((__VALUE__) == FLASH_TYPEPROGRAM_FAST)) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h index fc10f8ebe4..3000c6d92a 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h @@ -53,7 +53,7 @@ * */ -#if defined (STM32WB55xx) || defined (STM32WB50xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB50xx) /* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | *_____________________________________________________________________________________________ @@ -355,7 +355,6 @@ /** * @brief AF 15 selection */ - #define GPIO_AF15_EVENTOUT ((uint8_t)0x0f) /*!< EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0f) @@ -363,6 +362,241 @@ #endif +#if defined (STM32WB35xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ +#define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */ +#define GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00) /*!< JTMS-SWDIO Alternate Function mapping */ +#define GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00) /*!< JTCK-SWCLK Alternate Function mapping */ +#define GPIO_AF0_JTDI ((uint8_t)0x00) /*!< JTDI Alternate Function mapping */ +#define GPIO_AF0_RTC_OUT ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */ +#define GPIO_AF0_JTD_TRACE ((uint8_t)0x00) /*!< JTDO-TRACESWO Alternate Function mapping */ +#define GPIO_AF0_NJTRST ((uint8_t)0x00) /*!< NJTRST Alternate Function mapping */ +#define GPIO_AF0_TRACED0 ((uint8_t)0x00) /*!< TRACED0 Alternate Function mapping */ +#define GPIO_AF0_TRACED1 ((uint8_t)0x00) /*!< TRACED1 Alternate Function mapping */ +#define GPIO_AF0_TRACED2 ((uint8_t)0x00) /*!< TRACED2 Alternate Function mapping */ +#define GPIO_AF0_TRACED3 ((uint8_t)0x00) /*!< TRACED3 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_SPI1 ((uint8_t)0x03) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF3_SPI2 ((uint8_t)0x03) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF4_SPI1 ((uint8_t)0x04) /*!< SPI1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_MCO ((uint8_t)0x06) /*!< MCO Alternate Function mapping */ +#define GPIO_AF6_RF_DTB0 ((uint8_t)0x06) /*!< RF_DTB0 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB1 ((uint8_t)0x06) /*!< RF_DTB1 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB2 ((uint8_t)0x06) /*!< RF_DTB2 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB3 ((uint8_t)0x06) /*!< RF_DTB3 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB4 ((uint8_t)0x06) /*!< RF_DTB4 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB5 ((uint8_t)0x06) /*!< RF_DTB5 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB6 ((uint8_t)0x06) /*!< RF_DTB6 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB7 ((uint8_t)0x06) /*!< RF_DTB7 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB8 ((uint8_t)0x06) /*!< RF_DTB8 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB9 ((uint8_t)0x06) /*!< RF_DTB9 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB10 ((uint8_t)0x06) /*!< RF_DTB10 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB11 ((uint8_t)0x06) /*!< RF_DTB11 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB12 ((uint8_t)0x06) /*!< RF_DTB12 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB13 ((uint8_t)0x06) /*!< RF_DTB13 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB14 ((uint8_t)0x06) /*!< RF_DTB14 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB15 ((uint8_t)0x06) /*!< RF_DTB15 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB16 ((uint8_t)0x06) /*!< RF_DTB16 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB17 ((uint8_t)0x06) /*!< RF_DTB17 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB18 ((uint8_t)0x06) /*!< RF_DTB18 Alternate Function mapping */ +#define GPIO_AF6_RF_MISO ((uint8_t)0x06) /*!< RF_MISO Alternate Function mapping */ +#define GPIO_AF6_RF_MOSI ((uint8_t)0x06) /*!< RF_MOSI Alternate Function mapping */ +#define GPIO_AF6_RF_SCK ((uint8_t)0x06) /*!< RF_SCK Alternate Function mapping */ +#define GPIO_AF6_RF_NSS ((uint8_t)0x06) /*!< RF_NSS Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ + #define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /*!< QUADSPI Alternate Function mapping */ +#define GPIO_AF10_USB ((uint8_t)0x0A) /*!< USB Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /*!< COMP1 Alternate Function mapping */ +#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /*!< COMP2 Alternate Function mapping */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /*!< TIM1 Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0F) && ((AF) != (uint8_t)0x0B) && ((AF) != (uint8_t)0x0D)) + +#endif + +#if defined (STM32WB30xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ +#define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */ +#define GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00) /*!< JTMS-SWDIO Alternate Function mapping */ +#define GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00) /*!< JTCK-SWCLK Alternate Function mapping */ +#define GPIO_AF0_JTDI ((uint8_t)0x00) /*!< JTDI Alternate Function mapping */ +#define GPIO_AF0_RTC_OUT ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */ +#define GPIO_AF0_JTD_TRACE ((uint8_t)0x00) /*!< JTDO-TRACESWO Alternate Function mapping */ +#define GPIO_AF0_NJTRST ((uint8_t)0x00) /*!< NJTRST Alternate Function mapping */ +#define GPIO_AF0_TRACED0 ((uint8_t)0x00) /*!< TRACED0 Alternate Function mapping */ +#define GPIO_AF0_TRACED1 ((uint8_t)0x00) /*!< TRACED1 Alternate Function mapping */ +#define GPIO_AF0_TRACED2 ((uint8_t)0x00) /*!< TRACED2 Alternate Function mapping */ +#define GPIO_AF0_TRACED3 ((uint8_t)0x00) /*!< TRACED3 Alternate Function mapping */ + + /** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF4_SPI1 ((uint8_t)0x04) /*!< SPI1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_MCO ((uint8_t)0x06) /*!< MCO Alternate Function mapping */ +#define GPIO_AF6_RF_DTB0 ((uint8_t)0x06) /*!< RF_DTB0 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB1 ((uint8_t)0x06) /*!< RF_DTB1 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB2 ((uint8_t)0x06) /*!< RF_DTB2 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB3 ((uint8_t)0x06) /*!< RF_DTB3 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB4 ((uint8_t)0x06) /*!< RF_DTB4 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB5 ((uint8_t)0x06) /*!< RF_DTB5 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB6 ((uint8_t)0x06) /*!< RF_DTB6 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB7 ((uint8_t)0x06) /*!< RF_DTB7 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB8 ((uint8_t)0x06) /*!< RF_DTB8 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB9 ((uint8_t)0x06) /*!< RF_DTB9 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB10 ((uint8_t)0x06) /*!< RF_DTB10 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB11 ((uint8_t)0x06) /*!< RF_DTB11 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB12 ((uint8_t)0x06) /*!< RF_DTB12 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB13 ((uint8_t)0x06) /*!< RF_DTB13 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB14 ((uint8_t)0x06) /*!< RF_DTB14 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB15 ((uint8_t)0x06) /*!< RF_DTB15 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB16 ((uint8_t)0x06) /*!< RF_DTB16 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB17 ((uint8_t)0x06) /*!< RF_DTB17 Alternate Function mapping */ +#define GPIO_AF6_RF_DTB18 ((uint8_t)0x06) /*!< RF_DTB18 Alternate Function mapping */ +#define GPIO_AF6_RF_MISO ((uint8_t)0x06) /*!< RF_MISO Alternate Function mapping */ +#define GPIO_AF6_RF_MOSI ((uint8_t)0x06) /*!< RF_MOSI Alternate Function mapping */ +#define GPIO_AF6_RF_SCK ((uint8_t)0x06) /*!< RF_SCK Alternate Function mapping */ +#define GPIO_AF6_RF_NSS ((uint8_t)0x06) /*!< RF_NSS Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /*!< TIM1 Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0F) && ((AF) != (uint8_t)0x0A) && ((AF) != (uint8_t)0x0B) && ((AF) != (uint8_t)0x0D)) + +#endif + /** * @} @@ -380,7 +614,7 @@ /** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index * @{ */ -#if defined (STM32WB55xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ ((__GPIOx__) == (GPIOB))? 1uL :\ ((__GPIOx__) == (GPIOC))? 2uL :\ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2s.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2s.h new file mode 100644 index 0000000000..b1fcb0ab49 --- /dev/null +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2s.h @@ -0,0 +1,546 @@ +/** + ****************************************************************************** + * @file stm32wbxx_hal_i2s.h + * @author MCD Application Team + * @brief Header file of I2S HAL module. + ****************************************************************************** + * @attention + * + *

                                                                                          © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

                                                                                          + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBxx_HAL_I2S_H +#define STM32WBxx_HAL_I2S_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbxx_hal_def.h" + +#if defined(SPI_I2S_SUPPORT) +/** @addtogroup STM32WBxx_HAL_Driver + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Types I2S Exported Types + * @{ + */ + +/** + * @brief I2S Init structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +} I2S_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ + HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ + HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ + HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */ + HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */ +} HAL_I2S_StateTypeDef; + +/** + * @brief I2S handle Structure definition + */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1) +typedef struct __I2S_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +{ + SPI_TypeDef *Instance; /*!< I2S registers base address */ + + I2S_InitTypeDef Init; /*!< I2S communication parameters */ + + uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */ + + __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */ + + __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */ + + uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */ + + __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */ + + __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter + (This field is initialized at the + same value as transfer size at the + beginning of the transfer and + decremented when a sample is received + NbSamplesReceived = RxBufferSize-RxBufferCount) */ + DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */ + + __IO HAL_LockTypeDef Lock; /*!< I2S locking object */ + + __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */ + + __IO uint32_t ErrorCode; /*!< I2S Error code + This parameter can be a value of @ref I2S_Error */ + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */ + void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */ + void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */ + void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */ + void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */ + void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */ + +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} I2S_HandleTypeDef; + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL I2S Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */ + HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */ + HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */ + HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */ + HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */ + HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */ + HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */ + +} HAL_I2S_CallbackIDTypeDef; + +/** + * @brief HAL I2S Callback pointer definition + */ +typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */ + +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_Exported_Constants I2S Exported Constants + * @{ + */ +/** @defgroup I2S_Error I2S Error + * @{ + */ +#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ +#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */ +#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */ +#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */ +#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) +#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup I2S_Mode I2S Mode + * @{ + */ +#define I2S_MODE_SLAVE_TX (0x00000000U) +#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) +#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) +#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)) +/** + * @} + */ + +/** @defgroup I2S_Standard I2S Standard + * @{ + */ +#define I2S_STANDARD_PHILIPS (0x00000000U) +#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) +#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) +#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)) +#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)) +/** + * @} + */ + +/** @defgroup I2S_Data_Format I2S Data Format + * @{ + */ +#define I2S_DATAFORMAT_16B (0x00000000U) +#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) +#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)) +#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)) +/** + * @} + */ + +/** @defgroup I2S_MCLK_Output I2S MCLK Output + * @{ + */ +#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE) +#define I2S_MCLKOUTPUT_DISABLE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2S_Audio_Frequency I2S Audio Frequency + * @{ + */ +#define I2S_AUDIOFREQ_192K (192000U) +#define I2S_AUDIOFREQ_96K (96000U) +#define I2S_AUDIOFREQ_48K (48000U) +#define I2S_AUDIOFREQ_44K (44100U) +#define I2S_AUDIOFREQ_32K (32000U) +#define I2S_AUDIOFREQ_22K (22050U) +#define I2S_AUDIOFREQ_16K (16000U) +#define I2S_AUDIOFREQ_11K (11025U) +#define I2S_AUDIOFREQ_8K (8000U) +#define I2S_AUDIOFREQ_DEFAULT (2U) +/** + * @} + */ + +/** @defgroup I2S_Clock_Polarity I2S Clock Polarity + * @{ + */ +#define I2S_CPOL_LOW (0x00000000U) +#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL) +/** + * @} + */ + +/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition + * @{ + */ +#define I2S_IT_TXE SPI_CR2_TXEIE +#define I2S_IT_RXNE SPI_CR2_RXNEIE +#define I2S_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup I2S_Flags_Definition I2S Flags Definition + * @{ + */ +#define I2S_FLAG_TXE SPI_SR_TXE +#define I2S_FLAG_RXNE SPI_SR_RXNE + +#define I2S_FLAG_UDR SPI_SR_UDR +#define I2S_FLAG_OVR SPI_SR_OVR +#define I2S_FLAG_FRE SPI_SR_FRE + +#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE +#define I2S_FLAG_BSY SPI_SR_BSY + +#define I2S_FLAG_MASK (SPI_SR_RXNE\ + | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup I2S_Exported_macros I2S Exported Macros + * @{ + */ + +/** @brief Reset I2S handle state + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) +#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2S_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SPI peripheral (in I2S mode). + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + +/** @brief Disable the specified SPI peripheral (in I2S mode). + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + +/** @brief Enable the specified I2S interrupts. + * @param __HANDLE__ specifies the I2S Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) + +/** @brief Disable the specified I2S interrupts. + * @param __HANDLE__ specifies the I2S Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) + +/** @brief Checks if the specified I2S interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the I2S Handle. + * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. + * @param __INTERRUPT__ specifies the I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified I2S flag is set or not. + * @param __HANDLE__ specifies the I2S Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2S_FLAG_RXNE: Receive buffer not empty flag + * @arg I2S_FLAG_TXE: Transmit buffer empty flag + * @arg I2S_FLAG_UDR: Underrun flag + * @arg I2S_FLAG_OVR: Overrun flag + * @arg I2S_FLAG_FRE: Frame error flag + * @arg I2S_FLAG_CHSIDE: Channel Side flag + * @arg I2S_FLAG_BSY: Busy flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the I2S OVR pending flag. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \ + __IO uint32_t tmpreg_ovr = 0x00U; \ + tmpreg_ovr = (__HANDLE__)->Instance->DR; \ + tmpreg_ovr = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_ovr); \ + }while(0U) +/** @brief Clears the I2S UDR pending flag. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\ + __IO uint32_t tmpreg_udr = 0x00U;\ + tmpreg_udr = ((__HANDLE__)->Instance->SR);\ + UNUSED(tmpreg_udr); \ + }while(0U) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2S_Exported_Functions + * @{ + */ + +/** @addtogroup I2S_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s); +void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); +void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, + pI2S_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2S_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); + +/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ +void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); +/** + * @} + */ + +/** @addtogroup I2S_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control and State functions ************************************/ +HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2S_Private_Macros I2S Private Macros + * @{ + */ + +/** @brief Check whether the specified SPI flag is set or not. + * @param __SR__ copy of I2S SR regsiter. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2S_FLAG_RXNE: Receive buffer not empty flag + * @arg I2S_FLAG_TXE: Transmit buffer empty flag + * @arg I2S_FLAG_UDR: Underrun error flag + * @arg I2S_FLAG_OVR: Overrun flag + * @arg I2S_FLAG_CHSIDE: Channel side flag + * @arg I2S_FLAG_BSY: Busy flag + * @retval SET or RESET. + */ +#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\ + & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) + +/** @brief Check whether the specified SPI Interrupt is set or not. + * @param __CR2__ copy of I2S CR2 regsiter. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval SET or RESET. + */ +#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks if I2S Mode parameter is in allowed range. + * @param __MODE__ specifies the I2S Mode. + * This parameter can be a value of @ref I2S_Mode + * @retval None + */ +#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ + ((__MODE__) == I2S_MODE_SLAVE_RX) || \ + ((__MODE__) == I2S_MODE_MASTER_TX) || \ + ((__MODE__) == I2S_MODE_MASTER_RX)) + +#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ + ((__STANDARD__) == I2S_STANDARD_MSB) || \ + ((__STANDARD__) == I2S_STANDARD_LSB) || \ + ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \ + ((__STANDARD__) == I2S_STANDARD_PCM_LONG)) + +#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \ + ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \ + ((__FORMAT__) == I2S_DATAFORMAT_24B) || \ + ((__FORMAT__) == I2S_DATAFORMAT_32B)) + +#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \ + ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE)) + +#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \ + ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \ + ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) + +/** @brief Checks if I2S Serial clock steady state parameter is in allowed range. + * @param __CPOL__ specifies the I2S serial clock steady state. + * This parameter can be a value of @ref I2S_Clock_Polarity + * @retval None + */ +#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \ + ((__CPOL__) == I2S_CPOL_HIGH)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SPI_I2S_SUPPORT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBxx_HAL_I2S_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h index 58f0bc39ba..df07fd2fcd 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h @@ -235,12 +235,22 @@ typedef struct * * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1U) ?\ - (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\ - ((((((uint8_t)(__FLAG__)) >> 5U) == 2U)) ?\ - (PWR->SR2 & (1U << ((__FLAG__) & 31U))) :\ - (PWR->EXTSCR & (1U << ((__FLAG__) & 31U))) ) ) - +#define __HAL_PWR_GET_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR1) ? \ + ( \ + PWR->SR1 & (1UL << ((__FLAG__) & 31UL)) \ + ) \ + : \ + ( \ + (((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR2) ? \ + ( \ + PWR->SR2 & (1UL << ((__FLAG__) & 31UL)) \ + ) \ + : \ + ( \ + PWR->EXTSCR & (1UL << ((__FLAG__) & 31UL)) \ + ) \ + ) \ + ) /** @brief Clear a specific PWR flag. * @note Clearing of flags {PWR_FLAG_STOP, PWR_FLAG_SB} @@ -280,13 +290,18 @@ typedef struct * * @retval None */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1U) ?\ - ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\ - (PWR->SCR = (__FLAG__)) : (PWR->SCR = (1U << ((__FLAG__) & 31U))) ) :\ - ( (((uint8_t)(__FLAG__)) == PWR_FLAG_CRITICAL_RF_PHASE) ?\ - SET_BIT (PWR->EXTSCR, PWR_EXTSCR_CCRPF) : ( ((((uint8_t)((__FLAG__)) & 31U) <= PWR_EXTSCR_C1STOPF_Pos) ?\ - SET_BIT (PWR->EXTSCR, PWR_EXTSCR_C1CSSF): SET_BIT (PWR->EXTSCR, PWR_EXTSCR_C2CSSF)) ) )) - +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_EXTSCR) ? \ + ( \ + PWR->EXTSCR = (1UL << (((__FLAG__) & PWR_FLAG_EXTSCR_CLR_MASK) >> PWR_FLAG_EXTSCR_CLR_POS)) \ + ) \ + : \ + ( \ + (((__FLAG__)) == PWR_FLAG_WU) ? \ + (PWR->SCR = PWR_SCR_CWUF) : \ + (PWR->SCR = (1UL << ((__FLAG__) & 31UL))) \ + ) \ + ) + /** * @brief Enable the PVD Extended Interrupt C1 Line. * @retval None diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr_ex.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr_ex.h index b7367f4e60..612cfa28cb 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr_ex.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr_ex.h @@ -323,62 +323,62 @@ typedef struct * - XX : Status register (2 bits) * - 01: SR1 register * - 10: SR2 register - * - 11: C2_SCR register + * - 11: EXTSCR register * The only exception is PWR_FLAG_WUF, encompassing all * wake-up flags and set to PWR_SR1_WUF. * @{ */ /*--------------------------------SR1-------------------------------*/ -#define PWR_FLAG_WUF1 (0x0020U) /*!< Wakeup event on wakeup pin 1 */ +#define PWR_FLAG_WUF1 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF1_Pos) /*!< Wakeup event on wakeup pin 1 */ #if defined(PWR_CR3_EWUP2) -#define PWR_FLAG_WUF2 (0x0021U) /*!< Wakeup event on wakeup pin 2 */ +#define PWR_FLAG_WUF2 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF2_Pos) /*!< Wakeup event on wakeup pin 2 */ #endif #if defined(PWR_CR3_EWUP3) -#define PWR_FLAG_WUF3 (0x0022U) /*!< Wakeup event on wakeup pin 3 */ +#define PWR_FLAG_WUF3 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF3_Pos) /*!< Wakeup event on wakeup pin 3 */ #endif -#define PWR_FLAG_WUF4 (0x0023U) /*!< Wakeup event on wakeup pin 4 */ +#define PWR_FLAG_WUF4 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF4_Pos) /*!< Wakeup event on wakeup pin 4 */ #if defined(PWR_CR3_EWUP5) -#define PWR_FLAG_WUF5 (0x0024U) /*!< Wakeup event on wakeup pin 5 */ +#define PWR_FLAG_WUF5 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF5_Pos) /*!< Wakeup event on wakeup pin 5 */ #endif -#define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */ +#define PWR_FLAG_WU (PWR_FLAG_REG_SR1 | PWR_SR1_WUF) /*!< Encompass wakeup event on all wakeup pins */ #if defined(PWR_CR5_SMPSEN) -#define PWR_FLAG_FRCBYPI (0x0027U) /*!< SMPS Forced in Bypass Interrupt Flag */ +#define PWR_FLAG_FRCBYPI (PWR_FLAG_REG_SR1 | PWR_SR1_SMPSFBF_Pos) /*!< SMPS Forced in Bypass Interrupt Flag */ #endif -#define PWR_FLAG_BHWF (0x0029U) /*!< BLE_Host WakeUp Flag */ -#define PWR_FLAG_RFPHASEI (0x002BU) /*!< Radio Phase Interrupt Flag */ -#define PWR_FLAG_BLEACTI (0x002CU) /*!< BLE Activity Interrupt Flag */ -#define PWR_FLAG_802ACTI (0x002DU) /*!< 802.15.4 Activity Interrupt Flag */ -#define PWR_FLAG_HOLDC2I (0x002EU) /*!< CPU2 on-Hold Interrupt Flag */ -#define PWR_FLAG_WUFI (0x002FU) /*!< Wakeup on internal wakeup line */ +#define PWR_FLAG_BHWF (PWR_FLAG_REG_SR1 | PWR_SR1_BLEWUF_Pos) /*!< BLE_Host WakeUp Flag */ +#define PWR_FLAG_RFPHASEI (PWR_FLAG_REG_SR1 | PWR_SR1_CRPEF_Pos) /*!< Radio Phase Interrupt Flag */ +#define PWR_FLAG_BLEACTI (PWR_FLAG_REG_SR1 | PWR_SR1_BLEAF_Pos) /*!< BLE Activity Interrupt Flag */ +#define PWR_FLAG_802ACTI (PWR_FLAG_REG_SR1 | PWR_SR1_802AF_Pos) /*!< 802.15.4 Activity Interrupt Flag */ +#define PWR_FLAG_HOLDC2I (PWR_FLAG_REG_SR1 | PWR_SR1_C2HF_Pos) /*!< CPU2 on-Hold Interrupt Flag */ +#define PWR_FLAG_WUFI (PWR_FLAG_REG_SR1 | PWR_SR1_WUFI_Pos) /*!< Wakeup on internal wakeup line */ /*--------------------------------SR2-------------------------------*/ #if defined(PWR_CR5_SMPSEN) -#define PWR_FLAG_SMPSRDYF (0x0040U) /*!< SMPS Ready Flag */ -#define PWR_FLAG_SMPSBYPF (0x0041U) /*!< SMPS Bypass Flag */ +#define PWR_FLAG_SMPSRDYF (PWR_FLAG_REG_SR2 | PWR_SR2_SMPSBF_Pos) /*!< SMPS Ready Flag */ +#define PWR_FLAG_SMPSBYPF (PWR_FLAG_REG_SR2 | PWR_SR2_SMPSF_Pos) /*!< SMPS Bypass Flag */ #endif -#define PWR_FLAG_REGLPS (0x0048U) /*!< Low-power regulator start flag */ -#define PWR_FLAG_REGLPF (0x0049U) /*!< Low-power regulator flag */ +#define PWR_FLAG_REGLPS (PWR_FLAG_REG_SR2 | PWR_SR2_REGLPS_Pos) /*!< Low-power regulator start flag */ +#define PWR_FLAG_REGLPF (PWR_FLAG_REG_SR2 | PWR_SR2_REGLPF_Pos) /*!< Low-power regulator flag */ #if defined(PWR_CR1_VOS) -#define PWR_FLAG_VOSF (0x004AU) /*!< Voltage scaling flag */ +#define PWR_FLAG_VOSF (PWR_FLAG_REG_SR2 | PWR_SR2_VOSF_Pos) /*!< Voltage scaling flag */ #endif -#define PWR_FLAG_PVDO (0x004BU) /*!< Power Voltage Detector output flag */ +#define PWR_FLAG_PVDO (PWR_FLAG_REG_SR2 | PWR_SR2_PVDO_Pos) /*!< Power Voltage Detector output flag */ -#define PWR_FLAG_PVMO1 (0x004CU) /*!< Power Voltage Monitoring 1 output flag */ -#define PWR_FLAG_PVMO3 (0x004EU) /*!< Power Voltage Monitoring 3 output flag */ +#define PWR_FLAG_PVMO1 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO1_Pos) /*!< Power Voltage Monitoring 1 output flag */ +#define PWR_FLAG_PVMO3 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO3_Pos) /*!< Power Voltage Monitoring 3 output flag */ /*------------------------------EXTSCR---------------------------*/ -#define PWR_FLAG_SB (0x0068U) /*!< System Standby flag for CPU1 */ -#define PWR_FLAG_STOP (0x0069U) /*!< System Stop flag for CPU1 */ +#define PWR_FLAG_SB (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1SBF_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Standby flag for CPU1 */ +#define PWR_FLAG_STOP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1STOPF_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop flag for CPU1 */ -#define PWR_FLAG_C2SB (0x006AU) /*!< System Standby flag for CPU2 */ -#define PWR_FLAG_C2STOP (0x006BU) /*!< System Stop flag for CPU2 */ +#define PWR_FLAG_C2SB (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2SBF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Standby flag for CPU2 */ +#define PWR_FLAG_C2STOP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2STOPF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop flag for CPU2 */ -#define PWR_FLAG_CRITICAL_RF_PHASE (0x006DU) /*!< Critical radio system phase flag */ -#define PWR_FLAG_C1DEEPSLEEP (0x006EU) /*!< CPU1 DeepSleep Flag */ -#define PWR_FLAG_C2DEEPSLEEP (0x006FU) /*!< CPU2 DeepSleep Flag */ +#define PWR_FLAG_CRITICAL_RF_PHASE (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_CRPF_Pos | (PWR_EXTSCR_CCRPF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< Critical radio system phase flag */ +#define PWR_FLAG_C1DEEPSLEEP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1DS_Pos) /*!< CPU1 DeepSleep Flag */ +#define PWR_FLAG_C2DEEPSLEEP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2DS_Pos) /*!< CPU2 DeepSleep Flag */ /** * @} */ @@ -436,6 +436,19 @@ typedef struct * @} */ +/** @defgroup PWR_FLAG_REG PWR flag register + * @{ + */ +#define PWR_FLAG_REG_SR1 (0x20UL) /* Bitfield to indicate PWR flag located in register PWR_SR1 */ +#define PWR_FLAG_REG_SR2 (0x40UL) /* Bitfield to indicate PWR flag located in register PWR_SR2 */ +#define PWR_FLAG_REG_EXTSCR (0x60UL) /* Bitfield to indicate PWR flag located in register PWR_EXTSCR */ +#define PWR_FLAG_REG_MASK (PWR_FLAG_REG_SR1 | PWR_FLAG_REG_SR2 | PWR_FLAG_REG_EXTSCR) /* Bitfield mask to indicate PWR flag location in PWR register */ +#define PWR_FLAG_EXTSCR_CLR_POS (16UL) /* Bitfield for register PWR_EXTSCR clearable bits positions: position of bitfield in flag literals */ +#define PWR_FLAG_EXTSCR_CLR_MASK ((PWR_EXTSCR_C1CSSF_Pos | PWR_EXTSCR_C2CSSF_Pos | PWR_EXTSCR_CCRPF_Pos) << PWR_FLAG_EXTSCR_CLR_POS) /* Bitfield for register PWR_EXTSCR clearable bits positions: mask of bitfield in flag literals */ +/** + * @} + */ + /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc.h index 36c647b0d4..1643d2ffee 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc.h @@ -120,9 +120,9 @@ extern "C" { #if defined(SAI1) #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_ADCCLK) == RCC_PLLSAI1_ADCCLK) || \ - (((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ - (((__VALUE__) & RCC_PLLSAI1_USBCLK) == RCC_PLLSAI1_USBCLK)) && \ - (((__VALUE__) & ~(RCC_PLLSAI1_ADCCLK|RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_USBCLK)) == 0U)) + (((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ + (((__VALUE__) & RCC_PLLSAI1_USBCLK) == RCC_PLLSAI1_USBCLK)) && \ + (((__VALUE__) & ~(RCC_PLLSAI1_ADCCLK | RCC_PLLSAI1_SAI1CLK | RCC_PLLSAI1_USBCLK)) == 0U)) #endif #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ ((__RANGE__) == RCC_MSIRANGE_1) || \ @@ -164,7 +164,14 @@ extern "C" { ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) -#define IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) || ((__MCOX__) == RCC_MCO3) ) +#if defined(RCC_MCO3_SUPPORT) +#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1) || \ + ((__MCOX__) == RCC_MCO2) || \ + ((__MCOX__) == RCC_MCO3)) +#else +#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1) || \ + ((__MCOX__) == RCC_MCO2)) +#endif #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ @@ -510,6 +517,9 @@ typedef struct #define RCC_PLL_SAI1CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI1CLK selection from main PLL */ #endif #define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */ +#if defined(SPI_I2S_SUPPORT) +#define RCC_PLL_I2SCLK RCC_PLLCFGR_PLLPEN /*!< PLLI2SCLK selection from main PLL */ +#endif /** * @} */ @@ -629,7 +639,9 @@ typedef struct */ #define RCC_MCO1 0x00000000U /*!< MCO1 index */ #define RCC_MCO2 0x00000001U /*!< MCO2 index */ +#if defined(RCC_MCO3_SUPPORT) #define RCC_MCO3 0x00000002U /*!< MCO3 index */ +#endif #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 1 MCO*/ /** @@ -729,7 +741,9 @@ typedef struct #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ +#if defined(SAI1) #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ +#endif /* Flags in the BDCR register */ #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ @@ -1216,7 +1230,7 @@ typedef struct #define __HAL_RCC_C2GPIOE_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) #define __HAL_RCC_C2GPIOH_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) #define __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_ADC) -#if defined(GPIOD) +#if defined(AES1) #define __HAL_RCC_C2AES1_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_AES1) #endif @@ -2921,6 +2935,7 @@ typedef struct * @arg @ref RCC_PLL_USBCLK This Clock is used to generate the clock for the USB FS (48 MHz) * @arg @ref RCC_PLL_RNGCLK This clock is used to generate the clock for RNG * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 64MHz) + * @arg @ref RCC_PLL_I2SCLK This Clock is used to generate the clock for the I2S * @retval None */ #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc_ex.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc_ex.h index 230929ec61..789a28856a 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc_ex.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc_ex.h @@ -59,7 +59,14 @@ extern "C" { /** @addtogroup RCCEx_Private_Macros * @{ */ -#define IS_RCC_LSCO(__LSCOX__) ( ((__LSCOX__) == RCC_LSCO1) || ((__LSCOX__) == RCC_LSCO2) || ((__LSCOX__) == RCC_LSCO3) ) +#if defined(RCC_LSCO3_SUPPORT) +#define IS_RCC_LSCO(__LSCOX__) (((__LSCOX__) == RCC_LSCO1) || \ + ((__LSCOX__) == RCC_LSCO2) || \ + ((__LSCOX__) == RCC_LSCO3)) +#else +#define IS_RCC_LSCO(__LSCOX__) (((__LSCOX__) == RCC_LSCO1) || \ + ((__LSCOX__) == RCC_LSCO2)) +#endif #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) @@ -67,8 +74,8 @@ extern "C" { #if defined(LPUART1) && defined(I2C3) && defined(SAI1) && defined(USB) && defined(RCC_SMPS_SUPPORT) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ @@ -79,10 +86,25 @@ extern "C" { (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \ (((__SELECTION__) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS)) +#elif defined(LPUART1) && defined(USB) && defined(RCC_SMPS_SUPPORT) && defined(SPI_I2S_SUPPORT) +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \ + (((__SELECTION__) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)) #else #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ @@ -118,9 +140,9 @@ extern "C" { #endif #if defined(SAI1) -#define IS_RCC_SAI1CLK(__SOURCE__) \ +#define IS_RCC_SAI1CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) #endif @@ -145,6 +167,7 @@ extern "C" { ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE)) +#if defined(USB) #if defined(SAI1) #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ @@ -157,17 +180,24 @@ extern "C" { ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) #endif +#endif -#if defined(SAI1) +#if defined(STM32WB55xx) || defined (STM32WB5Mxx) #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ + (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) +#elif defined(STM32WB35xx) +#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) #else #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) #endif @@ -190,6 +220,14 @@ extern "C" { ((__SOURCE__) == RCC_SMPSCLKSOURCE_HSE)) #endif +#if defined(SPI_I2S_SUPPORT) +#define IS_RCC_I2SCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2SCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_I2SCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2SCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_I2SCLKSOURCE_PIN)) +#endif + #if defined(SAI1) #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U)) @@ -299,8 +337,10 @@ typedef struct This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ #endif +#if defined(USB) uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG). This parameter can be a value of @ref RCCEx_USB_Clock_Source */ +#endif uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB). This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ @@ -322,6 +362,11 @@ typedef struct uint32_t SmpsDivSelection; /*!< Specifies SMPS clock division factor. This parameter can be a value of @ref RCCEx_SMPS_Clock_Divider */ #endif + +#if defined(SPI_I2S_SUPPORT) + uint32_t I2sClockSelection; /*!< Specifies I2s clock source. + This parameter can be a value of @ref RCCEx_I2s_Clock_Source */ +#endif } RCC_PeriphCLKInitTypeDef; @@ -389,7 +434,9 @@ typedef struct */ #define RCC_LSCO1 0x00000000U /*!< LSCO1 index */ #define RCC_LSCO2 0x00000001U /*!< LSCO2 index */ +#if defined(RCC_LSCO3_SUPPORT) #define RCC_LSCO3 0x00000002U /*!< LSCO3 index */ +#endif /** * @} */ @@ -421,7 +468,9 @@ typedef struct #define RCC_PERIPHCLK_SAI1 0x00000040U /*!< SAI1 Peripheral Clock Selection */ #endif #define RCC_PERIPHCLK_CLK48SEL 0x00000100U /*!< 48 MHz clock source selection */ +#if defined(USB) #define RCC_PERIPHCLK_USB RCC_PERIPHCLK_CLK48SEL /*!< USB Peripheral Clock Selection */ +#endif #define RCC_PERIPHCLK_RNG 0x00000200U /*!< RNG Peripheral Clock Selection */ #define RCC_PERIPHCLK_ADC 0x00000400U /*!< ADC Peripheral Clock Selection */ #define RCC_PERIPHCLK_RTC 0x00000800U /*!< RTC Peripheral Clock Selection */ @@ -429,6 +478,9 @@ typedef struct #if defined(RCC_SMPS_SUPPORT) #define RCC_PERIPHCLK_SMPS 0x00002000U /*!< SMPS Peripheral Clock Selection */ #endif +#if defined(SPI_I2S_SUPPORT) +#define RCC_PERIPHCLK_I2S 0x00004000U /*!< I2S Peripheral Clock Selection */ +#endif /** * @} */ @@ -527,24 +579,30 @@ typedef struct * @} */ +#if defined(USB) /** @defgroup RCCEx_USB_Clock_Source USB Clock Source * @{ */ #define RCC_USBCLKSOURCE_HSI48 LL_RCC_USB_CLKSOURCE_HSI48 /*!< HSI48 clock selected as USB clock */ +#if defined(SAI1) #define RCC_USBCLKSOURCE_PLLSAI1 LL_RCC_USB_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "Q" clock selected as USB clock */ +#endif #define RCC_USBCLKSOURCE_PLL LL_RCC_USB_CLKSOURCE_PLL /*!< PLL "Q" clock selected as USB clock */ #define RCC_USBCLKSOURCE_MSI LL_RCC_USB_CLKSOURCE_MSI /*!< MSI clock selected as USB clock */ /** * @} */ +#endif /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source * @{ */ #define RCC_ADCCLKSOURCE_NONE LL_RCC_ADC_CLKSOURCE_NONE /*!< None clock selected as ADC clock */ -#if defined(SAI1) +#if defined(STM32WB55xx) || defined (STM32WB5Mxx) #define RCC_ADCCLKSOURCE_PLLSAI1 LL_RCC_ADC_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "R" clock selected as ADC clock */ +#elif defined(STM32WB35xx) +#define RCC_ADCCLKSOURCE_HSI LL_RCC_ADC_CLKSOURCE_HSI /*!< HSI clock selected as ADC clock */ #endif #define RCC_ADCCLKSOURCE_PLL LL_RCC_ADC_CLKSOURCE_PLL /*!< PLL "P" clock selected as ADC clock */ #define RCC_ADCCLKSOURCE_SYSCLK LL_RCC_ADC_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as ADC clock */ @@ -611,6 +669,19 @@ typedef struct */ #endif +#if defined(SPI_I2S_SUPPORT) +/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source + * @{ + */ +#define RCC_I2SCLKSOURCE_NONE LL_RCC_I2S_CLKSOURCE_NONE /*!< No clock selected as I2S clock */ +#define RCC_I2SCLKSOURCE_PLL LL_RCC_I2S_CLKSOURCE_PLL /*!< PLL "Q" clock selected as I2S clock source */ +#define RCC_I2SCLKSOURCE_HSI LL_RCC_I2S_CLKSOURCE_HSI /*!< HSI clock selected as I2S clock */ +#define RCC_I2SCLKSOURCE_PIN LL_RCC_I2S_CLKSOURCE_PIN /*!< External clock selected as I2S clock */ +/** + * @} + */ +#endif + /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line * @{ */ @@ -1068,20 +1139,20 @@ typedef struct * @arg @ref RCC_RNGCLKSOURCE_LSE LSE clock selected as RNG clock * @retval None */ -#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ - do { \ - if (((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSI) \ +#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ + do { \ + if (((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSI) \ || ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSE) \ || ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_CLK48)) \ - { \ + { \ LL_RCC_SetRNGClockSource((__RNG_CLKSOURCE__)); \ - } \ - else \ - { \ + } \ + else \ + { \ uint32_t tmp = (__RNG_CLKSOURCE__) &(~CLK48_MASK); \ - LL_RCC_SetRNGClockSource(RCC_RNGCLKSOURCE_CLK48); \ + LL_RCC_SetRNGClockSource(RCC_RNGCLKSOURCE_CLK48); \ LL_RCC_SetCLK48ClockSource(tmp); \ - } \ + } \ } while(0U) /** @brief Macro to get the direct RNG clock. @@ -1094,6 +1165,7 @@ typedef struct */ #define __HAL_RCC_GET_RNG_SOURCE() LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE) +#if defined(USB) /** @brief Macro to configure the USB clock (USBCLK). * * @note USB and RNG peripherals share the same 48MHz clock source. @@ -1116,14 +1188,17 @@ typedef struct * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock */ #define __HAL_RCC_GET_USB_SOURCE() LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE) +#endif /** @brief Macro to configure the ADC interface clock. * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. * This parameter can be one of the following values: * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock - * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock (*) * @arg @ref RCC_ADCCLKSOURCE_PLL PLL Clock selected as ADC clock * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock (*) + * @note (*) Value not defined for all devices * @retval None */ #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) LL_RCC_SetADCClockSource(__ADC_CLKSOURCE__) @@ -1131,9 +1206,11 @@ typedef struct /** @brief Macro to get the ADC clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock - * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock (*) * @arg @ref RCC_ADCCLKSOURCE_PLL PLL Clock selected as ADC clock * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock (*) + * @note (*) Value not defined for all devices */ #define __HAL_RCC_GET_ADC_SOURCE() LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE) @@ -1217,6 +1294,28 @@ typedef struct * @{ */ +#if defined(SPI_I2S_SUPPORT) +/** @brief Macro to configure the I2S clock (I2SCLK). + * @param __I2S_CLKSOURCE__ specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2SCLKSOURCE_NONE No clock selected as I2S clock + * @arg @ref RCC_I2SCLKSOURCE_PLL PLL "Q" selected as I2S clock + * @arg @ref RCC_I2SCLKSOURCE_HSI HSI selected as I2S clock + * @arg @ref RCC_I2SCLKSOURCE_PIN External clock selected as I2S clock + * @retval None + */ +#define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__) LL_RCC_SetI2SClockSource(__I2S_CLKSOURCE__) + +/** @brief Macro to get the I2S clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2SCLKSOURCE_NONE No clock selected as I2S clock + * @arg @ref RCC_I2SCLKSOURCE_PLL PLL "Q" selected as I2S clock + * @arg @ref RCC_I2SCLKSOURCE_HSI HSI selected as I2S clock + * @arg @ref RCC_I2SCLKSOURCE_PIN External clock selected as I2S clock + */ +#define __HAL_RCC_GET_I2S_SOURCE() LL_RCC_GetI2SClockSource(LL_RCC_I2S_CLKSOURCE) +#endif + #if defined(SAI1) /** @brief Enable PLLSAI1RDY interrupt. * @retval None diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h index ce4b09ee43..bf05e3bde5 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h @@ -523,6 +523,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ @@ -1312,6 +1321,31 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) + /** * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. @@ -1331,6 +1365,8 @@ mode. /** * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. * @param __HANDLE__ TIM handle. * @param __COUNTER__ specifies the Counter register new value. * @retval None @@ -1640,29 +1676,29 @@ mode. ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) -#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ - ((__BASE__) == TIM_DMABASE_CR2) || \ - ((__BASE__) == TIM_DMABASE_SMCR) || \ - ((__BASE__) == TIM_DMABASE_DIER) || \ - ((__BASE__) == TIM_DMABASE_SR) || \ - ((__BASE__) == TIM_DMABASE_EGR) || \ - ((__BASE__) == TIM_DMABASE_CCMR1) || \ - ((__BASE__) == TIM_DMABASE_CCMR2) || \ - ((__BASE__) == TIM_DMABASE_CCER) || \ - ((__BASE__) == TIM_DMABASE_CNT) || \ - ((__BASE__) == TIM_DMABASE_PSC) || \ - ((__BASE__) == TIM_DMABASE_ARR) || \ - ((__BASE__) == TIM_DMABASE_RCR) || \ - ((__BASE__) == TIM_DMABASE_CCR1) || \ - ((__BASE__) == TIM_DMABASE_CCR2) || \ - ((__BASE__) == TIM_DMABASE_CCR3) || \ - ((__BASE__) == TIM_DMABASE_CCR4) || \ - ((__BASE__) == TIM_DMABASE_BDTR) || \ - ((__BASE__) == TIM_DMABASE_OR) || \ - ((__BASE__) == TIM_DMABASE_CCMR3) || \ - ((__BASE__) == TIM_DMABASE_CCR5) || \ - ((__BASE__) == TIM_DMABASE_CCR6) || \ - ((__BASE__) == TIM_DMABASE_AF1) || \ +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_OR) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6) || \ + ((__BASE__) == TIM_DMABASE_AF1) || \ ((__BASE__) == TIM_DMABASE_AF2)) #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) @@ -1673,6 +1709,9 @@ mode. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENALE)) + #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h index e11d35cf8b..4fbb1fd39b 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h @@ -1272,7 +1272,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT (4) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) * @@ -1466,7 +1466,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT (4) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) * @@ -2340,9 +2340,12 @@ __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: - * - Do not use with interruption or DMA since these modes - * have to clear immediately the EOC flag to free the - * IRQ vector sequencer. + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and @@ -2393,9 +2396,12 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: - * - Do not use with interruption or DMA since these modes - * have to clear immediately the EOC flag to free the - * IRQ vector sequencer. + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and @@ -2549,7 +2555,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT (4) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) * @@ -3126,7 +3132,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT (4) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) * @@ -3621,7 +3627,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT (4) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) * @arg @ref LL_ADC_CHANNEL_VBAT (4) * diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_comp.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_comp.h index 49d720eb8c..4348e8c494 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_comp.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_comp.h @@ -293,7 +293,7 @@ typedef struct /** * @brief Set window mode of a pair of comparators instances - * (2 consecutive COMP instances odd and even COMP and COMP). + * (2 consecutive COMP instances COMP and COMP). * @rmtoll CSR WINMODE LL_COMP_SetCommonWindowMode * @param COMPxy_COMMON Comparator common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() ) @@ -311,7 +311,7 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COM /** * @brief Get window mode of a pair of comparators instances - * (2 consecutive COMP instances odd and even COMP and COMP). + * (2 consecutive COMP instances COMP and COMP). * @rmtoll CSR WINMODE LL_COMP_GetCommonWindowMode * @param COMPxy_COMMON Comparator common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() ) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_exti.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_exti.h index d2ef804247..7f9f596411 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_exti.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_exti.h @@ -107,16 +107,26 @@ typedef struct #define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ #define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ #define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ #define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ +#endif #define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ +#endif #define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ #define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ +#endif #define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ #define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ +#endif + +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) #define LL_EXTI_LINE_ALL_0_31 (LL_EXTI_LINE_0 | LL_EXTI_LINE_1 | LL_EXTI_LINE_2 | \ LL_EXTI_LINE_3 | LL_EXTI_LINE_4 | LL_EXTI_LINE_5 | \ LL_EXTI_LINE_6 | LL_EXTI_LINE_7 | LL_EXTI_LINE_8 | \ @@ -127,6 +137,16 @@ typedef struct LL_EXTI_LINE_21 | LL_EXTI_LINE_22 | LL_EXTI_LINE_23 | \ LL_EXTI_LINE_24 | LL_EXTI_LINE_25 | LL_EXTI_LINE_28 | \ LL_EXTI_LINE_29 | LL_EXTI_LINE_30 | LL_EXTI_LINE_31) /*!< All Extended line not reserved*/ +#else +#define LL_EXTI_LINE_ALL_0_31 (LL_EXTI_LINE_0 | LL_EXTI_LINE_1 | LL_EXTI_LINE_2 | \ + LL_EXTI_LINE_3 | LL_EXTI_LINE_4 | LL_EXTI_LINE_5 | \ + LL_EXTI_LINE_6 | LL_EXTI_LINE_7 | LL_EXTI_LINE_8 | \ + LL_EXTI_LINE_9 | LL_EXTI_LINE_10 | LL_EXTI_LINE_11 | \ + LL_EXTI_LINE_12 | LL_EXTI_LINE_13 | LL_EXTI_LINE_14 | \ + LL_EXTI_LINE_15 | LL_EXTI_LINE_16 | LL_EXTI_LINE_17 | \ + LL_EXTI_LINE_18 | LL_EXTI_LINE_19 | LL_EXTI_LINE_22 | \ + LL_EXTI_LINE_24 | LL_EXTI_LINE_29 | LL_EXTI_LINE_30) /*!< All Extended line not reserved*/ +#endif #define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ #define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ @@ -136,14 +156,14 @@ typedef struct #define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ #define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */ #define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */ -#if defined (STM32WB55xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) #define LL_EXTI_LINE_43 EXTI_IMR2_IM43 /*!< Extended line 43 */ #endif #define LL_EXTI_LINE_44 EXTI_IMR2_IM44 /*!< Extended line 44 */ #define LL_EXTI_LINE_45 EXTI_IMR2_IM45 /*!< Extended line 45 */ #define LL_EXTI_LINE_46 EXTI_IMR2_IM46 /*!< Extended line 46 */ #define LL_EXTI_LINE_48 EXTI_IMR2_IM48 /*!< Extended line 48 */ -#if defined (STM32WB55xx) +#if defined (STM32WB55xx) || defined (STM32WB5Mxx) #define LL_EXTI_LINE_ALL_32_63 (LL_EXTI_LINE_33 | LL_EXTI_LINE_36 | LL_EXTI_LINE_37 | \ LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | LL_EXTI_LINE_40 | \ LL_EXTI_LINE_41 | LL_EXTI_LINE_42 | LL_EXTI_LINE_43 | \ @@ -243,7 +263,7 @@ typedef struct /** * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -264,17 +284,18 @@ typedef struct * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_23 (*) * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_28 (*) * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_31 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) @@ -285,7 +306,7 @@ __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) /** * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2 * @rmtoll C2IMR1 IMx LL_C2_EXTI_EnableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -306,17 +327,18 @@ __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_23 (*) * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_28 (*) * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_31 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine) @@ -327,7 +349,7 @@ __STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine) /** * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 @@ -353,7 +375,7 @@ __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) /** * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2 * @rmtoll C2IMR2 IMx LL_C2_EXTI_EnableIT_32_63 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 @@ -379,7 +401,7 @@ __STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine) /** * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -400,17 +422,18 @@ __STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_23 (*) * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_28 (*) * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_31 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) @@ -421,7 +444,7 @@ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) /** * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2 * @rmtoll C2IMR1 IMx LL_C2_EXTI_DisableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -442,17 +465,18 @@ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_23 (*) * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_28 (*) * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_31 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine) @@ -463,7 +487,7 @@ __STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine) /** * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 @@ -489,7 +513,7 @@ __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) /** * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2 * @rmtoll C2IMR2 IMx LL_C2_EXTI_DisableIT_32_63 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 @@ -515,7 +539,7 @@ __STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine) /** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -536,17 +560,18 @@ __STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_23 (*) * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_28 (*) * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_31 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 + * (*) value not defined in all devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) @@ -557,7 +582,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) /** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2 * @rmtoll C2IMR1 IMx LL_C2_EXTI_IsEnabledIT_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -578,17 +603,18 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_23 (*) * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_25 (*) + * @arg @ref LL_EXTI_LINE_28 (*) * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_31 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 + * (*) value not defined in all devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) @@ -599,7 +625,7 @@ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) /** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 @@ -625,7 +651,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) /** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2 * @rmtoll C2IMR2 IMx LL_C2_EXTI_IsEnabledIT_32_63 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 @@ -659,7 +685,7 @@ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) /** * @brief Enable ExtiLine Event request for Lines in range 0 to 31 * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -679,9 +705,9 @@ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) @@ -692,7 +718,7 @@ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) /** * @brief Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2 * @rmtoll C2EMR1 EMx LL_C2_EXTI_EnableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -712,9 +738,9 @@ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine) @@ -728,7 +754,6 @@ __STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 - * @arg @ref LL_EXTI_LINE_ALL_32_63 * @retval None */ __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) @@ -742,7 +767,6 @@ __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 - * @arg @ref LL_EXTI_LINE_ALL_32_63 * @retval None */ __STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine) @@ -753,7 +777,7 @@ __STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine) /** * @brief Disable ExtiLine Event request for Lines in range 0 to 31 * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -773,9 +797,8 @@ __STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) * @retval None */ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) @@ -786,7 +809,7 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) /** * @brief Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2 * @rmtoll C2EMR1 EMx LL_C2_EXTI_DisableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -806,9 +829,9 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine) @@ -822,7 +845,7 @@ __STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 - * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) @@ -836,7 +859,6 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 - * @arg @ref LL_EXTI_LINE_ALL_32_63 * @retval None */ __STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine) @@ -847,7 +869,7 @@ __STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine) /** * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -867,9 +889,9 @@ __STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * (*) value not defined in all devices * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -881,7 +903,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) /** * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2 * @rmtoll C2EMR1 EMx LL_C2_EXTI_IsEnabledEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: + * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 @@ -901,9 +923,9 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * (*) value not defined in all devices * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -918,7 +940,6 @@ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 - * @arg @ref LL_EXTI_LINE_ALL_32_63 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) @@ -932,7 +953,6 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 - * @arg @ref LL_EXTI_LINE_ALL_32_63 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) @@ -979,9 +999,10 @@ __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) @@ -1000,9 +1021,10 @@ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) * condition. * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) @@ -1041,9 +1063,10 @@ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) @@ -1063,9 +1086,10 @@ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) * condition. * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) @@ -1097,9 +1121,10 @@ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) @@ -1111,9 +1136,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63 * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) @@ -1160,9 +1186,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1182,9 +1209,10 @@ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) * condition. * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) @@ -1222,9 +1250,10 @@ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1243,9 +1272,10 @@ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) * In this case, both generate a trigger condition. * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) @@ -1277,9 +1307,10 @@ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -1292,7 +1323,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63 * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 * @retval State of bit (1 or 0). @@ -1339,9 +1370,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1359,9 +1391,10 @@ __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) * register (by writing a 1 into the bit) * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) @@ -1403,9 +1436,10 @@ __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) @@ -1419,9 +1453,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) * line. This bit is cleared by writing a 1 to the bit. * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) @@ -1455,9 +1490,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @retval @note This bit is set when the selected edge event arrives on the interrupt */ __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) @@ -1471,9 +1507,10 @@ __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) * line. This bit is cleared by writing a 1 to the bit. * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval @note This bit is set when the selected edge event arrives on the interrupt */ __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine) @@ -1507,9 +1544,10 @@ __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_20 (*) + * @arg @ref LL_EXTI_LINE_21 (*) + * @arg @ref LL_EXTI_LINE_31 (*) + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) @@ -1523,9 +1561,10 @@ __STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) * line. This bit is cleared by writing a 1 to the bit. * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63 * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_33 (*) * @arg @ref LL_EXTI_LINE_40 * @arg @ref LL_EXTI_LINE_41 + * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lptim.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lptim.h index 5a0e723846..fdc820bec5 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lptim.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_lptim.h @@ -370,7 +370,7 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); } /** @@ -423,7 +423,7 @@ __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL)); } /** @@ -690,8 +690,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) /** * @brief Set LPTIM input 1 source (default GPIO). - * @rmtoll OR OR_0 LL_LPTIM_SetInput1Src - * @rmtoll OR OR_1 LL_LPTIM_SetInput1Src + * @rmtoll OR OR LL_LPTIM_SetInput1Src * @param LPTIMx Low-Power Timer instance * @param Src This parameter can be one of the following values: * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO @@ -702,12 +701,12 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) { - WRITE_REG(LPTIMx->OR, Src); + MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src); } /** * @brief Set LPTIM input 2 source (default GPIO). - * @rmtoll OR OR_0 LL_LPTIM_SetInput2Src + * @rmtoll OR OR LL_LPTIM_SetInput2Src * @param LPTIMx Low-Power Timer instance * @param Src This parameter can be one of the following values: * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO @@ -716,7 +715,7 @@ __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) */ __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) { - WRITE_REG(LPTIMx->OR, Src); + MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src); } /** @@ -766,7 +765,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); } /** @@ -1035,7 +1034,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); } /** @@ -1065,7 +1064,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL)); } /** @@ -1087,7 +1086,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); } /** @@ -1109,7 +1108,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); } /** @@ -1131,7 +1130,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL)); } /** @@ -1153,7 +1152,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); } /** @@ -1175,7 +1174,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); } /** @@ -1197,7 +1196,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); } /** @@ -1238,7 +1237,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL)); } /** @@ -1271,7 +1270,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL)); } /** @@ -1304,7 +1303,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL)); } /** @@ -1337,7 +1336,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL)); } /** @@ -1366,11 +1365,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). + * @retval State of bit(1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL)); } /** @@ -1399,11 +1398,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). + * @retval State of bit(1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL)); } /** @@ -1432,11 +1431,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). + * @retval State of bit(1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) { - return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL); + return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL); } /** diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h index 37cf247610..e448827aad 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h @@ -124,6 +124,12 @@ typedef struct #if !defined (HSI48_VALUE) #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ #endif /* HSI48_VALUE */ + +#if defined(SPI_I2S_SUPPORT) +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 48000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ +#endif /** * @} */ @@ -292,7 +298,6 @@ typedef struct * @} */ - /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler * @{ */ @@ -377,13 +382,13 @@ typedef struct * @} */ +#if defined(RCC_SMPS_SUPPORT) /** @defgroup RCC_LL_EC_SMPS_CLKSOURCE SMPS clock switch * @{ */ #define LL_RCC_SMPS_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as SMPS clock */ #define LL_RCC_SMPS_CLKSOURCE_MSI RCC_SMPSCR_SMPSSEL_0 /*!< MSI selection as SMPS clock */ #define LL_RCC_SMPS_CLKSOURCE_HSE RCC_SMPSCR_SMPSSEL_1 /*!< HSE selection as SMPS clock */ - /** * @} */ @@ -395,7 +400,6 @@ typedef struct #define LL_RCC_SMPS_CLKSOURCE_STATUS_MSI RCC_SMPSCR_SMPSSWS_0 /*!< MSI used as SMPS clock */ #define LL_RCC_SMPS_CLKSOURCE_STATUS_HSE RCC_SMPSCR_SMPSSWS_1 /*!< HSE used as SMPS clock */ #define LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK (RCC_SMPSCR_SMPSSWS_0|RCC_SMPSCR_SMPSSWS_1) /*!< No Clock used as SMPS clock */ - /** * @} */ @@ -407,13 +411,10 @@ typedef struct #define LL_RCC_SMPS_DIV_1 RCC_SMPSCR_SMPSDIV_0 /*!< SMPS clock division 1 */ #define LL_RCC_SMPS_DIV_2 RCC_SMPSCR_SMPSDIV_1 /*!< SMPS clock division 2 */ #define LL_RCC_SMPS_DIV_3 (RCC_SMPSCR_SMPSDIV_0|RCC_SMPSCR_SMPSDIV_1) /*!< SMPS clock division 3 */ - /** * @} */ - - - +#endif #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency @@ -437,6 +438,7 @@ typedef struct * @} */ +#if defined(LPUART1) /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE LPUART1 CLKSOURCE * @{ */ @@ -447,6 +449,7 @@ typedef struct /** * @} */ +#endif /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE I2Cx CLKSOURCE * @{ @@ -478,6 +481,7 @@ typedef struct * @} */ +#if defined(SAI1) /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE SAI1 CLKSOURCE * @{ */ @@ -488,6 +492,7 @@ typedef struct /** * @} */ +#endif /** @defgroup RCC_LL_EC_CLK48_CLKSOURCE CLK48 CLKSOURCE * @{ @@ -519,8 +524,10 @@ typedef struct * @{ */ #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as ADC clock*/ -#if defined(SAI1) +#if defined(STM32WB55xx) || defined (STM32WB5Mxx) #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 selected as ADC clock*/ +#elif defined(STM32WB35xx) +#define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_0 /*!< HSI selected as ADC clock*/ #endif #define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock*/ #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock*/ @@ -538,6 +545,19 @@ typedef struct * @} */ +#if defined(SPI_I2S_SUPPORT) +/** @defgroup RCC_LL_EC_I2SCLKSOURCE Peripheral I2S clock source selection + * @{ + */ +#define LL_RCC_I2S_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as I2S clock*/ +#define LL_RCC_I2S_CLKSOURCE_HSI RCC_CCIPR_I2SSEL_0 /*!< HSI clock used as I2S clock source */ +#define LL_RCC_I2S_CLKSOURCE_PLL RCC_CCIPR_I2SSEL_1 /*!< PLL clock used as I2S clock source */ +#define LL_RCC_I2S_CLKSOURCE_PIN RCC_CCIPR_I2SSEL /*!< External clock used as I2S clock source */ +/** + * @} + */ +#endif + /** @defgroup RCC_LL_EC_USART1 USART1 * @{ */ @@ -587,7 +607,7 @@ typedef struct /** @defgroup RCC_LL_EC_CLK48 CLK48 * @{ */ -#define LL_RCC_CLK48_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB clock source selection bits */ +#define LL_RCC_CLK48_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< CLK48 clock source selection bits */ /** * @} */ @@ -616,6 +636,16 @@ typedef struct * @} */ +#if defined(SPI_I2S_SUPPORT) +/** @defgroup RCC_LL_EC_I2S I2S + * @{ + */ +#define LL_RCC_I2S_CLKSOURCE RCC_CCIPR_I2SSEL /*!< I2S clock source selection bits */ +/** + * @} + */ +#endif + /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection * @{ */ @@ -734,6 +764,7 @@ typedef struct */ +#if defined(SAI1) /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLQ) * @{ */ @@ -799,6 +830,7 @@ typedef struct /** * @} */ +#endif /** * @} @@ -968,6 +1000,60 @@ typedef struct #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) +#if defined(SPI_I2S_SUPPORT) +/** + * @brief Helper macro to calculate the PLLPCLK frequency used on I2S domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) +#endif + /** * @brief Helper macro to calculate the PLLQCLK frequency used on 48M domain * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -2580,9 +2666,10 @@ __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) * @rmtoll CCIPR CLK48SEL LL_RCC_SetCLK48ClockSource * @param CLK48xSource This parameter can be one of the following values: * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 - * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI + * @note (*) Value not defined for all devices * @retval None */ __STATIC_INLINE void LL_RCC_SetCLK48ClockSource(uint32_t CLK48xSource) @@ -2590,6 +2677,7 @@ __STATIC_INLINE void LL_RCC_SetCLK48ClockSource(uint32_t CLK48xSource) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, CLK48xSource); } +#if defined(USB) /** * @brief Configure USB clock source * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource @@ -2604,6 +2692,7 @@ __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) { LL_RCC_SetCLK48ClockSource(USBxSource); } +#endif /** * @brief Configure RNG clock source @@ -2617,10 +2706,10 @@ __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE * @param CLK48xSource This parameter can be one of the following values: * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 - * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI - + * @note (*) Value not defined for all devices * @retval None */ __STATIC_INLINE void LL_RCC_ConfigRNGClockSource(uint32_t RNGxSource, uint32_t CLK48xSource) @@ -2638,9 +2727,11 @@ __STATIC_INLINE void LL_RCC_ConfigRNGClockSource(uint32_t RNGxSource, uint32_t C * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource * @param ADCxSource This parameter can be one of the following values: * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE - * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI (*) + * @note (*) Value not defined for all devices * @retval None */ __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) @@ -2648,6 +2739,23 @@ __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); } +#if defined(SPI_I2S_SUPPORT) +/** + * @brief Configure I2Sx clock source + * @rmtoll CCIPR I2SSEL LL_RCC_SetI2SClockSource + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S_CLKSOURCE_NONE + * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL + * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2SSEL, I2SxSource); +} +#endif + /** * @brief Get USARTx clock source * @rmtoll CCIPR USART1SEL LL_RCC_GetUSARTClockSource @@ -2761,16 +2869,18 @@ __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) * @param CLK48x This parameter can be one of the following values: * @arg @ref LL_RCC_CLK48_CLKSOURCE * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 - * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL - * @arg @ref LL_RCC_USB_CLKSOURCE_MSI + * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*) + * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL + * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI + * @note (*) Value not defined for all devices */ __STATIC_INLINE uint32_t LL_RCC_GetCLK48ClockSource(uint32_t CLK48x) { return (uint32_t)(READ_BIT(RCC->CCIPR, CLK48x)); } +#if defined(USB) /** * @brief Get USBx clock source * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource @@ -2786,6 +2896,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) { return LL_RCC_GetCLK48ClockSource(USBx); } +#endif /** * @brief Get ADCx clock source @@ -2794,15 +2905,34 @@ __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) * @arg @ref LL_RCC_ADC_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE - * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI (*) + * @note (*) Value not defined for all devices */ __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) { return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx)); } +#if defined(SPI_I2S_SUPPORT) +/** + * @brief Get I2Sx clock source + * @rmtoll CCIPR I2SSEL LL_RCC_GetI2SClockSource + * @param I2Sx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2S_CLKSOURCE_NONE + * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL + * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx)); +} +#endif /** * @} */ @@ -4403,7 +4533,9 @@ ErrorStatus LL_RCC_DeInit(void); * @{ */ void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +#if defined(RCC_SMPS_SUPPORT) uint32_t LL_RCC_GetSMPSClockFreq(void); +#endif uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); #if defined(LPUART1) @@ -4415,10 +4547,15 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); #endif uint32_t LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource); uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +#if defined(USB) uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); uint32_t LL_RCC_GetRTCClockFreq(void); uint32_t LL_RCC_GetRFWKPClockFreq(void); +#if defined(SPI_I2S_SUPPORT) +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); +#endif /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h index 65ddb0f045..9230ff78ab 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_spi.h @@ -1405,6 +1405,872 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); * @} */ +#if defined(SPI_I2S_SUPPORT) +/** @defgroup I2S_LL I2S + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure + * @{ + */ + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_LL_EC_MODE + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_STANDARD + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/ + + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/ + + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT + + This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/ + + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ + + Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity + and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/ + + + uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_LL_EC_POLARITY + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/ + +} LL_I2S_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants + * @{ + */ + +/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2S_ReadReg function + * @{ + */ +#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */ +#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */ +#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */ +#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */ +#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */ +#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ +#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ +#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_DATA_FORMAT Data format + * @{ + */ +#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */ +#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */ +#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */ +#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */ +#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_STANDARD I2s Standard + * @{ + */ +#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */ +#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */ +#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */ +#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */ +#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */ +#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */ +#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */ +#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor + * @{ + */ +#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */ +#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output + * @{ + */ +#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */ +#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency + * @{ + */ + +#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */ +#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */ +#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */ +#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */ +#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */ +#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */ +#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */ +#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */ +#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */ +#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros + * @{ + */ + +/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Select I2S mode and Enable I2S peripheral + * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n + * I2SCFGR I2SE LL_I2S_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +} + +/** + * @brief Disable I2S peripheral + * @rmtoll I2SCFGR I2SE LL_I2S_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +} + +/** + * @brief Check if I2S peripheral is enabled + * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); +} + +/** + * @brief Set I2S data frame length + * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n + * I2SCFGR CHLEN LL_I2S_SetDataFormat + * @param SPIx SPI Instance + * @param DataFormat This parameter can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_32B + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat); +} + +/** + * @brief Get I2S data frame length + * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n + * I2SCFGR CHLEN LL_I2S_GetDataFormat + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_32B + */ +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); +} + +/** + * @brief Set I2S clock polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + SET_BIT(SPIx->I2SCFGR, ClockPolarity); +} + +/** + * @brief Get I2S clock polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); +} + +/** + * @brief Set I2S standard protocol + * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n + * I2SCFGR PCMSYNC LL_I2S_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard); +} + +/** + * @brief Get I2S standard protocol + * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n + * I2SCFGR PCMSYNC LL_I2S_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + */ +__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); +} + +/** + * @brief Set I2S transfer mode + * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode); +} + +/** + * @brief Get I2S transfer mode + * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + */ +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); +} + +/** + * @brief Set I2S linear prescaler + * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear + * @param SPIx SPI Instance + * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear); +} + +/** + * @brief Get I2S linear prescaler + * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear + * @param SPIx SPI Instance + * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); +} + +/** + * @brief Set I2S parity prescaler + * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity + * @param SPIx SPI Instance + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U); +} + +/** + * @brief Get I2S parity prescaler + * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); +} + +/** + * @brief Enable the master clock ouput (Pin MCK) + * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Disable the master clock ouput (Pin MCK) + * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Check if the master clock ouput (Pin MCK) is enabled + * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL); +} + +#if defined(SPI_I2SCFGR_ASTRTEN) +/** + * @brief Enable asynchronous start + * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); +} + +/** + * @brief Disable asynchronous start + * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); +} + +/** + * @brief Check if asynchronous start is enabled + * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL); +} +#endif /* SPI_I2SCFGR_ASTRTEN */ + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_FLAG FLAG Management + * @{ + */ + +/** + * @brief Check if Rx buffer is not empty + * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_RXNE(SPIx); +} + +/** + * @brief Check if Tx buffer is empty + * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_TXE(SPIx); +} + +/** + * @brief Get busy flag + * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_BSY(SPIx); +} + +/** + * @brief Get overrun error flag + * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_OVR(SPIx); +} + +/** + * @brief Get underrun error flag + * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Get frame format error flag + * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_FRE(SPIx); +} + +/** + * @brief Get channel side flag. + * @note 0: Channel Left has to be transmitted or has been received\n + * 1: Channel Right has to be transmitted or has been received\n + * It has no significance in PCM mode. + * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL); +} + +/** + * @brief Clear overrun error flag + * @rmtoll SR OVR LL_I2S_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_OVR(SPIx); +} + +/** + * @brief Clear underrun error flag + * @rmtoll SR UDR LL_I2S_ClearFlag_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->SR; + (void)tmpreg; +} + +/** + * @brief Clear frame format error flag + * @rmtoll SR FRE LL_I2S_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_FRE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_IT Interrupt Management + * @{ + */ + +/** + * @brief Enable error IT + * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). + * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_ERR(SPIx); +} + +/** + * @brief Enable Rx buffer not empty IT + * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_RXNE(SPIx); +} + +/** + * @brief Enable Tx buffer empty IT + * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_TXE(SPIx); +} + +/** + * @brief Disable error IT + * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). + * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_ERR(SPIx); +} + +/** + * @brief Disable Rx buffer not empty IT + * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_RXNE(SPIx); +} + +/** + * @brief Disable Tx buffer empty IT + * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_TXE(SPIx); +} + +/** + * @brief Check if ERR IT is enabled + * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_ERR(SPIx); +} + +/** + * @brief Check if RXNE IT is enabled + * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_RXNE(SPIx); +} + +/** + * @brief Check if TXE IT is enabled + * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_TXE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DMA DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_RX(SPIx); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_RX(SPIx); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_RX(SPIx); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_TX(SPIx); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_TX(SPIx); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_TX(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DATA DATA Management + * @{ + */ + +/** + * @brief Read 16-Bits in data register + * @rmtoll DR DR LL_I2S_ReceiveData16 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) +{ + return LL_SPI_ReceiveData16(SPIx); +} + +/** + * @brief Write 16-Bits in data register + * @rmtoll DR DR LL_I2S_TransmitData16 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ + LL_SPI_TransmitData16(SPIx, TxData); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SPI_I2S_SUPPORT */ + #endif /* defined (SPI1) || defined (SPI2) */ /** diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_system.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_system.h index 89bacd0056..e8255451f0 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_system.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_system.h @@ -58,6 +58,16 @@ extern "C" { /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants * @{ */ +/** + * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values + */ +#define VREFBUF_SC0_CAL_ADDR ((uint8_t*) (0x1FFF75F0UL)) /*!< Address of VREFBUF trimming value for VRS=0, + VREF_SC0 in STM32WB datasheet */ +#define VREFBUF_SC1_CAL_ADDR ((uint8_t*) (0x1FFF7530UL)) /*!< Address of VREFBUF trimming value for VRS=1, + VREF_SC1 in STM32WB datasheet */ +/** + * @} + */ /** * @} @@ -1876,6 +1886,24 @@ __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void) return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS)); } +/** + * @brief Get the VREFBUF trimming value for VRS=0 (VREF_SC0) + * @retval Between 0 and 0x3F + */ +__STATIC_INLINE uint32_t LL_VREFBUF_SC0_GetCalibration(void) +{ + return (uint32_t)(*VREFBUF_SC0_CAL_ADDR); +} + +/** + * @brief Get the VREFBUF trimming value for VRS=1 (VREF_SC1) + * @retval Between 0 and 0x3F + */ +__STATIC_INLINE uint32_t LL_VREFBUF_SC1_GetCalibration(void) +{ + return (uint32_t)(*VREFBUF_SC1_CAL_ADDR); +} + /** * @brief Check if Voltage reference buffer is ready * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady @@ -1898,6 +1926,11 @@ __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void) /** * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage) + * @note Each VrefBuf voltage scale is calibrated in production for each device, + * data stored in flash memory. + * Functions @ref LL_VREFBUF_SC0_GetCalibration and + * @ref LL_VREFBUF_SC0_GetCalibration can be used to retrieve + * these calibration data. * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming * @param Value Between 0 and 0x3F * @retval None diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h index f7d2fc5c42..05256d95b7 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h @@ -120,30 +120,9 @@ static const uint8_t SHIFT_TAB_OISx[] = #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) /* Generic bit definitions for TIMx_AF1 register */ -#define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKIN input enable */ -#if defined(COMP1) && defined(COMP2) -#define TIMx_AF1_BKCOMP1E TIM1_AF1_BKCMP1E /*!< BRK COMP1 enable */ -#define TIMx_AF1_BKCOMP2E TIM1_AF1_BKCMP2E /*!< BRK COMP2 enable */ -#endif /* COMP1 && COMP2 */ #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ -#if defined(COMP1) && defined(COMP2) -#define TIMx_AF1_BKCOMP1P TIM1_AF1_BKCMP1P /*!< BRK COMP1 input polarity */ -#define TIMx_AF1_BKCOMP2P TIM1_AF1_BKCMP2P /*!< BRK COMP2 input polarity */ -#endif /* COMP1 && COMP2 */ #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */ -/* Generic bit definitions for TIMx_AF2 register */ -#define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /*!< BRK2 BKIN2 input enable */ -#if defined(COMP1) && defined(COMP2) -#define TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E /*!< BRK2 COMP1 enable */ -#define TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E /*!< BRK2 COMP2 enable */ -#endif /* COMP1 && COMP2 */ -#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK2 BKIN2 input polarity */ -#if defined(COMP1) && defined(COMP2) -#define TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P /*!< BRK2 COMP1 input polarity */ -#define TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P /*!< BRK2 COMP2 input polarity */ -#endif /* COMP1 && COMP2 */ - /* Remap mask definitions */ #define TIMx_OR_RMP_SHIFT 16U #define TIMx_OR_RMP_MASK 0x0000FFFFU @@ -252,13 +231,14 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ - uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ } LL_TIM_InitTypeDef; @@ -1141,7 +1121,7 @@ typedef struct /** @defgroup TIM_LL_EC_TIM2_ETR_RMP TIM2 External Trigger Remap * @{ */ -#define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR_RMP_MASK /*!< TIM2_ETR is connected to GPIO */ +#define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR_RMP_MASK /*!< TIM2_ETR is connected to GPIO */ #define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR_ETR_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ETR is connected to LSE */ /** * @} @@ -1681,7 +1661,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) * whether or not a timer instance supports a repetition counter. * @rmtoll RCR REP LL_TIM_SetRepetitionCounter * @param TIMx Timer instance - * @param RepetitionCounter between Min_Data=0 and Max_Data=255 + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. * @retval None */ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) @@ -1725,6 +1705,16 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); } +/** + * @brief Indicate whether update interrupt flag (UIF) copy is set. + * @param Counter Counter value + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter) +{ + return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); +} + /** * @} */ @@ -3295,8 +3285,8 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @brief Select the external trigger (ETR) input source. * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or * not a timer instance supports ETR source selection. - * @note When this function is called with LL_TIM_ETRSOURCE_GPIO, - * LL_TIM_ETRSOURCE_ADC1_AWD1, LL_TIM_ETRSOURCE_ADC1_AWD2 or + * @note When this function is called with LL_TIM_ETRSOURCE_GPIO, + * LL_TIM_ETRSOURCE_ADC1_AWD1, LL_TIM_ETRSOURCE_ADC1_AWD2 or * LL_TIM_ETRSOURCE_ADC1_AWD3, ETR source relies on TIMx ETR remapping * capability configured through the function @ref LL_TIM_SetRemap(). * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource @@ -3715,7 +3705,7 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB * TIM2_OR TI4_RMP LL_TIM_SetRemap\n * TIM2_OR TI1_RMP LL_TIM_SetRemap\n * TIM16_OR TI1_RMP LL_TIM_SetRemap\n - * TIM17_OR TI1_RMP LL_TIM_SetRemap\n + * TIM17_OR TI1_RMP LL_TIM_SetRemap * @param TIMx Timer instance * @param Remap Remap param depends on the TIMx. Description available only * in CHM version of the User Manual (not in .pdf). diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html index b1fbd9f0cb..73eb139a24 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html @@ -46,9 +46,65 @@

                                                                                          Purpose

                                                                                          Update History

                                                                                          - +

                                                                                          Main Changes

                                                                                          +

                                                                                          Introduction of STM32WB5M, STM32WB35xx and STM32WB30xx product

                                                                                          +

                                                                                          This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.

                                                                                          +

                                                                                          Added features:

                                                                                          +
                                                                                            +
                                                                                          • Introduction of I2S peripheral support. This only apply to STM32WB35xx.
                                                                                            • +
                                                                                          +
    • + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    PeripheralHeadline
    HAL/LLVREFBUF trimming calibration must be written by software
    HALHAL_SetTickFreq() should update frequency on Systick_LOAD register and uwTickFreq correctly
    GPIOLL_GPIO_Init() generate undesired pulse
    I2CHardFault in I2C_DMAXferCplt
    I2CIncorrectly enable interrupts in I2C_Enable_IRQ routine when InterruptRequest = I2C_XFER_CPLT_IT
    RCCCannot enable PLL if PLL OFF with identical PLL config
    RCCClock reconfiguration issues once PLLSAI used
    I2SAdd peripheral for STM32WB35xx
    +

    Backward Compatibility

    +

    This release is compatible with the previous versions.

    +
    +
    +
    + +
    +

    Main Changes

    Maitenance release

    @@ -92,7 +148,7 @@

    Maitenance release

    -

    Backward Compatibility

    +

    Backward Compatibility

    This release is compatible with the previous versions.

    Dependencies

    This software release is compatible with:

    @@ -102,7 +158,7 @@

    Dependencies

    -

    Main Changes

    +

    Main Changes

    Maitenance release

    @@ -174,7 +230,7 @@

    Maitenance release

    -

    Backward Compatibility

    +

    Backward Compatibility

    This release is compatible with the previous versions.

    Dependencies

    This software release is compatible with:

    @@ -184,7 +240,7 @@

    Dependencies

    -

    Main Changes

    +

    Main Changes

    STM32WB50xx introduction and maintenance release

    First release for STM32WBxx HAL drivers introducing stm32wb50xx devices.

    @@ -253,7 +309,7 @@

    STM32WB50xx introducti

    -

    Backward Compatibility

    +

    Backward Compatibility

    This release is compatible with the previous versions.

    Dependencies

    This software release is compatible with:

    @@ -263,7 +319,7 @@

    Dependencies

    -

    Main Changes

    +

    Main Changes

    Maintenance release

    Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.

    @@ -317,7 +373,7 @@

    Maintenance release

    -

    Backward Compatibility

    +

    Backward Compatibility

    This release is compatible with the previous versions.

    Dependencies

    This software release is compatible with:

    @@ -327,7 +383,7 @@

    Dependencies

    -

    Main Changes

    +

    Main Changes

    First release

    First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.

    diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c index 4432f0b198..564adc3c5e 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c @@ -56,7 +56,7 @@ * @brief STM32WBxx HAL Driver version number */ #define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBxx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32WBxx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ #define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\ @@ -79,7 +79,7 @@ */ __IO uint32_t uwTick; uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ -uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ /** * @} */ @@ -346,17 +346,29 @@ uint32_t HAL_GetTickPrio(void) * @brief Set new tick Freq. * @retval Status */ -HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) { HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + assert_param(IS_TICKFREQ(Freq)); if (uwTickFreq != Freq) { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ uwTickFreq = Freq; /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } } return status; @@ -366,7 +378,7 @@ HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) * @brief Return tick frequency. * @retval tick period in Hz */ -uint32_t HAL_GetTickFreq(void) +HAL_TickFreqTypeDef HAL_GetTickFreq(void) { return uwTickFreq; } @@ -626,14 +638,31 @@ uint32_t HAL_SYSCFG_IsEnabledSRAMFetch(void) * This requires VDDA equal to or higher than 2.4 V. * @arg @ref SYSCFG_VREFBUF_VOLTAGE_SCALE1 : VREF_OUT1 around 2.5 V. * This requires VDDA equal to or higher than 2.8 V. + * @note Retrieve the TrimmingValue from factory located at + * VREFBUF_SC0_CAL_ADDR or VREFBUF_SC1_CAL_ADDR addresses. * @retval None */ void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) { + uint32_t TrimmingValue; + /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); LL_VREFBUF_SetVoltageScaling(VoltageScaling); + + /* Restrieve Calibration data and store them into trimming field */ + if (VoltageScaling == SYSCFG_VREFBUF_VOLTAGE_SCALE0) + { + TrimmingValue = ((uint32_t) *VREFBUF_SC0_CAL_ADDR) & 0x3FU; + } + else + { + TrimmingValue = ((uint32_t) *VREFBUF_SC1_CAL_ADDR) & 0x3FU; + } + assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); + + HAL_SYSCFG_VREFBUF_TrimmingConfig(TrimmingValue); } /** @@ -655,6 +684,12 @@ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) /** * @brief Tune the Internal Voltage Reference buffer (VREFBUF). + * @note Each VrefBuf voltage scale is calibrated in production for each device, + * data stored in flash memory. + * Function @ref HAL_SYSCFG_VREFBUF_VoltageScalingConfig retrieves and + * applies this calibration data as trimming value at each scale change. + * Therefore, optionally, function @ref HAL_SYSCFG_VREFBUF_TrimmingConfig + * can be used in a second time to fine tune the trimming. * @param TrimmingValue specifies trimming code for VREFBUF calibration * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x3F * @retval None diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c index ab3de969b4..57db37d040 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c @@ -315,9 +315,9 @@ void HAL_FLASH_IRQHandler(void) /* return adress being programmed */ param = pFlash.Address; } - else if ((pFlash.ProcedureOnGoing & (FLASH_TYPEERASE_MASSERASE | FLASH_TYPEERASE_PAGES)) != 0U) + else if ((pFlash.ProcedureOnGoing & (FLASH_TYPEERASE_PAGES)) != 0U) { - /* return page number being erased (0 for mass erase) */ + /* return page number being erased */ param = pFlash.Page; } else @@ -389,7 +389,6 @@ void HAL_FLASH_IRQHandler(void) /** * @brief FLASH end of operation interrupt callback. * @param ReturnValue The value saved in this parameter depends on the ongoing procedure - * Mass Erase: 0 * Page Erase: Page which has been erased * Program: Address which was selected for data program * @retval None @@ -407,7 +406,6 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) /** * @brief FLASH operation error interrupt callback. * @param ReturnValue The value saved in this parameter depends on the ongoing procedure - * Mass Erase: 0 * Page Erase: Page number which returned an error * Program: Address which was selected for data program * @retval None diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c index 14976bbba6..ce938822f7 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c @@ -98,7 +98,6 @@ /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions * @{ */ -static void FLASH_MassErase(void); static void FLASH_AcknowledgePageErase(void); static void FLASH_FlushCaches(void); static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); @@ -139,7 +138,7 @@ static HAL_StatusTypeDef FLASH_OB_ProceedWriteOperation(void); * @{ */ /** - * @brief Perform a mass erase or erase the specified FLASH memory pages. + * @brief Perform an erase of the specified FLASH memory pages. * @note Before any operation, it is possible to check there is no operation suspended * by call HAL_FLASHEx_IsOperationSuspended() * @param[in] pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that @@ -168,17 +167,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t if (status == HAL_OK) { - if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /* Mass erase to be done */ - FLASH_MassErase(); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - /* If operation is completed or interrupted, no need to clear the Mass Erase Bit */ - } - else + if (pEraseInit->TypeErase == FLASH_TYPEERASE_PAGES) { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFFU; @@ -214,7 +203,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t } /** - * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. + * @brief Perform an erase of the specified FLASH memory pages with interrupt enabled. * @note Before any operation, it is possible to check there is no operation suspended * by call HAL_FLASHEx_IsOperationSuspended() * @param pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that @@ -250,15 +239,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /* Enable End of Operation and Error interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); - if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /* Set Page to 0 for Interrupt callback managment */ - pFlash.Page = 0; - - /* Proceed to Mass Erase */ - FLASH_MassErase(); - } - else + if (pEraseInit->TypeErase == FLASH_TYPEERASE_PAGES) { /* Erase by page to be done */ pFlash.NbPagesToErase = pEraseInit->NbPages; @@ -513,16 +494,6 @@ uint32_t HAL_FLASHEx_IsOperationSuspended(void) * @{ */ -/** - * @brief Mass erase of FLASH memory. - * @retval None - */ -static void FLASH_MassErase(void) -{ - /* Set the Mass Erase Bit and start bit */ - SET_BIT(FLASH->CR, (FLASH_CR_MER | FLASH_CR_STRT)); -} - /** * @brief Erase the specified FLASH memory page. * @param Page FLASH page to erase diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c index 078809e22c..852e018cb9 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c @@ -188,26 +188,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) if (iocurrent != 0x00u) { /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Alternate function mode selection */ - if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Alternate function parameters */ - assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3u]; - temp &= ~(0xFu << ((position & 0x07u) * 4u)); - temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); - GPIOx->AFR[position >> 3u] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); - GPIOx->MODER = temp; - /* In case of Output or Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) @@ -233,6 +213,26 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp |= ((GPIO_Init->Pull) << (position * 2u)); GPIOx->PUPDR = temp; + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3u]; + temp &= ~(0xFu << ((position & 0x07u) * 4u)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + GPIOx->AFR[position >> 3u] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + GPIOx->MODER = temp; + /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) @@ -314,9 +314,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) tmp &= (0x0FUL << (4u * (position & 0x03u))); if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) { - tmp = 0x0FuL << (4u * (position & 0x03u)); - SYSCFG->EXTICR[position >> 2u] &= ~tmp; - /* Clear EXTI line configuration */ EXTI->IMR1 &= ~(iocurrent); EXTI->EMR1 &= ~(iocurrent); @@ -324,6 +321,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Clear Rising Falling edge configuration */ EXTI->RTSR1 &= ~(iocurrent); EXTI->FTSR1 &= ~(iocurrent); + + tmp = 0x0FuL << (4u * (position & 0x03u)); + SYSCFG->EXTICR[position >> 2u] &= ~tmp; } /*------------------------- GPIO Mode Configuration --------------------*/ @@ -333,14 +333,14 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Configure the default Alternate Function in current IO */ GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ; - /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; - /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); } position++; diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c index 58a01f036e..c047cd0c47 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c @@ -351,13 +351,13 @@ /* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (0x00000001U) -#define I2C_XFER_RX_IT (0x00000002U) -#define I2C_XFER_LISTEN_IT (0x00000004U) +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */ -#define I2C_XFER_ERROR_IT (0x00000011U) -#define I2C_XFER_CPLT_IT (0x00000012U) -#define I2C_XFER_RELOAD_IT (0x00000012U) +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */ /* Private define Sequential Transfer Options default/reset value */ #define I2C_NO_OPTION_FRAME (0xFFFF0000U) @@ -410,6 +410,9 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + /* Private function to flush TXDR register */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); @@ -4251,9 +4254,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Locked */ __HAL_LOCK(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Set State at HAL_I2C_STATE_ABORT */ hi2c->State = HAL_I2C_STATE_ABORT; @@ -5001,6 +5016,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { uint32_t tmpoptions = hi2c->XferOptions; uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; /* Process locked */ __HAL_LOCK(hi2c); @@ -5079,8 +5095,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } @@ -5369,9 +5401,27 @@ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) */ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ @@ -5426,19 +5476,36 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); /* Reset handle parameters */ - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -5447,12 +5514,17 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + /* Flush TX register */ I2C_Flush_TXDR(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); - /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; @@ -5466,6 +5538,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5500,6 +5573,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5546,12 +5620,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -5565,6 +5653,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if (hi2c->hdmatx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); @@ -5572,6 +5663,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if (hi2c->hdmarx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); @@ -5608,7 +5702,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -5631,6 +5724,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5646,6 +5740,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5660,6 +5755,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5733,6 +5829,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { HAL_I2C_StateTypeDef tmpstate = hi2c->State; + uint32_t tmppreviousstate; /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; @@ -5752,7 +5849,6 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* keep HAL_I2C_STATE_LISTEN if set */ hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = I2C_Slave_ISR_IT; } else @@ -5767,16 +5863,19 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; } /* Abort DMA TX transfer if any */ - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } - if (hi2c->hdmatx != NULL) + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5792,13 +5891,20 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } /* Abort DMA RX transfer if any */ - else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } - if (hi2c->hdmarx != NULL) + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5814,10 +5920,28 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } - else if (hi2c->State == HAL_I2C_STATE_ABORT) + else + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5831,6 +5955,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } else { + hi2c->PreviousState = I2C_STATE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -6041,30 +6167,16 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Reset AbortCpltCallback */ - hi2c->hdmatx->XferAbortCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Check if come from abort from user */ - if (hi2c->State == HAL_I2C_STATE_ABORT) + if (hi2c->hdmatx != NULL) { - hi2c->State = HAL_I2C_STATE_READY; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AbortCpltCallback(hi2c); -#else - HAL_I2C_AbortCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmatx->XferAbortCallback = NULL; } - else + if (hi2c->hdmarx != NULL) { - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->ErrorCallback(hi2c); -#else - HAL_I2C_ErrorCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmarx->XferAbortCallback = NULL; } + + I2C_TreatErrorCallback(hi2c); } /** @@ -6341,19 +6453,19 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -6379,7 +6491,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; @@ -6433,19 +6545,19 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2s.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2s.c new file mode 100644 index 0000000000..22a0782551 --- /dev/null +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2s.c @@ -0,0 +1,1802 @@ +/** + ****************************************************************************** + * @file stm32wbxx_hal_i2s.c + * @author MCD Application Team + * @brief I2S HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Integrated Interchip Sound (I2S) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The I2S HAL driver can be used as follow: + + (#) Declare a I2S_HandleTypeDef handle structure. + (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API: + (##) Enable the SPIx interface clock. + (##) I2S pins configuration: + (+++) Enable the clock for the I2S GPIOs. + (+++) Configure these I2S pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT() + and HAL_I2S_Receive_IT() APIs). + (+++) Configure the I2Sx interrupt priority. + (+++) Enable the NVIC I2S IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA() + and HAL_I2S_Receive_DMA() APIs: + (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx Stream/Channel. + (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the + DMA Tx/Rx Stream/Channel. + + (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity + using HAL_I2S_Init() function. + + -@- The specific I2S interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process. + -@- Make sure that either: + (+@) PLLPCLK output is configured or + (+@) HSI is enabled or + (+@) External clock source is configured after setting correctly + the define constant EXTERNAL_CLOCK_VALUE in the stm32wbxx_hal_conf.h file. + + (#) Three mode of operations are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() + (+) Receive an amount of data in blocking mode using HAL_I2S_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() + (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback + (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() + (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback + (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxCpltCallback + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2S_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() + (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback + (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() + (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback + (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxCpltCallback + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2S_ErrorCallback + (+) Pause the DMA Transfer using HAL_I2S_DMAPause() + (+) Resume the DMA Transfer using HAL_I2S_DMAResume() + (+) Stop the DMA Transfer using HAL_I2S_DMAStop() + + *** I2S HAL driver macros list *** + =================================== + [..] + Below the list of most used macros in I2S HAL driver. + + (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) + (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) + (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts + (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts + (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not + + [..] + (@) You can refer to the I2S HAL driver header file for more useful macros + + *** I2S HAL driver macros list *** + =================================== + [..] + Callback registration: + + (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback. + + Function HAL_I2S_RegisterCallback() allows to register following callbacks: + (++) TxCpltCallback : I2S Tx Completed callback + (++) RxCpltCallback : I2S Rx Completed callback + (++) TxHalfCpltCallback : I2S Tx Half Completed callback + (++) RxHalfCpltCallback : I2S Rx Half Completed callback + (++) ErrorCallback : I2S Error callback + (++) MspInitCallback : I2S Msp Init callback + (++) MspDeInitCallback : I2S Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default + weak function. + HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (++) TxCpltCallback : I2S Tx Completed callback + (++) RxCpltCallback : I2S Rx Completed callback + (++) TxHalfCpltCallback : I2S Tx Half Completed callback + (++) RxHalfCpltCallback : I2S Rx Half Completed callback + (++) ErrorCallback : I2S Error callback + (++) MspInitCallback : I2S Msp Init callback + (++) MspDeInitCallback : I2S Msp DeInit callback + + [..] + By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + [..] + Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit() + or HAL_I2S_Init() function. + + [..] + When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbxx_hal.h" + +#ifdef HAL_I2S_MODULE_ENABLED + +#if defined(SPI_I2S_SUPPORT) +/** @addtogroup STM32WBxx_HAL_Driver + * @{ + */ + +/** @defgroup I2S I2S + * @brief I2S HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup I2S_Private_Functions I2S Private Functions + * @{ + */ +static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMAError(DMA_HandleTypeDef *hdma); +static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); +static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s); +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, + uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup I2S_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the I2Sx peripheral in simplex mode: + + (+) User must Implement HAL_I2S_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2S_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Standard + (++) Data Format + (++) MCLK Output + (++) Audio frequency + (++) Polarity + + (+) Call the function HAL_I2S_DeInit() to restore the default configuration + of the selected I2Sx peripheral. + @endverbatim + * @{ + */ + +/** + * @brief Initializes the I2S according to the specified parameters + * in the I2S_InitTypeDef and create the associated handle. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) +{ + uint32_t i2sdiv; + uint32_t i2sodd; + uint32_t packetlength; + uint32_t tmp; + uint32_t i2sclk = 0U; + + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); + assert_param(IS_I2S_MODE(hi2s->Init.Mode)); + assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); + assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); + assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); + + if (hi2s->State == HAL_I2S_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2s->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + /* Init the I2S Callback settings */ + hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hi2s->MspInitCallback == NULL) + { + hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hi2s->MspInitCallback(hi2s); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2S_MspInit(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + + hi2s->State = HAL_I2S_STATE_BUSY; + + /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ + SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ + SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD)); + hi2s->Instance->I2SPR = 0x0002U; + + /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/ + /* If the requested audio frequency is not the default, compute the prescaler */ + if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT) + { + /* Check the frame length (For the Prescaler computing) ********************/ + if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) + { + /* Packet length is 16 bits */ + packetlength = 16U; + } + else + { + /* Packet length is 32 bits */ + packetlength = 32U; + } + + /* I2S standard */ + if (hi2s->Init.Standard <= I2S_STANDARD_LSB) + { + /* In I2S standard packet lenght is multiplied by 2 */ + packetlength = packetlength * 2U; + } + + /* Get the source clock value: based on System Clock value */ + i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S); + + /* Compute the Real divider depending on the MCLK output state, with a floating point */ + if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) + { + /* MCLK output is enabled */ + if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) + { + tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U); + } + else + { + tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U); + } + } + else + { + /* MCLK output is disabled */ + tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U); + } + + /* Remove the flatting point */ + tmp = tmp / 10U; + + /* Check the parity of the divider */ + i2sodd = (uint32_t)(tmp & (uint32_t)1U); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint32_t)((tmp - i2sodd) / 2U); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint32_t)(i2sodd << 8U); + } + else + { + /* Set the default values */ + i2sdiv = 2U; + i2sodd = 0U; + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) + { + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER); + return HAL_ERROR; + } + + /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ + + /* Write to SPIx I2SPR register the computed value */ + hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); + + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + /* And configure the I2S with the I2S_InitStruct values */ + MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ + SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ + SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ + SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \ + (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \ + hi2s->Init.Standard | hi2s->Init.DataFormat | \ + hi2s->Init.CPOL)); + +#if defined(SPI_I2SCFGR_ASTRTEN) + if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG))) + { + /* Write to SPIx I2SCFGR */ + SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN); + } +#endif /* SPI_I2SCFGR_ASTRTEN */ + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the I2S peripheral + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); + + hi2s->State = HAL_I2S_STATE_BUSY; + + /* Disable the I2S Peripheral Clock */ + __HAL_I2S_DISABLE(hi2s); + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + if (hi2s->MspDeInitCallback == NULL) + { + hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hi2s->MspDeInitCallback(hi2s); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_I2S_MspDeInit(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief I2S MSP Init + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_MspInit could be implemented in the user file + */ +} + +/** + * @brief I2S MSP DeInit + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User I2S Callback + * To be used instead of the weak predefined callback + * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for the specified I2S. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, + pI2S_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2s); + + if (HAL_I2S_STATE_READY == hi2s->State) + { + switch (CallbackID) + { + case HAL_I2S_TX_COMPLETE_CB_ID : + hi2s->TxCpltCallback = pCallback; + break; + + case HAL_I2S_RX_COMPLETE_CB_ID : + hi2s->RxCpltCallback = pCallback; + break; + + case HAL_I2S_TX_HALF_COMPLETE_CB_ID : + hi2s->TxHalfCpltCallback = pCallback; + break; + + case HAL_I2S_RX_HALF_COMPLETE_CB_ID : + hi2s->RxHalfCpltCallback = pCallback; + break; + + case HAL_I2S_ERROR_CB_ID : + hi2s->ErrorCallback = pCallback; + break; + + case HAL_I2S_MSPINIT_CB_ID : + hi2s->MspInitCallback = pCallback; + break; + + case HAL_I2S_MSPDEINIT_CB_ID : + hi2s->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2S_STATE_RESET == hi2s->State) + { + switch (CallbackID) + { + case HAL_I2S_MSPINIT_CB_ID : + hi2s->MspInitCallback = pCallback; + break; + + case HAL_I2S_MSPDEINIT_CB_ID : + hi2s->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2s); + return status; +} + +/** + * @brief Unregister an I2S Callback + * I2S callback is redirected to the weak predefined callback + * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for the specified I2S. + * @param CallbackID ID of the callback to be unregistered + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2s); + + if (HAL_I2S_STATE_READY == hi2s->State) + { + switch (CallbackID) + { + case HAL_I2S_TX_COMPLETE_CB_ID : + hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_I2S_RX_COMPLETE_CB_ID : + hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_I2S_TX_HALF_COMPLETE_CB_ID : + hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_I2S_RX_HALF_COMPLETE_CB_ID : + hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_I2S_ERROR_CB_ID : + hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2S_MSPINIT_CB_ID : + hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2S_MSPDEINIT_CB_ID : + hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2S_STATE_RESET == hi2s->State) + { + switch (CallbackID) + { + case HAL_I2S_MSPINIT_CB_ID : + hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2S_MSPDEINIT_CB_ID : + hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2s); + return status; +} +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2S data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2S_Transmit() + (++) HAL_I2S_Receive() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2S_Transmit_IT() + (++) HAL_I2S_Receive_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2S_Transmit_DMA() + (++) HAL_I2S_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2S_TxCpltCallback() + (++) HAL_I2S_RxCpltCallback() + (++) HAL_I2S_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @param Timeout Timeout duration + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pTxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + } + + tmpreg_cfgr = hi2s->Instance->I2SCFGR; + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Wait until TXE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + while (hi2s->TxXferCount > 0U) + { + hi2s->Instance->DR = (*hi2s->pTxBuffPtr); + hi2s->pTxBuffPtr++; + hi2s->TxXferCount--; + + /* Wait until TXE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + /* Check if an underrun occurs */ + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) + { + /* Clear underrun flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + } + } + + /* Check if Slave mode is selected */ + if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) + || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX)) + { + /* Wait until Busy flag is reset */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + } + + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @param Timeout Timeout duration + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate + * in continuous way and as the I2S is not disabled at the end of the I2S transaction. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pRxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); + } + else + { + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Check if Master Receiver mode is selected */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) + { + /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read + access to the SPI_SR register. */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + } + + /* Receive data */ + while (hi2s->RxXferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR; + hi2s->pRxBuffPtr++; + hi2s->RxXferCount--; + + /* Check if an overrun occurs */ + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) + { + /* Clear overrun flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + } + } + + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pTxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + } + + /* Enable TXE and ERR interrupt */ + __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization + * between Master and Slave otherwise the I2S interrupt should be optimized. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pRxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); + } + else + { + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + /* Enable RXNE and ERR interrupt */ + __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to the Transmit data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pTxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + } + + /* Set the I2S Tx DMA Half transfer complete callback */ + hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; + + /* Set the I2S Tx DMA transfer complete callback */ + hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; + + /* Set the DMA error callback */ + hi2s->hdmatx->XferErrorCallback = I2S_DMAError; + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, + (uint32_t)hi2s->pTxBuffPtr, + (uint32_t)&hi2s->Instance->DR, + hi2s->TxXferSize)) + { + /* Update SPI error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + hi2s->State = HAL_I2S_STATE_READY; + + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Check if the I2S Tx request is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Enable Tx DMA Request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + } + + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + uint32_t tmpreg_cfgr; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pRxBuffPtr = pData; + + tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) + { + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); + } + else + { + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + /* Set the I2S Rx DMA Half transfer complete callback */ + hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; + + /* Set the I2S Rx DMA transfer complete callback */ + hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; + + /* Set the DMA error callback */ + hi2s->hdmarx->XferErrorCallback = I2S_DMAError; + + /* Check if Master Receiver mode is selected */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) + { + /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read + access to the SPI_SR register. */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + } + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, + hi2s->RxXferSize)) + { + /* Update SPI error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + hi2s->State = HAL_I2S_STATE_READY; + + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Check if the I2S Rx request is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Enable Rx DMA Request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + } + + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Pauses the audio DMA Stream/Channel playing from the Media. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) +{ + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State == HAL_I2S_STATE_BUSY_TX) + { + /* Disable the I2S DMA Tx request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + } + else if (hi2s->State == HAL_I2S_STATE_BUSY_RX) + { + /* Disable the I2S DMA Rx request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + } + else + { + /* nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief Resumes the audio DMA Stream/Channel playing from the Media. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) +{ + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State == HAL_I2S_STATE_BUSY_TX) + { + /* Enable the I2S DMA Tx request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + } + else if (hi2s->State == HAL_I2S_STATE_BUSY_RX) + { + /* Enable the I2S DMA Rx request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + } + else + { + /* nothing to do */ + } + + /* If the I2S peripheral is still not enabled, enable it */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief Stops the audio DMA Stream/Channel playing from the Media. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() + when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() + */ + + /* Disable the I2S Tx/Rx DMA requests */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Abort the I2S DMA tx Stream/Channel */ + if (hi2s->hdmatx != NULL) + { + /* Disable the I2S DMA tx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Abort the I2S DMA rx Stream/Channel */ + if (hi2s->hdmarx != NULL) + { + /* Disable the I2S DMA rx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + + hi2s->State = HAL_I2S_STATE_READY; + + return errorcode; +} + +/** + * @brief This function handles I2S interrupt request. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) +{ + uint32_t itsource = hi2s->Instance->CR2; + uint32_t itflag = hi2s->Instance->SR; + + /* I2S in mode Receiver ------------------------------------------------*/ + if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) && + (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET)) + { + I2S_Receive_IT(hi2s); + return; + } + + /* I2S in mode Tramitter -----------------------------------------------*/ + if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET)) + { + I2S_Transmit_IT(hi2s); + return; + } + + /* I2S interrupt error -------------------------------------------------*/ + if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET) + { + /* I2S Overrun error interrupt occurred ---------------------------------*/ + if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET) + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + } + + /* I2S Underrun error interrupt occurred --------------------------------*/ + if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET) + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + } + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Tx Transfer Half completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Transfer completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer half completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2S error callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2S state + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL state + */ +HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) +{ + return hi2s->State; +} + +/** + * @brief Return the I2S error code + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval I2S Error Code + */ +uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) +{ + return hi2s->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2S_Private_Functions I2S Private Functions + * @{ + */ +/** + * @brief DMA I2S transmit process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* if DMA is configured in DMA_NORMAL Mode */ + if (hdma->Init.Mode == DMA_NORMAL) + { + /* Disable Tx DMA Request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + + hi2s->TxXferCount = 0U; + hi2s->State = HAL_I2S_STATE_READY; + } + /* Call user Tx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxCpltCallback(hi2s); +#else + HAL_I2S_TxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S transmit process half complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user Tx half complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxHalfCpltCallback(hi2s); +#else + HAL_I2S_TxHalfCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S receive process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* if DMA is configured in DMA_NORMAL Mode */ + if (hdma->Init.Mode == DMA_NORMAL) + { + /* Disable Rx DMA Request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + hi2s->RxXferCount = 0U; + hi2s->State = HAL_I2S_STATE_READY; + } + /* Call user Rx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->RxCpltCallback(hi2s); +#else + HAL_I2S_RxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S receive process half complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user Rx half complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->RxHalfCpltCallback(hi2s); +#else + HAL_I2S_RxHalfCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S communication error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMAError(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Disable Rx and Tx DMA Request */ + CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); + hi2s->TxXferCount = 0U; + hi2s->RxXferCount = 0U; + + hi2s->State = HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) +{ + /* Transmit data */ + hi2s->Instance->DR = (*hi2s->pTxBuffPtr); + hi2s->pTxBuffPtr++; + hi2s->TxXferCount--; + + if (hi2s->TxXferCount == 0U) + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + hi2s->State = HAL_I2S_STATE_READY; + /* Call user Tx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxCpltCallback(hi2s); +#else + HAL_I2S_TxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) +{ + /* Receive data */ + (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR; + hi2s->pRxBuffPtr++; + hi2s->RxXferCount--; + + if (hi2s->RxXferCount == 0U) + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + hi2s->State = HAL_I2S_STATE_READY; + /* Call user Rx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->RxCpltCallback(hi2s); +#else + HAL_I2S_RxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } +} + +/** + * @brief This function handles I2S Communication Timeout. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Timeout Duration of the timeout + * @retval HAL status + */ +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, + uint32_t Timeout) +{ + uint32_t tickstart; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until flag is set to status*/ + while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SPI_I2S_SUPPORT */ + +#endif /* HAL_I2S_MODULE_ENABLED */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_irda.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_irda.c index 6768dcff1f..58aee4dc22 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_irda.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_irda.c @@ -113,8 +113,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback. - Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks: + Use Function HAL_IRDA_RegisterCallback() to register a user callback. + Function HAL_IRDA_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -129,9 +129,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default + Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -146,13 +146,13 @@ (+) MspDeInitCallback : IRDA MspDeInit. [..] - By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET + By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback(). + examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init() - and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init() + and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -161,8 +161,8 @@ in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit() - or @ref HAL_IRDA_Init() function. + using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit() + or HAL_IRDA_Init() function. [..] When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or @@ -753,28 +753,28 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD (++) HAL_IRDA_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_IRDA_Abort() - (+) HAL_IRDA_AbortTransmit() - (+) HAL_IRDA_AbortReceive() - (+) HAL_IRDA_Abort_IT() - (+) HAL_IRDA_AbortTransmit_IT() - (+) HAL_IRDA_AbortReceive_IT() + (++) HAL_IRDA_Abort() + (++) HAL_IRDA_AbortTransmit() + (++) HAL_IRDA_AbortReceive() + (++) HAL_IRDA_Abort_IT() + (++) HAL_IRDA_AbortTransmit_IT() + (++) HAL_IRDA_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_IRDA_AbortCpltCallback() - (+) HAL_IRDA_AbortTransmitCpltCallback() - (+) HAL_IRDA_AbortReceiveCpltCallback() + (++) HAL_IRDA_AbortCpltCallback() + (++) HAL_IRDA_AbortTransmitCpltCallback() + (++) HAL_IRDA_AbortReceiveCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. @endverbatim * @{ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c index 873f9630c8..df3c8bf1a1 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c @@ -174,7 +174,6 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ /** @addtogroup LPTIM_Private_Constants * @{ */ @@ -183,6 +182,25 @@ * @} */ +/* Private macro -------------------------------------------------------------*/ +/** @addtogroup LPTIM_Private_Macros + * @{ + */ +#if defined(LPTIM2) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) \ + (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT()) + +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) \ + (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT()) +#else +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() + +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() +#endif /* LPTIM2 */ +/** + * @} + */ + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) @@ -235,17 +253,20 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); - if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); - assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { - assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); } + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) + { + assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); + assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); + } assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); @@ -278,13 +299,17 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; - if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL)) + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL)); } - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL)); + } + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) + { + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT)); } /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ @@ -298,18 +323,28 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) hlptim->Init.UpdateMode | hlptim->Init.CounterSource); - if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL)) + /* Glitch filters for internal triggers and external inputs are configured + * only if an internal clock source is provided to the LPTIM + */ + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) { - tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + tmpcfgr |= (hlptim->Init.Trigger.SampleTime | hlptim->Init.UltraLowPowerClock.SampleTime); } - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + /* Configure the active edge or edges used by the counter only if LPTIM is + * clocked by an external clock source + */ + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + { + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity); + } + + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable External trigger and set the trigger source */ - tmpcfgr |= (hlptim->Init.Trigger.Source | - hlptim->Init.Trigger.ActiveEdge | - hlptim->Init.Trigger.SampleTime); + tmpcfgr |= (hlptim->Init.Trigger.Source | + hlptim->Init.Trigger.ActiveEdge); } /* Write to LPTIMx CFGR */ @@ -1438,6 +1473,9 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance); + /* Set TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; @@ -1505,6 +1543,9 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Set the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance); + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -1620,6 +1661,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance); + /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { @@ -1684,6 +1728,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Set the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance); + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -2304,17 +2351,17 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t { HAL_StatusTypeDef result = HAL_OK; uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL); - do + do + { + count--; + if (count == 0UL) { - count--; - if (count == 0UL) - { - result = HAL_TIMEOUT; - } + result = HAL_TIMEOUT; } - while((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); + } + while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); - return result; + return result; } /** @@ -2341,16 +2388,16 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /* Save LPTIM source clock */ switch ((uint32_t)hlptim->Instance) { - case LPTIM1_BASE: - tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE(); - break; + case LPTIM1_BASE: + tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE(); + break; #if defined(LPTIM2) - case LPTIM2_BASE: - tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE(); - break; + case LPTIM2_BASE: + tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE(); + break; #endif /* LPTIM2 */ - default: - break; + default: + break; } /* Save LPTIM configuration registers */ @@ -2363,18 +2410,18 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /*********** Reset LPTIM ***********/ switch ((uint32_t)hlptim->Instance) { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_FORCE_RESET(); - __HAL_RCC_LPTIM1_RELEASE_RESET(); - break; + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_FORCE_RESET(); + __HAL_RCC_LPTIM1_RELEASE_RESET(); + break; #if defined(LPTIM2) - case LPTIM2_BASE: - __HAL_RCC_LPTIM2_FORCE_RESET(); - __HAL_RCC_LPTIM2_RELEASE_RESET(); - break; + case LPTIM2_BASE: + __HAL_RCC_LPTIM2_FORCE_RESET(); + __HAL_RCC_LPTIM2_RELEASE_RESET(); + break; #endif /* LPTIM2 */ - default: - break; + default: + break; } /*********** Restore LPTIM Config ***********/ @@ -2383,16 +2430,16 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /* Force LPTIM source kernel clock from APB */ switch ((uint32_t)hlptim->Instance) { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1); - break; + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1); + break; #if defined(LPTIM2) - case LPTIM2_BASE: - __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_PCLK1); - break; + case LPTIM2_BASE: + __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_PCLK1); + break; #endif /* LPTIM2 */ - default: - break; + default: + break; } if (tmpCMP != 0UL) @@ -2427,16 +2474,16 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /* Restore LPTIM source kernel clock */ switch ((uint32_t)hlptim->Instance) { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_CONFIG(tmpclksource); - break; + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_CONFIG(tmpclksource); + break; #if defined(LPTIM2) - case LPTIM2_BASE: - __HAL_RCC_LPTIM2_CONFIG(tmpclksource); - break; + case LPTIM2_BASE: + __HAL_RCC_LPTIM2_CONFIG(tmpclksource); + break; #endif /* LPTIM2 */ - default: - break; + default: + break; } } diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.c index cf93e7ce54..f4ef20712b 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.c @@ -1770,46 +1770,7 @@ uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb) { uint32_t position; -#if defined(CORE_CM0PLUS) - if (msb > 0x7FU) - { - position = 8UL; - } - else if (msb > 0x3FU) - { - position = 7UL; - } - else if (msb > 0x1FU) - { - position = 6UL; - } - else if (msb > 0x0FU) - { - position = 5UL; - } - else if (msb > 0x07U) - { - position = 4UL; - } - else if (msb > 0x03U) - { - position = 3UL; - } - else if (msb > 0x01U) - { - position = 2UL; - } - else if (msb > 0x00U) - { - position = 1UL; - } - else - { - position = 0UL; - } -#else position = 32UL - __CLZ(msb); -#endif return (((byteNumber - 1UL) * 8UL) + position); } diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c index c6f2c02fd4..c0a8841620 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c @@ -76,7 +76,9 @@ #define LSI2_TIMEOUT_VALUE (3U) /* to be adjusted with DS */ #define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#if defined(SAI1) #define PLLSAI1_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#endif #define PRESCALER_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ #define LATENCY_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ @@ -272,6 +274,9 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) /* Get Start Tick*/ tickstart = HAL_GetTick(); + /* MSI PLL OFF */ + LL_RCC_MSI_DisablePLLMode(); + /* Set MSION bit */ LL_RCC_MSI_Enable(); @@ -378,6 +383,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) * @param RCC_OscInitStruct pointer to a @ref RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. + * @note The PLL source is not updated when used as PLLSAI1 clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) @@ -860,67 +866,127 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) + if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) { - /* Check if the PLL is used as system clock or not */ - if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + const uint32_t temp_pllconfig = RCC->PLLCFGR; + + /* PLL On ? */ + if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) { - if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Do nothing if PLL configuration is unchanged */ + if ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) || + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || + (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) { - /* Check the parameters */ - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); - assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); - assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); - assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while (LL_RCC_PLL_IsReady() != 0U) + /* Check if the PLL is used as system clock or not */ + if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) +#if defined(SAI1) + /* Check if main PLL can be updated */ + /* Not possible if the source is shared by other enabled PLLSAIx */ + if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U) + { - return HAL_TIMEOUT; + return HAL_ERROR; } - } + else +#endif + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); - /* Configure the main PLL clock source, multiplication and division factors. */ - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - RCC_OscInitStruct->PLL.PLLM, - RCC_OscInitStruct->PLL.PLLN, - RCC_OscInitStruct->PLL.PLLP, - RCC_OscInitStruct->PLL.PLLQ, - RCC_OscInitStruct->PLL.PLLR); + /* Get Start Tick*/ + tickstart = HAL_GetTick(); - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } - /* Enable PLL System Clock output. */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); - /* Get Start Tick*/ - tickstart = HAL_GetTick(); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ - while (LL_RCC_PLL_IsReady() == 0U) + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + /* PLL is already used as System core clock */ + return HAL_ERROR; + } + } + else + { + /* PLL configuration is unchanged */ + /* Re-enable PLL if it was disabled (ie. low power mode) */ + if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + { + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) { - return HAL_TIMEOUT; + if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } } } } - else + } + else + { + /* Check that PLL is not used as system clock or not */ + if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); + /* Disable all PLL outputs to save power */ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSOURCE_NONE); @@ -934,7 +1000,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ - while (LL_RCC_PLL_IsReady() != 0U) + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { @@ -942,28 +1008,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } } - } - else - { - /* Check if there is a request to disable the PLL used as System clock source */ - if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) - { - return HAL_ERROR; - } else { - /* Do not return HAL_ERROR if request repeats the current configuration */ - uint32_t pllcfgr = RCC->PLLCFGR; - - if ((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || - ((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) || - (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || - (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || - (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) - { - return HAL_ERROR; - } + /* PLL is already used as System core clock */ + return HAL_ERROR; } } } @@ -1302,7 +1350,8 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); } - else +#if defined(RCC_MCO3_SUPPORT) + else if (RCC_MCOx == RCC_MCO3) { /* MCO3 Clock Enable */ __MCO3_CLK_ENABLE(); @@ -1311,6 +1360,11 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M GPIO_InitStruct.Alternate = GPIO_AF6_MCO; HAL_GPIO_Init(MCO3_GPIO_PORT, &GPIO_InitStruct); } +#endif + else + { + ; + } /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ LL_RCC_ConfigMCO(RCC_MCOSource, RCC_MCODiv); diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c index 968e90f51f..b8cd418e32 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c @@ -42,7 +42,9 @@ /** @defgroup RCCEx_Private_Constants RCCEx Private Constants * @{ */ +#if defined(SAI1) #define PLLSAI1_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#endif #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ #define CLOCKSMPS_TIMEOUT_VALUE (5000U) /* 5 s */ @@ -55,9 +57,11 @@ #define LSCO2_GPIO_PORT GPIOH #define LSCO2_PIN GPIO_PIN_3 +#if defined(RCC_LSCO3_SUPPORT) #define __LSCO3_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() #define LSCO3_GPIO_PORT GPIOC #define LSCO3_PIN GPIO_PIN_12 +#endif #define LSI2_TIMEOUT_VALUE (3U) /* to be adjusted with DS */ @@ -128,16 +132,14 @@ static uint32_t RCC_PLLSAI1_GetFreqDomain_Q(void); * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock - * * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock - * * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock - * * @arg @ref RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock * @arg @ref RCC_PERIPHCLK_SMPS SMPS peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * * * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select @@ -170,12 +172,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* SAI1 clock source config set later after clock selection check */ break; +#if defined(SAI1) case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1 */ /* PLLSAI1 parameters N & P configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_ConfigNP(&(PeriphClkInit->PLLSAI1)); /* SAI1 clock source config set later after clock selection check */ break; - +#endif case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/ /* SAI1 clock source config set later after clock selection check */ @@ -325,6 +328,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #endif +#if defined(USB) /*-------------------------- USB clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) { @@ -336,21 +340,21 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Enable PLLQ output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_USBCLK); } - #if defined(SAI1) - if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) - { - /* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1)); + if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) + { + /* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */ + ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1)); - if (ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } + if (ret != HAL_OK) + { + /* set overall return value */ + status = ret; } + } #endif } +#endif /*-------------------------- RNG clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) @@ -384,17 +388,17 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #if defined(SAI1) - if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) - { - /* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_ConfigNR(&(PeriphClkInit->PLLSAI1)); + if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) + { + /* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */ + ret = RCCEx_PLLSAI1_ConfigNR(&(PeriphClkInit->PLLSAI1)); - if (ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } + if (ret != HAL_OK) + { + /* set overall return value */ + status = ret; } + } #endif } @@ -425,6 +429,24 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #endif +#if defined(SPI_I2S_SUPPORT) + /*-------------------- I2S clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + + /* Configure the I2S clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + + if (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL) + { + /* Enable RCC_PLL_I2SCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_I2SCLK); + } + } +#endif + return status; } @@ -434,7 +456,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * returns the configuration information for the Extended Peripherals * clocks(SAI1, LPTIM1, LPTIM2, I2C1, I2C3, LPUART1, - * USART1, RTC, ADCx, USB, RNG, RFWKP, SMPS). + * USART1, RTC, ADCx, USB, RNG, RFWKP, SMPS, I2S). * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) @@ -457,12 +479,18 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI1; #endif +#if defined(USB) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; +#endif #if defined(RCC_SMPS_SUPPORT) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SMPS; #endif +#if defined(SPI_I2S_SUPPORT) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S; +#endif + #if defined(SAI1) /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLSAI1.PLLN = LL_RCC_PLLSAI1_GetN(); @@ -501,8 +529,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the RTC clock source ------------------------------------------------*/ PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); +#if defined(USB) /* Get the USB clock source ------------------------------------------------*/ PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); +#endif /* Get the RNG clock source ------------------------------------------------*/ PeriphClkInit->RngClockSelection = HAL_RCCEx_GetRngCLKSource(); @@ -520,6 +550,11 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the SMPS clock source -----------------------------------------------*/ PeriphClkInit->SmpsClockSelection = __HAL_RCC_GET_SMPS_SOURCE(); #endif + +#if defined(SPI_I2S_SUPPORT) + /* Get the I2S clock source -----------------------------------------------*/ + PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE(); +#endif } /** @@ -538,14 +573,14 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - * * @arg @ref RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock * @arg @ref RCC_PERIPHCLK_SMPS SMPS peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * @retval Frequency in Hz */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { - uint32_t frequency; + uint32_t frequency = 0U; #if defined(RCC_SMPS_SUPPORT) uint32_t smps_prescaler_index = ((LL_RCC_GetSMPSPrescaler()) >> RCC_SMPSCR_SMPSDIV_Pos); @@ -566,7 +601,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (rtcClockSource == LL_RCC_RTC_CLKSOURCE_LSI) /* LSI clock used as RTC clock source */ @@ -579,7 +614,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (rtcClockSource == LL_RCC_RTC_CLKSOURCE_HSE_DIV32) /* HSE clock used as RTC clock source */ @@ -588,7 +623,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else /* No clock used as RTC clock source */ { - frequency = 0; + /* Nothing to do as frequency already initialized to 0U */ } } #if defined(SAI1) @@ -596,42 +631,44 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { switch (LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE)) { - case LL_RCC_SAI1_CLKSOURCE_HSI: /* HSI clock used as SAI1 clock source */ - if (LL_RCC_HSI_IsReady() == 1U) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; + case LL_RCC_SAI1_CLKSOURCE_HSI: /* HSI clock used as SAI1 clock source */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; - case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */ - if (LL_RCC_PLLSAI1_IsReady() == 1U) - { - frequency = RCC_PLLSAI1_GetFreqDomain_P(); - } - else - { - frequency = 0U; - } - break; +#if defined(SAI1) + case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */ + if (LL_RCC_PLLSAI1_IsReady() == 1U) + { + frequency = RCC_PLLSAI1_GetFreqDomain_P(); + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif - case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */ - if (LL_RCC_PLL_IsReady() == 1U) - { - frequency = RCC_PLL_GetFreqDomain_P(); - } - else - { - frequency = 0U; - } - break; + case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */ + if (LL_RCC_PLL_IsReady() == 1U) + { + frequency = RCC_PLL_GetFreqDomain_P(); + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; - default: /* External input clock used as SAI1 clock source */ - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - break; + default: /* External input clock used as SAI1 clock source */ + frequency = EXTERNAL_SAI1_CLOCK_VALUE; + break; } } #endif @@ -649,7 +686,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (rngClockSource == RCC_RNGCLKSOURCE_LSE) /* LSE clock used as RNG clock source */ @@ -660,7 +697,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (rngClockSource == RCC_RNGCLKSOURCE_PLL) /* PLL clock divided by 3 used as RNG clock source */ @@ -671,7 +708,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (rngClockSource == RCC_RNGCLKSOURCE_MSI) /* MSI clock divided by 3 used as RNG clock source */ @@ -682,7 +719,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else /* HSI48 clock divided by 3 used as RNG clock source */ @@ -693,95 +730,97 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } } +#if defined(USB) else if (PeriphClk == RCC_PERIPHCLK_USB) { switch (LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE)) { #if defined(SAI1) - case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */ - if (LL_RCC_PLLSAI1_IsReady() == 1U) - { - frequency = RCC_PLLSAI1_GetFreqDomain_Q(); - } - else - { - frequency = 0U; - } - break; + case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */ + if (LL_RCC_PLLSAI1_IsReady() == 1U) + { + frequency = RCC_PLLSAI1_GetFreqDomain_Q(); + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; #endif - case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ - if (LL_RCC_PLL_IsReady() == 1U) - { - frequency = RCC_PLL_GetFreqDomain_Q(); - } - else - { - frequency = 0U; - } - break; - case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */ - if (LL_RCC_MSI_IsReady() == 1U) - { - frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); - } - else - { - frequency = 0U; - } - break; + case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ + if (LL_RCC_PLL_IsReady() == 1U) + { + frequency = RCC_PLL_GetFreqDomain_Q(); + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; - default: /* HSI48 clock used as USB clock source */ - if (LL_RCC_HSI48_IsReady() == 1U) - { - frequency = HSI48_VALUE; - } - else - { - frequency = 0U; - } - break; + case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */ + if (LL_RCC_MSI_IsReady() == 1U) + { + frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + + default: /* HSI48 clock used as USB clock source */ + if (LL_RCC_HSI48_IsReady() == 1U) + { + frequency = HSI48_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; } } - +#endif else if (PeriphClk == RCC_PERIPHCLK_USART1) { switch (LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE)) { - case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ - frequency = HAL_RCC_GetSysClockFreq(); - break; + case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ + frequency = HAL_RCC_GetSysClockFreq(); + break; - case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady() == 1U) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; + case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; - case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady() == 1U) - { - frequency = LSE_VALUE; - } - else - { - frequency = 0U; - } - break; + case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + frequency = LSE_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; - default: /* USART1 Clock is PCLK2 */ - frequency = __LL_RCC_CALC_PCLK2_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ - LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB2Prescaler()); - break; + default: /* USART1 Clock is PCLK2 */ + frequency = __LL_RCC_CALC_PCLK2_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB2Prescaler()); + break; } } #if defined(LPUART1) @@ -789,36 +828,36 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { switch (LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE)) { - case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */ - frequency = HAL_RCC_GetSysClockFreq(); - break; + case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */ + frequency = HAL_RCC_GetSysClockFreq(); + break; - case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady() == 1U) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; + case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; - case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady() == 1U) - { - frequency = LSE_VALUE; - } - else - { - frequency = 0U; - } - break; + case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + frequency = LSE_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; - default: /* LPUART1 Clock is PCLK1 */ - frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ - LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler()); - break; + default: /* LPUART1 Clock is PCLK1 */ + frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler()); + break; } } #endif @@ -826,61 +865,71 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { switch (LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE)) { -#if defined(SAI1) - case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */ - if (LL_RCC_PLLSAI1_IsReady() == 1U) - { - frequency = RCC_PLLSAI1_GetFreqDomain_R(); - } - else - { - frequency = 0U; - } - break; +#if defined(STM32WB55xx) || defined (STM32WB5Mxx) + case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */ + if (LL_RCC_PLLSAI1_IsReady() == 1U) + { + frequency = RCC_PLLSAI1_GetFreqDomain_R(); + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#elif defined(STM32WB35xx) + case LL_RCC_ADC_CLKSOURCE_HSI: /* HSI clock used as ADC clock source */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; #endif - case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ - frequency = HAL_RCC_GetSysClockFreq(); - break; + case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ + frequency = HAL_RCC_GetSysClockFreq(); + break; - case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ - if (LL_RCC_PLL_IsReady() == 1U) - { - frequency = RCC_PLL_GetFreqDomain_P(); - } - else - { - frequency = 0U; - } - break; + case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as ADC clock source */ + if (LL_RCC_PLL_IsReady() == 1U) + { + frequency = RCC_PLL_GetFreqDomain_P(); + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; - default: /* No clock used as ADC clock source */ - frequency = 0; - break; + default: /* No clock used as ADC clock source */ + break; } } else if (PeriphClk == RCC_PERIPHCLK_I2C1) { switch (LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE)) { - case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ - frequency = HAL_RCC_GetSysClockFreq(); - break; + case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ + frequency = HAL_RCC_GetSysClockFreq(); + break; - case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady() == 1U) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; + case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; - default: /* I2C1 Clock is PCLK1 */ - frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ - LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler()); - break; + default: /* I2C1 Clock is PCLK1 */ + frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler()); + break; } } #if defined(I2C3) @@ -888,25 +937,25 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { switch (LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE)) { - case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */ - frequency = HAL_RCC_GetSysClockFreq(); - break; + case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */ + frequency = HAL_RCC_GetSysClockFreq(); + break; - case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady() == 1U) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; + case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; - default: /* I2C3 Clock is PCLK1 */ - frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ - LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler()); - break; + default: /* I2C3 Clock is PCLK1 */ + frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \ + LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler()); + break; } } #endif @@ -924,7 +973,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_HSI) /* LPTIM1 Clock is HSI Osc. */ @@ -935,7 +984,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_LSE) /* LPTIM1 Clock is LSE Osc. */ @@ -946,7 +995,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else /* LPTIM1 Clock is PCLK1 */ @@ -968,7 +1017,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (lptimClockSource == LL_RCC_LPTIM2_CLKSOURCE_HSI) /* LPTIM2 Clock is HSI Osc. */ @@ -979,7 +1028,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (lptimClockSource == LL_RCC_LPTIM2_CLKSOURCE_LSE) /* LPTIM2 Clock is LSE Osc. */ @@ -990,7 +1039,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else /* LPTIM2 Clock is PCLK1 */ @@ -1010,7 +1059,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_LSI) /* LSI clock used as RF Wakeup clock source */ @@ -1023,7 +1072,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024) /* HSE clock used as RF Wakeup clock source */ @@ -1032,7 +1081,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else /* No clock used as RF Wakeup clock source */ { - frequency = 0; + /* Nothing to do as frequency already initialized to 0U */ } } #if defined(RCC_SMPS_SUPPORT) @@ -1049,7 +1098,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSE) /* SMPS Clock source is HSE Osc. */ @@ -1061,41 +1110,62 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_MSI) /* SMPS Clock source is MSI Osc. */ { switch (LL_RCC_MSI_GetRange()) { - case LL_RCC_MSIRANGE_8: - frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_8) / SmpsPrescalerTable[smps_prescaler_index][4]; - break; - case LL_RCC_MSIRANGE_9: - frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_9) / SmpsPrescalerTable[smps_prescaler_index][3]; - break; - case LL_RCC_MSIRANGE_10: - frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_10) / SmpsPrescalerTable[smps_prescaler_index][2]; - break; - case LL_RCC_MSIRANGE_11: - frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_11) / SmpsPrescalerTable[smps_prescaler_index][1]; - break; - default: - frequency = 0U; - break; + case LL_RCC_MSIRANGE_8: + frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_8) / SmpsPrescalerTable[smps_prescaler_index][4]; + break; + case LL_RCC_MSIRANGE_9: + frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_9) / SmpsPrescalerTable[smps_prescaler_index][3]; + break; + case LL_RCC_MSIRANGE_10: + frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_10) / SmpsPrescalerTable[smps_prescaler_index][2]; + break; + case LL_RCC_MSIRANGE_11: + frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_11) / SmpsPrescalerTable[smps_prescaler_index][1]; + break; + default: + break; } frequency = frequency >> 1U; /* Systematic Div by 2 */ } else /* SMPS has no Clock */ { - frequency = 0U; + /* Nothing to do as frequency already initialized to 0U */ } } #endif - else +#if defined(SPI_I2S_SUPPORT) + if (PeriphClk == RCC_PERIPHCLK_I2S) { - frequency = 0U; + switch (LL_RCC_GetI2SClockSource(LL_RCC_I2S_CLKSOURCE)) + { + case LL_RCC_I2S_CLKSOURCE_PIN: /* I2S Clock is External clock */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_I2S_CLKSOURCE_HSI: /* I2S Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2S_CLKSOURCE_PLL: /* I2S Clock is PLL */ + frequency = RCC_PLL_GetFreqDomain_P(); + break; + + case LL_RCC_I2S_CLKSOURCE_NONE: /* No clock used as I2S clock source */ + default: + break; + } } +#endif return (frequency); } @@ -1334,7 +1404,7 @@ __weak void HAL_RCCEx_LSECSS_Callback(void) * @note PA2, PH3 or PC12 should be configured in alternate function mode. * @param RCC_LSCOx specifies the output direction for the clock source. * @arg @ref RCC_LSCO1 Clock source to output on LSCO1 pin(PA2) - * @arg @ref RCC_LSCO2 Clock source to output on LSCO2 pin(PH13) + * @arg @ref RCC_LSCO2 Clock source to output on LSCO2 pin(PH3) * @arg @ref RCC_LSCO3 Clock source to output on LSCO3 pin(PC12) * @param RCC_LSCOSource specifies the clock source to output. * This parameter can be one of the following values: @@ -1378,7 +1448,8 @@ void HAL_RCCEx_LSCOConfig(uint32_t RCC_LSCOx, uint32_t RCC_LSCOSource) HAL_GPIO_Init(LSCO2_GPIO_PORT, &GPIO_InitStruct); } - else +#if defined(RCC_LSCO3_SUPPORT) + else if (RCC_LSCOx == RCC_LSCO3) { /* LSCO3 Clock Enable */ __LSCO3_CLK_ENABLE(); @@ -1387,6 +1458,11 @@ void HAL_RCCEx_LSCOConfig(uint32_t RCC_LSCOx, uint32_t RCC_LSCOSource) GPIO_InitStruct.Alternate = GPIO_AF6_LSCO; HAL_GPIO_Init(LSCO3_GPIO_PORT, &GPIO_InitStruct); } +#endif + else + { + ; + } /* Update LSCOSEL clock source in Backup Domain control register */ if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smartcard.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smartcard.c index a24a035a0d..6f38d0c42c 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smartcard.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smartcard.c @@ -107,8 +107,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback. - Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: + Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback. + Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: (+) TxCpltCallback : Tx Complete Callback. (+) RxCpltCallback : Rx Complete Callback. (+) ErrorCallback : Error Callback. @@ -123,9 +123,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default + Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : Tx Complete Callback. @@ -140,13 +140,13 @@ (+) MspDeInitCallback : SMARTCARD MspDeInit. [..] - By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET + By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback(). + examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init() - and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init() + and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -155,8 +155,8 @@ in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit() - or @ref HAL_SMARTCARD_Init() function. + using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit() + or HAL_SMARTCARD_Init() function. [..] When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or @@ -722,59 +722,59 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. [..] - (+) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. + (#) There are two modes of transfer: + (##) Blocking mode: The communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. - (++) Non-Blocking mode: The communication is performed using Interrupts + (##) Non-Blocking mode: The communication is performed using Interrupts or DMA, the relevant API's return the HAL status. The end of the data processing will be indicated through the dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. - (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks + (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks will be executed respectively at the end of the Transmit or Receive process The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected. - (+) Blocking mode APIs are : - (++) HAL_SMARTCARD_Transmit() - (++) HAL_SMARTCARD_Receive() + (#) Blocking mode APIs are : + (##) HAL_SMARTCARD_Transmit() + (##) HAL_SMARTCARD_Receive() - (+) Non Blocking mode APIs with Interrupt are : - (++) HAL_SMARTCARD_Transmit_IT() - (++) HAL_SMARTCARD_Receive_IT() - (++) HAL_SMARTCARD_IRQHandler() + (#) Non Blocking mode APIs with Interrupt are : + (##) HAL_SMARTCARD_Transmit_IT() + (##) HAL_SMARTCARD_Receive_IT() + (##) HAL_SMARTCARD_IRQHandler() - (+) Non Blocking mode functions with DMA are : - (++) HAL_SMARTCARD_Transmit_DMA() - (++) HAL_SMARTCARD_Receive_DMA() + (#) Non Blocking mode functions with DMA are : + (##) HAL_SMARTCARD_Transmit_DMA() + (##) HAL_SMARTCARD_Receive_DMA() - (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_SMARTCARD_TxCpltCallback() - (++) HAL_SMARTCARD_RxCpltCallback() - (++) HAL_SMARTCARD_ErrorCallback() + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (##) HAL_SMARTCARD_TxCpltCallback() + (##) HAL_SMARTCARD_RxCpltCallback() + (##) HAL_SMARTCARD_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_SMARTCARD_Abort() - (+) HAL_SMARTCARD_AbortTransmit() - (+) HAL_SMARTCARD_AbortReceive() - (+) HAL_SMARTCARD_Abort_IT() - (+) HAL_SMARTCARD_AbortTransmit_IT() - (+) HAL_SMARTCARD_AbortReceive_IT() + (##) HAL_SMARTCARD_Abort() + (##) HAL_SMARTCARD_AbortTransmit() + (##) HAL_SMARTCARD_AbortReceive() + (##) HAL_SMARTCARD_Abort_IT() + (##) HAL_SMARTCARD_AbortTransmit_IT() + (##) HAL_SMARTCARD_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_SMARTCARD_AbortCpltCallback() - (+) HAL_SMARTCARD_AbortTransmitCpltCallback() - (+) HAL_SMARTCARD_AbortReceiveCpltCallback() + (##) HAL_SMARTCARD_AbortCpltCallback() + (##) HAL_SMARTCARD_AbortTransmitCpltCallback() + (##) HAL_SMARTCARD_AbortReceiveCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted. This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode. Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c index eeec812848..ce7a1e8da5 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c @@ -2625,10 +2625,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini } /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); @@ -2791,7 +2791,7 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Enable the encoder interface channels */ switch (Channel) @@ -2835,7 +2835,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -2881,7 +2881,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Enable the encoder interface channels */ /* Enable the capture compare Interrupts 1 and/or 2 */ @@ -2931,7 +2931,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -2986,7 +2986,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch uint32_t *pData2, uint16_t Length) { /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); if (htim->State == HAL_TIM_STATE_BUSY) { @@ -3120,7 +3120,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c index 11954768b3..e70227cb96 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c @@ -32,12 +32,11 @@ (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: - (++) Counter min (T[5;0] = 0x00) @64 MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 64s - (++) Counter max (T[5;0] = 0x3F) @64 MHz (PCLK1) with prescaler dividing by 128: + (++) Counter min (T[5;0] = 0x00) at 64 MHz (PCLK1) with zero prescaler: + max timeout before reset: approximately 64us + (++) Counter max (T[5;0] = 0x3F) at 64 MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 524.28ms - ============================================================================== ##### How to use this driver ##### ============================================================================== @@ -67,26 +66,26 @@ [..] The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions - @ref HAL_WWDG_RegisterCallback() to register a user callback. + HAL_WWDG_RegisterCallback() to register a user callback. - (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following + (+) Function HAL_WWDG_RegisterCallback() allows to register following callbacks: (++) EwiCallback : callback for Early WakeUp Interrupt. (++) MspInitCallback : WWDG MspInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to - the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback() + (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to + the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID. This function allows to reset following callbacks: (++) EwiCallback : callback for Early WakeUp Interrupt. (++) MspInitCallback : WWDG MspInit. [..] - When calling @ref HAL_WWDG_Init function, callbacks are reset to the + When calling HAL_WWDG_Init function, callbacks are reset to the corresponding legacy weak (surcharged) functions: - @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have + HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have not been registered before. [..] diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c index 09853b4d2d..daf9f6ae2b 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c @@ -190,9 +190,6 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru if (currentpin != 0x00u) { - /* Pin Mode configuration */ - LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) { /* Check Speed mode parameters */ @@ -200,6 +197,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru /* Speed mode configuration */ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType); } /* Pull-up Pull down resistor configuration*/ @@ -220,19 +223,13 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); } } + + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); } pinpos++; } - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) - { - /* Check Output mode parameters */ - assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); - - /* Output mode configuration*/ - LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); - - } return (SUCCESS); } diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c index 16cde97df7..ea02936b29 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_lptim.c @@ -207,16 +207,16 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) /* Save LPTIM source clock */ switch ((uint32_t)LPTIMx) { - case LPTIM1_BASE: - tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); - break; + case LPTIM1_BASE: + tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); + break; #if defined(LPTIM2) - case LPTIM2_BASE: - tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE); - break; + case LPTIM2_BASE: + tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE); + break; #endif /* LPTIM2 */ - default: - break; + default: + break; } /* Save LPTIM configuration registers */ @@ -237,16 +237,16 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) /* Force LPTIM source kernel clock from APB */ switch ((uint32_t)LPTIMx) { - case LPTIM1_BASE: - LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1); - break; + case LPTIM1_BASE: + LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1); + break; #if defined(LPTIM2) - case LPTIM2_BASE: - LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK1); - break; + case LPTIM2_BASE: + LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK1); + break; #endif /* LPTIM2 */ - default: - break; + default: + break; } if (tmpCMP != 0UL) @@ -259,7 +259,8 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } + while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_CMPOK(LPTIMx); } @@ -274,7 +275,8 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } + while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_ARROK(LPTIMx); } diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c index 1a964c467d..23aa838de0 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c @@ -72,6 +72,9 @@ #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE)) +#if defined(SPI_I2S_SUPPORT) +#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE) +#endif /** * @} */ @@ -81,7 +84,9 @@ * @{ */ uint32_t RCC_PLL_GetFreqDomain_SYS(void); +#if defined(SAI1) uint32_t RCC_PLL_GetFreqDomain_SAI(void); +#endif uint32_t RCC_PLL_GetFreqDomain_ADC(void); uint32_t RCC_PLL_GetFreqDomain_48M(void); @@ -91,6 +96,10 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void); uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void); #endif +#if defined(SPI_I2S_SUPPORT) +uint32_t RCC_PLL_GetFreqDomain_I2S(void); +#endif + uint32_t RCC_GetSystemClockFreq(void); @@ -349,7 +358,6 @@ uint32_t LL_RCC_GetSMPSClockFreq(void) return smps_frequency; } - #endif /** @@ -616,12 +624,15 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) } break; +#if defined(SAI1) case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */ if (LL_RCC_PLLSAI1_IsReady() == 1U) { sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI(); } break; +#endif + case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */ if (LL_RCC_PLL_IsReady() == 1U) { @@ -775,7 +786,7 @@ uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) adc_frequency = RCC_GetSystemClockFreq(); break; - case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ + case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as ADC clock source */ if (LL_RCC_PLL_IsReady() == 1U) { adc_frequency = RCC_PLL_GetFreqDomain_ADC(); @@ -874,6 +885,46 @@ uint32_t LL_RCC_GetRFWKPClockFreq(void) return rfwkp_frequency; } +#if defined(SPI_I2S_SUPPORT) +/** + * @brief Return I2Sx clock frequency + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S_CLKSOURCE + * @retval I2S clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLLs (PLL) is not ready + */ +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) +{ + uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource)); + + /* I2SCLK clock frequency */ + switch (LL_RCC_GetI2SClockSource(I2SxSource)) + { + case LL_RCC_I2S_CLKSOURCE_PLL: /* I2S2 Clock is PLL"P" */ + if (LL_RCC_PLL_IsReady() == 1U) + { + i2s_frequency = RCC_PLL_GetFreqDomain_I2S(); + } + break; + + case LL_RCC_I2S_CLKSOURCE_PIN: /* I2S2 Clock is External clock */ + i2s_frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_I2S_CLKSOURCE_HSI: /* HSI clock used as I2S clock source */ + default: + if (LL_RCC_HSI_IsReady() == 1U) + { + i2s_frequency = HSI_VALUE; + } + break; + } + return i2s_frequency; +} +#endif /** * @} @@ -1312,6 +1363,36 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) } #endif +#if defined(SPI_I2S_SUPPORT) +/** + * @brief Return PLL clock frequency used for I2S domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_I2S(void) +{ + uint32_t pllinputfreq, pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + I2S Domain clock = PLL_VCO / PLLP + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); +} +#endif + /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c index 8d8c4220a2..13017194f9 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c @@ -21,6 +21,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32wbxx_ll_spi.h" #include "stm32wbxx_ll_bus.h" +#include "stm32wbxx_ll_rcc.h" #ifdef USE_FULL_ASSERT #include "stm32_assert.h" @@ -232,6 +233,10 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) status = SUCCESS; } +#if defined (SPI_I2S_SUPPORT) + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2S_SUPPORT */ return status; } @@ -268,6 +273,251 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) * @} */ +#if defined(SPI_I2S_SUPPORT) +/** @addtogroup I2S_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2S_LL_Private_Constants I2S Private Constants + * @{ + */ +/* I2S registers Masks */ +#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ + SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ + SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) + +#define I2S_I2SPR_CLEAR_MASK 0x0002U +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Private_Macros I2S Private Macros + * @{ + */ + +#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) + +#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \ + || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) + +#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ + || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ + || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ + || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ + || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) + +#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ + || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ + || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ + || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)) + +#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \ + || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) + +#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ + && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ + || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) + +#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U) + +#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \ + || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2S_LL_Exported_Functions + * @{ + */ + +/** @addtogroup I2S_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the SPI/I2S registers to their default reset values. + * @param SPIx SPI Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are de-initialized + * - ERROR: SPI registers are not de-initialized + */ +ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) +{ + return LL_SPI_DeInit(SPIx); +} + +/** + * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. + * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), + * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @param SPIx SPI Instance + * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are Initialized + * - ERROR: SPI registers are not Initialized + */ +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) +{ + uint32_t i2sdiv = 2U; + uint32_t i2sodd = 0U; + uint32_t packetlength = 1U; + uint32_t tmp; + uint32_t sourceclock; + ErrorStatus status = ERROR; + + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); + assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); + assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); + assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); + assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); + assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); + + if (LL_I2S_IsEnabled(SPIx) == 0x00000000U) + { + /*---------------------------- SPIx I2SCFGR Configuration -------------------- + * Configure SPIx I2SCFGR with parameters: + * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit + * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits + * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits + * - ClockPolarity: SPI_I2SCFGR_CKPOL bit + */ + + /* Write to SPIx I2SCFGR */ + MODIFY_REG(SPIx->I2SCFGR, + I2S_I2SCFGR_CLEAR_MASK, + I2S_InitStruct->Mode | I2S_InitStruct->Standard | + I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | + SPI_I2SCFGR_I2SMOD); + + /*---------------------------- SPIx I2SPR Configuration ---------------------- + * Configure SPIx I2SPR with parameters: + * - MCLKOutput: SPI_I2SPR_MCKOE bit + * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits + */ + + /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) + * else, default values are used: i2sodd = 0U, i2sdiv = 2U. + */ + if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) + { + /* Check the frame length (For the Prescaler computing) + * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). + */ + if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) + { + /* Packet length is 32 bits */ + packetlength = 2U; + } + + /* If an external I2S clock has to be used, the specific define should be set + in the project configuration or in the stm32wbxx_ll_rcc.h file */ + /* Get the I2S source clock value */ + sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S_CLKSOURCE); + + /* Compute the Real divider depending on the MCLK output state with a floating point */ + if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) + { + /* MCLK output is enabled */ + tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); + } + else + { + /* MCLK output is disabled */ + tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); + } + + /* Remove the floating point */ + tmp = tmp / 10U; + + /* Check the parity of the divider */ + i2sodd = (tmp & (uint16_t)0x0001U); + + /* Compute the i2sdiv prescaler */ + i2sdiv = ((tmp - i2sodd) / 2U); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (i2sodd << 8U); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) + { + /* Set the default values */ + i2sdiv = 2U; + i2sodd = 0U; + } + + /* Write to SPIx I2SPR register the computed value */ + WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput); + + status = SUCCESS; + } + return status; +} + +/** + * @brief Set each @ref LL_I2S_InitTypeDef field to default value. + * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) +{ + /*--------------- Reset I2S init structure parameters values -----------------*/ + I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; + I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; + I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; + I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; + I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; + I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; +} + +/** + * @brief Set linear and parity prescaler. + * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n + * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). + * @param SPIx SPI Instance + * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF. + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) +{ + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); + assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); + + /* Write to SPIx I2SPR */ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SPI_I2S_SUPPORT */ + #endif /* defined (SPI1) || defined (SPI2) */ /** diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c index a3f240a165..ba79b2a2ed 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c @@ -262,7 +262,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; TIM_InitStruct->Autoreload = 0xFFFFFFFFU; TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; - TIM_InitStruct->RepetitionCounter = (uint8_t)0x00; + TIM_InitStruct->RepetitionCounter = 0x00000000U; } /** diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 694e83033a..7417c0aea4 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -2,18 +2,18 @@ * STM32F0: 1.7.3 * STM32F1: 1.1.4 - * STM32F2: 1.2.3 + * STM32F2: 1.2.4 * STM32F3: 1.5.3 * STM32F4: 1.7.7 * STM32F7: 1.2.7 * STM32G0: 1.3.0 * STM32G4: 1.1.1 - * STM32H7: 1.7.0 + * STM32H7: 1.8.0 * STM32L0: 1.10.2 * STM32L1: 1.4.0 - * STM32L4: 1.11.0 + * STM32L4: 1.11.1 * STM32MP1: 1.2.0 - * STM32WB: 1.4.0 + * STM32WB: 1.5.0 Release notes of each STM32YYxx HAL Drivers available here: diff --git a/system/STM32H7xx/system_stm32h7xx.c b/system/STM32H7xx/system_stm32h7xx.c index 5af504250d..42400ed61f 100644 --- a/system/STM32H7xx/system_stm32h7xx.c +++ b/system/STM32H7xx/system_stm32h7xx.c @@ -2,9 +2,7 @@ ****************************************************************************** * @file system_stm32h7xx.c * @author MCD Application Team - * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. - * This provides system initialization template function is case of - * an application using a single core STM32H7 device + * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from * user application: @@ -12,7 +10,7 @@ * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * - SystemCoreClock variable: Contains the core clock, it can be used * by the user application to setup the SysTick * timer or configure other parameters. * @@ -67,7 +65,7 @@ */ /************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM */ +/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */ /* #define DATA_IN_D2_SRAM */ /*!< Uncomment the following line if you need to relocate your vector Table in @@ -149,6 +147,7 @@ void SystemInit (void) /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; +#if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; @@ -157,7 +156,16 @@ void SystemInit (void) /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; +#else + /* Reset CDCFGR1 register */ + RCC->CDCFGR1 = 0x00000000; + + /* Reset CDCFGR2 register */ + RCC->CDCFGR2 = 0x00000000; + /* Reset SRDCFGR register */ + RCC->SRDCFGR = 0x00000000; +#endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x00000000; @@ -186,27 +194,48 @@ void SystemInit (void) /* Disable all interrupts */ RCC->CIER = 0x00000000; +#if (STM32H7_DEV_ID == 0x450UL) + /* dual core CM7 or single core line */ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) { /* if stm32h7 revY*/ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; } +#endif #if defined (DATA_IN_D2_SRAM) - /* in case of initialized data in D2 SRAM , enable the D2 SRAM clock */ + /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); +#elif defined(RCC_AHB2ENR_D2SRAM2EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); +#else + RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); +#endif /* RCC_AHB2ENR_D2SRAM3EN */ + tmpreg = RCC->AHB2ENR; (void) tmpreg; #endif /* DATA_IN_D2_SRAM */ - /* Configure the Vector Table location add offset address ------------------*/ +#if defined(DUAL_CORE) && defined(CORE_CM4) + /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif /* VECT_TAB_SRAM */ + +#else + + /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/ #ifdef VECT_TAB_SRAM - SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ + SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */ #else SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ #endif +#endif /*DUAL_CORE && CORE_CM4*/ } @@ -250,22 +279,24 @@ void SystemInit (void) void SystemCoreClockUpdate (void) { uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + uint32_t common_system_clock; float_t fracn1, pllvco; + /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ - SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); break; case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ - SystemCoreClock = CSI_VALUE; + common_system_clock = CSI_VALUE; break; case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; + common_system_clock = HSE_VALUE; break; case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ @@ -302,29 +333,48 @@ void SystemCoreClockUpdate (void) break; } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; - SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); } else { - SystemCoreClock = 0U; + common_system_clock = 0U; } break; default: - SystemCoreClock = CSI_VALUE; + common_system_clock = CSI_VALUE; break; } /* Compute SystemClock frequency --------------------------------------------------*/ +#if defined (RCC_D1CFGR_D1CPRE) tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; - /* SystemCoreClock frequency : CM7 CPU frequency */ - SystemCoreClock >>= tmp; + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; + + /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + +#else + tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]; + + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; /* SystemD2Clock frequency : AXI and AHBs Clock frequency */ - SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); + +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ } + /** * @} */ diff --git a/system/STM32WBxx/system_stm32wbxx.c b/system/STM32WBxx/system_stm32wbxx.c index 1028f8b239..eafd710b9d 100644 --- a/system/STM32WBxx/system_stm32wbxx.c +++ b/system/STM32WBxx/system_stm32wbxx.c @@ -144,7 +144,7 @@ const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \ 4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */ -#if defined(STM32WB55xx) +#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \ {2UL,6UL,4UL,3UL,2UL,4UL}, \ {4UL,12UL,8UL,6UL,4UL,8UL}, \ @@ -206,7 +206,7 @@ void SystemInit(void) /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x22041000U; -#if defined(STM32WB55xx) +#if defined(STM32WB55xx) || defined(STM32WB5Mxx) /* Reset PLLSAI1CFGR register */ RCC->PLLSAI1CFGR = 0x22041000U; #endif