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Add e2e mir test for checked arithmetic.
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‎tests/mir-opt/pre-codegen/checked_ops.checked_shl.PreCodegen.after.mir

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// MIR for `checked_shl` after PreCodegen
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fn checked_shl(_1: u32, _2: u32) -> Option<u32> {
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debug x => _1; // in scope 0 at $DIR/checked_ops.rs:+0:20: +0:21
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debug rhs => _2; // in scope 0 at $DIR/checked_ops.rs:+0:28: +0:31
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let mut _0: std::option::Option<u32>; // return place in scope 0 at $DIR/checked_ops.rs:+0:41: +0:52
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scope 1 (inlined core::num::<impl u32>::checked_shl) { // at $DIR/checked_ops.rs:14:7: 14:23
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debug self => _1; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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debug rhs => _2; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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let mut _13: (u32, bool); // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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let _14: u32; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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let _15: bool; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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let mut _16: bool; // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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scope 2 {
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debug a => _14; // in scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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debug b => _15; // in scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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}
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scope 3 (inlined core::num::<impl u32>::overflowing_shl) { // at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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debug self => _1; // in scope 3 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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debug rhs => _2; // in scope 3 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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let mut _11: u32; // in scope 3 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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let mut _12: bool; // in scope 3 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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scope 4 (inlined core::num::<impl u32>::wrapping_shl) { // at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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debug self => _1; // in scope 4 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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debug rhs => _2; // in scope 4 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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let mut _3: u32; // in scope 4 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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let mut _4: u32; // in scope 4 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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scope 5 {
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scope 6 (inlined core::num::<impl u32>::unchecked_shl) { // at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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debug self => _1; // in scope 6 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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debug rhs => _4; // in scope 6 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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let mut _5: (u32,); // in scope 6 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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let mut _6: u32; // in scope 6 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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let mut _10: u32; // in scope 6 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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scope 7 {
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scope 8 (inlined core::num::<impl u32>::unchecked_shl::conv) { // at $SRC_DIR/core/src/num/mod.rs:LL:COL
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debug x => _6; // in scope 8 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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let mut _7: std::result::Result<u32, std::convert::Infallible>; // in scope 8 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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let mut _9: std::option::Option<u32>; // in scope 8 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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scope 9 {
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scope 10 (inlined <u32 as TryInto<u32>>::try_into) { // at $SRC_DIR/core/src/num/mod.rs:LL:COL
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debug self => _6; // in scope 10 at $SRC_DIR/core/src/convert/mod.rs:LL:COL
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scope 11 (inlined <u32 as TryFrom<u32>>::try_from) { // at $SRC_DIR/core/src/convert/mod.rs:LL:COL
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debug value => _6; // in scope 11 at $SRC_DIR/core/src/convert/mod.rs:LL:COL
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scope 21 (inlined <u32 as Into<u32>>::into) { // at $SRC_DIR/core/src/convert/mod.rs:LL:COL
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debug self => _6; // in scope 21 at $SRC_DIR/core/src/convert/mod.rs:LL:COL
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scope 22 (inlined <u32 as From<u32>>::from) { // at $SRC_DIR/core/src/convert/mod.rs:LL:COL
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debug t => _6; // in scope 22 at $SRC_DIR/core/src/convert/mod.rs:LL:COL
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}
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}
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}
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}
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scope 12 (inlined Result::<u32, Infallible>::ok) { // at $SRC_DIR/core/src/num/mod.rs:LL:COL
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debug self => _7; // in scope 12 at $SRC_DIR/core/src/result.rs:LL:COL
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let _8: u32; // in scope 12 at $SRC_DIR/core/src/result.rs:LL:COL
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scope 13 {
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debug x => _8; // in scope 13 at $SRC_DIR/core/src/result.rs:LL:COL
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}
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}
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scope 14 (inlined #[track_caller] Option::<u32>::unwrap_unchecked) { // at $SRC_DIR/core/src/num/mod.rs:LL:COL
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debug self => _9; // in scope 14 at $SRC_DIR/core/src/option.rs:LL:COL
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let mut _17: &std::option::Option<u32>; // in scope 14 at $SRC_DIR/core/src/option.rs:LL:COL
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scope 15 {
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debug val => _10; // in scope 15 at $SRC_DIR/core/src/option.rs:LL:COL
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}
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scope 16 {
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scope 18 (inlined unreachable_unchecked) { // at $SRC_DIR/core/src/option.rs:LL:COL
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scope 19 {
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scope 20 (inlined unreachable_unchecked::runtime) { // at $SRC_DIR/core/src/intrinsics.rs:LL:COL
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}
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}
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}
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}
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scope 17 (inlined Option::<u32>::is_some) { // at $SRC_DIR/core/src/option.rs:LL:COL
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debug self => _17; // in scope 17 at $SRC_DIR/core/src/option.rs:LL:COL
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}
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}
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}
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}
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}
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}
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}
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}
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}
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}
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bb0: {
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StorageLive(_14); // scope 0 at $DIR/checked_ops.rs:+1:7: +1:23
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StorageLive(_15); // scope 0 at $DIR/checked_ops.rs:+1:7: +1:23
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StorageLive(_13); // scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageLive(_11); // scope 3 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageLive(_6); // scope 3 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageLive(_4); // scope 5 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageLive(_3); // scope 5 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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_3 = const 31_u32; // scope 5 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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_4 = BitAnd(_2, move _3); // scope 5 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageDead(_3); // scope 5 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageLive(_10); // scope 7 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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StorageLive(_5); // scope 7 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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_5 = (_4,); // scope 7 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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_6 = move (_5.0: u32); // scope 7 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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StorageLive(_9); // scope 9 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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StorageLive(_7); // scope 9 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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_7 = Result::<u32, Infallible>::Ok(_6); // scope 11 at $SRC_DIR/core/src/convert/mod.rs:LL:COL
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StorageLive(_8); // scope 9 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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_8 = move ((_7 as Ok).0: u32); // scope 12 at $SRC_DIR/core/src/result.rs:LL:COL
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_9 = Option::<u32>::Some(move _8); // scope 13 at $SRC_DIR/core/src/result.rs:LL:COL
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StorageDead(_8); // scope 9 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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StorageDead(_7); // scope 9 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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StorageLive(_17); // scope 9 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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_10 = move ((_9 as Some).0: u32); // scope 14 at $SRC_DIR/core/src/option.rs:LL:COL
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StorageDead(_17); // scope 9 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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StorageDead(_9); // scope 9 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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StorageDead(_5); // scope 7 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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_11 = unchecked_shl::<u32>(_1, move _10) -> [return: bb1, unwind unreachable]; // scope 7 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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// mir::Constant
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// + span: $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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// + literal: Const { ty: unsafe extern "rust-intrinsic" fn(u32, u32) -> u32 {unchecked_shl::<u32>}, val: Value(<ZST>) }
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}
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bb1: {
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StorageDead(_10); // scope 7 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageDead(_4); // scope 5 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageDead(_6); // scope 3 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageLive(_12); // scope 3 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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_12 = Ge(_2, const _); // scope 3 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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_13 = (move _11, move _12); // scope 3 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageDead(_12); // scope 3 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageDead(_11); // scope 3 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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_14 = (_13.0: u32); // scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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_15 = (_13.1: bool); // scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageDead(_13); // scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageLive(_16); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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_16 = unlikely(_15) -> [return: bb2, unwind unreachable]; // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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// mir::Constant
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// + span: $SRC_DIR/core/src/num/mod.rs:LL:COL
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// + literal: Const { ty: extern "rust-intrinsic" fn(bool) -> bool {unlikely}, val: Value(<ZST>) }
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}
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bb2: {
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switchInt(move _16) -> [0: bb3, otherwise: bb4]; // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
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}
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bb3: {
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_0 = Option::<u32>::Some(_14); // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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goto -> bb5; // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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}
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bb4: {
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_0 = Option::<u32>::None; // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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goto -> bb5; // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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}
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bb5: {
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StorageDead(_16); // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageDead(_15); // scope 0 at $DIR/checked_ops.rs:+1:7: +1:23
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StorageDead(_14); // scope 0 at $DIR/checked_ops.rs:+1:7: +1:23
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return; // scope 0 at $DIR/checked_ops.rs:+2:2: +2:2
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}
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}

‎tests/mir-opt/pre-codegen/checked_ops.ilog2.PreCodegen.after.mir

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// MIR for `ilog2` after PreCodegen
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fn ilog2(_1: u32) -> u32 {
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debug x => _1; // in scope 0 at $DIR/checked_ops.rs:+0:14: +0:15
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let mut _0: u32; // return place in scope 0 at $DIR/checked_ops.rs:+0:25: +0:28
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scope 1 (inlined #[track_caller] core::num::<impl u32>::ilog2) { // at $DIR/checked_ops.rs:19:7: 19:14
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debug self => _1; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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let mut _2: std::option::Option<u32>; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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let mut _3: isize; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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let mut _4: !; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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scope 2 {
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debug log => _0; // in scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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}
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}
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bb0: {
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StorageLive(_2); // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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_2 = core::num::<impl u32>::checked_ilog2(_1) -> bb1; // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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// mir::Constant
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// + span: $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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// + literal: Const { ty: fn(u32) -> Option<u32> {core::num::<impl u32>::checked_ilog2}, val: Value(<ZST>) }
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}
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bb1: {
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_3 = discriminant(_2); // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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switchInt(move _3) -> [1: bb2, otherwise: bb3]; // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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}
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bb2: {
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_0 = ((_2 as Some).0: u32); // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageDead(_2); // scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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return; // scope 0 at $DIR/checked_ops.rs:+2:2: +2:2
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}
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bb3: {
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_4 = core::num::int_log10::panic_for_nonpositive_argument(); // scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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// mir::Constant
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// + span: $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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// + literal: Const { ty: fn() -> ! {core::num::int_log10::panic_for_nonpositive_argument}, val: Value(<ZST>) }
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}
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}

‎tests/mir-opt/pre-codegen/checked_ops.rs

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// compile-flags: -O -Zmir-opt-level=2 -Cdebuginfo=2
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// ignore-debug
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#![crate_type = "lib"]
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#![feature(step_trait)]
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// EMIT_MIR checked_ops.step_forward.PreCodegen.after.mir
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pub fn step_forward(x: u32, n: usize) -> u32 {
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std::iter::Step::forward(x, n)
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}
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// EMIT_MIR checked_ops.checked_shl.PreCodegen.after.mir
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pub fn checked_shl(x: u32, rhs: u32) -> Option<u32> {
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x.checked_shl(rhs)
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}
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// EMIT_MIR checked_ops.ilog2.PreCodegen.after.mir
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pub fn ilog2(x: u32) -> u32 {
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x.ilog2()
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}

‎tests/mir-opt/pre-codegen/checked_ops.step_forward.PreCodegen.after.mir

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// MIR for `step_forward` after PreCodegen
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fn step_forward(_1: u32, _2: usize) -> u32 {
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debug x => _1; // in scope 0 at $DIR/checked_ops.rs:+0:21: +0:22
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debug n => _2; // in scope 0 at $DIR/checked_ops.rs:+0:29: +0:30
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let mut _0: u32; // return place in scope 0 at $DIR/checked_ops.rs:+0:42: +0:45
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scope 1 (inlined <u32 as Step>::forward) { // at $DIR/checked_ops.rs:9:5: 9:35
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debug start => _1; // in scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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debug n => _2; // in scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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let _3: std::option::Option<u32>; // in scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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let mut _4: &std::option::Option<u32>; // in scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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let mut _7: bool; // in scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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let mut _8: u32; // in scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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scope 2 {
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}
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scope 3 (inlined Option::<u32>::is_none) { // at $SRC_DIR/core/src/iter/range.rs:LL:COL
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debug self => _4; // in scope 3 at $SRC_DIR/core/src/option.rs:LL:COL
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let mut _6: bool; // in scope 3 at $SRC_DIR/core/src/option.rs:LL:COL
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scope 4 (inlined Option::<u32>::is_some) { // at $SRC_DIR/core/src/option.rs:LL:COL
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debug self => _4; // in scope 4 at $SRC_DIR/core/src/option.rs:LL:COL
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let mut _5: isize; // in scope 4 at $SRC_DIR/core/src/option.rs:LL:COL
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}
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}
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scope 5 (inlined core::num::<impl u32>::wrapping_add) { // at $SRC_DIR/core/src/iter/range.rs:LL:COL
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debug self => _1; // in scope 5 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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debug rhs => _8; // in scope 5 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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}
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}
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bb0: {
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StorageLive(_7); // scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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StorageLive(_4); // scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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StorageLive(_3); // scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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_3 = <u32 as Step>::forward_checked(_1, _2) -> bb1; // scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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// mir::Constant
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// + span: $SRC_DIR/core/src/iter/range.rs:LL:COL
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// + literal: Const { ty: fn(u32, usize) -> Option<u32> {<u32 as Step>::forward_checked}, val: Value(<ZST>) }
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}
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bb1: {
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_4 = &_3; // scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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StorageLive(_6); // scope 3 at $SRC_DIR/core/src/option.rs:LL:COL
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_5 = discriminant((*_4)); // scope 4 at $SRC_DIR/core/src/option.rs:LL:COL
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_6 = Eq(_5, const 1_isize); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
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_7 = Not(move _6); // scope 3 at $SRC_DIR/core/src/option.rs:LL:COL
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StorageDead(_6); // scope 3 at $SRC_DIR/core/src/option.rs:LL:COL
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StorageDead(_3); // scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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StorageDead(_4); // scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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switchInt(move _7) -> [0: bb3, otherwise: bb2]; // scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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}
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bb2: {
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assert(!const true, "attempt to compute `{} + {}`, which would overflow", const _, const 1_u32) -> bb3; // scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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}
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bb3: {
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StorageDead(_7); // scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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StorageLive(_8); // scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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_8 = _2 as u32 (IntToInt); // scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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_0 = Add(_1, _8); // scope 5 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
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StorageDead(_8); // scope 1 at $SRC_DIR/core/src/iter/range.rs:LL:COL
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return; // scope 0 at $DIR/checked_ops.rs:+2:2: +2:2
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}
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}

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