@@ -81,6 +81,21 @@ static struct nu_spi_var spi5_var = {
81
81
#endif
82
82
};
83
83
84
+ /* Change to QSPI version functions
85
+ *
86
+ * In most cases, we can control degraded QSPI H/W to standard through BSP SPI driver
87
+ * directly as if it is just SPI H/W. However, BSP SPI driver distinguishes among
88
+ * SPI H/W instances in below functions:
89
+ *
90
+ * SPI_Open
91
+ * SPI_Close
92
+ * SPI_SetBusClock
93
+ * SPI_GetBusClock
94
+ *
95
+ * In these cases, we must change to QSPI version instead for QSPI H/W.
96
+ */
97
+ static int spi_is_qspi (spi_t * obj );
98
+
84
99
/* Synchronous version of SPI_ENABLE()/SPI_DISABLE() macros
85
100
*
86
101
* The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI
@@ -207,7 +222,11 @@ void spi_free(spi_t *obj)
207
222
}
208
223
#endif
209
224
210
- SPI_Close ((SPI_T * ) NU_MODBASE (obj -> spi .spi ));
225
+ if (spi_is_qspi (obj )) {
226
+ QSPI_Close ((QSPI_T * ) NU_MODBASE (obj -> spi .spi ));
227
+ } else {
228
+ SPI_Close ((SPI_T * ) NU_MODBASE (obj -> spi .spi ));
229
+ }
211
230
212
231
const struct nu_modinit_s * modinit = get_modinit (obj -> spi .spi , spi_modinit_tab );
213
232
MBED_ASSERT (modinit != NULL );
@@ -242,11 +261,19 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
242
261
243
262
SPI_DISABLE_SYNC (spi_base );
244
263
245
- SPI_Open (spi_base ,
246
- slave ? SPI_SLAVE : SPI_MASTER ,
247
- (mode == 0 ) ? SPI_MODE_0 : (mode == 1 ) ? SPI_MODE_1 : (mode == 2 ) ? SPI_MODE_2 : SPI_MODE_3 ,
248
- bits ,
249
- SPI_GetBusClock (spi_base ));
264
+ if (spi_is_qspi (obj )) {
265
+ QSPI_Open ((QSPI_T * ) spi_base ,
266
+ slave ? QSPI_SLAVE : QSPI_MASTER ,
267
+ (mode == 0 ) ? QSPI_MODE_0 : (mode == 1 ) ? QSPI_MODE_1 : (mode == 2 ) ? QSPI_MODE_2 : QSPI_MODE_3 ,
268
+ bits ,
269
+ QSPI_GetBusClock ((QSPI_T * )spi_base ));
270
+ } else {
271
+ SPI_Open (spi_base ,
272
+ slave ? SPI_SLAVE : SPI_MASTER ,
273
+ (mode == 0 ) ? SPI_MODE_0 : (mode == 1 ) ? SPI_MODE_1 : (mode == 2 ) ? SPI_MODE_2 : SPI_MODE_3 ,
274
+ bits ,
275
+ SPI_GetBusClock (spi_base ));
276
+ }
250
277
// NOTE: Hardcode to be MSB first.
251
278
SPI_SET_MSB_FIRST (spi_base );
252
279
@@ -275,7 +302,11 @@ void spi_frequency(spi_t *obj, int hz)
275
302
276
303
SPI_DISABLE_SYNC (spi_base );
277
304
278
- SPI_SetBusClock ((SPI_T * ) NU_MODBASE (obj -> spi .spi ), hz );
305
+ if (spi_is_qspi (obj )) {
306
+ QSPI_SetBusClock ((QSPI_T * ) NU_MODBASE (obj -> spi .spi ), hz );
307
+ } else {
308
+ SPI_SetBusClock ((SPI_T * ) NU_MODBASE (obj -> spi .spi ), hz );
309
+ }
279
310
}
280
311
281
312
@@ -611,6 +642,13 @@ uint8_t spi_active(spi_t *obj)
611
642
return vec ? 1 : 0 ;
612
643
}
613
644
645
+ static int spi_is_qspi (spi_t * obj )
646
+ {
647
+ SPI_T * spi_base = (SPI_T * ) NU_MODBASE (obj -> spi .spi );
648
+
649
+ return (spi_base == ((SPI_T * ) QSPI0 ) || spi_base == ((SPI_T * ) QSPI1 ));
650
+ }
651
+
614
652
static int spi_writeable (spi_t * obj )
615
653
{
616
654
// Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive
@@ -904,9 +942,7 @@ static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma)
904
942
*/
905
943
static uint32_t spi_fifo_depth (spi_t * obj )
906
944
{
907
- SPI_T * spi_base = (SPI_T * ) NU_MODBASE (obj -> spi .spi );
908
-
909
- if (spi_base == ((SPI_T * ) QSPI0 ) || spi_base == ((SPI_T * ) QSPI1 )) {
945
+ if (spi_is_qspi (obj )) {
910
946
return 8 ;
911
947
}
912
948
0 commit comments