@@ -19,21 +19,23 @@ __attribute__((weak)) void yield() {
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}
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static FspTimer main_timer;
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- // specifying these details as constants makes micros() faster !
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- # define _timer_type AGT_TIMER
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- # define _timer_index 0
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- # define _timer_get_underflow_bit () R_AGT0->AGTCR_b.TUNDF
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- # define _timer_clock_divider TIMER_SOURCE_DIV_8 // dividers 1, 2 and 8 work because _timer_period is < 16-bit. the divider 4 seems not supported: acts as 1
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- # define _timer_clock_freq 24000000UL
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- # define _timer_counts_per_us (_timer_clock_freq / (( 1 << _timer_clock_divider) * 1000000UL ))
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- # define _timer_period (_timer_counts_per_us * 1000UL )
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- # define TIMER_PRIORITY 8
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+ const uint8_t _timer_type = AGT_TIMER;
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+ const uint8_t _timer_index = 0 ;
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+ inline uint8_t _timer_get_underflow_bit () { return R_AGT0-> AGTCR_b . TUNDF ; }
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+ // clock divider 8 works for the Uno R4 and Portenta C33 both because _timer_period is < 16-bit.
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+ // on the Uno R4 the AGT clock is 24 MHz / 8 -> 3000 ticks per ms
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+ // on the Portenta C33 the AGT clock is 50 Mhz / 8 -> 6250 ticks per ms
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+ const timer_source_div_t _timer_clock_divider = TIMER_SOURCE_DIV_8;
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+ uint32_t _timer_period;
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+ const uint8_t TIMER_PRIORITY = 8 ;
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static void timer_micros_callback (timer_callback_args_t __attribute ((unused))* p_args) {
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agt_time_ms += 1 ;
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}
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void startAgt () {
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+ const uint32_t _timer_clock_freq = R_FSP_SystemClockHzGet (_timer_type == AGT_TIMER ? FSP_PRIV_CLOCK_PCLKB : FSP_PRIV_CLOCK_PCLKD);
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+ _timer_period = _timer_clock_freq / ((1 << _timer_clock_divider) * 1000UL );
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main_timer.begin (TIMER_MODE_PERIODIC, _timer_type, _timer_index, _timer_period, 1 , _timer_clock_divider, timer_micros_callback);;
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main_timer.setup_overflow_irq (TIMER_PRIORITY);
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main_timer.open ();
@@ -61,5 +63,5 @@ unsigned long micros() {
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}
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NVIC_EnableIRQ (main_timer.get_cfg ()->cycle_end_irq );
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uint32_t const up_counts = (_timer_period - 1 ) - down_counts;
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- return (ms * 1000 ) + (up_counts / _timer_counts_per_us );
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+ return (ms * 1000 ) + (( up_counts * 1000 ) / _timer_period );
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}
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