From cb8969156f22988f76a8ffcf2a258d0506f140d3 Mon Sep 17 00:00:00 2001
From: Charles Hong <charleshong@berkeley.edu>
Date: Thu, 8 May 2025 14:51:19 -0700
Subject: [PATCH] Fix dffs

---
 dataset_code-complete-iccad2023/Prob053_m2014_q4d_ref.sv     | 2 +-
 dataset_code-complete-iccad2023/Prob104_mt2015_muxdff_ref.sv | 2 +-
 dataset_spec-to-rtl/Prob034_dff8_ref.sv                      | 2 +-
 dataset_spec-to-rtl/Prob053_m2014_q4d_ref.sv                 | 2 +-
 dataset_spec-to-rtl/Prob104_mt2015_muxdff_ref.sv             | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/dataset_code-complete-iccad2023/Prob053_m2014_q4d_ref.sv b/dataset_code-complete-iccad2023/Prob053_m2014_q4d_ref.sv
index ef0b791..aca8694 100644
--- a/dataset_code-complete-iccad2023/Prob053_m2014_q4d_ref.sv
+++ b/dataset_code-complete-iccad2023/Prob053_m2014_q4d_ref.sv
@@ -6,7 +6,7 @@ module RefModule (
 );
 
   initial
-    out = 0;
+    out = 1'hx;
 
   always@(posedge clk) begin
     out <= in ^ out;
diff --git a/dataset_code-complete-iccad2023/Prob104_mt2015_muxdff_ref.sv b/dataset_code-complete-iccad2023/Prob104_mt2015_muxdff_ref.sv
index 0fdac4f..a6de384 100644
--- a/dataset_code-complete-iccad2023/Prob104_mt2015_muxdff_ref.sv
+++ b/dataset_code-complete-iccad2023/Prob104_mt2015_muxdff_ref.sv
@@ -7,7 +7,7 @@ module RefModule (
   output reg Q
 );
 
-  initial Q=0;
+  initial Q=1'hx;
   always @(posedge clk)
     Q <= L ? r_in : q_in;
 
diff --git a/dataset_spec-to-rtl/Prob034_dff8_ref.sv b/dataset_spec-to-rtl/Prob034_dff8_ref.sv
index dea15fb..f9f00f3 100644
--- a/dataset_spec-to-rtl/Prob034_dff8_ref.sv
+++ b/dataset_spec-to-rtl/Prob034_dff8_ref.sv
@@ -6,7 +6,7 @@ module RefModule (
 );
 
   initial
-    q = 8'h0;
+    q = 8'hx;
 
   always @(posedge clk)
     q <= d;
diff --git a/dataset_spec-to-rtl/Prob053_m2014_q4d_ref.sv b/dataset_spec-to-rtl/Prob053_m2014_q4d_ref.sv
index ef0b791..aca8694 100644
--- a/dataset_spec-to-rtl/Prob053_m2014_q4d_ref.sv
+++ b/dataset_spec-to-rtl/Prob053_m2014_q4d_ref.sv
@@ -6,7 +6,7 @@ module RefModule (
 );
 
   initial
-    out = 0;
+    out = 1'hx;
 
   always@(posedge clk) begin
     out <= in ^ out;
diff --git a/dataset_spec-to-rtl/Prob104_mt2015_muxdff_ref.sv b/dataset_spec-to-rtl/Prob104_mt2015_muxdff_ref.sv
index 0fdac4f..a6de384 100644
--- a/dataset_spec-to-rtl/Prob104_mt2015_muxdff_ref.sv
+++ b/dataset_spec-to-rtl/Prob104_mt2015_muxdff_ref.sv
@@ -7,7 +7,7 @@ module RefModule (
   output reg Q
 );
 
-  initial Q=0;
+  initial Q=1'hx;
   always @(posedge clk)
     Q <= L ? r_in : q_in;