diff --git a/.github/issue_template.md b/.github/issue_template.md new file mode 100644 index 00000000000..32a3386b221 --- /dev/null +++ b/.github/issue_template.md @@ -0,0 +1,48 @@ +Note: This is just a template, so feel free to use/remove the unnecessary things + +### Description +- Type: Bug | Enhancement | Question +- Related issue: `#abc` +- Priority: Blocker | Major | Minor + +--------------------------------------------------------------- +## Bug + +**Target** +K64F|?? + +**Toolchain:** +GCC_ARM|ARM|IAR + +**Toolchain version:** + +**mbed-cli version:** +(`mbed --version`) + +**meed-os sha:** +(`git log -n1 --oneline`) + +**DAPLink version:** + +**Expected behavior** + +**Actual behavior** + +**Steps to reproduce** + +---------------------------------------------------------------- +## Enhancement + +**Reason to enhance or problem with existing solution** + +**Suggested enhancement** + +**Pros** + +**Cons** + +----------------------------------------------------------------- + +## Question + +**How to?** diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md new file mode 100644 index 00000000000..ca274f9b597 --- /dev/null +++ b/.github/pull_request_template.md @@ -0,0 +1,39 @@ +Notes: +* Pull requests will not be accepted until the submitter has agreed to the [contributer agreement](https://github.com/ARMmbed/mbed-os/blob/master/CONTRIBUTING.md). +* This is just a template, so feel free to use/remove the unnecessary things + +## Description +A few sentences describing the overall goals of the pull request's commits. + + +## Status +**READY/IN DEVELOPMENT/HOLD** + + +## Migrations +If this PR changes any APIs or behaviors, give a short description of what *API users* should do when this PR is merged. + +YES | NO + + +## Related PRs +List related PRs against other branches: + +branch | PR +------ | ------ +other_pr_production | [link]() +other_pr_master | [link]() + + +## Todos +- [ ] Tests +- [ ] Documentation + + +## Deploy notes +Notes regarding the deployment of this PR. These should note any +required changes in the build environment, tools, compilers, etc. + + +## Steps to test or reproduce +Outline the steps to test or reproduce the PR here. diff --git a/TESTS/host_tests/timing_drift_auto.py b/TESTS/host_tests/timing_drift_auto.py new file mode 100644 index 00000000000..585a534233b --- /dev/null +++ b/TESTS/host_tests/timing_drift_auto.py @@ -0,0 +1,106 @@ +""" +mbed SDK +Copyright (c) 2011-2013 ARM Limited + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + +from mbed_host_tests import BaseHostTest + + +class TimingDriftTest(BaseHostTest): + """ This test is reading single characters from stdio + and measures time between their occurrences. + """ + __result = None + + # This is calculated later: average_drift_max * number of tick events + total_drift_max = None + + average_drift_max = 0.05 + ticks = [] + start_time = None + finish_time = None + dut_seconds_passed = None + total_time = None + total_drift = None + average_drift = None + + def _callback_result(self, key, value, timestamp): + # We should not see result data in this test + self.__result = False + + def _callback_end(self, key, value, timestamp): + """ {{end;%s}}} """ + self.log("Received end event, timestamp: %f" % timestamp) + self.notify_complete(result=self.result(print_stats=True)) + + + def _callback_tick(self, key, value, timestamp): + """ {{tick;%d}}} """ + self.log("tick! %f" % timestamp) + self.ticks.append((key, value, timestamp)) + + + def setup(self): + self.register_callback("end", self._callback_end) + self.register_callback('tick', self._callback_tick) + + + def result(self, print_stats=True): + self.dut_seconds_passed = len(self.ticks) - 1 + + if self.dut_seconds_passed < 1: + if print_stats: + self.log("FAIL: failed to receive at least two tick events") + self.__result = False + return self.__result + + self.total_drift_max = self.dut_seconds_passed * self.average_drift_max + + self.start_time = self.ticks[0][2] + self.finish_time = self.ticks[-1][2] + self.total_time = self.finish_time - self.start_time + self.total_drift = self.total_time - self.dut_seconds_passed + self.average_drift = self.total_drift / self.dut_seconds_passed + + if print_stats: + self.log("Start: %f" % self.start_time) + self.log("Finish: %f" % self.finish_time) + self.log("Total time taken: %f" % self.total_time) + + total_drift_ratio_string = "Total drift/Max total drift: %f/%f" + self.log(total_drift_ratio_string % (self.total_drift, + self.total_drift_max)) + + average_drift_ratio_string = "Average drift/Max average drift: %f/%f" + self.log(average_drift_ratio_string % (self.average_drift, + self.average_drift_max)) + + + if abs(self.total_drift) > self.total_drift_max: + if print_stats: + self.log("FAIL: Total drift exceeded max total drift") + self.__result = False + elif self.average_drift > self.average_drift_max: + if print_stats: + self.log("FAIL: Average drift exceeded max average drift") + self.__result = False + else: + self.__result = True + + return self.__result + + + def teardown(self): + pass \ No newline at end of file diff --git a/TESTS/integration/threaded_blinky/main.cpp b/TESTS/integration/threaded_blinky/main.cpp deleted file mode 100644 index 34e3e201768..00000000000 --- a/TESTS/integration/threaded_blinky/main.cpp +++ /dev/null @@ -1,29 +0,0 @@ -#include "test_env.h" -#include "mbed.h" -#include "rtos.h" - -#if defined(MBED_RTOS_SINGLE_THREAD) - #error [NOT_SUPPORTED] test not supported -#endif - -DigitalOut led1(LED1); - - -void led1_thread(void const *args) { - int count = 0; - while (true) { - Thread::wait(1000); - greentea_send_kv("tick", count); - count++; - led1 = !led1; - } -} - -int main() { - GREENTEA_SETUP(20, "wait_us_auto"); - - Thread thread(led1_thread); - - while (true) { - } -} \ No newline at end of file diff --git a/TESTS/mbed_drivers/lp_timeout/main.cpp b/TESTS/mbed_drivers/lp_timeout/main.cpp index 2f8b5201640..6effbe39090 100644 --- a/TESTS/mbed_drivers/lp_timeout/main.cpp +++ b/TESTS/mbed_drivers/lp_timeout/main.cpp @@ -43,11 +43,15 @@ void lp_timeout_1s_deepsleep(void) { complete = false; - timestamp_t start = us_ticker_read(); + /* + * We use here lp_ticker_read() instead of us_ticker_read() for start and + * end because the microseconds timer might be disable during deepsleep. + */ + timestamp_t start = lp_ticker_read(); lpt.attach(&cb_done, 1); deepsleep(); while (!complete); - timestamp_t end = us_ticker_read(); + timestamp_t end = lp_ticker_read(); /* It takes longer to wake up from deep sleep */ TEST_ASSERT_UINT32_WITHIN(LONG_TIMEOUT, 1000000, end - start); diff --git a/TESTS/mbed_drivers/mem_trace/main.cpp b/TESTS/mbed_drivers/mem_trace/main.cpp new file mode 100644 index 00000000000..5b10b45a621 --- /dev/null +++ b/TESTS/mbed_drivers/mem_trace/main.cpp @@ -0,0 +1,289 @@ +/* + * Copyright (c) 2013-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity/unity.h" +#include "utest/utest.h" +#include "mbed_mem_trace.h" +#include +#include +#include + +#ifndef MBED_MEM_TRACING_ENABLED + #error [NOT_SUPPORTED] test not supported +#endif + +using namespace utest::v1; + +/******************************************************************************/ +/* Helper functions and data structures */ +/******************************************************************************/ + +// This structure keeps data about the various memory allocation operations, +// as traced by 'test_trace_cb' below. +#define TEST_MAX_MEMORY_OPS 10 +// Trace results for all possible operations +typedef struct { + uint8_t op; + void *res; + union { + struct { + size_t arg_size; + } malloc_info; + struct { + void *arg_ptr; + size_t arg_size; + } realloc_info; + struct { + size_t arg_nmemb; + size_t arg_size; + } calloc_info; + struct { + void *arg_ptr; + } free_info; + }; +} mem_trace_data_t; +// Memory operation statistics +typedef struct { + mem_trace_data_t op_data[TEST_MAX_MEMORY_OPS]; + uint32_t total_ops; + bool invalid_op, overflow; +} stats_t; +static stats_t stats; + +// Clear all the memory statistics +static void test_clear_stats() { + memset(&stats, 0, sizeof(stats)); +} + +// Memory tracer callback that records each operation in "stats" (above) +extern "C" void test_trace_cb(uint8_t op, void *res, void *caller, ...) { + va_list va; + mem_trace_data_t *pmem = stats.op_data + stats.total_ops; + + if (stats.total_ops >= TEST_MAX_MEMORY_OPS) { + stats.overflow = true; + return; + } + va_start(va, caller); + pmem->op = op; + pmem->res = res; + switch(op) { + case MBED_MEM_TRACE_MALLOC: + pmem->malloc_info.arg_size = va_arg(va, size_t); + break; + + case MBED_MEM_TRACE_REALLOC: + pmem->realloc_info.arg_ptr = va_arg(va, void *); + pmem->realloc_info.arg_size = va_arg(va, size_t); + break; + + case MBED_MEM_TRACE_CALLOC: + pmem->calloc_info.arg_nmemb = va_arg(va, size_t); + pmem->calloc_info.arg_size = va_arg(va, size_t); + break; + + case MBED_MEM_TRACE_FREE: + pmem->free_info.arg_ptr = va_arg(va, void *); + break; + + default: + stats.invalid_op = true; + } + stats.total_ops ++; + va_end(va); +} + +// Generic sanity checks for the tracer +static void check_sanity(uint32_t expected_ops) { + TEST_ASSERT_FALSE(stats.overflow); + TEST_ASSERT_FALSE(stats.invalid_op); + TEST_ASSERT_EQUAL_UINT32(stats.total_ops, expected_ops); +} + +// Check a "malloc" operation +static void check_malloc_op(const mem_trace_data_t *p, void *expected_res, size_t expected_arg_size) { + TEST_ASSERT_EQUAL_UINT8(p->op, MBED_MEM_TRACE_MALLOC); + TEST_ASSERT_EQUAL_PTR(p->res, expected_res); + TEST_ASSERT_EQUAL_UINT32(p->malloc_info.arg_size, expected_arg_size); +} + +// Check a "free" operation +static void check_free_op(const mem_trace_data_t *p, void *expected_arg_ptr) { + TEST_ASSERT_EQUAL_UINT8(p->op, MBED_MEM_TRACE_FREE); + TEST_ASSERT_EQUAL_PTR(p->free_info.arg_ptr, expected_arg_ptr); +} + +// Check a "realloc" operation +static void check_realloc_op(const mem_trace_data_t *p, void *expected_res, void *expected_arg_ptr, size_t expected_arg_size) { + TEST_ASSERT_EQUAL_UINT8(p->op, MBED_MEM_TRACE_REALLOC); + TEST_ASSERT_EQUAL_PTR(p->res, expected_res); + TEST_ASSERT_EQUAL_UINT32(p->realloc_info.arg_ptr, expected_arg_ptr); + TEST_ASSERT_EQUAL_UINT32(p->realloc_info.arg_size, expected_arg_size); +} + +// Check a "calloc" operation +static void check_calloc_op(const mem_trace_data_t *p, void *expected_res, size_t expected_arg_nmemb, size_t expected_arg_size) { + TEST_ASSERT_EQUAL_UINT8(p->op, MBED_MEM_TRACE_CALLOC); + TEST_ASSERT_EQUAL_PTR(p->res, expected_res); + TEST_ASSERT_EQUAL_UINT32(p->calloc_info.arg_nmemb, expected_arg_nmemb); + TEST_ASSERT_EQUAL_UINT32(p->calloc_info.arg_size, expected_arg_size); +} + +/******************************************************************************/ +/* Tests */ +/******************************************************************************/ + +// Allocate a single buffer, then free it. Check that tracing matches the operations. +static void test_case_single_malloc_free() { + const size_t block_size = 126; + const mem_trace_data_t *pmem = stats.op_data; + + test_clear_stats(); + mbed_mem_trace_set_callback(test_trace_cb); + // Allocate a single memory block + void *p = malloc(block_size); + TEST_ASSERT_NOT_EQUAL(p, NULL); + // Free the memory block + free(p); + // Stop tracing + mbed_mem_trace_set_callback(NULL); + // Check tracer result + check_sanity(2); + check_malloc_op(pmem ++, p, block_size); + check_free_op(pmem, p); +} + +// Test all memory operations (malloc, realloc, free, calloc) +static void test_case_all_memory_ops() { + const size_t malloc_size = 40, realloc_size = 80, nmemb = 25, size = 10; + const mem_trace_data_t *pmem = stats.op_data; + + test_clear_stats(); + mbed_mem_trace_set_callback(test_trace_cb); + // Allocate a single memory block, the realloc it + void *p_malloc = malloc(malloc_size); + TEST_ASSERT_NOT_EQUAL(p_malloc, NULL); + void *p_realloc = realloc(p_malloc, realloc_size); + TEST_ASSERT_NOT_EQUAL(p_realloc, NULL); + // Use calloc() now + void *p_calloc = calloc(nmemb, size); + //TEST_ASSERT_NOT_EQUAL(p_calloc, NULL); + // Free the realloc() pointer first, then the calloc() one + free(p_realloc); + free(p_calloc); + // Stop tracing + mbed_mem_trace_set_callback(NULL); + // Check tracer result + check_sanity(6); + check_malloc_op(pmem ++, p_malloc, malloc_size); + check_realloc_op(pmem ++, p_realloc, p_malloc, realloc_size); + // calloc() calls malloc() internally + check_malloc_op(pmem ++, p_calloc, nmemb * size); + check_calloc_op(pmem ++, p_calloc, nmemb, size); + check_free_op(pmem ++, p_realloc); + check_free_op(pmem, p_calloc); +} + +// Test that tracing is off when using a NULL callback +static void test_case_trace_off() { + const size_t malloc_size = 10; + + test_clear_stats(); + // We don't want any tracing + mbed_mem_trace_set_callback(NULL); + // Allocate a buffer and free it + void *p_malloc = malloc(malloc_size); + TEST_ASSERT_NOT_EQUAL(p_malloc, NULL); + free(p_malloc); + // Check that we didn't trace anything + check_sanity(0); +} + +// Test partial tracing (start tracing, stop tracing, restart later) +static void test_case_partial_trace() { + const size_t malloc_size_1 = 20, malloc_size_2 = 30; + const mem_trace_data_t *pmem = stats.op_data; + + test_clear_stats(); + // Start tracing + mbed_mem_trace_set_callback(test_trace_cb); + // Allocate a buffer + void *p_malloc_1 = malloc(malloc_size_1); + TEST_ASSERT_NOT_EQUAL(p_malloc_1, NULL); + // Disable tracing before freeing the first buffer + mbed_mem_trace_set_callback(NULL); + free(p_malloc_1); + // Allocate another buffer (still not traced) + void *p_malloc_2 = malloc(malloc_size_2); + TEST_ASSERT_NOT_EQUAL(p_malloc_2, NULL); + // Re-enable tracing + mbed_mem_trace_set_callback(test_trace_cb); + // And free the second buffer (this operation should be tracer) + free(p_malloc_2); + // Stop tracing + mbed_mem_trace_set_callback(NULL); + // Check tracer result + check_sanity(2); + check_malloc_op(pmem ++, p_malloc_1, malloc_size_1); + check_free_op(pmem, p_malloc_2); +} + +// Test new/delete tracing +static void test_case_new_delete() { + const mem_trace_data_t *pmem = stats.op_data; + + test_clear_stats(); + // Start tracing + mbed_mem_trace_set_callback(test_trace_cb); + // Test new, new[], delete and delete[] + int *p_int = new int; + int *p_int_array = new int[10]; + delete p_int; + delete[] p_int_array; + // Stop tracing + mbed_mem_trace_set_callback(NULL); + // Check tracer result + check_sanity(4); + check_malloc_op(pmem ++, p_int, sizeof(int)); + check_malloc_op(pmem ++, p_int_array, 10 * sizeof(int)); + check_free_op(pmem ++, p_int); + check_free_op(pmem ++, p_int_array); +} + +static Case cases[] = { + Case("single malloc/free", test_case_single_malloc_free), + Case("all memory operations", test_case_all_memory_ops), + Case("trace off", test_case_trace_off), + Case("partial trace", test_case_partial_trace), + Case("test new/delete", test_case_new_delete) +}; + +static status_t greentea_test_setup(const size_t number_of_cases) { + GREENTEA_SETUP(20, "default_auto"); + return greentea_test_setup_handler(number_of_cases); +} + +static Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); + +int main() { + // Disable stdout buffering to prevent any unwanted allocations + setvbuf(stdout, NULL, _IONBF, 0); + Harness::run(specification); +} + diff --git a/TESTS/mbed_drivers/race_test/main.cpp b/TESTS/mbed_drivers/race_test/main.cpp new file mode 100644 index 00000000000..006c9a12b2f --- /dev/null +++ b/TESTS/mbed_drivers/race_test/main.cpp @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2016-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed.h" +#include "rtos.h" +#include "greentea-client/test_env.h" +#include "unity/unity.h" +#include "utest/utest.h" +#include "SingletonPtr.h" +#include + +using namespace utest::v1; + +#define TEST_STACK_SIZE 1024 +static uint32_t instance_count = 0; + +class TestClass { +public: + TestClass() { + printf("TestClass ctor start\r\n"); + Thread::wait(500); + instance_count++; + printf("TestClass ctor end\r\n"); + } + + void do_something() { + printf("Do something called\r\n"); + } + + ~TestClass() { + instance_count--; + } +}; + +static TestClass* get_test_class() +{ + static TestClass tc; + return &tc; +} + +static SingletonPtr test_class; + +static void main_func_race() +{ + get_test_class(); +} + +static void main_class_race() +{ + test_class->do_something(); +} + +void test_case_func_race() +{ + printf("Running function race test\r\n"); + Callback cb(main_func_race); + Thread *t1 = new Thread(osPriorityNormal, TEST_STACK_SIZE); + Thread *t2 = new Thread(osPriorityNormal, TEST_STACK_SIZE); + + // Start start first thread + t1->start(cb); + // Start second thread while the first is inside the constructor + Thread::wait(250); + t2->start(cb); + + // Wait for the threads to finish + t1->join(); + t2->join(); + + delete t1; + delete t2; + + TEST_ASSERT_EQUAL_UINT32(1, instance_count); + + // Reset instance count + instance_count = 0; +} + +void test_case_class_race() +{ + printf("Running class race test\r\n"); + Callback cb(main_class_race); + Thread *t1 = new Thread(osPriorityNormal, TEST_STACK_SIZE); + Thread *t2 = new Thread(osPriorityNormal, TEST_STACK_SIZE); + + // Start start first thread + t1->start(cb); + // Start second thread while the first is inside the constructor + Thread::wait(250); + t2->start(cb); + + // Wait for the threads to finish + t1->join(); + t2->join(); + + delete t1; + delete t2; + + TEST_ASSERT_EQUAL_UINT32(1, instance_count); + + // Reset instance count + instance_count = 0; +} + +Case cases[] = { + Case("function init race", test_case_func_race), + Case("class init race", test_case_class_race), +}; + +utest::v1::status_t greentea_test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(20, "default_auto"); + return greentea_test_setup_handler(number_of_cases); +} + +Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); + +int main() +{ + Harness::run(specification); +} diff --git a/TESTS/mbed_drivers/stats/main.cpp b/TESTS/mbed_drivers/stats/main.cpp new file mode 100644 index 00000000000..f1cb47830b1 --- /dev/null +++ b/TESTS/mbed_drivers/stats/main.cpp @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2013-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity/unity.h" +#include "utest/utest.h" +#include "mbed_stats.h" +#include +#include + +#if !defined(MBED_HEAP_STATS_ENABLED) || !MBED_HEAP_STATS_ENABLED || defined(__ICCARM__) + #error [NOT_SUPPORTED] test not supported +#endif + +using namespace utest::v1; + +#define ALLOCATION_SIZE_DEFAULT 564 +#define ALLOCATION_SIZE_SMALL 124 +#define ALLOCATION_SIZE_LARGE 790 +#define ALLOCATION_SIZE_FAIL (1024 * 1024 *1024) + +typedef void* (*malloc_cb_t) (uint32_t size); + +static void* thunk_malloc(uint32_t size); +static void* thunk_calloc_1(uint32_t size); +static void* thunk_calloc_4(uint32_t size); +static void* thunk_realloc(uint32_t size); + +malloc_cb_t malloc_thunk_array[] = { + thunk_malloc, + thunk_calloc_1, + thunk_calloc_4, + thunk_realloc, +}; + +void test_case_malloc_free_size() +{ + printf("Initial print to setup stdio buffers\n"); + mbed_stats_heap_t stats_start; + mbed_stats_heap_t stats_current; + void *data; + + mbed_stats_heap_get(&stats_start); + + for (uint32_t i = 0; i < sizeof(malloc_thunk_array) / sizeof(malloc_cb_t); i++) { + + // Allocate memory and assert size change + data = malloc_thunk_array[i](ALLOCATION_SIZE_DEFAULT); + TEST_ASSERT(data != NULL); + mbed_stats_heap_get(&stats_current); + uint32_t increase = stats_current.current_size - stats_start.current_size; + TEST_ASSERT_EQUAL_UINT32(ALLOCATION_SIZE_DEFAULT, increase); + TEST_ASSERT_EQUAL_UINT32(stats_start.total_size + ALLOCATION_SIZE_DEFAULT * (i + 1), stats_current.total_size); + TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_cnt + 1, stats_current.alloc_cnt); + TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_fail_cnt, stats_current.alloc_fail_cnt); + + // Free memory and assert back to starting size + free(data); + mbed_stats_heap_get(&stats_current); + TEST_ASSERT_EQUAL_UINT32(stats_start.current_size, stats_current.current_size); + TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_cnt, stats_current.alloc_cnt); + TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_fail_cnt, stats_current.alloc_fail_cnt); + } +} + +void test_case_allocate_zero() +{ + mbed_stats_heap_t stats_start; + mbed_stats_heap_t stats_current; + void *data; + + mbed_stats_heap_get(&stats_start); + + for (uint32_t i = 0; i < sizeof(malloc_thunk_array) / sizeof(malloc_cb_t); i++) { + + // Allocate memory and assert size change + data = malloc_thunk_array[i](0); + // Return can be NULL + mbed_stats_heap_get(&stats_current); + TEST_ASSERT_EQUAL_UINT32(stats_start.current_size, stats_current.current_size); + TEST_ASSERT_EQUAL_UINT32(stats_start.total_size, stats_current.total_size); + TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_fail_cnt, stats_current.alloc_fail_cnt); + + // Free memory and assert back to starting size + free(data); + mbed_stats_heap_get(&stats_current); + TEST_ASSERT_EQUAL_UINT32(stats_start.current_size, stats_current.current_size); + TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_cnt, stats_current.alloc_cnt); + TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_fail_cnt, stats_current.alloc_fail_cnt); + } +} + +void test_case_allocate_fail() +{ + mbed_stats_heap_t stats_start; + mbed_stats_heap_t stats_current; + void *data; + + mbed_stats_heap_get(&stats_start); + + for (uint32_t i = 0; i < sizeof(malloc_thunk_array) / sizeof(malloc_cb_t); i++) { + + // Trigger a failure by trying to allocate a buffer that won't fit + data = malloc_thunk_array[i](ALLOCATION_SIZE_FAIL); + TEST_ASSERT(data == NULL); + mbed_stats_heap_get(&stats_current); + TEST_ASSERT_EQUAL_UINT32(stats_start.current_size, stats_current.current_size); + TEST_ASSERT_EQUAL_UINT32(stats_start.total_size, stats_current.total_size); + TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_cnt, stats_current.alloc_cnt); + TEST_ASSERT_EQUAL_UINT32(stats_start.alloc_fail_cnt + i + 1, stats_current.alloc_fail_cnt); + } +} + +static void* thunk_malloc(uint32_t size) +{ + printf("Malloc thunk\n"); + return malloc(size); +} + +static void* thunk_calloc_1(uint32_t size) +{ + printf("Calloc thunk 1 byte\n"); + return calloc(size / 1, 1); +} + +static void* thunk_calloc_4(uint32_t size) +{ + printf("Calloc thunk 4 bytes\n"); + return calloc(size / 4, 4); +} + + +static void* thunk_realloc(uint32_t size) +{ + printf("Realloc thunk\n"); + return realloc(NULL, size); +} + +void test_case_realloc_size() +{ + mbed_stats_heap_t stats_start; + mbed_stats_heap_t stats_current; + uint32_t increase; + void *data; + + mbed_stats_heap_get(&stats_start); + + // Allocate memory and assert size change + data = realloc(NULL, ALLOCATION_SIZE_DEFAULT); + TEST_ASSERT(data != NULL); + mbed_stats_heap_get(&stats_current); + increase = stats_current.current_size - stats_start.current_size; + TEST_ASSERT_EQUAL_UINT32(increase, ALLOCATION_SIZE_DEFAULT); + + // Decrease size and assert size change + data = realloc(data, ALLOCATION_SIZE_SMALL); + TEST_ASSERT(data != NULL); + mbed_stats_heap_get(&stats_current); + increase = stats_current.current_size - stats_start.current_size; + TEST_ASSERT_EQUAL_UINT32(increase, ALLOCATION_SIZE_SMALL); + + // Increase size and assert size change + data = realloc(data, ALLOCATION_SIZE_LARGE); + TEST_ASSERT(data != NULL); + mbed_stats_heap_get(&stats_current); + increase = stats_current.current_size - stats_start.current_size; + TEST_ASSERT_EQUAL_UINT32(increase, ALLOCATION_SIZE_LARGE); + + // Free memory and assert back to starting size + free(data); + mbed_stats_heap_get(&stats_current); + TEST_ASSERT_EQUAL_UINT32(stats_start.current_size, stats_current.current_size); +} + +Case cases[] = { + Case("malloc and free size", test_case_malloc_free_size), + Case("allocate size zero", test_case_allocate_zero), + Case("allocation failure", test_case_allocate_fail), + Case("realloc size", test_case_realloc_size), +}; + +utest::v1::status_t greentea_test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(20, "default_auto"); + return greentea_test_setup_handler(number_of_cases); +} + +Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); + +int main() +{ + Harness::run(specification); +} diff --git a/TESTS/mbed_drivers/ticker/main.cpp b/TESTS/mbed_drivers/ticker/main.cpp index f4b26c44260..d615adea43f 100644 --- a/TESTS/mbed_drivers/ticker/main.cpp +++ b/TESTS/mbed_drivers/ticker/main.cpp @@ -21,6 +21,7 @@ using namespace utest::v1; static const int ONE_SECOND_MS = 1000; +static const int total_ticks = 10; DigitalOut led1(LED1); DigitalOut led2(LED2); @@ -28,25 +29,23 @@ DigitalOut led2(LED2); Ticker *ticker1; Ticker *ticker2; +volatile int ticker_count = 0; +volatile bool print_tick = false; + void send_kv_tick() { - static int count = 0; - if (count < 10) { - greentea_send_kv("tick", count); - } else if (count == 10) { - count = 0; - Harness::validate_callback(); + if (ticker_count <= total_ticks) { + print_tick = true; } - count++; } void ticker_callback_0(void) { - static int ticker_count = 0; - if (ticker_count >= ONE_SECOND_MS) { + static int fast_ticker_count = 0; + if (fast_ticker_count >= ONE_SECOND_MS) { send_kv_tick(); - ticker_count = 0; + fast_ticker_count = 0; led1 = !led1; } - ticker_count++; + fast_ticker_count++; } void ticker_callback_1(void) { @@ -78,26 +77,38 @@ void ticker_callback_2_switch_to_1(void) { ticker_callback_2(); } -utest::v1::control_t test_case_1x_ticker() { +void wait_and_print() { + while(ticker_count <= total_ticks) { + if (print_tick) { + print_tick = false; + greentea_send_kv("tick", ticker_count++); + } + } +} + +void test_case_1x_ticker() { led1 = 0; led2 = 0; + ticker_count = 0; ticker1->attach_us(ticker_callback_0, ONE_SECOND_MS); - return CaseTimeout(15 * ONE_SECOND_MS); + wait_and_print(); } -control_t test_case_2x_ticker() { +void test_case_2x_ticker() { led1 = 0; led2 = 0; + ticker_count = 0; ticker1->attach(&ticker_callback_1, 1.0); ticker2->attach(&ticker_callback_2_led, 2.0); - return CaseTimeout(15 * ONE_SECOND_MS); + wait_and_print(); } -utest::v1::control_t test_case_2x_callbacks() { +void test_case_2x_callbacks() { led1 = 0; led2 = 0; + ticker_count = 0; ticker1->attach(ticker_callback_1_switch_to_2, 1.0); - return CaseTimeout(15 * ONE_SECOND_MS); + wait_and_print(); } utest::v1::status_t one_ticker_case_setup_handler_t(const Case *const source, const size_t index_of_case) { @@ -130,7 +141,7 @@ Case cases[] = { }; utest::v1::status_t greentea_test_setup(const size_t number_of_cases) { - GREENTEA_SETUP(60, "wait_us_auto"); + GREENTEA_SETUP((total_ticks + 5) * 3, "timing_drift_auto"); return greentea_test_setup_handler(number_of_cases); } diff --git a/TESTS/mbed_drivers/timeout/main.cpp b/TESTS/mbed_drivers/timeout/main.cpp index 1317475db41..c7aa1aad149 100644 --- a/TESTS/mbed_drivers/timeout/main.cpp +++ b/TESTS/mbed_drivers/timeout/main.cpp @@ -20,43 +20,33 @@ using namespace utest::v1; -Timeout timer; +Timeout timeout; DigitalOut led(LED1); - -namespace { - const int MS_INTERVALS = 1000; -} +volatile int ticker_count = 0; +volatile bool print_tick = false; +static const int total_ticks = 10; +const int ONE_SECOND_US = 1000000; void send_kv_tick() { - static int count = 0; - if (count < 10) { - greentea_send_kv("tick", count); - } else if (count == 10) { - Harness::validate_callback(); + if (ticker_count <= total_ticks) { + timeout.attach_us(send_kv_tick, ONE_SECOND_US); + print_tick = true; } - count++; } -void toggleOff(void); - -void toggleOn(void) { - static int toggle_counter = 0; - if (toggle_counter == MS_INTERVALS) { - led = !led; - send_kv_tick(); - toggle_counter = 0; +void wait_and_print() { + while(ticker_count <= total_ticks) { + if (print_tick) { + print_tick = false; + greentea_send_kv("tick", ticker_count++); + led = !led; + } } - toggle_counter++; - timer.attach_us(toggleOff, 500); -} - -void toggleOff(void) { - timer.attach_us(toggleOn, 500); } -control_t test_case_ticker() { - toggleOn(); - return CaseTimeout(15 * 1000); +void test_case_ticker() { + timeout.attach_us(send_kv_tick, ONE_SECOND_US); + wait_and_print(); } // Test cases @@ -65,7 +55,7 @@ Case cases[] = { }; utest::v1::status_t greentea_test_setup(const size_t number_of_cases) { - GREENTEA_SETUP(20, "wait_us_auto"); + GREENTEA_SETUP(total_ticks + 5, "timing_drift_auto"); return greentea_test_setup_handler(number_of_cases); } diff --git a/TESTS/mbed_drivers/wait_us/main.cpp b/TESTS/mbed_drivers/wait_us/main.cpp index 429f2409cb9..f984c9bdd54 100644 --- a/TESTS/mbed_drivers/wait_us/main.cpp +++ b/TESTS/mbed_drivers/wait_us/main.cpp @@ -18,18 +18,23 @@ #include "greentea-client/test_env.h" #include "utest/utest.h" +/** + NOTE: This test will have a bit of inherent drift due to it being + single-threaded, so having a drift that is non-zero should be ok. However, + it should still be well under the limit. +**/ + + using namespace utest::v1; DigitalOut led(LED1); +volatile bool print_tick = false; +const int ONE_SECOND_US = 1000000; +const int total_ticks = 10; -void test_case_ticker() { - for (int i=0; i < 10; ++i) { - // 10 secs... - for (int j = 0; j < 1000; ++j) { - // 1000 * 1000us = 1 sec - wait_us(1000); - } - led = !led; // Blink +void test_case_ticker() { + for (int i = 0; i <= total_ticks; i++) { + wait_us(ONE_SECOND_US); greentea_send_kv("tick", i); } } @@ -40,7 +45,7 @@ Case cases[] = { }; utest::v1::status_t greentea_test_setup(const size_t number_of_cases) { - GREENTEA_SETUP(20, "wait_us_auto"); + GREENTEA_SETUP(total_ticks + 5, "timing_drift_auto"); return greentea_test_setup_handler(number_of_cases); } diff --git a/TESTS/mbed_hal/lp_ticker/main.cpp b/TESTS/mbed_hal/lp_ticker/main.cpp index 5cf1608bbf6..a634ff6a73a 100644 --- a/TESTS/mbed_hal/lp_ticker/main.cpp +++ b/TESTS/mbed_hal/lp_ticker/main.cpp @@ -69,11 +69,15 @@ void lp_ticker_1s_deepsleep() ticker_remove_event(lp_ticker_data, &delay_event); delay_ts = lp_ticker_read() + 1000000; - timestamp_t start = us_ticker_read(); + /* + * We use here lp_ticker_read() instead of us_ticker_read() for start and + * end because the microseconds timer might be disable during deepsleep. + */ + timestamp_t start = lp_ticker_read(); ticker_insert_event(lp_ticker_data, &delay_event, delay_ts, (uint32_t)&delay_event); deepsleep(); while (!complete); - timestamp_t end = us_ticker_read(); + timestamp_t end = lp_ticker_read(); TEST_ASSERT_UINT32_WITHIN(LONG_TIMEOUT, 1000000, end - start); TEST_ASSERT_TRUE(complete); diff --git a/TESTS/mbedmicro-rtos-mbed/basic/main.cpp b/TESTS/mbedmicro-rtos-mbed/basic/main.cpp index a696020b45d..434e55de442 100644 --- a/TESTS/mbedmicro-rtos-mbed/basic/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/basic/main.cpp @@ -29,25 +29,31 @@ #define STACK_SIZE DEFAULT_STACK_SIZE #endif +#define SIGNAL_PRINT_TICK 0x01 + DigitalOut led1(LED1); -DigitalOut led2(LED2); -void led2_thread(void const *argument) { - static int count = 0; - while (true) { - led2 = !led2; - Thread::wait(1000); - greentea_send_kv("tick", count++); +const int total_ticks = 10; + +void print_tick_thread() { + for (int i = 0; i <= total_ticks; i++) { + Thread::signal_wait(SIGNAL_PRINT_TICK); + greentea_send_kv("tick", i); + led1 = !led1; } } int main() { - GREENTEA_SETUP(15, "wait_us_auto"); - - Thread thread(led2_thread, NULL, osPriorityNormal, STACK_SIZE); - - while (true) { - led1 = !led1; - Thread::wait(500); + GREENTEA_SETUP(total_ticks + 5, "timing_drift_auto"); + + Thread tick_thread(osPriorityNormal, STACK_SIZE); + tick_thread.start(print_tick_thread); + + for (int i = 0; i <= total_ticks; i++) { + Thread::wait(1000); + tick_thread.signal_set(SIGNAL_PRINT_TICK); } + + tick_thread.join(); + GREENTEA_TESTSUITE_RESULT(1); } diff --git a/TESTS/mbedmicro-rtos-mbed/threads/main.cpp b/TESTS/mbedmicro-rtos-mbed/threads/main.cpp index 1fb638b3cd9..cebe9b2f847 100644 --- a/TESTS/mbedmicro-rtos-mbed/threads/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/threads/main.cpp @@ -59,6 +59,12 @@ void increment_with_murder(counter_t* counter) { (*counter)++; } +void self_terminate(Thread *self) { + self->terminate(); + // Code should not get here + TEST_ASSERT(0); +} + // Tests that spawn tasks in different configurations template void test_single_thread() { @@ -97,6 +103,13 @@ void test_serial_threads() { TEST_ASSERT_EQUAL(counter, N); } +void test_self_terminate() { + Thread *thread = new Thread(osPriorityNormal, STACK_SIZE); + thread->start(thread, self_terminate); + thread->join(); + delete thread; +} + utest::v1::status_t test_setup(const size_t number_of_cases) { GREENTEA_SETUP(40, "default_auto"); return verbose_test_setup_handler(number_of_cases); @@ -123,6 +136,8 @@ Case cases[] = { Case("Testing single thread with murder", test_single_thread), Case("Testing parallel threads with murder", test_parallel_threads<3, increment_with_murder>), Case("Testing serial threads with murder", test_serial_threads<10, increment_with_murder>), + + Case("Testing thread self terminate", test_self_terminate), }; Specification specification(test_setup, cases); diff --git a/TESTS/mbedmicro-rtos-mbed/timer/main.cpp b/TESTS/mbedmicro-rtos-mbed/timer/main.cpp index 472d38b4560..035ac31c668 100644 --- a/TESTS/mbedmicro-rtos-mbed/timer/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/timer/main.cpp @@ -6,23 +6,25 @@ #error [NOT_SUPPORTED] test not supported #endif +int total_ticks = 10; +volatile int current_tick = 0; + DigitalOut LEDs[4] = { DigitalOut(LED1), DigitalOut(LED2), DigitalOut(LED3), DigitalOut(LED4) }; void blink(void const *n) { static int blink_counter = 0; - static int count = 0; const int led_id = int(n); LEDs[led_id] = !LEDs[led_id]; - if (++blink_counter == 75) { - greentea_send_kv("tick", count++); + if (++blink_counter == 75 && current_tick <= total_ticks) { + greentea_send_kv("tick", current_tick++); blink_counter = 0; } } int main(void) { - GREENTEA_SETUP(15, "wait_us_auto"); + GREENTEA_SETUP(total_ticks + 5, "timing_drift_auto"); RtosTimer led_1_timer(blink, osTimerPeriodic, (void *)0); RtosTimer led_2_timer(blink, osTimerPeriodic, (void *)1); @@ -33,6 +35,17 @@ int main(void) { led_2_timer.start(100); led_3_timer.start(50); led_4_timer.start(25); + + while(current_tick <= total_ticks) { + Thread::wait(10); + } + + led_4_timer.stop(); + led_3_timer.stop(); + led_2_timer.stop(); + led_1_timer.stop(); + + GREENTEA_TESTSUITE_RESULT(1); Thread::wait(osWaitForever); } diff --git a/TESTS/storage_abstraction/basicAPI/basicAPI.cpp b/TESTS/storage_abstraction/basicAPI/basicAPI.cpp index bc31905e3e4..05fbe6d896f 100644 --- a/TESTS/storage_abstraction/basicAPI/basicAPI.cpp +++ b/TESTS/storage_abstraction/basicAPI/basicAPI.cpp @@ -135,7 +135,7 @@ control_t test_initialize(const size_t call_count) TEST_ASSERT(rc >= ARM_DRIVER_OK); if (rc == ARM_DRIVER_OK) { TEST_ASSERT_EQUAL(1, capabilities.asynchronous_ops); - return (call_count < REPEAT_INSTANCES) ? (CaseTimeout(200) + CaseRepeatAll) : CaseNext; + return (call_count < REPEAT_INSTANCES) ? (CaseTimeout(200) + CaseRepeatAll) : (control_t) CaseNext; } TEST_ASSERT(rc == 1); diff --git a/features/frameworks/utest/source/utest_default_handlers.cpp b/features/frameworks/utest/source/utest_default_handlers.cpp index 7124af76f28..f487e2dcea6 100644 --- a/features/frameworks/utest/source/utest_default_handlers.cpp +++ b/features/frameworks/utest/source/utest_default_handlers.cpp @@ -34,6 +34,7 @@ const handlers_t utest::v1::verbose_continue_handlers = { verbose_case_failure_handler }; +const handlers_t& utest::v1::default_handlers = greentea_abort_handlers; // --- SPECIAL HANDLERS --- static void test_failure_handler(const failure_t failure) { diff --git a/features/frameworks/utest/source/utest_greentea_handlers.cpp b/features/frameworks/utest/source/utest_greentea_handlers.cpp index b55407d098f..bfc6858221d 100644 --- a/features/frameworks/utest/source/utest_greentea_handlers.cpp +++ b/features/frameworks/utest/source/utest_greentea_handlers.cpp @@ -21,6 +21,7 @@ #include "greentea-client/test_env.h" #include "utest/utest_stack_trace.h" #include "utest/utest_serial.h" +#include "mbed_stats.h" using namespace utest::v1; @@ -105,7 +106,10 @@ utest::v1::status_t utest::v1::greentea_test_setup_handler(const size_t number_o void utest::v1::greentea_test_teardown_handler(const size_t passed, const size_t failed, const failure_t failure) { UTEST_LOG_FUNCTION(); + mbed_stats_heap_t heap_stats; verbose_test_teardown_handler(passed, failed, failure); + mbed_stats_heap_get(&heap_stats); + greentea_send_kv("max_heap_usage",heap_stats.max_size); greentea_send_kv(TEST_ENV_TESTCASE_SUMMARY, passed, failed); int result = !(failed || (failure.reason && !(failure.reason & REASON_IGNORE))); GREENTEA_TESTSUITE_RESULT(result); diff --git a/features/frameworks/utest/source/utest_harness.cpp b/features/frameworks/utest/source/utest_harness.cpp index 4246d59726f..52b8513bcd2 100644 --- a/features/frameworks/utest/source/utest_harness.cpp +++ b/features/frameworks/utest/source/utest_harness.cpp @@ -36,7 +36,7 @@ namespace const Case *case_current = NULL; size_t case_index = 0; - control_t case_control = control_t(REPEAT_SETUP_TEARDOWN); + base_control_t case_control = { REPEAT_SETUP_TEARDOWN, TIMEOUT_UNDECLR }; size_t case_repeat_count = 1; void *case_timeout_handle = NULL; @@ -47,8 +47,13 @@ namespace size_t case_failed = 0; size_t case_failed_before = 0; - handlers_t defaults = default_handlers; - handlers_t handlers = defaults; + struct DefaultHandlers : public handlers_t { + DefaultHandlers() : handlers_t(default_handlers) { } + DefaultHandlers(const handlers_t& other) : handlers_t(other) { } + }; + + SingletonPtr defaults; + SingletonPtr handlers; location_t location = LOCATION_UNKNOWN; @@ -110,10 +115,10 @@ bool Harness::run(const Specification& specification) return false; test_cases = specification.cases; test_length = specification.length; - defaults = specification.defaults; - handlers.test_setup = defaults.get_handler(specification.setup_handler); - handlers.test_teardown = defaults.get_handler(specification.teardown_handler); - handlers.test_failure = defaults.get_handler(specification.failure_handler); + *defaults.get() = specification.defaults; + handlers->test_setup = defaults->get_handler(specification.setup_handler); + handlers->test_teardown = defaults->get_handler(specification.teardown_handler); + handlers->test_failure = defaults->get_handler(specification.failure_handler); test_index_of_case = 0; test_passed = 0; @@ -127,16 +132,16 @@ bool Harness::run(const Specification& specification) int setup_status = 0; failure_t failure(REASON_NONE, location); - if (handlers.test_setup) { - setup_status = handlers.test_setup(test_length); + if (handlers->test_setup) { + setup_status = handlers->test_setup(test_length); if (setup_status == STATUS_CONTINUE) setup_status = 0; else if (setup_status < STATUS_CONTINUE) failure.reason = REASON_TEST_SETUP; else if (setup_status > signed(test_length)) failure.reason = REASON_CASE_INDEX; } if (failure.reason != REASON_NONE) { - if (handlers.test_failure) handlers.test_failure(failure); - if (handlers.test_teardown) handlers.test_teardown(0, 0, failure); + if (handlers->test_failure) handlers->test_failure(failure); + if (handlers->test_teardown) handlers->test_teardown(0, 0, failure); test_cases = NULL; exit(1); return true; @@ -150,8 +155,8 @@ bool Harness::run(const Specification& specification) scheduler.post(run_next_case, 0); if (scheduler.run() != 0) { failure.reason = REASON_SCHEDULER; - if (handlers.test_failure) handlers.test_failure(failure); - if (handlers.test_teardown) handlers.test_teardown(0, 0, failure); + if (handlers->test_failure) handlers->test_failure(failure); + if (handlers->test_teardown) handlers->test_teardown(0, 0, failure); test_cases = NULL; exit(1); return true; @@ -167,11 +172,12 @@ void Harness::raise_failure(const failure_reason_t reason) if (test_cases == NULL) return; utest::v1::status_t fail_status = STATUS_ABORT; + if (handlers->test_failure) handlers->test_failure(failure_t(reason, location)); + if (handlers->case_failure) fail_status = handlers->case_failure(case_current, failure_t(reason, location)); + { UTEST_ENTER_CRITICAL_SECTION; - if (handlers.test_failure) handlers.test_failure(failure_t(reason, location)); - if (handlers.case_failure) fail_status = handlers.case_failure(case_current, failure_t(reason, location)); if (fail_status != STATUS_IGNORE) case_failed++; if ((fail_status == STATUS_ABORT) && case_timeout_handle) @@ -183,25 +189,25 @@ void Harness::raise_failure(const failure_reason_t reason) } if (fail_status == STATUS_ABORT || reason & REASON_CASE_SETUP) { - if (handlers.case_teardown && location != LOCATION_CASE_TEARDOWN) { + if (handlers->case_teardown && location != LOCATION_CASE_TEARDOWN) { location_t fail_loc(location); location = LOCATION_CASE_TEARDOWN; - utest::v1::status_t teardown_status = handlers.case_teardown(case_current, case_passed, case_failed, failure_t(reason, fail_loc)); + utest::v1::status_t teardown_status = handlers->case_teardown(case_current, case_passed, case_failed, failure_t(reason, fail_loc)); if (teardown_status < STATUS_CONTINUE) raise_failure(REASON_CASE_TEARDOWN); else if (teardown_status > signed(test_length)) raise_failure(REASON_CASE_INDEX); else if (teardown_status >= 0) case_index = teardown_status - 1; // Restore case failure location once we have dealt with case teardown location = fail_loc; - handlers.case_teardown = NULL; + handlers->case_teardown = NULL; } } if (fail_status == STATUS_ABORT) { test_failed++; failure_t fail(reason, location); location = LOCATION_TEST_TEARDOWN; - if (handlers.test_teardown) handlers.test_teardown(test_passed, test_failed, fail); + if (handlers->test_teardown) handlers->test_teardown(test_passed, test_failed, fail); exit(test_failed); die(); } @@ -217,8 +223,8 @@ void Harness::schedule_next_case() if (case_control.repeat & REPEAT_SETUP_TEARDOWN || !(case_control.repeat & (REPEAT_ON_TIMEOUT | REPEAT_ON_VALIDATE))) { location = LOCATION_CASE_TEARDOWN; - if (handlers.case_teardown) { - utest::v1::status_t status = handlers.case_teardown(case_current, case_passed, case_failed, + if (handlers->case_teardown) { + utest::v1::status_t status = handlers->case_teardown(case_current, case_passed, case_failed, case_failed ? failure_t(REASON_CASES, LOCATION_UNKNOWN) : failure_t(REASON_NONE)); if (status < STATUS_CONTINUE) raise_failure(REASON_CASE_TEARDOWN); else if (status > signed(test_length)) raise_failure(REASON_CASE_INDEX); @@ -297,9 +303,9 @@ void Harness::run_next_case() UTEST_LOG_FUNCTION(); if(case_current < (test_cases + test_length)) { - handlers.case_setup = defaults.get_handler(case_current->setup_handler); - handlers.case_teardown = defaults.get_handler(case_current->teardown_handler); - handlers.case_failure = defaults.get_handler(case_current->failure_handler); + handlers->case_setup = defaults->get_handler(case_current->setup_handler); + handlers->case_teardown = defaults->get_handler(case_current->teardown_handler); + handlers->case_failure = defaults->get_handler(case_current->failure_handler); if (case_current->is_empty()) { location = LOCATION_UNKNOWN; @@ -320,7 +326,7 @@ void Harness::run_next_case() if (setup_repeat & REPEAT_SETUP_TEARDOWN) { location = LOCATION_CASE_SETUP; - if (handlers.case_setup && (handlers.case_setup(case_current, test_index_of_case) != STATUS_CONTINUE)) { + if (handlers->case_setup && (handlers->case_setup(case_current, test_index_of_case) != STATUS_CONTINUE)) { raise_failure(REASON_CASE_SETUP); schedule_next_case(); return; @@ -360,9 +366,9 @@ void Harness::run_next_case() UTEST_LEAVE_CRITICAL_SECTION; } } - else if (handlers.test_teardown) { + else if (handlers->test_teardown) { location = LOCATION_TEST_TEARDOWN; - handlers.test_teardown(test_passed, test_failed, test_failed ? failure_t(REASON_CASES, LOCATION_UNKNOWN) : failure_t(REASON_NONE)); + handlers->test_teardown(test_passed, test_failed, test_failed ? failure_t(REASON_CASES, LOCATION_UNKNOWN) : failure_t(REASON_NONE)); test_cases = NULL; exit(test_failed); } else { diff --git a/features/frameworks/utest/source/utest_shim.cpp b/features/frameworks/utest/source/utest_shim.cpp index ae5b47179a5..6b5ab7596a9 100644 --- a/features/frameworks/utest/source/utest_shim.cpp +++ b/features/frameworks/utest/source/utest_shim.cpp @@ -66,7 +66,7 @@ static volatile utest_v1_harness_callback_t minimal_callback; static volatile utest_v1_harness_callback_t ticker_callback; // Timeout object used to control the scheduling of test case callbacks -Timeout utest_timeout_object; +SingletonPtr utest_timeout_object; static void ticker_handler() { @@ -77,7 +77,9 @@ static void ticker_handler() static int32_t utest_us_ticker_init() { UTEST_LOG_FUNCTION(); - // Ticker scheduler does not require any initialisation so return immediately + // initialize the Timeout object to makes sure it is not initialized in + // interrupt context. + utest_timeout_object.get(); return 0; } static void *utest_us_ticker_post(const utest_v1_harness_callback_t callback, timestamp_t delay_ms) @@ -88,7 +90,7 @@ static void *utest_us_ticker_post(const utest_v1_harness_callback_t callback, ti if (delay_ms) { ticker_callback = callback; // fire the interrupt in 1000us * delay_ms - utest_timeout_object.attach_us(ticker_handler, delay_us); + utest_timeout_object->attach_us(ticker_handler, delay_us); } else { @@ -102,7 +104,7 @@ static int32_t utest_us_ticker_cancel(void *handle) { UTEST_LOG_FUNCTION(); (void) handle; - utest_timeout_object.detach(); + utest_timeout_object->detach(); return 0; } static int32_t utest_us_ticker_run() diff --git a/features/frameworks/utest/source/utest_types.cpp b/features/frameworks/utest/source/utest_types.cpp index f9d6ed55cf2..16a753248eb 100644 --- a/features/frameworks/utest/source/utest_types.cpp +++ b/features/frameworks/utest/source/utest_types.cpp @@ -114,3 +114,22 @@ const char* utest::v1::stringify(utest::v1::status_t status) } return "Unknown Status"; } + + +const utest::v1::base_control_t utest::v1::CaseNext = { REPEAT_NONE, TIMEOUT_NONE }; + +const utest::v1::base_control_t utest::v1::CaseNoRepeat = { REPEAT_NONE, TIMEOUT_UNDECLR }; + +const utest::v1::base_control_t utest::v1::CaseRepeatAll = { REPEAT_ALL, TIMEOUT_UNDECLR }; + +const utest::v1::base_control_t utest::v1::CaseRepeatHandler = { REPEAT_HANDLER, TIMEOUT_UNDECLR }; + +const utest::v1::base_control_t utest::v1::CaseNoTimeout = { REPEAT_UNDECLR, TIMEOUT_NONE }; + +const utest::v1::base_control_t utest::v1::CaseAwait = { REPEAT_UNDECLR, TIMEOUT_FOREVER }; + +// equal to CaeReapeatAll +const utest::v1::base_control_t utest::v1::CaseRepeat = { REPEAT_ALL, TIMEOUT_UNDECLR }; + +// equal to CaseRepeatHandler +const utest::v1::base_control_t utest::v1::CaseRepeatHandlerOnly = { REPEAT_HANDLER, TIMEOUT_UNDECLR }; diff --git a/features/frameworks/utest/utest/utest_default_handlers.h b/features/frameworks/utest/utest/utest_default_handlers.h index 46e907a13a1..965e089c60e 100644 --- a/features/frameworks/utest/utest/utest_default_handlers.h +++ b/features/frameworks/utest/utest/utest_default_handlers.h @@ -185,7 +185,7 @@ namespace v1 { extern const handlers_t selftest_handlers; /// The greentea aborting handlers are the default - const handlers_t default_handlers = greentea_abort_handlers; + extern const handlers_t& default_handlers; } // namespace v1 } // namespace utest diff --git a/features/frameworks/utest/utest/utest_types.h b/features/frameworks/utest/utest/utest_types.h index f7b66825283..37cf64294de 100644 --- a/features/frameworks/utest/utest/utest_types.h +++ b/features/frameworks/utest/utest/utest_types.h @@ -120,6 +120,23 @@ namespace v1 { /// Stringifies a status. const char* stringify(utest::v1::status_t status); + /** POD version of the class control_t. + * It is used to instantiate const control_t objects as PODs + * and prevent them to be included in the final binary. + * @note: control_pod_t can be converted to control_t by copy construction. + */ + struct base_control_t { + repeat_t repeat; + uint32_t timeout; + + repeat_t inline get_repeat() const { + return repeat; + } + uint32_t inline get_timeout() const { + return timeout; + } + }; + /** Control class for specifying test case attributes * * This class encapsulated control information about test cases which, when returned from @@ -148,24 +165,26 @@ namespace v1 { * * In the future, more control information may be added transparently and backwards compatible. */ - struct control_t + struct control_t : private base_control_t { - control_t() : repeat(REPEAT_UNDECLR), timeout(TIMEOUT_UNDECLR) {} + control_t() : base_control_t(make_base_control_t(REPEAT_UNDECLR, TIMEOUT_UNDECLR)) {} control_t(repeat_t repeat, uint32_t timeout_ms) : - repeat(repeat), timeout(timeout_ms) {} + base_control_t(make_base_control_t(repeat, timeout_ms)) {} control_t(repeat_t repeat) : - repeat(repeat), timeout(TIMEOUT_UNDECLR) {} + base_control_t(make_base_control_t(repeat, TIMEOUT_UNDECLR)) {} control_t(uint32_t timeout_ms) : - repeat(REPEAT_UNDECLR), timeout(timeout_ms) {} + base_control_t(make_base_control_t(REPEAT_UNDECLR, timeout_ms)) {} - control_t - inline operator+(const control_t& rhs) const { + control_t(const base_control_t& other) : + base_control_t(other) {} + + friend control_t operator+(const control_t& lhs, const control_t& rhs) { control_t result( - repeat_t(this->repeat | rhs.repeat), - (rhs.timeout == TIMEOUT_NONE) ? rhs.timeout : this->timeout); + repeat_t(lhs.repeat | rhs.repeat), + (rhs.timeout == TIMEOUT_NONE) ? rhs.timeout : lhs.timeout); if (result.timeout != TIMEOUT_NONE && result.timeout > rhs.timeout) { result.timeout = rhs.timeout; @@ -196,25 +215,46 @@ namespace v1 { } private: - repeat_t repeat; - uint32_t timeout; + static base_control_t make_base_control_t(repeat_t repeat, uint32_t timeout) { + base_control_t result = { + repeat, + timeout + }; + return result; + } + friend class Harness; }; + /// @see operator+ in control_t + inline control_t operator+(const base_control_t& lhs, const base_control_t& rhs) { + return control_t(lhs) + control_t(rhs); + } + + /// @see operator+ in control_t + inline control_t operator+(const base_control_t& lhs, const control_t& rhs) { + return control_t(lhs) + rhs; + } + + /// @see operator+ in control_t + inline control_t operator+(const control_t& lhs, const base_control_t& rhs) { + return lhs + control_t(rhs); + } + /// does not repeat this test case and immediately moves on to the next one without timeout - const control_t CaseNext(REPEAT_NONE, TIMEOUT_NONE); + extern const base_control_t CaseNext; /// does not repeat this test case, moves on to the next one - const control_t CaseNoRepeat(REPEAT_NONE); + extern const base_control_t CaseNoRepeat; /// repeats the test case handler with calling teardown and setup handlers - const control_t CaseRepeatAll(REPEAT_ALL); + extern const base_control_t CaseRepeatAll; /// repeats only the test case handler without calling teardown and setup handlers - const control_t CaseRepeatHandler(REPEAT_HANDLER); + extern const base_control_t CaseRepeatHandler; /// No timeout, immediately moves on to the next case, but allows repeats - const control_t CaseNoTimeout(TIMEOUT_NONE); + extern const base_control_t CaseNoTimeout; /// Awaits until the callback is validated and never times out. Use with caution! - const control_t CaseAwait(TIMEOUT_FOREVER); + extern const base_control_t CaseAwait; /// Alias class for asynchronous timeout control in milliseconds inline control_t CaseTimeout(uint32_t ms) { return ms; } @@ -341,8 +381,11 @@ namespace v1 { // deprecations - __deprecated_message("Use CaseRepeatAll instead.") const control_t CaseRepeat = CaseRepeatAll; - __deprecated_message("Use CaseRepeatHandler instead.") const control_t CaseRepeatHandlerOnly = CaseRepeatHandler; + __deprecated_message("Use CaseRepeatAll instead.") + extern const base_control_t CaseRepeat; + + __deprecated_message("Use CaseRepeatHandler instead.") + extern const base_control_t CaseRepeatHandlerOnly; __deprecated_message("Use REASON_NONE instead.") const failure_reason_t FAILURE_NONE = REASON_NONE; __deprecated_message("Use REASON_UNKNOWN instead.") const failure_reason_t FAILURE_UNKNOWN = REASON_UNKNOWN; diff --git a/features/net/FEATURE_IPV4/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7_eth_init.c b/features/net/FEATURE_IPV4/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7_eth_init.c new file mode 100644 index 00000000000..a3fd1b54f49 --- /dev/null +++ b/features/net/FEATURE_IPV4/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7_eth_init.c @@ -0,0 +1,87 @@ +#include "stm32f7xx_hal.h" + +/** + * Override HAL Eth Init function + */ +void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +{ + GPIO_InitTypeDef GPIO_InitStructure; + if (heth->Instance == ETH) { + + /* Enable GPIOs clocks */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + + /** ETH GPIO Configuration + RMII_REF_CLK ----------------------> PA1 + RMII_MDIO -------------------------> PA2 + RMII_MDC --------------------------> PC1 + RMII_MII_CRS_DV -------------------> PA7 + RMII_MII_RXD0 ---------------------> PC4 + RMII_MII_RXD1 ---------------------> PC5 + RMII_MII_RXER ---------------------> PD5 + RMII_MII_TX_EN --------------------> PG11 + RMII_MII_TXD0 ---------------------> PG13 + RMII_MII_TXD1 ---------------------> PG14 + */ + /* Configure PA1, PA2 and PA7 */ + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; + GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Alternate = GPIO_AF11_ETH; + GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7; + HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Configure PC1, PC4 and PC5 */ + GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; + HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Configure PD5 */ + GPIO_InitStructure.Pin = GPIO_PIN_5; + HAL_GPIO_Init(GPIOD, &GPIO_InitStructure); + + /* Configure PG11, PG13 and PG14 */ + GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14; + HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); + + /* Enable the Ethernet global Interrupt */ + HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); + HAL_NVIC_EnableIRQ(ETH_IRQn); + + /* Enable ETHERNET clock */ + __HAL_RCC_ETH_CLK_ENABLE(); + } +} + +/** + * Override HAL Eth DeInit function + */ +void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +{ + if (heth->Instance == ETH) { + /* Peripheral clock disable */ + __HAL_RCC_ETH_CLK_DISABLE(); + + /** ETH GPIO Configuration + RMII_REF_CLK ----------------------> PA1 + RMII_MDIO -------------------------> PA2 + RMII_MDC --------------------------> PC1 + RMII_MII_CRS_DV -------------------> PA7 + RMII_MII_RXD0 ---------------------> PC4 + RMII_MII_RXD1 ---------------------> PC5 + RMII_MII_RXER ---------------------> PD5 + RMII_MII_TX_EN --------------------> PG11 + RMII_MII_TXD0 ---------------------> PG13 + RMII_MII_TXD1 ---------------------> PG14 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_5); + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14); + + /* Disable the Ethernet global Interrupt */ + NVIC_DisableIRQ(ETH_IRQn); + } +} \ No newline at end of file diff --git a/features/net/FEATURE_IPV4/lwip-interface/lwip_stack.c b/features/net/FEATURE_IPV4/lwip-interface/lwip_stack.c index cb67d700962..4e600f012fd 100644 --- a/features/net/FEATURE_IPV4/lwip-interface/lwip_stack.c +++ b/features/net/FEATURE_IPV4/lwip-interface/lwip_stack.c @@ -278,6 +278,11 @@ static int lwip_socket_bind(nsapi_stack_t *stack, nsapi_socket_t handle, nsapi_a return NSAPI_ERROR_PARAMETER; } + if ((s->conn->type == NETCONN_TCP && s->conn->pcb.tcp->local_port != 0) || + (s->conn->type == NETCONN_UDP && s->conn->pcb.udp->local_port != 0)) { + return NSAPI_ERROR_PARAMETER; + } + err_t err = netconn_bind(s->conn, (ip_addr_t *)addr.bytes, port); return lwip_err_remap(err); } @@ -308,6 +313,9 @@ static int lwip_socket_accept(nsapi_stack_t *stack, nsapi_socket_t *handle, nsap { struct lwip_socket *s = (struct lwip_socket *)server; struct lwip_socket *ns = lwip_arena_alloc(); + if (!ns) { + return NSAPI_ERROR_NO_SOCKET; + } err_t err = netconn_accept(s->conn, &ns->conn); if (err != ERR_OK) { diff --git a/features/net/FEATURE_IPV6/nanostack-interface/NanostackInterface.cpp b/features/net/FEATURE_IPV6/nanostack-interface/NanostackInterface.cpp index 23dbc886ba2..adb4f4829f1 100644 --- a/features/net/FEATURE_IPV6/nanostack-interface/NanostackInterface.cpp +++ b/features/net/FEATURE_IPV6/nanostack-interface/NanostackInterface.cpp @@ -368,6 +368,7 @@ void NanostackSocket::data_free_all(void) // No mode requirement NanostackBuffer *buffer = rxBufChain; + rxBufChain = NULL; while (buffer != NULL) { NanostackBuffer *next_buffer = buffer->next; FREE(buffer); diff --git a/features/net/network-socket/TCPServer.cpp b/features/net/network-socket/TCPServer.cpp index c3c23b0bcd7..cd2e82cf6cc 100644 --- a/features/net/network-socket/TCPServer.cpp +++ b/features/net/network-socket/TCPServer.cpp @@ -76,16 +76,19 @@ int TCPServer::accept(TCPSocket *connection) connection->_lock.unlock(); break; - } - - if (NSAPI_ERROR_WOULD_BLOCK == ret) { + } else if (NSAPI_ERROR_WOULD_BLOCK != ret) { + break; + } else { int32_t count; + // Release lock before blocking so other threads + // accessing this object aren't blocked _lock.unlock(); count = _accept_sem.wait(_timeout); _lock.lock(); if (count < 1) { + // Semaphore wait timed out so break out and return ret = NSAPI_ERROR_WOULD_BLOCK; break; } diff --git a/features/net/network-socket/TCPServer.h b/features/net/network-socket/TCPServer.h index f57c5f5ad96..da187f86aa4 100644 --- a/features/net/network-socket/TCPServer.h +++ b/features/net/network-socket/TCPServer.h @@ -41,13 +41,11 @@ class TCPServer : public Socket { * * @param stack Network stack as target for socket */ - TCPServer(NetworkStack *stack); - - template - TCPServer(IF *iface) + template + TCPServer(S *stack) : _pending(0), _accept_sem(0) { - open(iface->get_stack()); + open(stack); } /** Destroy a socket diff --git a/features/storage/FEATURE_STORAGE/TESTS/cfstore/add_del/add_del.cpp b/features/storage/FEATURE_STORAGE/TESTS/cfstore/add_del/add_del.cpp index 32a95581e63..f55a9998cec 100644 --- a/features/storage/FEATURE_STORAGE/TESTS/cfstore/add_del/add_del.cpp +++ b/features/storage/FEATURE_STORAGE/TESTS/cfstore/add_del/add_del.cpp @@ -45,6 +45,8 @@ using namespace utest::v1; +#define CFSTORE_ADD_DEL_MALLOC_SIZE 1024 + static char cfstore_add_del_utest_msg_g[CFSTORE_UTEST_MSG_BUF_SIZE]; #ifdef YOTTA_CFG_CFSTORE_UVISOR @@ -277,11 +279,104 @@ control_t cfstore_add_del_test_04(const size_t call_count) return CaseNext; } +/** @brief Delete and attribute after an internal realloc of the cfstore memory area + * + * This test case goes through the following steps: + * 1. Creates attribute att_1 of size x, and write some data. This causes an internal + * cfstore realloc to allocate heap memory for the attribute. + * 2. Allocates some memory on the heap. Typically, this will be immediately after the + * memory used by cfstore for the KV area. This means that if any cfstore reallocs are + * made to increase size the memory area will have to move. + * 3. Creates attribute att_2 of size y. This causes an internal cfstore realloc to move + * the KV memory area to a new location. + * 4. Delete att_1. This causes an internal realloc to shrink the area and tests that the + * internal data structures that contain pointers to different parts of the KV area + * are updated correctly. + * 5. Allocates some memory on the heap. If the heap has been corrupted, this will likely trigger + * a crash + * + * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors. + */ +control_t cfstore_add_del_test_05_end(const size_t call_count) +{ + char data[] = "some test data"; + char filename[] = "file1"; + char filename2[] = "file2"; + int32_t ret = ARM_DRIVER_ERROR; + void *test_buf1 = NULL; + void *test_buf2 = NULL; + ARM_CFSTORE_DRIVER *cfstoreDriver = &cfstore_driver; + ARM_CFSTORE_KEYDESC keyDesc1; + ARM_CFSTORE_HANDLE_INIT(hkey1); + ARM_CFSTORE_KEYDESC keyDesc2; + ARM_CFSTORE_HANDLE_INIT(hkey2); + ARM_CFSTORE_SIZE count = sizeof(data); + + CFSTORE_FENTRYLOG("%s:entered\n", __func__); + (void) call_count; + + /* step 1 */ + memset(&keyDesc1, 0, sizeof(keyDesc1)); + keyDesc1.drl = ARM_RETENTION_NVM; + keyDesc1.flags.read = true; + keyDesc1.flags.write = true; + ret = cfstoreDriver->Create(filename, 1024, &keyDesc1, hkey1); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_add_del_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: failed to create attribute 1 (ret=%d)\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_add_del_utest_msg_g); + + /* Write data to file */ + ret = cfstoreDriver->Write(hkey1, (const char *)data, &count); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_add_del_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: failed to write to attribute 1 (ret=%d)\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_add_del_utest_msg_g); + + /* step 2 */ + test_buf1 = malloc(CFSTORE_ADD_DEL_MALLOC_SIZE); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_add_del_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: failed to allocate memory (test_buf1=%p)\n", __func__, test_buf1); + TEST_ASSERT_MESSAGE(test_buf1 != NULL, cfstore_add_del_utest_msg_g); + + /* step 3 */ + memset(&keyDesc2, 0, sizeof(keyDesc2)); + keyDesc2.drl = ARM_RETENTION_NVM; + keyDesc2.flags.read = true; + keyDesc2.flags.write = true; + ret = cfstoreDriver->Create(filename2, 1024, &keyDesc2, hkey2); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_add_del_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: failed to create attribute 2 (ret=%d)\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_add_del_utest_msg_g); + + /* Write data to file */ + count = sizeof(data); + ret = cfstoreDriver->Write(hkey2, (const char *)data, &count); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_add_del_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: failed to write to attribute 2 (ret=%d)\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_add_del_utest_msg_g); + + /* step 4 */ + ret = cfstoreDriver->Delete(hkey1); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_add_del_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: failed to delete to attribute 1 (ret=%d)\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_add_del_utest_msg_g); + + ret = cfstoreDriver->Close(hkey1); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_add_del_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: failed to close to attribute 1 (ret=%d)\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_add_del_utest_msg_g); + + /* step 5 */ + test_buf2 = malloc(CFSTORE_ADD_DEL_MALLOC_SIZE); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_add_del_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: failed to allocate memory (test_buf2=%p)\n", __func__, test_buf2); + TEST_ASSERT_MESSAGE(test_buf2 != NULL, cfstore_add_del_utest_msg_g); + + /* clean up */ + ret = cfstoreDriver->Close(hkey2); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_add_del_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: failed to close to attribute 2 (ret=%d)\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_add_del_utest_msg_g); + free(test_buf2); + free(test_buf1); + + return CaseNext; +} /// @cond CFSTORE_DOXYGEN_DISABLE utest::v1::status_t greentea_setup(const size_t number_of_cases) { - GREENTEA_SETUP(100, "default_auto"); + GREENTEA_SETUP(300, "default_auto"); return greentea_test_setup_handler(number_of_cases); } @@ -296,6 +391,8 @@ Case cases[] = { Case("ADD_DEL_test_03_start", cfstore_utest_default_start), Case("ADD_DEL_test_03_end", cfstore_add_del_test_03_end), Case("ADD_DEL_test_04", cfstore_add_del_test_04), + Case("ADD_DEL_test_05_start", cfstore_utest_default_start), + Case("ADD_DEL_test_05_end", cfstore_add_del_test_05_end), }; diff --git a/features/storage/FEATURE_STORAGE/TESTS/cfstore/close/close.cpp b/features/storage/FEATURE_STORAGE/TESTS/cfstore/close/close.cpp index 341915ea0de..5d64b3e3a55 100644 --- a/features/storage/FEATURE_STORAGE/TESTS/cfstore/close/close.cpp +++ b/features/storage/FEATURE_STORAGE/TESTS/cfstore/close/close.cpp @@ -75,14 +75,14 @@ static control_t cfstore_close_test_00(const size_t call_count) * * The is a basic test case which does the following: * - 01. create a key with handle hkey1 - * - 02. write data of hkey + * - 02. write data of hkey1 * - 03. opens KV with 2nd handle, hkey2 * - 04. read data with hkey2 and make sure its the same as that written with hkey1 * - 05. write new data with hkey2 * - 06. delete hkey2 * - 07. close hkey2 * - 08. read hkey1 and make sure the data is the newly written data i.e. the key hasnt - * been deleted yet + * been deleted yet * - 09. try to open KV and make sure unable to do so, as KV is deleting * - 10. close hkey1 * - 11. try to open KV and make sure unable to do so because its now been deleted diff --git a/features/storage/FEATURE_STORAGE/TESTS/cfstore/create/create.cpp b/features/storage/FEATURE_STORAGE/TESTS/cfstore/create/create.cpp index 400e2ea79a8..7090ac7ae14 100644 --- a/features/storage/FEATURE_STORAGE/TESTS/cfstore/create/create.cpp +++ b/features/storage/FEATURE_STORAGE/TESTS/cfstore/create/create.cpp @@ -51,6 +51,7 @@ using namespace utest::v1; #else #define CFSTORE_CREATE_GREENTEA_TIMEOUT_S 60 #endif +#define CFSTORE_CREATE_MALLOC_SIZE 1024 static char cfstore_create_utest_msg_g[CFSTORE_UTEST_MSG_BUF_SIZE]; @@ -272,15 +273,14 @@ static control_t cfstore_create_test_00(const size_t call_count) } -/** @brief +/** @brief Test case to change the value blob size of pre-existing key. * - * Test case to change the value blob size of pre-existing key. * The test does the following: * - creates a cfstore with ~10 entries. - * - for a mid-cfstore entry, grow the value blob size + * - for a mid-cfstore entry, double the value blob size. * - check all the cfstore entries can be read correctly and their * data agrees with the data supplied upon creation. - * - grow the mid-entry value blob size to be ~double the initial size. + * - shrink the mid-entry value blob size to be ~half the initial size. * - check all the cfstore entries can be read correctly and their * data agrees with the data supplied upon creation. * @@ -501,14 +501,13 @@ control_t cfstore_create_test_04_end(const size_t call_count) return CaseNext; } -/**@brief - * - * Test to create ~500 kvs. The amount of data store in the cfstore is as follows: - * - total = (220*500)+(256/64)*500*501/2 500*8 = 8236000 = 8.236M + +/** + * @brief Support function for test cases 05 * - * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors. + * Create enough KV's to consume the whole of available memory */ -control_t cfstore_create_test_05_end(const size_t call_count) +int32_t cfstore_create_test_05_core(const size_t call_count, uint32_t* bytes_stored_ex) { int32_t ret = ARM_DRIVER_ERROR; uint32_t i = 0; @@ -523,7 +522,10 @@ control_t cfstore_create_test_05_end(const size_t call_count) ARM_CFSTORE_DRIVER* drv = &cfstore_driver; CFSTORE_FENTRYLOG("%s:entered\n", __func__); - (void) call_count; + + /* Initialize() */ + cfstore_utest_default_start(call_count); + value_buf = (char*) malloc(max_value_buf_size); CFSTORE_TEST_UTEST_MESSAGE(cfstore_create_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: out of memory.\n", __func__); TEST_ASSERT_MESSAGE(value_buf != NULL, cfstore_create_utest_msg_g); @@ -549,6 +551,48 @@ control_t cfstore_create_test_05_end(const size_t call_count) free(value_buf); CFSTORE_TEST_UTEST_MESSAGE(cfstore_create_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: Uninitialize() call failed.\n", __func__); TEST_ASSERT_MESSAGE(drv->Uninitialize() >= ARM_DRIVER_OK, cfstore_create_utest_msg_g); + if(bytes_stored_ex){ + *bytes_stored_ex = bytes_stored; + } + return ret; +} + + +/** + * @brief Test case to check cfstore recovers from out of memory + * errors without leaking memory + * + * This test case does the following: + * 1. Start loop. + * 2. Initializes CFSTORE. + * 3. Creates as many KVs as required to run out of memory. The number of bytes B + * allocated before running out of memory is recorded. + * 4. For loop i, check that B_i = B_i-1 for i>0 i.e. that no memory has been leaked + * 5. Uninitialize(), which should clean up any cfstore internal state including + * freeing the internal memeory area. + * 6. Repeat from step 1 N times. + */ +control_t cfstore_create_test_05(const size_t call_count) +{ + uint32_t i = 0; + int32_t ret = ARM_DRIVER_ERROR; + uint32_t bytes_stored = 0; + uint32_t bytes_stored_prev = 0; + const uint32_t max_loops = 50; + + CFSTORE_FENTRYLOG("%s:entered\n", __func__); + for(i = 0; i < max_loops; i++) { + ret = cfstore_create_test_05_core(call_count, &bytes_stored); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_create_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: cfstore_create_test_05_core() failed (ret = %d.\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_create_utest_msg_g); + + if(i > 1) { + CFSTORE_TEST_UTEST_MESSAGE(cfstore_create_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: memory leak: stored %d bytes on loop %d, but %d bytes on loop %d .\n", __func__, (int) bytes_stored, (int) i, (int) bytes_stored_prev, (int) i-1); + TEST_ASSERT_MESSAGE(bytes_stored == bytes_stored_prev, cfstore_create_utest_msg_g); + + } + bytes_stored_prev = bytes_stored; + } return CaseNext; } @@ -580,9 +624,8 @@ cfstore_create_key_name_validate_t cfstore_create_test_06_data[] = { /// @endcond -/**@brief - * - * Test whether a key name can be created or not. +/** + * @brief Test whether a key name can be created or not. * * @param key_name * name of the key to create in the store @@ -663,6 +706,109 @@ control_t cfstore_create_test_06_end(const size_t call_count) return CaseNext; } + +/** @brief Test case to change the value blob size of pre-existing + * key in a way that causes the memory area to realloc-ed, + * + * The test is a modified version of cfstore_create_test_01_end which + * - creates KVs, + * - mallocs a memory object on the heap + * - increases the size of one of the existing KVs, causing the + * internal memory area to be realloc-ed. + * + * In detail, the test does the following: + * 1. creates a cfstore with ~10 entries. This causes the configuration + * store to realloc() heap memory for KV storage. + * 2. mallocs a memory object on heap. + * 3. for a mid-cfstore entry, double the value blob size. This will cause the + * cfstore memory area to be realloced. + * 4. check all the cfstore entries can be read correctly and their + * data agrees with the data supplied upon creation. + * 5. shrink the mid-entry value blob size to be ~half the initial size. + * check all the cfstore entries can be read correctly and their + * data agrees with the data supplied upon creation. + * + * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors. + */ +control_t cfstore_create_test_07_end(const size_t call_count) +{ + int32_t ret = ARM_DRIVER_ERROR; + void *test_buf1 = NULL; + ARM_CFSTORE_FMODE flags; + cfstore_kv_data_t* node = NULL; + ARM_CFSTORE_DRIVER* drv = &cfstore_driver; + + CFSTORE_FENTRYLOG("%s:entered\n", __func__); + (void) call_count; + memset(&flags, 0, sizeof(flags)); + + /* step 1 */ + ret = cfstore_test_create_table(cfstore_create_test_01_data_step_01); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_create_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Failed to add cfstore_create_test_01_data_head (ret=%d).\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_create_utest_msg_g); + + /* step 2 */ + test_buf1 = malloc(CFSTORE_CREATE_MALLOC_SIZE); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_create_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: failed to allocate memory (test_buf1=%p)\n", __func__, test_buf1); + TEST_ASSERT_MESSAGE(test_buf1 != NULL, cfstore_create_utest_msg_g); + + /* step 3. find cfstore_create_test_01_data[0] and grow the KV MID_ENTRY_01 to MID_ENTRY_02 */ + ret = cfstore_create_test_KV_change(&cfstore_create_test_01_data[0], &cfstore_create_test_01_data[1]); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_create_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Failed to increase size of KV (ret=%d).\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_create_utest_msg_g); + + /* step 4. Now check that the KVs are all present and correct */ + node = cfstore_create_test_01_data_step_02; + while(node->key_name != NULL) + { + ret = cfstore_test_check_node_correct(node); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_create_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:node (key_name=\"%s\", value=\"%s\") not correct in cfstore\n", __func__, node->key_name, node->value); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_create_utest_msg_g); + node++; + } + /* revert CFSTORE_LOG for more trace */ + CFSTORE_DBGLOG("KV successfully increased in size and other KVs remained unchanged.%s", "\n"); + + /* Shrink the KV from KV MID_ENTRY_02 to MID_ENTRY_03 */ + ret = cfstore_create_test_KV_change(&cfstore_create_test_01_data[1], &cfstore_create_test_01_data[2]); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_create_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Failed to decrease size of KV (ret=%d).\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_create_utest_msg_g); + + /* Step 5. Now check that the KVs are all present and correct */ + node = cfstore_create_test_01_data_step_03; + while(node->key_name != NULL) + { + ret = cfstore_test_check_node_correct(node); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_create_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:node (key_name=\"%s\", value=\"%s\") not correct in cfstore\n", __func__, node->key_name, node->value); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_create_utest_msg_g); + node++; + } + /* revert CFSTORE_LOG for more trace */ + CFSTORE_DBGLOG("KV successfully decreased in size and other KVs remained unchanged.%s", "\n"); + + /* Delete the KV */ + ret = cfstore_test_delete(cfstore_create_test_01_data[2].key_name); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_create_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:failed to delete node(key_name=\"%s\")\n", __func__, node->key_name); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_create_utest_msg_g); + + /* Now check that the KVs are all present and correct */ + node = cfstore_create_test_01_data_step_04; + while(node->key_name != NULL) + { + ret = cfstore_test_check_node_correct(node); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_create_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:node (key_name=\"%s\", value=\"%s\") not correct in cfstore\n", __func__, node->key_name, node->value); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_create_utest_msg_g); + node++; + } + + free(test_buf1); + ret = drv->Uninitialize(); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_create_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: Uninitialize() call failed.\n", __func__); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_create_utest_msg_g); + return CaseNext; +} + + /// @cond CFSTORE_DOXYGEN_DISABLE utest::v1::status_t greentea_setup(const size_t number_of_cases) { @@ -682,10 +828,11 @@ Case cases[] = { Case("CREATE_test_03_end", cfstore_create_test_03_end), Case("CREATE_test_04_start", cfstore_utest_default_start), Case("CREATE_test_04_end", cfstore_create_test_04_end), - Case("CREATE_test_05_start", cfstore_utest_default_start), - Case("CREATE_test_05_end", cfstore_create_test_05_end), + Case("CREATE_test_05", cfstore_create_test_05), Case("CREATE_test_06_start", cfstore_utest_default_start), Case("CREATE_test_06_end", cfstore_create_test_06_end), + Case("CREATE_test_07_start", cfstore_utest_default_start), + Case("CREATE_test_07_end", cfstore_create_test_07_end), }; diff --git a/features/storage/FEATURE_STORAGE/TESTS/cfstore/find/find.cpp b/features/storage/FEATURE_STORAGE/TESTS/cfstore/find/find.cpp index 3d19148b050..7ef3075de9c 100644 --- a/features/storage/FEATURE_STORAGE/TESTS/cfstore/find/find.cpp +++ b/features/storage/FEATURE_STORAGE/TESTS/cfstore/find/find.cpp @@ -428,6 +428,77 @@ control_t cfstore_find_test_06_end(const size_t call_count) CFSTORE_TEST_UTEST_MESSAGE(cfstore_find_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: find_count=%d doesnt match the number of entries in match table = %d.\n", __func__, (int) find_count, (int) (sizeof(cfstore_find_test_06_data_match_results)/sizeof(cfstore_kv_data_t))-1); TEST_ASSERT_MESSAGE(find_count == (sizeof(cfstore_find_test_06_data_match_results)/sizeof(cfstore_kv_data_t))-1, cfstore_find_utest_msg_g); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_find_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: expected ret == ARM_CFSTORE_DRIVER_ERROR_KEY_NOT_FOUND, but ret = %d.\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret == ARM_CFSTORE_DRIVER_ERROR_KEY_NOT_FOUND, cfstore_find_utest_msg_g); + + ret = drv->Uninitialize(); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_find_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: Uninitialize() call failed.\n", __func__); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_find_utest_msg_g); + return CaseNext; +} + +/** + * @brief test case to check Find() with previous NULL pointer works + * + * @return on success returns CaseNext to continue to next test case, otherwise will assert on errors. + */ +control_t cfstore_find_test_07_end(const size_t call_count) +{ + const char* key_name_query = "0123456789abcdef0123456.y*"; + char key_name[CFSTORE_KEY_NAME_MAX_LENGTH+1]; + uint8_t len = CFSTORE_KEY_NAME_MAX_LENGTH+1; + int32_t ret = ARM_DRIVER_ERROR; + int32_t find_count = 0; + ARM_CFSTORE_DRIVER* drv = &cfstore_driver; + ARM_CFSTORE_HANDLE_INIT(next); + cfstore_kv_data_t* node = NULL; + + ret = cfstore_test_create_table(cfstore_find_test_06_data); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_find_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Failed to add cfstore_find_test_06_data table data (ret=%d).\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_find_utest_msg_g); + + while(true) + { + + ret = drv->Find(key_name_query, NULL, next); + if(ret == ARM_CFSTORE_DRIVER_ERROR_KEY_NOT_FOUND) { + /* no more attributes found matching search criteria.*/ + break; + } + + CFSTORE_TEST_UTEST_MESSAGE(cfstore_find_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: Find() failed(ret=%d).\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_find_utest_msg_g); + + len = CFSTORE_KEY_NAME_MAX_LENGTH+1; + ret = drv->GetKeyName(next, key_name, &len); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_find_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: failed to get key name for next (ret=%d).\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_find_utest_msg_g); + + CFSTORE_LOG("%s:Found entry key_name=%s\n", __func__, key_name); + node = cfstore_find_test_06_data_match_results; + while(node->key_name != NULL){ + if(strncmp(node->key_name, key_name, CFSTORE_KEY_NAME_MAX_LENGTH) == 0){ + find_count++; + break; + } + node++; + } + CFSTORE_TEST_UTEST_MESSAGE(cfstore_find_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: unable to find match in match table for %s.\n", __func__, key_name); + TEST_ASSERT_MESSAGE(node->key_name != NULL, cfstore_find_utest_msg_g); + + /* delete the KV so it wont be found when queried is repeated*/ + ret = drv->Delete(next); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_find_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: Delete() on next handled failed(ret=%d).\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_find_utest_msg_g); + + ret = drv->Close(next); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_find_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: Close() on next handled failed(ret=%d).\n", __func__, (int) ret); + TEST_ASSERT_MESSAGE(ret >= ARM_DRIVER_OK, cfstore_find_utest_msg_g); + } + + CFSTORE_TEST_UTEST_MESSAGE(cfstore_find_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: find_count=%d doesnt match the number of entries in match table = %d.\n", __func__, (int) find_count, (int) (sizeof(cfstore_find_test_06_data_match_results)/sizeof(cfstore_kv_data_t))-1); + TEST_ASSERT_MESSAGE(find_count == (sizeof(cfstore_find_test_06_data_match_results)/sizeof(cfstore_kv_data_t))-1, cfstore_find_utest_msg_g); + CFSTORE_TEST_UTEST_MESSAGE(cfstore_find_utest_msg_g, CFSTORE_UTEST_MSG_BUF_SIZE, "%s:Error: expected ret == ret == ARM_CFSTORE_DRIVER_ERROR_KEY_NOT_FOUND, but ret = %d.\n", __func__, (int) ret); TEST_ASSERT_MESSAGE(ret == ARM_CFSTORE_DRIVER_ERROR_KEY_NOT_FOUND, cfstore_find_utest_msg_g); @@ -458,6 +529,8 @@ Case cases[] = { Case("FIND_test_05_end", cfstore_find_test_05_end), Case("FIND_test_06_start", cfstore_utest_default_start), Case("FIND_test_06_end", cfstore_find_test_06_end), + Case("FIND_test_07_start", cfstore_utest_default_start), + Case("FIND_test_07_end", cfstore_find_test_07_end), }; diff --git a/features/storage/FEATURE_STORAGE/TESTS/cfstore/flush/flush.cpp b/features/storage/FEATURE_STORAGE/TESTS/cfstore/flush/flush.cpp index 3aa9da5baa9..c752f3a1bbf 100644 --- a/features/storage/FEATURE_STORAGE/TESTS/cfstore/flush/flush.cpp +++ b/features/storage/FEATURE_STORAGE/TESTS/cfstore/flush/flush.cpp @@ -585,8 +585,19 @@ static void cfstore_flush_fsm_state_set(cfstore_fsm_t* fsm, cfstore_flush_fsm_st static control_t cfstore_flush_test_02_k64f(void) { cfstore_flush_ctx_t* ctx = cfstore_flush_ctx_get(); + ARM_CFSTORE_CAPABILITIES caps; + const ARM_CFSTORE_DRIVER* drv = &cfstore_driver; CFSTORE_FENTRYLOG("%s:entered: \r\n", __func__); + memset(&caps, 0, sizeof(caps)); + caps = drv->GetCapabilities(); + if(caps.asynchronous_ops == false){ + /* This is a async mode only test. If this test is not built for sync mode, then skip testing return true + * This means the test will conveniently pass when run in CI as part of async mode testing */ + CFSTORE_LOG("*** Skipping test as binary built for flash journal sync mode, and this test is async-only%s", "\n"); + return CaseNext; + } + cfstore_flush_ctx_init(ctx); cfstore_flush_fsm_state_set(&ctx->fsm, cfstore_flush_fsm_state_initializing, ctx); return CaseTimeout(CFSTORE_FLUSH_GREENTEA_TIMEOUT_S*1000); diff --git a/features/storage/FEATURE_STORAGE/cfstore/source/cfstore_config.h b/features/storage/FEATURE_STORAGE/cfstore/source/cfstore_config.h index abe9c623b3d..fe7b76f702f 100644 --- a/features/storage/FEATURE_STORAGE/cfstore/source/cfstore_config.h +++ b/features/storage/FEATURE_STORAGE/cfstore/source/cfstore_config.h @@ -56,4 +56,10 @@ #define CFSTORE_CONFIG_BACKEND_FLASH_ENABLED #endif +// todo: fixup for storage driver using more than the STORAGE_xxx namespace: +#if defined DEVICE_STORAGE_CONFIG_HARDWARE_MTD_K64F_ASYNC_OPS +#define CFSTORE_STORAGE_DRIVER_CONFIG_HARDWARE_MTD_ASYNC_OPS DEVICE_STORAGE_CONFIG_HARDWARE_MTD_K64F_ASYNC_OPS +#endif + + #endif /*__CFSTORE_CONFIG_H*/ diff --git a/features/storage/FEATURE_STORAGE/cfstore/source/cfstore_debug.h b/features/storage/FEATURE_STORAGE/cfstore/source/cfstore_debug.h index fe236ddf1de..d9f096fae91 100644 --- a/features/storage/FEATURE_STORAGE/cfstore/source/cfstore_debug.h +++ b/features/storage/FEATURE_STORAGE/cfstore/source/cfstore_debug.h @@ -28,6 +28,7 @@ }while(0); #define noCFSTORE_DEBUG +//#define CFSTORE_DEBUG #ifdef CFSTORE_DEBUG extern uint32_t cfstore_optDebug_g; diff --git a/features/storage/FEATURE_STORAGE/cfstore/source/cfstore_test.c b/features/storage/FEATURE_STORAGE/cfstore/source/cfstore_test.c index 700e4e4b253..af164de3e70 100644 --- a/features/storage/FEATURE_STORAGE/cfstore/source/cfstore_test.c +++ b/features/storage/FEATURE_STORAGE/cfstore/source/cfstore_test.c @@ -380,7 +380,6 @@ int32_t cfstore_test_delete_all(void) /* as expected, no more keys have been found by the Find()*/ ret = ARM_DRIVER_OK; } - // todo: find portable format specification CFSTORE_FENTRYLOG("%s:exiting (ret=%ld).\r\n", __func__, ret); CFSTORE_FENTRYLOG("%s:exiting (ret=%d).\r\n", __func__, (int) ret); return ret; } diff --git a/features/storage/FEATURE_STORAGE/cfstore/source/configuration_store.c b/features/storage/FEATURE_STORAGE/cfstore/source/configuration_store.c index 2c18dcd8a6e..efcfff34e68 100644 --- a/features/storage/FEATURE_STORAGE/cfstore/source/configuration_store.c +++ b/features/storage/FEATURE_STORAGE/cfstore/source/configuration_store.c @@ -242,7 +242,7 @@ static int32_t cfstore_fsm_state_set(cfstore_fsm_t* fsm, cfstore_fsm_state_t new static int32_t cfstore_get_key_name_ex(cfstore_area_hkvt_t *hkvt, char* key_name, uint8_t *key_name_len); -/* Walking Area HKVT's While Inserted a New HKVT: +/* Walking Area HKVT's While Inserting a New HKVT: * Implementation Note 1 [NOTE1] * * The implementation must address the following problem: @@ -259,11 +259,6 @@ static int32_t cfstore_get_key_name_ex(cfstore_area_hkvt_t *hkvt, char* key_name * - The Find() walk is terminated when the hkvt header pointer is found to * point to cfstore_ctx_g.area_0_tail i.e. when this arises then the * iterator knows its come to the end of the hkvt's in the area. - * - When inserting a new KV, the last operation to be performed is to - * update cfstore_ctx_g.area_0_tail to point to the new tail. This - * operation also reveals the new KV to other operations including - * the Find(). All the header, key, value and tail data for the - * HKVT must be setup correctly before the tail pointer is updated. * * Memory Management (todo: future support) * Implementation Note 2 [NOTE2] @@ -336,8 +331,9 @@ static int32_t cfstore_get_key_name_ex(cfstore_area_hkvt_t *hkvt, char* key_name * to facilitate reading/writing to flash. * - accessed in app & intr context; hence needs CS protection. * - * @param area_0_end - * pointer to end area_0 of area_0 memblock (last memory address). + * @param area_0_len + * length of the area used for storing KVs, including padding to + * round to nearest program unit * * @param rw_area0_lock * lock used to make CS re-entrant e.g. only 1 flush operation can be @@ -372,6 +368,7 @@ typedef struct cfstore_ctx_t ARM_POWER_STATE power_state; uint8_t *area_0_head; uint8_t *area_0_tail; + size_t area_0_len; cfstore_fsm_t fsm; int32_t status; @@ -440,11 +437,11 @@ typedef struct cfstore_flash_journal_error_code_node /* * Globals */ -#ifndef STORAGE_DRIVER_CONFIG_HARDWARE_MTD_ASYNC_OPS +#ifndef CFSTORE_STORAGE_DRIVER_CONFIG_HARDWARE_MTD_ASYNC_OPS static ARM_CFSTORE_CAPABILITIES cfstore_caps_g = { .asynchronous_ops = 1, .uvisor_support_enabled = 0 }; #else -static ARM_CFSTORE_CAPABILITIES cfstore_caps_g = { .asynchronous_ops = STORAGE_DRIVER_CONFIG_HARDWARE_MTD_ASYNC_OPS, .uvisor_support_enabled = 0 }; -#endif /* STORAGE_DRIVER_CONFIG_HARDWARE_MTD_ASYNC_OPS */ +static ARM_CFSTORE_CAPABILITIES cfstore_caps_g = { .asynchronous_ops = CFSTORE_STORAGE_DRIVER_CONFIG_HARDWARE_MTD_ASYNC_OPS, .uvisor_support_enabled = 0 }; +#endif /* CFSTORE_STORAGE_DRIVER_CONFIG_HARDWARE_MTD_ASYNC_OPS */ static const ARM_DRIVER_VERSION cfstore_driver_version_g = { .api = ARM_CFSTORE_API_VERSION, .drv = ARM_CFSTORE_DRV_VERSION }; @@ -573,16 +570,6 @@ static void cfstore_client_notify_data_init(cfstore_client_notify_data_t* data, * cfstore_ctx_t methods */ -/* @brief helper function to reset cfstore_ctx_g state when out of memory is received from malloc */ -static void cfstore_ctx_reset(cfstore_ctx_t* ctx) -{ - CFSTORE_ASSERT(ctx!= NULL); - CFSTORE_INIT_LIST_HEAD(&ctx->file_list); - ctx->area_0_head = NULL; - ctx->area_0_tail = NULL; - return; -} - /* @brief helper function to report whether the initialisation flag has been set in the cfstore_ctx_g */ static bool cfstore_ctx_is_initialised(cfstore_ctx_t* ctx) { @@ -602,8 +589,15 @@ static inline cfstore_ctx_t* cfstore_ctx_get(void) #endif } -/* @brief helper function to compute the size of the sram area in bytes */ -static ARM_CFSTORE_SIZE cfstore_ctx_get_area_len(void) +/** @brief helper function to compute the total size of the KVs stored in the + * sram area in bytes. + * + * Note: + * - sram_area_size = cfstore_ctx_get_kv_total_len() + padding + * - padding rounds up cfstore_ctx_get_kv_total_len() to + * be a multiple of flash program_unit size. + */ +static ARM_CFSTORE_SIZE cfstore_ctx_get_kv_total_len(void) { ARM_CFSTORE_SIZE size = 0; cfstore_ctx_t* ctx = cfstore_ctx_get(); @@ -732,7 +726,7 @@ void *cfstore_realloc(void *ptr, ARM_CFSTORE_SIZE size) #endif /* CFSTORE_YOTTA_CFG_CFSTORE_SRAM_ADDR */ -#ifdef TARGET_LIKE_X86_LINUX_NATIVE +#ifdef CFSTORE_TARGET_LIKE_X86_LINUX_NATIVE static inline void cfstore_critical_section_init(CFSTORE_LOCK* lock){ *lock = 0; } static inline void cfstore_critical_section_lock(CFSTORE_LOCK* lock, const char* tag){ (void) tag; __sync_fetch_and_add(lock, 1); } static inline void cfstore_critical_section_unlock(CFSTORE_LOCK* lock, const char* tag){(void) tag; __sync_fetch_and_sub(lock, 1); } @@ -818,14 +812,14 @@ static CFSTORE_INLINE int32_t cfstore_hkvt_refcount_inc(cfstore_area_hkvt_t* hkv return ret; } -#endif /* TARGET_LIKE_X86_LINUX_NATIVE */ +#endif /* CFSTORE_TARGET_LIKE_X86_LINUX_NATIVE */ /* * security/permissions helper functions */ -#ifdef noCFG_CFSTORE_UVISOR +#ifdef YOTTA_CFG_CFSTORE_UVISOR /** * @brief check that a client (cfstore-uvisor client box) is the "owner" of the * KV. Owner means the client that can create or created the KV. This is @@ -921,7 +915,7 @@ static int32_t cfstore_is_client_kv_owner(const char* key_name, int32_t* cfstore { CFSTORE_FENTRYLOG("%s:entered\n", __func__); /* - #ifdef YOTTA_CFG_CFSTORE_UVISOR +#ifdef YOTTA_CFG_CFSTORE_UVISOR return cfstore_uvisor_is_client_kv_owner(key_name, cfstore_uvisor_box_id); #else return ARM_DRIVER_OK; @@ -956,7 +950,7 @@ static bool cfstore_is_kv_client_deletable(cfstore_file_t* file) return true; } -#ifdef YOTTA_CFG_CFSTORE_UVISOR_to_debug +#ifdef YOTTA_CFG_CFSTORE_UVISOR /* @brief helper function to determine whether this cfstore-uvisor client box can read a given KV */ static bool cfstore_is_kv_client_readable(cfstore_area_hkvt_t* hkvt) { @@ -1038,7 +1032,7 @@ static bool cfstore_is_kv_client_executable(cfstore_area_hkvt_t* hkvt) } return bret; } -#endif // YOTTA_CFG_CFSTORE_UVISOR_to_debug +#endif /* YOTTA_CFG_CFSTORE_UVISOR */ /* @brief helper function to determine whether this client can read a given KV */ static bool cfstore_is_kv_client_readable(cfstore_area_hkvt_t* hkvt) @@ -1306,7 +1300,29 @@ static int32_t cfstore_get_next_hkvt(cfstore_area_hkvt_t* prev, cfstore_area_hkv static CFSTORE_INLINE void cfstore_hkvt_dump(cfstore_area_hkvt_t* hkvt, const char* tag); -/* set the tail pointer */ +/** @brief Set the context tail pointer area_0_tail to point to the end of the + * last KV in the memory area. + * + * This function walks hkvt entries in the KV area to find the memory + * address after the end of the last KV, and then sets the area tail pointer + * area_0_tail to that address. The function therefore relies on the + * head, key, value, tail fields being correct. + * + * Notes: + * - This function should only be called after the memory area is loaded from + * flash and the area_0_tail pointer needs setting. The only way to do this + * (at the present time) is to walk the list of KVs, which is what this function + * does. The only other place the code sets area_0_tail is cfstore_realloc_ex(), + * and this state of affairs shouldnt change i.e. its unnecessary for + * other functions to change area_0_tail. + * - When loading the area_0 image from falsh, cfstore_realloc_ex() is used + * to allocate the memory with ctx->expected_blob_size as the size. Thus + * area_0_tail will be initially set to + * area_0_tail = area_0_head + expected_blob_size (1) + * and thereby may include padding used to align the area size to a + * flash program unit boundary. cfstore_flash_set_tail() is used to + * set area_0_tail correctly. + */ static int32_t cfstore_flash_set_tail(void) { int32_t ret = ARM_DRIVER_ERROR; @@ -1315,20 +1331,31 @@ static int32_t cfstore_flash_set_tail(void) uint8_t* tail = NULL; cfstore_area_hkvt_t hkvt; - /* walk the area to find the last KV */ CFSTORE_FENTRYLOG("%s:entered: \n", __func__); CFSTORE_ASSERT(ctx != NULL); cfstore_hkvt_init(&hkvt); + + /* Check for cases where the tail pointer is already set correctly + * e.g. where the area is of zero length */ + if(cfstore_ctx_get_kv_total_len() == 0) { + /* tail pointer already set correctly */ + return ARM_DRIVER_OK; + } ptr = ctx->area_0_head; - /* ctx->area_0_tail has been set to the end of the sram area allocated, but this is now refined so - * as to point to the end of the last KV */ tail = ctx->area_0_tail; - while(ptr < tail) { + while(ptr <= tail) { + CFSTORE_FENTRYLOG("%s:ptr=%p, tail=%p: \n", __func__, ptr, tail); hkvt = cfstore_get_hkvt_from_head_ptr(ptr); + if(cfstore_hkvt_is_valid(&hkvt, tail) == false) { + CFSTORE_ERRLOG("%s:Error:found invalid hkvt entry in area\n", __func__); + break; + } cfstore_hkvt_dump(&hkvt, __func__); - /* when the length between the hkvt.tail and tail (set to the end of the area including padding) + /* when the length between the hkvt.tail and tail * is less than the minimum KV length then we have found the last KV, and can set the - * area_0_tail correctly to the end of the last KV */ + * area_0_tail correctly to the end of the last KV. This works OK for the present support + * (where flash_program_unit ~ sizeof(cfstore_area_header_t)) but may need + * revisiting where flash_program_unit > sizeof(cfstore_area_header_t) */ if((uint32_t)(tail - hkvt.tail) < sizeof(cfstore_area_header_t)){ /* ptr is last KV in area as there isn't space for another header */ ctx->area_0_tail = hkvt.tail; @@ -1340,6 +1367,116 @@ static int32_t cfstore_flash_set_tail(void) return ret; } + +/** @brief Function to realloc the SRAM area used to store KVs. + * + * This function consolidates the code needed to: + * - realloc the memory + * - when the start of the SRAM area moves, update data structures + * which point into SRAM area (e.g. open files cfstore_file_t head pointers). + * + * The function assumes: + * - the cfstore_file_t::head pointers are valid i.e. point to the + * correct locations in the KV area for each file. + * + * @param size + * total KV size in bytes storage required. Note this does not include + * padding to round up to the nearest multiple of flash program unit + * as this is computed and added in this function. + * + * @param allocated_size + * total size in bytes that was allocated (value returned to caller). + * This may be larger than the requested size due to rounding to align with a + * flash program unit boundary. + */ +static int32_t cfstore_realloc_ex(ARM_CFSTORE_SIZE size, uint64_t *allocated_size) +{ + uint8_t* ptr = NULL; + int32_t ret = ARM_DRIVER_ERROR; + int32_t len_diff = 0; + cfstore_ctx_t* ctx = cfstore_ctx_get(); + cfstore_file_t* file; + cfstore_list_node_t* node; + cfstore_list_node_t* file_list = &ctx->file_list; + ARM_CFSTORE_SIZE total_kv_size = size; + + /* Switch on the size of the sram area to create: + * - if size > 0 (but may be shrinking) then use REALLOC. + * - if size == 0 then the area is being deleted so free the memory + * Note: + * - realloc can return NULL when the last KV is deleted + * - It also appears that realloc can return non-zero ptr when size = 0. + * Hence for this case free() is used. + */ + CFSTORE_FENTRYLOG("%s:entered:\n", __func__); + CFSTORE_TP(CFSTORE_TP_MEM, "%s:cfstore_ctx_g.area_0_head=%p, cfstore_ctx_g.area_0_tail=%p, cfstore_ctx_g.area_0_len=%d, size=%d, \n", __func__, ctx->area_0_head, ctx->area_0_tail, (int) ctx->area_0_len, (int) size); + + if(size > 0) + { + /* In the general case (size % program_unit > 0). The new area_0 size is + * aligned to a flash program_unit boundary to facilitate r/w to flash + * and so the memory realloc size is calculated to align, as follows */ + if(size % cfstore_ctx_get_program_unit(ctx) > 0){ + size += (cfstore_ctx_get_program_unit(ctx) - (size % cfstore_ctx_get_program_unit(ctx))); + } + + ptr = (uint8_t*) CFSTORE_REALLOC((void*) ctx->area_0_head, size); + if(ptr == NULL){ + CFSTORE_ERRLOG("%s:Error: unable to allocate memory (size=%d)\n", __func__, (int) size); + /* realloc() has failed to allocate the required memory object. If previously + * allocation has been made, the old memory object remains allocated. On error, the client + * is expected to clean up including making a call to Uninitialize() which will free the + * old memory object. + */ + return ARM_CFSTORE_DRIVER_ERROR_OUT_OF_MEMORY; + } + /* check realloc() hasn't move area in memory from cfstore_ctx_g.area_0_head */ + if(ptr != ctx->area_0_head){ + /* realloc() has moved the area in memory */ + CFSTORE_TP(CFSTORE_TP_MEM, "%s: realloc() has moved memory area and area_0_head ptr must change. old cfstore_ctx_g.area_0_head=%p, new head ptr=%p)\n", __func__, ctx->area_0_head, ptr); + + /* now have to walk the file list updating head pointers to point into the realloc-ed + * To begin with, leave the relative position of the file pointers unaltered */ + node = file_list->next; + while(node != file_list){ + file = (cfstore_file_t*) node; + file->head = (uint8_t *) (file->head - ctx->area_0_head); + file->head = (uint8_t *) ((int32_t) file->head + (int32_t) ptr); + node = node->next; + } + ctx->area_0_head = ptr; + } + + /* If the area is growing then zero the new space at the end of the area */ + len_diff = size - (int32_t) ctx->area_0_len; + if(len_diff > 0) { + memset(ptr + ctx->area_0_len, 0, len_diff); + } + /* Set area_0_tail to be the memory address after the end of the last KV in the memory area. + * This is the only place that area_0_tail should be changed, apart from cfstore_flash_set_tail() + * which is only called when attributes are loaded from flash. + */ + ctx->area_0_len = size; + ctx->area_0_tail = ptr + total_kv_size; + if(allocated_size != NULL) { + *allocated_size = size; + } + } + else + { + /* size = 0 so delete the memory */ + CFSTORE_FREE((void*) ctx->area_0_head); + ctx->area_0_head = NULL; + ctx->area_0_tail = NULL; + ctx->area_0_len = 0; + } + CFSTORE_TP(CFSTORE_TP_MEM, "%s:cfstore_ctx_g.area_0_head=%p, cfstore_ctx_g.area_0_tail=%p\n", __func__, ctx->area_0_head, ctx->area_0_tail); + ret = ARM_DRIVER_OK; + return ret; + +} + + #ifdef CFSTORE_CONFIG_BACKEND_FLASH_ENABLED /* @@ -1464,7 +1601,6 @@ static int32_t cfstore_fsm_init_on_entry(void* context) CFSTORE_FENTRYLOG("%s:entered\n", __func__); ret = FlashJournal_initialize(&ctx->jrnl, drv, &FLASH_JOURNAL_STRATEGY_SEQUENTIAL, cfstore_flash_journal_callback); - CFSTORE_FENTRYLOG("%s:here\n", __func__); CFSTORE_TP(CFSTORE_TP_FSM, "%s:FlashJournal_initialize ret=%d\n", __func__, (int) ret); if(ret < ARM_DRIVER_OK){ CFSTORE_ERRLOG("%s:Error: failed to initialize flash journaling layer (ret=%d)\n", __func__, (int) ret); @@ -1520,7 +1656,6 @@ static int32_t cfstore_fsm_initing(void* context) */ static int32_t cfstore_fsm_read_on_entry(void* context) { - uint8_t* ptr = NULL; int32_t ret = 0; FlashJournal_Status_t status = JOURNAL_STATUS_ERROR; cfstore_ctx_t* ctx = (cfstore_ctx_t*) context; @@ -1535,32 +1670,18 @@ static int32_t cfstore_fsm_read_on_entry(void* context) cfstore_fsm_state_set(&ctx->fsm, cfstore_fsm_state_ready, ctx); ret = ARM_CFSTORE_DRIVER_ERROR_INTERNAL; goto out; - } if(ctx->info.sizeofJournaledBlob > 0) { - /* setup the expected blob size for writing - * This is a multiple of program unit so the write doesnt fail due to unaligned log */ + /* setup the expected blob size for writing */ ctx->expected_blob_size = ctx->info.sizeofJournaledBlob; - if(ctx->expected_blob_size % ctx->info.program_unit > 0){ - ctx->expected_blob_size += (ctx->info.program_unit - (ctx->info.sizeofJournaledBlob % ctx->info.program_unit)); - } - /* grow the area by the size of the stored blob */ - ptr = (uint8_t*) CFSTORE_REALLOC((void*) ctx->area_0_head, ctx->expected_blob_size); - if(ptr == NULL){ - CFSTORE_ERRLOG("%s:Error: unable to allocate memory (size=%lu)\n", __func__, (long unsigned int) ctx->info.sizeofJournaledBlob); - cfstore_ctx_reset(ctx); - ret = ARM_CFSTORE_DRIVER_ERROR_OUT_OF_MEMORY; + ret = cfstore_realloc_ex(ctx->expected_blob_size, &ctx->expected_blob_size); + if(ret < ARM_DRIVER_OK){ + CFSTORE_ERRLOG("%s:Error: cfstore_realloc_ex() failed (ret=%d)\n", __func__, (int) ret); /* move to ready state. cfstore client is expected to Uninitialize() before further calls */ cfstore_fsm_state_set(&ctx->fsm, cfstore_fsm_state_ready, ctx); goto out; } - memset(ptr, 0, ctx->expected_blob_size); - if(ptr != ctx->area_0_head){ - CFSTORE_TP(CFSTORE_TP_FSM, "%s:cfstore_ctx_g.area_0_head pointer changed (cfstore_ctx_g.area_0_head=%p, ptr=%p)\n", __func__, ctx->area_0_head, ptr); - ctx->area_0_head = ptr; - ctx->area_0_tail = ctx->area_0_head + ctx->info.sizeofJournaledBlob; - } ret = FlashJournal_read(&ctx->jrnl, (void*) ctx->area_0_head, ctx->info.sizeofJournaledBlob); if(ret < ARM_DRIVER_OK){ CFSTORE_ERRLOG("%s:Error: failed to initialize flash journaling layer (ret=%d)\n", __func__, (int) ret); @@ -1692,7 +1813,7 @@ int32_t cfstore_fsm_log_on_entry(void* context) return cfstore_flash_map_error(status); } /* compute the expected_blob_size = area_size plus the padding at the end of the area to align with program_unit*/ - ctx->expected_blob_size = cfstore_ctx_get_area_len(); + ctx->expected_blob_size = cfstore_ctx_get_kv_total_len(); if(ctx->expected_blob_size % info.program_unit > 0){ ctx->expected_blob_size += (info.program_unit - (ctx->expected_blob_size % info.program_unit)); } @@ -2111,82 +2232,86 @@ static int32_t cfstore_flash_flush(cfstore_ctx_t* ctx) #endif /* CFSTORE_CONFIG_BACKEND_FLASH_ENABLED */ -/** @brief internal delete helper function. - * @note must be called within critical section. - */ + +/** @brief After a cfstore KV area memmove() operation, update the file pointers + * to reflect the new location in memory of KVs. + * + * @param head + * the position at which size_diff bytes have been inserted/deleted + * + * @param size_diff + * Change in size (size difference) of the KV memory area. + * - size_diff > 0 => increase in area, |size_diff| bytes have been inserted at head, + * and the previously following KVs shifted up to higher memory addresses + * - size_diff < 0 => decrease in area, |size_diff| bytes have been removed at head, + * and the previously following KVs shifted down to lower memory addresses + * */ +static int32_t cfstore_file_update(uint8_t* head, int32_t size_diff) +{ + cfstore_ctx_t* ctx = cfstore_ctx_get(); + cfstore_file_t* file; + cfstore_list_node_t* node; + cfstore_list_node_t* file_list = &ctx->file_list; + + CFSTORE_FENTRYLOG("%s:entered:(ctx->area_0_head=%p, ctx->area_0_tail=%p)\n", __func__, ctx->area_0_head, ctx->area_0_tail); + + /* walk the file list updating head pointers for the KVs that remain*/ + node = file_list->next; + while(node != file_list){ + /* Any KV positioned later in the area than the deleted KV will require file head pointers updating. + * If file's head pointer is beyond the deleted KV tail then the file->head needs to be updated + * to reflect the memove + */ + file = (cfstore_file_t*) node; + if(file->head >= head){ + /* sign of sign_diff used to move file->head up/down in memory*/ + file->head += size_diff; + } + node = node->next; + } + return ARM_DRIVER_OK; +} + + static int32_t cfstore_delete_ex(cfstore_area_hkvt_t* hkvt) { - uint8_t* ptr = NULL; int32_t ret = ARM_DRIVER_ERROR; ARM_CFSTORE_SIZE kv_size = 0; - ARM_CFSTORE_SIZE area_size = 0; + ARM_CFSTORE_SIZE kv_total_size = 0; ARM_CFSTORE_SIZE realloc_size = 0; /* size aligned to flash program_unit size */ cfstore_ctx_t* ctx = cfstore_ctx_get(); - cfstore_file_t* file; - cfstore_list_node_t* node; - cfstore_list_node_t* file_list = &ctx->file_list; CFSTORE_FENTRYLOG("%s:entered:(ctx->area_0_head=%p, ctx->area_0_tail=%p)\n", __func__, ctx->area_0_head, ctx->area_0_tail); kv_size = cfstore_hkvt_get_size(hkvt); - area_size = cfstore_ctx_get_area_len(); + kv_total_size = cfstore_ctx_get_kv_total_len(); + + /* Note the following: + * 1. memmove() above shifts the position of the KVs falling after the deleted KV to be at + * lower memory addresses. The code (A) updates the cfstore_file_t::head pointers for these KVs + * so they point to the new locations. + * 2. The operation at 1. above has to happen before the realloc because realloc() can move the + * start of heap block to a new location, in which case all cfstore_file_t::head pointers + * need to be updated. cfstore_realloc() can only do this starting from a set of correct + * cfstore_file_t::head pointers i.e. after 1. has been completed. + */ memmove(hkvt->head, hkvt->tail, ctx->area_0_tail - hkvt->tail); /* zero the deleted KV memory */ memset(ctx->area_0_tail-kv_size, 0, kv_size); - /* In the general case the new ((area_size - kv_size) % program_unit > 0). The new area_size is - * aligned to a program_unit boundary to facilitate r/w to flash and so the memory realloc size - * is calculated to align, as follows */ - /* setup the reallocation memory size. */ - realloc_size = area_size - kv_size; - if(realloc_size % cfstore_ctx_get_program_unit(ctx) > 0){ - realloc_size += (cfstore_ctx_get_program_unit(ctx) - (realloc_size % cfstore_ctx_get_program_unit(ctx))); + /* The KV area has shrunk so a negative size_diff should be indicated to cfstore_file_update(). */ + ret = cfstore_file_update(hkvt->head, -1 * kv_size); + if(ret < ARM_DRIVER_OK){ + CFSTORE_ERRLOG("%s:Error:file update failed\n", __func__); + goto out0; } - /* realloc() can return non-zero ptr for size = 0 when the last KV is deleted */ - if(realloc_size > 0) - { - ptr = (uint8_t*) CFSTORE_REALLOC((void*) ctx->area_0_head, realloc_size); - /* realloc can return NULL when the last KV is deleted. - * It also appears that realloc can return non-zero ptr even when realloc_size = 0 */ - if(ptr == NULL){ - CFSTORE_ERRLOG("%s:Error:realloc failed\n", __func__); - cfstore_ctx_reset(ctx); - return ARM_CFSTORE_DRIVER_ERROR_OUT_OF_MEMORY; - } - /* check realloc() hasnt move area in memory from cfstore_ctx_g.area_0_head */ - if(ptr != ctx->area_0_head){ - CFSTORE_TP(CFSTORE_TP_DELETE, "%s: cfstore_ctx_g.area_0_head pointer changed (cfstore_ctx_g.area_0_head=%p, cfstore_ctx_g.area_0_tail=%p)\n", __func__, ctx->area_0_head, ptr); - /* realloc() has moved the area in memory */ - ctx->area_0_head = ptr; - } - /* set tail to be the end of the new area, which will be updated by cfstore_flash_set_tail */ - ctx->area_0_tail = ptr + area_size - kv_size; - ret = cfstore_flash_set_tail(); - if(ret < ARM_DRIVER_OK){ - CFSTORE_ERRLOG("%s:Error: cfstore_flash_set_tail() failed (ret=%d)\n", __func__, (int) ret); - goto out0; - } - /* now have to walk the file list updating head pointers for the KVs that remain*/ - node = file_list->next; - while(node != file_list){ - /* Any KV positioned later in the area than the deleted KV will require file head pointers updating. - * If file's head pointer is beyond the deleted KV tail then the file->head needs to be updated - * to reflect the memove */ - file = (cfstore_file_t*) node; - if(file->head >= hkvt->head){ - file->head -= kv_size; - } - node = node->next; - } - } - else - { - /* realloc_size = 0 */ - CFSTORE_FREE((void*) ctx->area_0_head); - ctx->area_0_head = NULL; - ctx->area_0_tail = NULL; + /* setup the reallocation memory size. */ + realloc_size = kv_total_size - kv_size; + ret = cfstore_realloc_ex(realloc_size, NULL); + if(ret < ARM_DRIVER_OK){ + CFSTORE_ERRLOG("%s:Error:realloc failed\n", __func__); + goto out0; } - ret = ARM_DRIVER_OK; out0: return ret; } @@ -2238,7 +2363,7 @@ static int32_t cfstore_file_destroy(cfstore_file_t* file) CFSTORE_ASSERT(cfstore_hkvt_is_valid(&hkvt, cfstore_ctx_get()->area_0_tail) == true); ret = ARM_DRIVER_OK; cfstore_hkvt_refcount_dec(&hkvt, &refcount); - CFSTORE_TP(CFSTORE_TP_FILE, "%s:refcount =%d\n", __func__, (int)refcount); + CFSTORE_TP(CFSTORE_TP_FILE, "%s:refcount =%d file->head=%p\n", __func__, (int)refcount, file->head); if(refcount == 0){ /* check for delete */ CFSTORE_TP(CFSTORE_TP_FILE, "%s:checking delete flag\n", __func__); @@ -2693,7 +2818,7 @@ static int32_t cfstore_get_value_len(ARM_CFSTORE_HANDLE hkey, ARM_CFSTORE_SIZE * goto out0; } /* getting a value len doesnt change the sram area so this can happen independently of - * an oustanding async operation. its unnecessary to check the fsm state */ + * an outstanding async operation. its unnecessary to check the fsm state */ ret = cfstore_validate_handle(hkey); if(ret < ARM_DRIVER_OK){ CFSTORE_ERRLOG("%s:Error: invalid handle.\n", __func__); @@ -2724,8 +2849,8 @@ static int32_t cfstore_get_value_len(ARM_CFSTORE_HANDLE hkey, ARM_CFSTORE_SIZE * /* @brief debug trace a struct cfstore_area_hkvt_t, providing values for key field. */ static CFSTORE_INLINE void cfstore_hkvt_dump(cfstore_area_hkvt_t* hkvt, const char* tag) { -/* #define noSymbol */ -#ifdef noSymbol +/* #define CFSTORE_HKVT_DUMP_ON */ +#ifdef CFSTORE_HKVT_DUMP_ON char kname[CFSTORE_KEY_NAME_MAX_LENGTH+1]; char value[CFSTORE_KEY_NAME_MAX_LENGTH+1]; uint32_t klen = 0; @@ -2757,7 +2882,7 @@ static CFSTORE_INLINE void cfstore_hkvt_dump(cfstore_area_hkvt_t* hkvt, const ch (void) hkvt; (void) tag; -#endif /* noSymbol */ +#endif /* CFSTORE_HKVT_DUMP_ON */ } static CFSTORE_INLINE void cfstore_flags_dump(ARM_CFSTORE_FMODE flag, const char* tag) @@ -2779,7 +2904,8 @@ static CFSTORE_INLINE void cfstore_flags_dump(ARM_CFSTORE_FMODE flag, const char static CFSTORE_INLINE void cfstore_file_dump(cfstore_file_t* file, const char* tag) { -#ifdef noSymbol +/*#define CFSTORE_FILE_DUMP_ON */ +#ifdef CFSTORE_FILE_DUMP_ON cfstore_area_hkvt_t hkvt; CFSTORE_TP(CFSTORE_TP_VERBOSE3, "%s:*** Dumping File Contents : Start ***\n", tag); @@ -2794,7 +2920,7 @@ static CFSTORE_INLINE void cfstore_file_dump(cfstore_file_t* file, const char* t (void) file; (void) tag; -#endif /* noSymbol */ +#endif /* CFSTORE_FILE_DUMP_ON */ } /* dump sram contents of cfstore in a useful manner for debugging */ @@ -3056,7 +3182,8 @@ static int32_t cfstore_find(const char* key_name_query, const ARM_CFSTORE_HANDLE ret = ARM_CFSTORE_DRIVER_ERROR_INVALID_HANDLE; goto out1; } - } else if(!cfstore_file_is_empty(previous)){ + } else if(previous != NULL && !cfstore_file_is_empty(previous)){ + CFSTORE_TP(CFSTORE_TP_FIND, "%s:Invalid previous hkey buffer.\n", __func__); ret = ARM_CFSTORE_DRIVER_ERROR_INVALID_HANDLE_BUF; goto out1; } @@ -3123,8 +3250,10 @@ static int32_t cfstore_find(const char* key_name_query, const ARM_CFSTORE_HANDLE * @note rw_lock must be held by the caller of this function rw_area0_lock */ static int32_t cfstore_recreate(const char* key_name, ARM_CFSTORE_SIZE value_len, ARM_CFSTORE_HANDLE hkey, cfstore_area_hkvt_t* hkvt) { - uint8_t* ptr = NULL; + uint8_t* old_area_0_head = NULL; int32_t kv_size_diff = 0; + int32_t ret = ARM_DRIVER_ERROR; + size_t memmove_len = 0; ARM_CFSTORE_SIZE area_size = 0; ARM_CFSTORE_FMODE flags; cfstore_ctx_t* ctx = cfstore_ctx_get(); @@ -3141,48 +3270,51 @@ static int32_t cfstore_recreate(const char* key_name, ARM_CFSTORE_SIZE value_len return ARM_DRIVER_OK; } + /* grow the area by the size of the new KV */ + area_size = cfstore_ctx_get_kv_total_len(); + /* store the area_0_head, and move length for later updating hkvt if realloc moves KV area */ + old_area_0_head = ctx->area_0_head; + memmove_len = ctx->area_0_tail - hkvt->tail; + CFSTORE_TP(CFSTORE_TP_CREATE, "%s:cfstore_ctx_g.area_0_head=%p, cfstore_ctx_g.area_0_tail=%p\n", __func__, ctx->area_0_head, ctx->area_0_tail); CFSTORE_TP(CFSTORE_TP_CREATE, "%s:sizeof(header)=%d, sizeof(key)=%d, sizeof(value)=%d, kv_size_diff=%d, area_size=%d\n", __func__, (int) sizeof(cfstore_area_header_t), (int)(strlen(key_name)), (int)value_len, (int) kv_size_diff, (int) area_size); - - /* grow the area by the size of the new KV */ - area_size = cfstore_ctx_get_area_len(); if (kv_size_diff < 0){ /* value blob size shrinking => do memmove() before realloc() which will free memory */ - memmove(hkvt->tail + kv_size_diff, hkvt->tail, ctx->area_0_tail - hkvt->tail); - //todo: wip: do we have to update file pointers for KVs after the one thats changed size? - } - ptr = (uint8_t*) CFSTORE_REALLOC((void*) ctx->area_0_head, area_size + kv_size_diff); - if(ptr == NULL){ - CFSTORE_ERRLOG("%s:realloc failed for key_name=%s\n", __func__, key_name); - cfstore_ctx_reset(ctx); - return ARM_CFSTORE_DRIVER_ERROR_OUT_OF_MEMORY; - } - if(ptr != ctx->area_0_head){ - CFSTORE_TP(CFSTORE_TP_CREATE, "%s:cfstore_ctx_g.area_0_head pointer changed (cfstore_ctx_g.area_0_head=%p, cfstore_ctx_g.area_0_tail=%p)\n", __func__, ctx->area_0_head, ptr); - /* This covers the cases where CFSTORE_REALLOC() has moved the area in memory - * As realloc() has caused the memory to move, hkvt needs re-initialising */ - hkvt->head += ptr - ctx->area_0_head; - hkvt->key += ptr - ctx->area_0_head; - hkvt->value += ptr - ctx->area_0_head; - hkvt->tail += ptr - ctx->area_0_head; - /* Set head and tail to old relative position in new area */ - ctx->area_0_head = ptr; - ctx->area_0_tail = ctx->area_0_head + area_size; - //todo: wip: do we have to update file pointers for KVs after the memory has moved? + memmove(hkvt->tail + kv_size_diff, hkvt->tail, memmove_len); + ret = cfstore_file_update(hkvt->head, kv_size_diff); + if(ret < ARM_DRIVER_OK){ + CFSTORE_ERRLOG("%s:Error:file update failed\n", __func__); + goto out0; + } + } + + ret = cfstore_realloc_ex(area_size + kv_size_diff, NULL); + if(ret < ARM_DRIVER_OK){ + CFSTORE_ERRLOG("%s:Error:file realloc failed\n", __func__); + goto out0; + } + if(old_area_0_head != ctx->area_0_head){ + /* As realloc() has caused the memory to move, hkvt needs re-initialising */ + hkvt->head += ctx->area_0_head - old_area_0_head; + hkvt->key += ctx->area_0_head - old_area_0_head; + hkvt->value += ctx->area_0_head - old_area_0_head; + hkvt->tail += ctx->area_0_head - old_area_0_head; } if(kv_size_diff > 0) { /* value blob size growing requires memmove() after realloc() */ - memset(ctx->area_0_tail, 0, kv_size_diff); - memmove(hkvt->tail+kv_size_diff, hkvt->tail, ctx->area_0_tail - hkvt->tail); - //todo: wip: do we have to update file pointers for KVs after the one thats changed size? + memmove(hkvt->tail+kv_size_diff, hkvt->tail, memmove_len); + ret = cfstore_file_update(hkvt->head, kv_size_diff); + if(ret < ARM_DRIVER_OK){ + CFSTORE_ERRLOG("%s:Error:file update failed\n", __func__); + goto out0; + } } /* hkvt->head, hkvt->key and hkvt->value remain unchanged but hkvt->tail has moved. Update it.*/ hkvt->tail = hkvt->tail + kv_size_diff; /* set the new value length in the header */ cfstore_hkvt_set_value_len(hkvt, value_len); - ctx->area_0_tail = ctx->area_0_head + area_size + kv_size_diff; cfstore_file_create(hkvt, flags, hkey, &ctx->file_list); ctx->area_dirty_flag = true; @@ -3190,7 +3322,9 @@ static int32_t cfstore_recreate(const char* key_name, ARM_CFSTORE_SIZE value_len cfstore_hkvt_dump(hkvt, __func__); cfstore_dump_contents(__func__); #endif - return ARM_DRIVER_OK; + ret = ARM_DRIVER_OK; +out0: + return ret; } @@ -3198,7 +3332,6 @@ static int32_t cfstore_recreate(const char* key_name, ARM_CFSTORE_SIZE value_len static int32_t cfstore_create(const char* key_name, ARM_CFSTORE_SIZE value_len, const ARM_CFSTORE_KEYDESC* kdesc, ARM_CFSTORE_HANDLE hkey) { bool b_acl_default = false; - uint8_t* ptr = NULL; int32_t ret = ARM_DRIVER_ERROR; int32_t cfstore_uvisor_box_id = 0; ARM_CFSTORE_SIZE area_size = 0; @@ -3288,39 +3421,14 @@ static int32_t cfstore_create(const char* key_name, ARM_CFSTORE_SIZE value_len, * In the general case the new ((area_size + kv_size) % program_unit > 0). The new area_size is * aligned to a program_unit boundary to facilitate r/w to flash and so the memory realloc size * is calculated to align, as follows */ - area_size = cfstore_ctx_get_area_len(); - // moved to flash_init() and program_unit stored in ctx - /* - status = FlashJournal_getInfo(&ctx->jrnl, &info); - if(status < JOURNAL_STATUS_OK){ - CFSTORE_TP(CFSTORE_TP_CREATE, "%s:Error: failed get journal info (status=%d)\n", __func__, (int) status); - ret = cfstore_flash_map_error(status); - goto out1; - } - */ + area_size = cfstore_ctx_get_kv_total_len(); /* setup the reallocation memory size. */ realloc_size = area_size + kv_size; - if(realloc_size % cfstore_ctx_get_program_unit(ctx) > 0){ - realloc_size += (cfstore_ctx_get_program_unit(ctx) - (realloc_size % cfstore_ctx_get_program_unit(ctx))); - } - ptr = (uint8_t*) CFSTORE_REALLOC((void*) ctx->area_0_head, realloc_size); - if(ptr == NULL){ - CFSTORE_ERRLOG("%s:realloc failed for key_name=%s\n", __func__, key_name); - cfstore_ctx_reset(ctx); - ret = ARM_CFSTORE_DRIVER_ERROR_OUT_OF_MEMORY; + ret = cfstore_realloc_ex(realloc_size, NULL); + if(ret < ARM_DRIVER_OK){ + CFSTORE_ERRLOG("%s:Error:file realloc failed\n", __func__); goto out1; } - if(ptr != ctx->area_0_head){ - CFSTORE_TP(CFSTORE_TP_CREATE, "%s:cfstore_ctx_g.area_0_head pointer changed (cfstore_ctx_g.area_0_head=%p, cfstore_ctx_g.area_0_tail=%p)\n", __func__, ctx->area_0_head, ptr); - /* this covers the following cases: - * - this is the first KV insertion in the area, which is special as both area head/tail pointers need setting. - * - realloc() has move the area in memory */ - ctx->area_0_head = ptr; - ctx->area_0_tail = ctx->area_0_head + area_size; - } - - /* check realloc() hasnt move area in memory from cfstore_ctx_g.area_0_head*/ - CFSTORE_TP(CFSTORE_TP_CREATE, "%s:cfstore_ctx_g.area_0_head=%p, ptr=%p\n", __func__, ctx->area_0_head, ptr); /* determine if should adopt a default behavior for acl permission setting */ if(cfstore_acl_is_default(kdesc->acl)){ @@ -3329,8 +3437,8 @@ static int32_t cfstore_create(const char* key_name, ARM_CFSTORE_SIZE value_len, b_acl_default = true; } /* set the header up, then copy key_name into header */ - memset(ctx->area_0_tail, 0, kv_size); - hdr = (cfstore_area_header_t*) ctx->area_0_tail; + hdr = (cfstore_area_header_t*) (ctx->area_0_head + area_size); + CFSTORE_FENTRYLOG("%s:hdr=%p\n", __func__, hdr); hdr->klength = (uint8_t) strlen(key_name); hdr->vlength = value_len; hdr->perm_owner_read = b_acl_default ? true : kdesc->acl.perm_owner_read; @@ -3340,8 +3448,6 @@ static int32_t cfstore_create(const char* key_name, ARM_CFSTORE_SIZE value_len, hdr->perm_other_write = kdesc->acl.perm_other_write; hdr->perm_other_execute = kdesc->acl.perm_other_execute; strncpy((char*)hdr + sizeof(cfstore_area_header_t), key_name, strlen(key_name)); - /* Updating the area_0_tail pointer reveals the inserted KV to other operations. See [NOTE1] for details.*/ - ctx->area_0_tail = ctx->area_0_head + area_size + kv_size; hkvt = cfstore_get_hkvt_from_head_ptr((uint8_t*) hdr); if(cfstore_flags_is_default(kdesc->flags)){ /* set as read-only by default default */ @@ -3817,6 +3923,9 @@ static int32_t cfstore_uninitialise(void) int32_t ret = ARM_DRIVER_ERROR; ARM_STORAGE_CAPABILITIES caps; cfstore_ctx_t* ctx = cfstore_ctx_get(); + cfstore_file_t* file; + cfstore_list_node_t* node; + cfstore_list_node_t* file_list = &ctx->file_list; CFSTORE_FENTRYLOG("%s:entered\n", __func__); memset(&caps, 0, sizeof(caps)); @@ -3834,7 +3943,7 @@ static int32_t cfstore_uninitialise(void) } if(ctx->init_ref_count > 0) { ctx->init_ref_count--; - CFSTORE_TP(CFSTORE_TP_INIT, "%s:Debug: decemented init_ref_count (%d).\n", __func__, (int) ctx->init_ref_count); + CFSTORE_TP(CFSTORE_TP_INIT, "%s:Debug: decremented init_ref_count (%d).\n", __func__, (int) ctx->init_ref_count); } if(ctx->init_ref_count == 0) { @@ -3842,10 +3951,14 @@ static int32_t cfstore_uninitialise(void) /* check file list is empty and if not, free the items */ if(ctx->file_list.next != ctx->file_list.prev) { - /* list is not empty. walk the list and free the entries */ - // todo: wip: free items on the file list + /* list is not empty. walk the list and close the files, cleaning up state */ + node = file_list->next; + while(node != file_list){ + file = (cfstore_file_t*) node; + cfstore_close((ARM_CFSTORE_HANDLE) file); + node = node->next; + } } - ret = cfstore_flash_deinit(); if(ret < ARM_DRIVER_OK){ CFSTORE_ERRLOG("%s:Error: failed to uninitialise flash journal layer.\n", __func__); @@ -4121,3 +4234,4 @@ ARM_CFSTORE_DRIVER cfstore_driver = }; #endif /* YOTTA_CFG_CFSTORE_UVISOR */ + diff --git a/features/storage/FEATURE_STORAGE/flash-journal/flash-journal-strategy-sequential/config.h b/features/storage/FEATURE_STORAGE/flash-journal/flash-journal-strategy-sequential/config.h index f96eae908ac..4a126107270 100644 --- a/features/storage/FEATURE_STORAGE/flash-journal/flash-journal-strategy-sequential/config.h +++ b/features/storage/FEATURE_STORAGE/flash-journal/flash-journal-strategy-sequential/config.h @@ -18,6 +18,8 @@ #ifndef __FLASH_JOURNAL_CONFIG_H__ #define __FLASH_JOURNAL_CONFIG_H__ +#ifndef SEQUENTIAL_FLASH_JOURNAL_MAX_LOGGED_BLOBS #define SEQUENTIAL_FLASH_JOURNAL_MAX_LOGGED_BLOBS 4 +#endif #endif /* __FLASH_JOURNAL_CONFIG_H__ */ diff --git a/hal/api/CAN.h b/hal/api/CAN.h index a96c2b86b96..3d0e8491a49 100644 --- a/hal/api/CAN.h +++ b/hal/api/CAN.h @@ -203,7 +203,9 @@ class CAN { EpIrq, AlIrq, BeIrq, - IdIrq + IdIrq, + + IrqCnt }; /** Attach a function to call whenever a CAN frame received interrupt is @@ -246,7 +248,7 @@ class CAN { virtual void lock(); virtual void unlock(); can_t _can; - Callback _irq[9]; + Callback _irq[IrqCnt]; PlatformMutex _mutex; }; diff --git a/hal/api/SerialBase.h b/hal/api/SerialBase.h index 1d7ae7c34dd..45df1ce04b6 100644 --- a/hal/api/SerialBase.h +++ b/hal/api/SerialBase.h @@ -55,7 +55,9 @@ class SerialBase { enum IrqType { RxIrq = 0, - TxIrq + TxIrq, + + IrqCnt }; enum Flow { @@ -231,7 +233,7 @@ class SerialBase { #endif serial_t _serial; - Callback _irq[2]; + Callback _irq[IrqCnt]; int _baud; }; diff --git a/hal/api/mbed.h b/hal/api/mbed.h index 97f650c61e3..0a95efc5eb4 100644 --- a/hal/api/mbed.h +++ b/hal/api/mbed.h @@ -16,7 +16,7 @@ #ifndef MBED_H #define MBED_H -#define MBED_LIBRARY_VERSION 125 +#define MBED_LIBRARY_VERSION 126 #if MBED_CONF_RTOS_PRESENT #include "rtos/rtos.h" diff --git a/hal/api/mbed_mem_trace.h b/hal/api/mbed_mem_trace.h new file mode 100644 index 00000000000..2ca7ac76add --- /dev/null +++ b/hal/api/mbed_mem_trace.h @@ -0,0 +1,138 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MBED_MEM_TRACE_H__ +#define __MBED_MEM_TRACE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/* Operation types for tracer */ +enum { + MBED_MEM_TRACE_MALLOC, + MBED_MEM_TRACE_REALLOC, + MBED_MEM_TRACE_CALLOC, + MBED_MEM_TRACE_FREE +}; + +/* Prefix for the output of the default tracer */ +#define MBED_MEM_DEFAULT_TRACER_PREFIX "#" + +/** + * Type of the callback used by the memory tracer. This callback is called when a memory + * allocation operation (malloc, realloc, calloc, free) is called and tracing is enabled + * for that memory allocation function. + * + * @param op the ID of the operation (MBED_MEM_TRACE_MALLOC, MBED_MEM_TRACE_REALLOC, + * MBED_MEM_TRACE_CALLOC or MBED_MEM_TRACE_FREE). + * @param res the result that the memory operation returned (NULL for 'free'). + * @param caller the caller of the memory operation. Note that the value of 'caller' might be + * unreliable. + * + * The rest of the parameters passed 'mbed_mem_trace_cb_t' are the same as the memory operations + * that triggered its call (see 'man malloc' for details): + * + * - for malloc: cb(MBED_MEM_TRACE_MALLOC, res, caller, size). + * - for realloc: cb(MBED_MEM_TRACE_REALLOC, res, caller, ptr, size). + * - for calloc: cb(MBED_MEM_TRACE_CALLOC, res, caller, nmemb, size). + * - for free: cb(MBED_MEM_TRACE_FREE, NULL, caller, ptr). + */ +typedef void (*mbed_mem_trace_cb_t)(uint8_t op, void *res, void* caller, ...); + +/** + * Set the callback used by the memory tracer (use NULL for disable tracing). + * + * @param cb the callback to call on each memory operation. + */ +void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb); + +/** + * Trace a call to 'malloc'. + * @param res the result of running 'malloc'. + * @param size the 'size' argument given to 'malloc'. + * @param caller the caller of the memory operation. + * @return 'res' (the first argument). + */ +void *mbed_mem_trace_malloc(void *res, size_t size, void *caller); + +/** + * Trace a call to 'realloc'. + * @param res the result of running 'realloc'. + * @param ptr the 'ptr' argument given to 'realloc'. + * @param size the 'size' argument given to 'realloc'. + * + * @return 'res' (the first argument). + */ +void *mbed_mem_trace_realloc(void *res, void *ptr, size_t size, void *caller); + +/** + * Trace a call to 'calloc'. + * @param res the result of running 'calloc'. + * @param nmemb the 'nmemb' argument given to 'calloc'. + * @param size the 'size' argument given to 'calloc'. + * @param caller the caller of the memory operation. + * @Return 'res' (the first argument). + */ +void *mbed_mem_trace_calloc(void *res, size_t num, size_t size, void *caller); + +/** + * Trace a call to 'free'. + * @param ptr the 'ptr' argument given to 'free'. + * @param caller the caller of the memory operation. + */ +void mbed_mem_trace_free(void *ptr, void *caller); + +/** + * Default memory trace callback. DO NOT CALL DIRECTLY. It is meant to be used + * as the second argument of 'mbed_mem_trace_setup'. + * + * The default callback outputs trace data using 'printf', in a format that's + * easily parsable by an external tool. For each memory operation, the callback + * outputs a line that begins with '#:<0xresult>;<0xcaller>-': + * + * - 'op' identifies the memory operation ('m' for 'malloc', 'r' for 'realloc', + * 'c' for 'calloc' and 'f' for 'free'). + * - 'result' (base 16) is the result of the memor operation. This is always NULL + * for 'free', since 'free' doesn't return anything. + * -'caller' (base 16) is the caller of the memory operation. Note that the value + * of 'caller' might be unreliable. + * + * The rest of the output depends on the operation being traced: + * + * - for 'malloc': 'size', where 'size' is the original argument to 'malloc'. + * - for 'realloc': '0xptr;size', where 'ptr' (base 16) and 'size' are the original arguments to 'realloc'. + * - for 'calloc': 'nmemb;size', where 'nmemb' and 'size' are the original arguments to 'calloc'. + * - for 'free': '0xptr', where 'ptr' (base 16) is the original argument to 'free'. + * + * Examples: + * + * - '#m:0x20003240;0x600d-50' encodes a 'malloc' that returned 0x20003240, was called + * by the instruction at 0x600D with a the 'size' argument equal to 50. + * - '#f:0x0;0x602f-0x20003240' encodes a 'free' that was called by the instruction at + * 0x602f with the 'ptr' argument equal to 0x20003240. + */ +void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...); + +#ifdef __cplusplus +} +#endif + +#endif// #ifndef __MBED_MEM_TRACE_H__ + diff --git a/hal/api/mbed_stats.h b/hal/api/mbed_stats.h new file mode 100644 index 00000000000..9a0cae89933 --- /dev/null +++ b/hal/api/mbed_stats.h @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016-2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_STATS_H +#define MBED_STATS_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t current_size; /**< Bytes allocated currently. */ + uint32_t max_size; /**< Max bytes allocated at a given time. */ + uint32_t total_size; /**< Cumulative sum of bytes ever allocated. */ + uint32_t alloc_cnt; /**< Current number of allocations. */ + uint32_t alloc_fail_cnt; /**< Number of failed allocations. */ +} mbed_stats_heap_t; + +/** + * Fill the passed in structure with heap stats. + */ +void mbed_stats_heap_get(mbed_stats_heap_t *stats); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/api/toolchain.h b/hal/api/toolchain.h index e7bff5fd706..f02bae058de 100644 --- a/hal/api/toolchain.h +++ b/hal/api/toolchain.h @@ -240,6 +240,29 @@ */ #define MBED_DEPRECATED_SINCE(D, M) MBED_DEPRECATED(M " [since " D "]") +/** MBED_CALLER_ADDR() + * Returns the caller of the current function. + * + * @note + * This macro is only implemented for GCC and ARMCC. + * + * @code + * #include "toolchain.h" + * + * printf("This function was called from %p", MBED_CALLER_ADDR()); + * @endcode + * + * @return Address of the calling function + */ +#ifndef MBED_CALLER_ADDR +#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM) +#define MBED_CALLER_ADDR() __builtin_extract_return_addr(__builtin_return_address(0)) +#elif defined(__CC_ARM) +#define MBED_CALLER_ADDR() __builtin_return_address(0) +#else +#define MBED_CALLER_ADDR() (NULL) +#endif +#endif // FILEHANDLE declaration #if defined(TOOLCHAIN_ARM) diff --git a/hal/common/mbed_alloc_wrappers.cpp b/hal/common/mbed_alloc_wrappers.cpp new file mode 100644 index 00000000000..6f6be1b50f5 --- /dev/null +++ b/hal/common/mbed_alloc_wrappers.cpp @@ -0,0 +1,338 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_mem_trace.h" +#include "mbed_stats.h" +#include "toolchain.h" +#include "SingletonPtr.h" +#include "PlatformMutex.h" +#include +#include +#include +#include + +/* There are two memory tracers in mbed OS: + +- the first can be used to detect the maximum heap usage at runtime. It is + activated by defining the MBED_HEAP_STATS_ENABLED macro. +- the second can be used to trace each memory call by automatically invoking + a callback on each memory operation (see hal/api/mbed_mem_trace.h). It is + activated by defining the MBED_MEM_TRACING_ENABLED macro. + +Both tracers can be activated and deactivated in any combination. If both tracers +are active, the second one (MBED_MEM_TRACING_ENABLED) will trace the first one's +(MBED_HEAP_STATS_ENABLED) memory calls.*/ + +/******************************************************************************/ +/* Implementation of the runtime max heap usage checker */ +/******************************************************************************/ + +/* Size must be a multiple of 8 to keep alignment */ +typedef struct { + uint32_t size; + uint32_t pad; +} alloc_info_t; + +#ifdef MBED_MEM_TRACING_ENABLED +static SingletonPtr mem_trace_mutex; +#endif +#ifdef MBED_HEAP_STATS_ENABLED +static SingletonPtr malloc_stats_mutex; +static mbed_stats_heap_t heap_stats = {0, 0, 0, 0, 0}; +#endif + +void mbed_stats_heap_get(mbed_stats_heap_t *stats) +{ +#ifdef MBED_HEAP_STATS_ENABLED + malloc_stats_mutex->lock(); + memcpy(stats, &heap_stats, sizeof(mbed_stats_heap_t)); + malloc_stats_mutex->unlock(); +#else + memset(stats, 0, sizeof(mbed_stats_heap_t)); +#endif +} + +/******************************************************************************/ +/* GCC memory allocation wrappers */ +/******************************************************************************/ + +#if defined(TOOLCHAIN_GCC) + +#ifdef FEATURE_UVISOR +#include "uvisor-lib/uvisor-lib.h" +#endif/* FEATURE_UVISOR */ + +extern "C" { + void * __real__malloc_r(struct _reent * r, size_t size); + void * __real__realloc_r(struct _reent * r, void * ptr, size_t size); + void __real__free_r(struct _reent * r, void * ptr); + void* __real__calloc_r(struct _reent * r, size_t nmemb, size_t size); +} + +// TODO: memory tracing doesn't work with uVisor enabled. +#if !defined(FEATURE_UVISOR) + +extern "C" void * __wrap__malloc_r(struct _reent * r, size_t size) { + void *ptr = NULL; +#ifdef MBED_HEAP_STATS_ENABLED + malloc_stats_mutex->lock(); + alloc_info_t *alloc_info = (alloc_info_t*)__real__malloc_r(r, size + sizeof(alloc_info_t)); + if (alloc_info != NULL) { + alloc_info->size = size; + ptr = (void*)(alloc_info + 1); + heap_stats.current_size += size; + heap_stats.total_size += size; + heap_stats.alloc_cnt += 1; + if (heap_stats.current_size > heap_stats.max_size) { + heap_stats.max_size = heap_stats.current_size; + } + } else { + heap_stats.alloc_fail_cnt += 1; + } + malloc_stats_mutex->unlock(); +#else // #ifdef MBED_HEAP_STATS_ENABLED + ptr = __real__malloc_r(r, size); +#endif // #ifdef MBED_HEAP_STATS_ENABLED +#ifdef MBED_MEM_TRACING_ENABLED + mem_trace_mutex->lock(); + mbed_mem_trace_malloc(ptr, size, MBED_CALLER_ADDR()); + mem_trace_mutex->unlock(); +#endif // #ifdef MBED_MEM_TRACING_ENABLED + return ptr; +} + +extern "C" void * __wrap__realloc_r(struct _reent * r, void * ptr, size_t size) { + void *new_ptr = NULL; +#ifdef MBED_HEAP_STATS_ENABLED + // Implement realloc_r with malloc and free. + // The function realloc_r can't be used here directly since + // it can call into __wrap__malloc_r (returns ptr + 4) or + // resize memory directly (returns ptr + 0). + + // Note - no lock needed since malloc and free are thread safe + + // Get old size + uint32_t old_size = 0; + if (ptr != NULL) { + alloc_info_t *alloc_info = ((alloc_info_t*)ptr) - 1; + old_size = alloc_info->size; + } + + // Allocate space + if (size != 0) { + new_ptr = malloc(size); + } + + // If the new buffer has been allocated copy the data to it + // and free the old buffer + if (new_ptr != NULL) { + uint32_t copy_size = (old_size < size) ? old_size : size; + memcpy(new_ptr, (void*)ptr, copy_size); + free(ptr); + } +#else // #ifdef MBED_HEAP_STATS_ENABLED + new_ptr = __real__realloc_r(r, ptr, size); +#endif // #ifdef MBED_HEAP_STATS_ENABLED +#ifdef MBED_MEM_TRACING_ENABLED + mem_trace_mutex->lock(); + mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR()); + mem_trace_mutex->unlock(); +#endif // #ifdef MBED_MEM_TRACING_ENABLED + return new_ptr; +} + +extern "C" void __wrap__free_r(struct _reent * r, void * ptr) { +#ifdef MBED_HEAP_STATS_ENABLED + malloc_stats_mutex->lock(); + alloc_info_t *alloc_info = NULL; + if (ptr != NULL) { + alloc_info = ((alloc_info_t*)ptr) - 1; + heap_stats.current_size -= alloc_info->size; + heap_stats.alloc_cnt -= 1; + } + __real__free_r(r, (void*)alloc_info); + malloc_stats_mutex->unlock(); +#else // #ifdef MBED_HEAP_STATS_ENABLED + __real__free_r(r, ptr); +#endif // #ifdef MBED_HEAP_STATS_ENABLED +#ifdef MBED_MEM_TRACING_ENABLED + mem_trace_mutex->lock(); + mbed_mem_trace_free(ptr, MBED_CALLER_ADDR()); + mem_trace_mutex->unlock(); +#endif // #ifdef MBED_MEM_TRACING_ENABLED +} + +#endif // if !defined(FEATURE_UVISOR) + +extern "C" void * __wrap__calloc_r(struct _reent * r, size_t nmemb, size_t size) { + void *ptr = NULL; +#ifdef MBED_HEAP_STATS_ENABLED + // Note - no lock needed since malloc is thread safe + + ptr = malloc(nmemb * size); + if (ptr != NULL) { + memset(ptr, 0, nmemb * size); + } +#else // #ifdef MBED_HEAP_STATS_ENABLED + ptr = __real__calloc_r(r, nmemb, size); +#endif // #ifdef MBED_HEAP_STATS_ENABLED +#ifdef MBED_MEM_TRACING_ENABLED + mem_trace_mutex->lock(); + mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR()); + mem_trace_mutex->unlock(); +#endif // #ifdef MBED_MEM_TRACING_ENABLED + return ptr; +} + + +/******************************************************************************/ +/* ARMCC memory allocation wrappers */ +/******************************************************************************/ + +#elif defined(TOOLCHAIN_ARM) // #if defined(TOOLCHAIN_GCC) + +/* Enable hooking of memory function only if tracing is also enabled */ +#if defined(MBED_MEM_TRACING_ENABLED) || defined(MBED_HEAP_STATS_ENABLED) + +extern "C" { + void *$Super$$malloc(size_t size); + void *$Super$$realloc(void *ptr, size_t size); + void *$Super$$calloc(size_t nmemb, size_t size); + void $Super$$free(void *ptr); +} + +extern "C" void* $Sub$$malloc(size_t size) { + void *ptr = NULL; +#ifdef MBED_HEAP_STATS_ENABLED + malloc_stats_mutex->lock(); + alloc_info_t *alloc_info = (alloc_info_t*)$Super$$malloc(size + sizeof(alloc_info_t)); + if (alloc_info != NULL) { + alloc_info->size = size; + ptr = (void*)(alloc_info + 1); + heap_stats.current_size += size; + heap_stats.total_size += size; + heap_stats.alloc_cnt += 1; + if (heap_stats.current_size > heap_stats.max_size) { + heap_stats.max_size = heap_stats.current_size; + } + } else { + heap_stats.alloc_fail_cnt += 1; + } + malloc_stats_mutex->unlock(); +#else // #ifdef MBED_HEAP_STATS_ENABLED + ptr = $Super$$malloc(size); +#endif // #ifdef MBED_HEAP_STATS_ENABLED +#ifdef MBED_MEM_TRACING_ENABLED + mem_trace_mutex->lock(); + mbed_mem_trace_malloc(ptr, size, MBED_CALLER_ADDR()); + mem_trace_mutex->unlock(); +#endif // #ifdef MBED_MEM_TRACING_ENABLED + return ptr; +} + +extern "C" void* $Sub$$realloc(void *ptr, size_t size) { + void *new_ptr = NULL; +#ifdef MBED_HEAP_STATS_ENABLED + // Note - no lock needed since malloc and free are thread safe + + // Get old size + uint32_t old_size = 0; + if (ptr != NULL) { + alloc_info_t *alloc_info = ((alloc_info_t*)ptr) - 1; + old_size = alloc_info->size; + } + + // Allocate space + if (size != 0) { + new_ptr = malloc(size); + } + + // If the new buffer has been allocated copy the data to it + // and free the old buffer + if (new_ptr != NULL) { + uint32_t copy_size = (old_size < size) ? old_size : size; + memcpy(new_ptr, (void*)ptr, copy_size); + free(ptr); + } +#else // #ifdef MBED_HEAP_STATS_ENABLED + new_ptr = $Super$$realloc(ptr, size); +#endif // #ifdef MBED_HEAP_STATS_ENABLED +#ifdef MBED_MEM_TRACING_ENABLED + mem_trace_mutex->lock(); + mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR()); + mem_trace_mutex->unlock(); +#endif // #ifdef MBED_MEM_TRACING_ENABLED + return new_ptr; +} + +extern "C" void *$Sub$$calloc(size_t nmemb, size_t size) { + void *ptr = NULL; +#ifdef MBED_HEAP_STATS_ENABLED + // Note - no lock needed since malloc is thread safe + ptr = malloc(nmemb * size); + if (ptr != NULL) { + memset(ptr, 0, nmemb * size); + } +#else // #ifdef MBED_HEAP_STATS_ENABLED + ptr = $Super$$calloc(nmemb, size); +#endif // #ifdef MBED_HEAP_STATS_ENABLED +#ifdef MBED_MEM_TRACING_ENABLED + mem_trace_mutex->lock(); + mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR()); + mem_trace_mutex->unlock(); +#endif // #ifdef MBED_MEM_TRACING_ENABLED + return ptr; +} + +extern "C" void $Sub$$free(void *ptr) { +#ifdef MBED_HEAP_STATS_ENABLED + malloc_stats_mutex->lock(); + alloc_info_t *alloc_info = NULL; + if (ptr != NULL) { + alloc_info = ((alloc_info_t*)ptr) - 1; + heap_stats.current_size -= alloc_info->size; + heap_stats.alloc_cnt -= 1; + } + $Super$$free((void*)alloc_info); + malloc_stats_mutex->unlock(); +#else // #ifdef MBED_HEAP_STATS_ENABLED + $Super$$free(ptr); +#endif // #ifdef MBED_HEAP_STATS_ENABLED +#ifdef MBED_MEM_TRACING_ENABLED + mem_trace_mutex->lock(); + mbed_mem_trace_free(ptr, MBED_CALLER_ADDR()); + mem_trace_mutex->unlock(); +#endif // #ifdef MBED_MEM_TRACING_ENABLED +} + +#endif // #if defined(MBED_MEM_TRACING_ENABLED) || defined(MBED_HEAP_STATS_ENABLED) + +/******************************************************************************/ +/* Allocation wrappers for other toolchains are not supported yet */ +/******************************************************************************/ + +#else // #if defined(TOOLCHAIN_GCC) + +#ifdef MBED_MEM_TRACING_ENABLED +#warning Memory tracing is not supported with the current toolchain. +#endif + +#ifdef MBED_HEAP_STATS_ENABLED +#warning Heap statistics are not supported with the current toolchain. +#endif + +#endif // #if defined(TOOLCHAIN_GCC) + diff --git a/hal/common/mbed_critical.c b/hal/common/mbed_critical.c index 0afe0d5ad73..f65f67a8b5d 100644 --- a/hal/common/mbed_critical.c +++ b/hal/common/mbed_critical.c @@ -86,6 +86,11 @@ void core_util_critical_section_exit(void) #if EXCLUSIVE_ACCESS +/* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */ +#if defined (__CC_ARM) +#pragma diag_suppress 3731 +#endif + bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue) { uint8_t currentValue = __LDREXB((volatile uint8_t*)ptr); diff --git a/hal/common/mbed_mem_trace.c b/hal/common/mbed_mem_trace.c new file mode 100644 index 00000000000..ab753fadc71 --- /dev/null +++ b/hal/common/mbed_mem_trace.c @@ -0,0 +1,115 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include "mbed_mem_trace.h" +#include "critical.h" + +/****************************************************************************** + * Internal variables, functions and helpers + *****************************************************************************/ + +/* The callback function that will be called after a traced memory operations finishes. */ +static mbed_mem_trace_cb_t mem_trace_cb; +/* 'trave_level' guards "trace inside trace" situations (for example, the implementation + * of realloc() might call malloc() internally, and since malloc() is also traced, this could + * result in two calls to the callback function instead of one. */ +static uint8_t trace_level; + +/****************************************************************************** + * Public interface + *****************************************************************************/ + +void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb) { + mem_trace_cb = cb; +} + +void *mbed_mem_trace_malloc(void *res, size_t size, void *caller) { + if (mem_trace_cb) { + if (core_util_atomic_incr_u8(&trace_level, 1) == 1) { + mem_trace_cb(MBED_MEM_TRACE_MALLOC, res, caller, size); + } + core_util_atomic_decr_u8(&trace_level, 1); + } + return res; +} + +void *mbed_mem_trace_realloc(void *res, void *ptr, size_t size, void *caller) { + if (mem_trace_cb) { + if (core_util_atomic_incr_u8(&trace_level, 1) == 1) { + mem_trace_cb(MBED_MEM_TRACE_REALLOC, res, caller, ptr, size); + } + core_util_atomic_decr_u8(&trace_level, 1); + } + return res; +} + +void *mbed_mem_trace_calloc(void *res, size_t num, size_t size, void *caller) { + if (mem_trace_cb) { + if (core_util_atomic_incr_u8(&trace_level, 1) == 1) { + mem_trace_cb(MBED_MEM_TRACE_CALLOC, res, caller, num, size); + } + core_util_atomic_decr_u8(&trace_level, 1); + } + return res; +} + +void mbed_mem_trace_free(void *ptr, void *caller) { + if (mem_trace_cb) { + if (core_util_atomic_incr_u8(&trace_level, 1) == 1) { + mem_trace_cb(MBED_MEM_TRACE_FREE, NULL, caller, ptr); + } + core_util_atomic_decr_u8(&trace_level, 1); + } +} + +void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...) { + va_list va; + size_t temp_s1, temp_s2; + void *temp_ptr; + + va_start(va, caller); + switch(op) { + case MBED_MEM_TRACE_MALLOC: + temp_s1 = va_arg(va, size_t); + printf(MBED_MEM_DEFAULT_TRACER_PREFIX "m:%p;%p-%u\n", res, caller, temp_s1); + break; + + case MBED_MEM_TRACE_REALLOC: + temp_ptr = va_arg(va, void*); + temp_s1 = va_arg(va, size_t); + printf(MBED_MEM_DEFAULT_TRACER_PREFIX "r:%p;%p-%p;%u\n", res, caller, temp_ptr, temp_s1); + break; + + case MBED_MEM_TRACE_CALLOC: + temp_s1 = va_arg(va, size_t); + temp_s2 = va_arg(va, size_t); + printf(MBED_MEM_DEFAULT_TRACER_PREFIX "c:%p;%p-%u;%u\n", res, caller, temp_s1, temp_s2); + break; + + case MBED_MEM_TRACE_FREE: + temp_ptr = va_arg(va, void*); + printf(MBED_MEM_DEFAULT_TRACER_PREFIX "f:%p;%p-%p\n", res, caller, temp_ptr); + break; + + default: + printf("?\n"); + } + va_end(va); +} + diff --git a/hal/common/retarget.cpp b/hal/common/retarget.cpp index f268e2da10e..c42190fbc4b 100644 --- a/hal/common/retarget.cpp +++ b/hal/common/retarget.cpp @@ -24,7 +24,9 @@ #include "SingletonPtr.h" #include "PlatformMutex.h" #include "mbed_error.h" +#include "mbed_stats.h" #include +#include #if DEVICE_STDIO_MESSAGES #include #endif @@ -478,26 +480,11 @@ extern "C" WEAK void __cxa_pure_virtual(void) { #endif #if defined(TOOLCHAIN_GCC) -#ifdef FEATURE_UVISOR + +#ifdef FEATURE_UVISOR #include "uvisor-lib/uvisor-lib.h" #endif/* FEATURE_UVISOR */ -#ifndef FEATURE_UVISOR -extern "C" { -void * __wrap__malloc_r(struct _reent * r, size_t size) { - extern void * __real__malloc_r(struct _reent * r, size_t size); - return __real__malloc_r(r, size); -} -void * __wrap__realloc_r(struct _reent * r, void * ptr, size_t size) { - extern void * __real__realloc_r(struct _reent * r, void * ptr, size_t size); - return __real__realloc_r(r, ptr, size); -} -void __wrap__free_r(struct _reent * r, void * ptr) { - extern void __real__free_r(struct _reent * r, void * ptr); - __real__free_r(r, ptr); -} -} -#endif/* FEATURE_UVISOR */ extern "C" WEAK void software_init_hook_rtos(void) { @@ -684,6 +671,8 @@ char* mbed_gets(char*s, int size, FILE *_file){ #endif } +} // namespace mbed + #if defined (__ICCARM__) // Stub out locks when an rtos is not present extern "C" WEAK void __iar_system_Mtxinit(__iar_Rmtx *mutex) {} @@ -723,9 +712,44 @@ extern "C" void __env_unlock( struct _reent *_r ) { __rtos_env_unlock(_r); } -#endif -} // namespace mbed +#define CXA_GUARD_INIT_DONE (1 << 0) +#define CXA_GUARD_INIT_IN_PROGRESS (1 << 1) +#define CXA_GUARD_MASK (CXA_GUARD_INIT_DONE | CXA_GUARD_INIT_IN_PROGRESS) + +extern "C" int __cxa_guard_acquire(int *guard_object_p) +{ + uint8_t *guard_object = (uint8_t *)guard_object_p; + if (CXA_GUARD_INIT_DONE == (*guard_object & CXA_GUARD_MASK)) { + return 0; + } + singleton_lock(); + if (CXA_GUARD_INIT_DONE == (*guard_object & CXA_GUARD_MASK)) { + singleton_unlock(); + return 0; + } + MBED_ASSERT(0 == (*guard_object & CXA_GUARD_MASK)); + *guard_object = *guard_object | CXA_GUARD_INIT_IN_PROGRESS; + return 1; +} + +extern "C" void __cxa_guard_release(int *guard_object_p) +{ + uint8_t *guard_object = (uint8_t *)guard_object_p; + MBED_ASSERT(CXA_GUARD_INIT_IN_PROGRESS == (*guard_object & CXA_GUARD_MASK)); + *guard_object = (*guard_object & ~CXA_GUARD_MASK) | CXA_GUARD_INIT_DONE; + singleton_unlock(); +} + +extern "C" void __cxa_guard_abort(int *guard_object_p) +{ + uint8_t *guard_object = (uint8_t *)guard_object_p; + MBED_ASSERT(CXA_GUARD_INIT_IN_PROGRESS == (*guard_object & CXA_GUARD_MASK)); + *guard_object = *guard_object & ~CXA_GUARD_INIT_IN_PROGRESS; + singleton_unlock(); +} + +#endif void *operator new(std::size_t count) { diff --git a/hal/targets.json b/hal/targets.json index 9e5416a7b52..8bbdf763e3d 100644 --- a/hal/targets.json +++ b/hal/targets.json @@ -624,11 +624,12 @@ "core": "Cortex-M0", "default_toolchain": "uARM", "extra_labels": ["STM", "STM32F0", "STM32F031K6"], + "macros": ["DEVICE_RTC_LSI=1"], "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"], "inherits": ["Target"], "progen": {"target": "nucleo-f031k6"}, "detect_code": ["0791"], - "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "default_build": "small", "release_versions": ["2"] }, @@ -637,11 +638,12 @@ "core": "Cortex-M0", "default_toolchain": "uARM", "extra_labels": ["STM", "STM32F0", "STM32F042K6"], + "macros": ["DEVICE_RTC_LSI=1"], "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"], "inherits": ["Target"], "progen": {"target": "nucleo-f042k6"}, "detect_code": ["0785"], - "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "default_build": "small", "release_versions": ["2"] }, @@ -690,7 +692,7 @@ "inherits": ["Target"], "progen": {"target": "nucleo-f103rb"}, "detect_code": ["0700"], - "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "release_versions": ["2", "5"] }, "NUCLEO_F207ZG": { @@ -702,9 +704,9 @@ "inherits": ["Target"], "progen": {"target": "nucleo-f207zg"}, "detect_code": ["0835"], - "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "features": ["IPV4"], - "release_versions": ["2"] + "release_versions": ["2", "5"] }, "NUCLEO_F302R8": { "supported_form_factors": ["ARDUINO", "MORPHO"], @@ -724,6 +726,7 @@ "core": "Cortex-M4F", "default_toolchain": "ARM", "extra_labels": ["STM", "STM32F3", "STM32F303K8"], + "macros": ["DEVICE_RTC_LSI=1"], "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"], "inherits": ["Target"], "progen": {"target": "nucleo-f303k8"}, @@ -744,6 +747,19 @@ "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "release_versions": ["2", "5"] }, + "NUCLEO_F303ZE": { + "supported_form_factors": ["ARDUINO", "MORPHO"], + "core": "Cortex-M4F", + "fpu": "single", + "default_toolchain": "uARM", + "extra_labels": ["STM", "STM32F3", "STM32F303ZE"], + "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"], + "inherits": ["Target"], + "progen": {"target": "nucleo-f303ze"}, + "detect_code": ["0745"], + "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], + "release_versions": ["2"] + }, "NUCLEO_F334R8": { "supported_form_factors": ["ARDUINO", "MORPHO"], "core": "Cortex-M4F", @@ -814,8 +830,8 @@ "extra_labels": ["STM", "STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xx"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], "progen": {"target": "nucleo-f429zi"}, - "macros": ["MBEDTLS_ENTROPY_HARDWARE_ALT"], - "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], + "macros": ["MBEDTLS_ENTROPY_HARDWARE_ALT", "DEVICE_RTC_LSI=1"], + "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "detect_code": ["0796"], "features": ["IPV4"], "release_versions": ["2", "5"] @@ -842,7 +858,7 @@ "progen": {"target": "nucleo-f446ze"}, "detect_code": ["0778"], "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], - "release_versions": ["2"] + "release_versions": ["2", "5"] }, "B96B_F446VE": { @@ -1022,18 +1038,20 @@ "core": "Cortex-M4F", "default_toolchain": "ARM", "extra_labels": ["STM", "STM32F3", "STM32F303", "STM32F303VC"], + "macros": ["DEVICE_RTC_LSI=1"], "supported_toolchains": ["GCC_ARM"], - "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"] + "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"] }, "DISCO_F334C8": { "inherits": ["Target"], "core": "Cortex-M4F", "default_toolchain": "ARM", "extra_labels": ["STM", "STM32F3", "STM32F334C8"], + "macros": ["DEVICE_RTC_LSI=1"], "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"], "progen": {"target": "disco-f334c8"}, "detect_code": ["0810"], - "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "default_lib": "small", "release_versions": ["2"] }, @@ -1050,10 +1068,10 @@ "core": "Cortex-M4F", "default_toolchain": "ARM", "extra_labels": ["STM", "STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xx"], - "macros": ["MBEDTLS_ENTROPY_HARDWARE_ALT"], + "macros": ["MBEDTLS_ENTROPY_HARDWARE_ALT", "DEVICE_RTC_LSI=1"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], "progen": {"target": "disco-f429zi"}, - "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "release_versions": ["2", "5"] }, "DISCO_F469NI": { @@ -1093,6 +1111,18 @@ "features": ["IPV4"], "release_versions": ["2", "5"] }, + "DISCO_F769NI": { + "inherits": ["Target"], + "core": "Cortex-M7FD", + "extra_labels": ["STM", "STM32F7", "STM32F769", "STM32F769NI"], + "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], + "default_toolchain": "ARM", + "progen": {"target": "disco-f769ni"}, + "detect_code": ["0817"], + "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], + "features": ["IPV4"], + "release_versions": ["2"] + }, "DISCO_L476VG": { "inherits": ["Target"], "core": "Cortex-M4F", @@ -1101,7 +1131,7 @@ "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"], "progen": {"target": "disco-l476vg"}, "detect_code": ["0820"], - "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "release_versions": ["2", "5"] }, "MTS_MDOT_F405RG": { @@ -1148,10 +1178,11 @@ "core": "Cortex-M3", "default_toolchain": "uARM", "extra_labels": ["STM", "STM32L1", "STM32L152RC"], + "macros": ["DEVICE_RTC_LSI=1"], "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"], "progen": {"target": "stm32l151rc"}, "detect_code": ["4100"], - "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "default_build": "small", "release_versions": ["2"] }, @@ -1180,9 +1211,10 @@ "default_toolchain": "uARM", "program_cycle_s": 1.5, "extra_labels": ["STM", "STM32L1", "STM32L151RC"], + "macros": ["DEVICE_RTC_LSI=1"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM"], "progen": {"target": "stm32l151rc"}, - "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "RTC_LSI", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "default_build": "small" }, "MCU_NRF51": { @@ -1550,6 +1582,22 @@ "extra_labels_add": ["NRF51_MICROBIT"], "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"] }, + "MTM_MTCONNECT04S": { + "inherits": ["MCU_NRF51_32K"], + "progen": {"target": "mtm-mtconnect04s"}, + "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"], + "release_versions": ["2"] + }, + "MTM_MTCONNECT04S_BOOT": { + "inherits": ["MCU_NRF51_32K_BOOT"], + "extra_labels_add": ["MTM_CONNECT04S"], + "macros_add": ["TARGET_MTM_CONNECT04S"] + }, + "MTM_MTCONNECT04S_OTA": { + "inherits": ["MCU_NRF51_32K_OTA"], + "extra_labels_add": ["MTM_CONNECT04S"], + "macros_add": ["TARGET_MTM_CONNECT04S"] + }, "TY51822R3": { "inherits": ["MCU_NRF51_32K_UNIFIED"], @@ -2001,6 +2049,34 @@ "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], "release_versions": ["2", "5"] }, + "DELTA_DFBM_NQ620": { + "supported_form_factors": ["ARDUINO"], + "inherits": ["MCU_NRF52"], + "progen": {"target": "dfbm-nq620"}, + "macros_add": [ + "BOARD_PCA10040", + "NRF52_PAN_12", + "NRF52_PAN_15", + "NRF52_PAN_58", + "NRF52_PAN_55", + "NRF52_PAN_54", + "NRF52_PAN_31", + "NRF52_PAN_30", + "NRF52_PAN_51", + "NRF52_PAN_36", + "NRF52_PAN_53", + "S132", + "CONFIG_GPIO_AS_PINRESET", + "BLE_STACK_SUPPORT_REQD", + "SWI_DISABLE0", + "NRF52_PAN_20", + "NRF52_PAN_64", + "NRF52_PAN_62", + "NRF52_PAN_63" + ], + "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], + "release_versions": ["2", "5"] + }, "BLUEPILL_F103C8": { "core": "Cortex-M3", "default_toolchain": "GCC_ARM", diff --git a/hal/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/startup_LPC11U68.cpp b/hal/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/startup_LPC11U68.cpp index 2acd2af4abc..6faa114bc23 100644 --- a/hal/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/startup_LPC11U68.cpp +++ b/hal/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/startup_LPC11U68.cpp @@ -137,7 +137,8 @@ AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) { /* Reset entry point*/ -extern "C" void software_init_hook(void) __attribute__((weak)); +extern "C" void software_init_hook(void); +extern "C" void pre_main(void) __attribute__((weak)); AFTER_VECTORS void ResetISR(void) { unsigned int LoadAddr, ExeAddr, SectionLen; @@ -169,9 +170,10 @@ AFTER_VECTORS void ResetISR(void) { SystemInit(); - if (software_init_hook) - software_init_hook(); - else { + if (pre_main) { // give control to the RTOS + software_init_hook(); // this will also call __libc_init_array + } + else { // for BareMetal (non-RTOS) build __libc_init_array(); main(); } diff --git a/hal/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp b/hal/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp index 8aa0d83fe41..a9ffaf6250d 100644 --- a/hal/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp +++ b/hal/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp @@ -113,7 +113,8 @@ extern unsigned int __data_section_table; extern unsigned int __data_section_table_end; extern unsigned int __bss_section_table_end; -extern "C" void software_init_hook(void) __attribute__((weak)); +extern "C" void software_init_hook(void); +extern "C" void pre_main(void) __attribute__((weak)); AFTER_VECTORS void ResetISR(void) { unsigned int LoadAddr, ExeAddr, SectionLen; @@ -136,9 +137,10 @@ AFTER_VECTORS void ResetISR(void) { } SystemInit(); - if (software_init_hook) // give control to the RTOS + if (pre_main) { // give control to the RTOS software_init_hook(); // this will also call __libc_init_array - else { + } + else { // for BareMetal (non-RTOS) build __libc_init_array(); main(); } diff --git a/hal/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/startup_LPC11xx.cpp b/hal/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/startup_LPC11xx.cpp index 5532eadc917..c8807ea9b08 100644 --- a/hal/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/startup_LPC11xx.cpp +++ b/hal/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/startup_LPC11xx.cpp @@ -113,7 +113,8 @@ extern unsigned int __data_section_table; extern unsigned int __data_section_table_end; extern unsigned int __bss_section_table_end; -extern "C" void software_init_hook(void) __attribute__((weak)); +extern "C" void software_init_hook(void); +extern "C" void pre_main(void) __attribute__((weak)); AFTER_VECTORS void ResetISR(void) { unsigned int LoadAddr, ExeAddr, SectionLen; @@ -136,9 +137,10 @@ AFTER_VECTORS void ResetISR(void) { } SystemInit(); - if (software_init_hook) // give control to the RTOS + if (pre_main) { // give control to the RTOS software_init_hook(); // this will also call __libc_init_array - else { + } + else { // for BareMetal (non-RTOS) build __libc_init_array(); main(); } @@ -147,7 +149,7 @@ AFTER_VECTORS void ResetISR(void) { AFTER_VECTORS void NMI_Handler (void) {while(1){}} AFTER_VECTORS void HardFault_Handler(void) {while(1){}} -AFTER_VECTORS void SVC_Handler (void) {while(1){}} +AFTER_VECTORS void SVC_Handler (void) {while(1){}} AFTER_VECTORS void PendSV_Handler (void) {while(1){}} AFTER_VECTORS void SysTick_Handler (void) {while(1){}} AFTER_VECTORS void IntDefaultHandler(void) {while(1){}} diff --git a/hal/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_CR/startup_LPC15xx.cpp b/hal/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_CR/startup_LPC15xx.cpp index 3712091f14d..d0e6e2111ba 100644 --- a/hal/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_CR/startup_LPC15xx.cpp +++ b/hal/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_CR/startup_LPC15xx.cpp @@ -166,7 +166,8 @@ AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) { /* Reset entry point*/ -extern "C" void software_init_hook(void) __attribute__((weak)); +extern "C" void software_init_hook(void); +extern "C" void pre_main(void) __attribute__((weak)); AFTER_VECTORS void ResetISR(void) { unsigned int LoadAddr, ExeAddr, SectionLen; @@ -187,9 +188,10 @@ AFTER_VECTORS void ResetISR(void) { } SystemInit(); - if (software_init_hook) - software_init_hook(); - else { + if (pre_main) { // give control to the RTOS + software_init_hook(); // this will also call __libc_init_array + } + else { // for BareMetal (non-RTOS) build __libc_init_array(); main(); } diff --git a/hal/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/startup_LPC17xx.cpp b/hal/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/startup_LPC17xx.cpp index ebf805d76e0..569ae39f18c 100644 --- a/hal/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/startup_LPC17xx.cpp +++ b/hal/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/startup_LPC17xx.cpp @@ -130,7 +130,8 @@ AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) { for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0; } -extern "C" void software_init_hook(void) __attribute__((weak)); +extern "C" void software_init_hook(void); +extern "C" void pre_main(void) __attribute__((weak)); AFTER_VECTORS void ResetISR(void) { unsigned int LoadAddr, ExeAddr, SectionLen; @@ -151,9 +152,10 @@ AFTER_VECTORS void ResetISR(void) { } SystemInit(); - if (software_init_hook) // give control to the RTOS + if (pre_main) { // give control to the RTOS software_init_hook(); // this will also call __libc_init_array - else { + } + else { // for BareMetal (non-RTOS) build __libc_init_array(); main(); } diff --git a/hal/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/startup_lpc407x_8x.cpp b/hal/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/startup_lpc407x_8x.cpp index 56cf9768e2b..571e6abca3b 100644 --- a/hal/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/startup_lpc407x_8x.cpp +++ b/hal/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/startup_lpc407x_8x.cpp @@ -260,7 +260,8 @@ extern unsigned int __bss_section_table_end; // library. //***************************************************************************** -extern "C" void software_init_hook(void) __attribute__((weak)); +extern "C" void software_init_hook(void); +extern "C" void pre_main(void) __attribute__((weak)); __attribute__ ((section(".after_vectors"))) void @@ -319,26 +320,15 @@ ResetISR(void) { *pSCB_VTOR = (unsigned int)g_pfnVectors; } -//#ifdef __USE_CMSIS - SystemInit(); -//#endif - if (software_init_hook) // give control to the RTOS - software_init_hook(); // this will also call __libc_init_array - else { -#if defined (__cplusplus) - // - // Call C++ library initialisation - // - __libc_init_array(); -#endif - -#if defined (__REDLIB__) - // Call the Redlib library, which in turn calls main() - __main() ; -#else - main(); + SystemInit(); + if (pre_main) { // give control to the RTOS + software_init_hook(); // this will also call __libc_init_array + } + else { // for BareMetal (non-RTOS) build + __libc_init_array(); + main(); #endif - } + } // // main() shouldn't return, but if it does, we'll just enter an infinite loop // diff --git a/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/NCS36510.h b/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/NCS36510.h index e94b935f7d9..15c5e94967a 100644 --- a/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/NCS36510.h +++ b/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/NCS36510.h @@ -1,6 +1,6 @@ /**************************************************************************/ /** - * @file ARMCM3.h + * @file NCS36510.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * for CM3 Device Series * @version V1.05 diff --git a/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/cmsis_nvic.c b/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/cmsis_nvic.c index f84ddde08a9..94baebee658 100644 --- a/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/cmsis_nvic.c +++ b/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/cmsis_nvic.c @@ -7,9 +7,15 @@ * $Rev: 0.1 $ * $Date: 2015-11-06 $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. +* Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductorâ€). +* All rights reserved. This software and/or documentation is licensed by ON Semiconductor +* under limited terms and conditions. The terms and conditions pertaining to the software +* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf +* (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Softwareâ€) and +* if applicable the software license agreement. Do not use this software and/or +* documentation unless you have carefully read and you agree to the limited terms and +* conditions. By using this software and/or documentation, you agree to the limited +* terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF @@ -18,10 +24,11 @@ * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * @endinternal * -* @ingroup app +* @ingroup * * @details */ + #include #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM diff --git a/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/cmsis_nvic.h b/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/cmsis_nvic.h index b25793941e7..62f15e2e7db 100644 --- a/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/cmsis_nvic.h +++ b/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/cmsis_nvic.h @@ -7,9 +7,15 @@ * $Rev: 0.1 $ * $Date: 2015-11-06 $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. +* Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductorâ€). +* All rights reserved. This software and/or documentation is licensed by ON Semiconductor +* under limited terms and conditions. The terms and conditions pertaining to the software +* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf +* (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Softwareâ€) and +* if applicable the software license agreement. Do not use this software and/or +* documentation unless you have carefully read and you agree to the limited terms and +* conditions. By using this software and/or documentation, you agree to the limited +* terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF @@ -18,7 +24,7 @@ * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * @endinternal * -* @ingroup app +* @ingroup * * @details */ diff --git a/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/system_NCS36510.c b/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/system_NCS36510.c index f897a83c01e..8bf95ae8129 100644 --- a/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/system_NCS36510.c +++ b/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/system_NCS36510.c @@ -1,5 +1,5 @@ /**************************************************************************//** - * @file system_ARMCM3.c + * @file system_NCS36510.c * @brief CMSIS Cortex-M3 Device System Source File * for CM3 Device Series * @version V1.05 diff --git a/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/system_NCS36510.h b/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/system_NCS36510.h index abaeb7394f2..0f277e9f1f4 100644 --- a/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/system_NCS36510.h +++ b/hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/system_NCS36510.h @@ -1,5 +1,5 @@ /**************************************************************************//** - * @file system_ARMCM3.h + * @file system_NCS36510.h * @brief CMSIS Cortex-M3 Device System Header File * for CM3 Device Series * @version V1.05 diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_MICRO/startup_stm32f303xe.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_MICRO/startup_stm32f303xe.S new file mode 100644 index 00000000000..fbc2e00a8a5 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_MICRO/startup_stm32f303xe.S @@ -0,0 +1,407 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f303xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 12-Sept-2014 +;* Description : STM32F303xE devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20004000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX + DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FMC_IRQHandler ; FMC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD ADC4_IRQHandler ; ADC4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3 + DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6 + DCD COMP7_IRQHandler ; COMP7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD USB_HP_IRQHandler ; USB High Priority remap + DCD USB_LP_IRQHandler ; USB Low Priority remap + DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI + DCD TIM20_BRK_IRQHandler ; TIM20 Break + DCD TIM20_UP_IRQHandler ; TIM20 Update + DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger and Commutation + DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_TSC_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN_RX0_IRQHandler [WEAK] + EXPORT CAN_RX1_IRQHandler [WEAK] + EXPORT CAN_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT ADC4_IRQHandler [WEAK] + EXPORT COMP1_2_3_IRQHandler [WEAK] + EXPORT COMP4_5_6_IRQHandler [WEAK] + EXPORT COMP7_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT USBWakeUp_RMP_IRQHandler [WEAK] + EXPORT TIM20_BRK_IRQHandler [WEAK] + EXPORT TIM20_UP_IRQHandler [WEAK] + EXPORT TIM20_TRG_COM_IRQHandler [WEAK] + EXPORT TIM20_CC_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_TSC_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN_TX_IRQHandler +USB_LP_CAN_RX0_IRQHandler +CAN_RX1_IRQHandler +CAN_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FMC_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +ADC4_IRQHandler +COMP1_2_3_IRQHandler +COMP4_5_6_IRQHandler +COMP7_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +USBWakeUp_RMP_IRQHandler +TIM20_BRK_IRQHandler +TIM20_UP_IRQHandler +TIM20_TRG_COM_IRQHandler +TIM20_CC_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler + + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_MICRO/stm32f303xe.sct b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_MICRO/stm32f303xe.sct new file mode 100644 index 00000000000..e861c23b2cf --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_MICRO/stm32f303xe.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F303RE: 512KB FLASH (0x80000) + 64KB SRAM (0x10000) +LR_IROM1 0x08000000 0x80000 { ; load region size_region + + ER_IROM1 0x08000000 0x80000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; 101 vectors = 404 bytes (0x194) to be reserved in RAM + RW_IRAM1 (0x20000000+0x194) (0x10000-0x194) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_STD/startup_stm32f303xe.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_STD/startup_stm32f303xe.S new file mode 100644 index 00000000000..536b08fa608 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_STD/startup_stm32f303xe.S @@ -0,0 +1,380 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f303xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 12-Sept-2014 +;* Description : STM32F303xE devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20004000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX + DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FMC_IRQHandler ; FMC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD ADC4_IRQHandler ; ADC4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3 + DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6 + DCD COMP7_IRQHandler ; COMP7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD USB_HP_IRQHandler ; USB High Priority remap + DCD USB_LP_IRQHandler ; USB Low Priority remap + DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI + DCD TIM20_BRK_IRQHandler ; TIM20 Break + DCD TIM20_UP_IRQHandler ; TIM20 Update + DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger and Commutation + DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_TSC_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN_RX0_IRQHandler [WEAK] + EXPORT CAN_RX1_IRQHandler [WEAK] + EXPORT CAN_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT ADC4_IRQHandler [WEAK] + EXPORT COMP1_2_3_IRQHandler [WEAK] + EXPORT COMP4_5_6_IRQHandler [WEAK] + EXPORT COMP7_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT USBWakeUp_RMP_IRQHandler [WEAK] + EXPORT TIM20_BRK_IRQHandler [WEAK] + EXPORT TIM20_UP_IRQHandler [WEAK] + EXPORT TIM20_TRG_COM_IRQHandler [WEAK] + EXPORT TIM20_CC_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_TSC_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN_TX_IRQHandler +USB_LP_CAN_RX0_IRQHandler +CAN_RX1_IRQHandler +CAN_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FMC_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +ADC4_IRQHandler +COMP1_2_3_IRQHandler +COMP4_5_6_IRQHandler +COMP7_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +USBWakeUp_RMP_IRQHandler +TIM20_BRK_IRQHandler +TIM20_UP_IRQHandler +TIM20_TRG_COM_IRQHandler +TIM20_CC_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler + + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_STD/stm32f303xe.sct b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_STD/stm32f303xe.sct new file mode 100644 index 00000000000..e861c23b2cf --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_STD/stm32f303xe.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F303RE: 512KB FLASH (0x80000) + 64KB SRAM (0x10000) +LR_IROM1 0x08000000 0x80000 { ; load region size_region + + ER_IROM1 0x08000000 0x80000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; 101 vectors = 404 bytes (0x194) to be reserved in RAM + RW_IRAM1 (0x20000000+0x194) (0x10000-0x194) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_STD/sys.cpp similarity index 70% rename from hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device.h rename to hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_STD/sys.cpp index f0799e9083e..bb665909b98 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_ARM_STD/sys.cpp @@ -1,6 +1,6 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer ******************************************************************************* * Copyright (c) 2014, STMicroelectronics * All rights reserved. @@ -26,29 +26,31 @@ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H +#ifdef __cplusplus +extern "C" { +#endif +#include +#include +extern char Image$$RW_IRAM1$$ZI$$Limit[]; +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif +#ifdef __cplusplus +} +#endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_GCC_ARM/STM32F303XE.ld b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_GCC_ARM/STM32F303XE.ld new file mode 100644 index 00000000000..a98a441f7d8 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_GCC_ARM/STM32F303XE.ld @@ -0,0 +1,155 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K + CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 16K + RAM (rwx) : ORIGIN = 0x20000194, LENGTH = 64K - 0x194 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S new file mode 100644 index 00000000000..efa5681b0e5 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S @@ -0,0 +1,505 @@ +/** + ****************************************************************************** + * @file startup_stm32f303xe.s + * @author MCD Application Team + * @version + * @date 12-Sept-2014 + * @brief STM32F303xE devices vector table for Atollic + * TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Atollic update: set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main +/** + * Calling the crt0 'cold-start' entry point. There __libc_init_array is called + * and when existing hardware_init_hook() and software_init_hook() before + * starting main(). software_init_hook() is available and has to be called due + * to initializsation when using rtos. +*/ + bl _start + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_TSC_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN_TX_IRQHandler + .word USB_LP_CAN_RX0_IRQHandler + .word CAN_RX1_IRQHandler + .word CAN_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FMC_IRQHandler + .word 0 + .word 0 + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ADC4_IRQHandler + .word 0 + .word 0 + .word COMP1_2_3_IRQHandler + .word COMP4_5_6_IRQHandler + .word COMP7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word USBWakeUp_RMP_IRQHandler + .word TIM20_BRK_IRQHandler + .word TIM20_UP_IRQHandler + .word TIM20_TRG_COM_IRQHandler + .word TIM20_CC_IRQHandler + .word FPU_IRQHandler + .word 0 + .word 0 + .word SPI4_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_TSC_IRQHandler + .thumb_set EXTI2_TSC_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN_TX_IRQHandler + .thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN_RX0_IRQHandler + .thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler + + .weak CAN_RX1_IRQHandler + .thumb_set CAN_RX1_IRQHandler,Default_Handler + + .weak CAN_SCE_IRQHandler + .thumb_set CAN_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ADC4_IRQHandler + .thumb_set ADC4_IRQHandler,Default_Handler + + .weak COMP1_2_3_IRQHandler + .thumb_set COMP1_2_3_IRQHandler,Default_Handler + + .weak COMP4_5_6_IRQHandler + .thumb_set COMP4_5_6_IRQHandler,Default_Handler + + .weak COMP7_IRQHandler + .thumb_set COMP7_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak USBWakeUp_RMP_IRQHandler + .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler + + .weak TIM20_BRK_IRQHandler + .thumb_set TIM20_BRK_IRQHandler,Default_Handler + + .weak TIM20_UP_IRQHandler + .thumb_set TIM20_UP_IRQHandler,Default_Handler + + .weak TIM20_TRG_COM_IRQHandler + .thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler + + .weak TIM20_CC_IRQHandler + .thumb_set TIM20_CC_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_IAR/startup_stm32f303xe.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_IAR/startup_stm32f303xe.S new file mode 100644 index 00000000000..e665a1bb6e9 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_IAR/startup_stm32f303xe.S @@ -0,0 +1,610 @@ +;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f303xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 12-Sept-2014 +;* Description : STM32F303RE/STM32F303VE/STM32F303ZE devices vector table +;* for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;*

© COPYRIGHT(c) 2014 STMicroelectronics

+;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; 0: Window WatchDog + DCD PVD_IRQHandler ; 1: PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; 2: Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; 3: RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; 4: FLASH + DCD RCC_IRQHandler ; 5: RCC + DCD EXTI0_IRQHandler ; 6: EXTI Line0 + DCD EXTI1_IRQHandler ; 7: EXTI Line1 + DCD EXTI2_TSC_IRQHandler ; 8: EXTI Line2 and Touch Sense controller + DCD EXTI3_IRQHandler ; 9: EXTI Line3 + DCD EXTI4_IRQHandler ; 10: EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; 11: DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; 12: DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; 13: DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; 14: DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; 15: DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; 16: DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; 17: DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; 18: ADC1 and ADC2 + DCD USB_HP_CAN_TX_IRQHandler ; 19: USB Device High Priority or CAN TX + DCD USB_LP_CAN_RX0_IRQHandler ; 20: USB Device Low Priority or CAN RX0 + DCD CAN_RX1_IRQHandler ; 21: CAN RX1 + DCD CAN_SCE_IRQHandler ; 22: CAN SCE + DCD EXTI9_5_IRQHandler ; 23: External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; 24: TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; 25: TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; 26: TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; 27: TIM1 Capture Compare + DCD TIM2_IRQHandler ; 28: TIM2 + DCD TIM3_IRQHandler ; 29: TIM3 + DCD TIM4_IRQHandler ; 30: TIM4 + DCD I2C1_EV_IRQHandler ; 31: I2C1 Event + DCD I2C1_ER_IRQHandler ; 32: I2C1 Error + DCD I2C2_EV_IRQHandler ; 33: I2C2 Event + DCD I2C2_ER_IRQHandler ; 34: I2C2 Error + DCD SPI1_IRQHandler ; 35: SPI1 + DCD SPI2_IRQHandler ; 36: SPI2 + DCD USART1_IRQHandler ; 37: USART1 + DCD USART2_IRQHandler ; 38: USART2 + DCD USART3_IRQHandler ; 39: USART3 + DCD EXTI15_10_IRQHandler ; 40: External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; 41: RTC Alarm (A and B) through EXTI Line + DCD USBWakeUp_IRQHandler ; 42: USB Wakeup through EXTI line + DCD TIM8_BRK_IRQHandler ; 43: TIM8 Break + DCD TIM8_UP_IRQHandler ; 44: TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; 45: TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; 46: TIM8 Capture Compare + DCD ADC3_IRQHandler ; 47: ADC3 + DCD FMC_IRQHandler ; 48: FMC + DCD 0 ; 49: Reserved + DCD 0 ; 50: Reserved + DCD SPI3_IRQHandler ; 51: SPI3 + DCD UART4_IRQHandler ; 52: UART4 + DCD UART5_IRQHandler ; 53: UART5 + DCD TIM6_DAC_IRQHandler ; 54: TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; 55: TIM7 + DCD DMA2_Channel1_IRQHandler ; 56: DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; 57: DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; 58: DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; 59: DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; 60: DMA2 Channel 5 + DCD ADC4_IRQHandler ; 61: ADC4 + DCD 0 ; 62: Reserved + DCD 0 ; 63: Reserved + DCD COMP1_2_3_IRQHandler ; 64: COMP1, COMP2 and COMP3 + DCD COMP4_5_6_IRQHandler ; 65: COMP4, COMP5 and COMP6 + DCD COMP7_IRQHandler ; 66: COMP7 + DCD 0 ; 67: Reserved + DCD 0 ; 68: Reserved + DCD 0 ; 69: Reserved + DCD 0 ; 70: Reserved + DCD 0 ; 71: Reserved + DCD I2C3_EV_IRQHandler ; 72: I2C3 Event + DCD I2C3_ER_IRQHandler ; 73: I2C3 Error + DCD USB_HP_IRQHandler ; 74: USB High Priority remap + DCD USB_LP_IRQHandler ; 75: USB Low Priority remap + DCD USBWakeUp_RMP_IRQHandler ; 76: USB Wakeup remap through EXTI + DCD TIM20_BRK_IRQHandler ; 77: TIM20 Break + DCD TIM20_UP_IRQHandler ; 78: TIM20 Update + DCD TIM20_TRG_COM_IRQHandler ; 79: TIM20 Trigger and Commutation + DCD TIM20_CC_IRQHandler ; 80: TIM20 Capture Compare + DCD FPU_IRQHandler ; 81: FPU + DCD 0 ; 82: Reserved + DCD 0 ; 83: Reserved + DCD SPI4_IRQHandler ; 84: SPI4 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_TSC_IRQHandler + B EXTI2_TSC_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_HP_CAN_TX_IRQHandler + B USB_HP_CAN_TX_IRQHandler + + PUBWEAK USB_LP_CAN_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_LP_CAN_RX0_IRQHandler + B USB_LP_CAN_RX0_IRQHandler + + PUBWEAK CAN_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN_RX1_IRQHandler + B CAN_RX1_IRQHandler + + PUBWEAK CAN_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN_SCE_IRQHandler + B CAN_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + + PUBWEAK ADC4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC4_IRQHandler + B ADC4_IRQHandler + + PUBWEAK COMP1_2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_2_3_IRQHandler + B COMP1_2_3_IRQHandler + + PUBWEAK COMP4_5_6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP4_5_6_IRQHandler + B COMP4_5_6_IRQHandler + + PUBWEAK COMP7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP7_IRQHandler + B COMP7_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + PUBWEAK USBWakeUp_RMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBWakeUp_RMP_IRQHandler + B USBWakeUp_RMP_IRQHandler + + PUBWEAK TIM20_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM20_BRK_IRQHandler + B TIM20_BRK_IRQHandler + + PUBWEAK TIM20_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM20_UP_IRQHandler + B TIM20_UP_IRQHandler + + PUBWEAK TIM20_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM20_TRG_COM_IRQHandler + B TIM20_TRG_COM_IRQHandler + + PUBWEAK TIM20_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM20_CC_IRQHandler + B TIM20_CC_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_IAR/stm32f303xe.icf b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_IAR/stm32f303xe.icf new file mode 100644 index 00000000000..9b1f074c538 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/TOOLCHAIN_IAR/stm32f303xe.icf @@ -0,0 +1,35 @@ +/* [ROM = 512kb = 0x80000] */ +define symbol __intvec_start__ = 0x08000000; +define symbol __region_ROM_start__ = 0x08000000; +define symbol __region_ROM_end__ = 0x0807FFFF; + +define symbol __region_CCMRAM_start__ = 0x10000000; +define symbol __region_CCMRAM_end__ = 0x10003FFF; + +/* [RAM = 64kb = 0x10000] Vector table dynamic copy: 101 vectors = 404 bytes (0x194) to be reserved in RAM */ +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x20000197; /* Add 4 more bytes to be aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x20000198; +define symbol __region_RAM_end__ = 0x2000FFFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; +define region CCMRAM_region = mem:[from __region_CCMRAM_start__ to __region_CCMRAM_end__]; + +/* Stack and Heap */ +/*Heap 1/4 of ram and stack 1/8*/ +define symbol __size_cstack__ = 0x2000; +define symbol __size_heap__ = 0x4000; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block STACKHEAP }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/device.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/cmsis.h similarity index 90% rename from hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/device.h rename to hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/cmsis.h index 578fc001322..8b9ba0fc384 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/device.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/cmsis.h @@ -1,4 +1,5 @@ /* mbed Microcontroller Library + * A generic CMSIS include header ******************************************************************************* * Copyright (c) 2014, STMicroelectronics * All rights reserved. @@ -27,15 +28,11 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H -//======================================= +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H -#define DEVICE_ID_LENGTH 24 - -#define LED_RED LED3 - -#include "objects.h" +#include "stm32f3xx.h" +#include "cmsis_nvic.h" #endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/cmsis_nvic.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/cmsis_nvic.c new file mode 100644 index 00000000000..2da63fc9af8 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/cmsis_nvic.c @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/cmsis_nvic.h similarity index 76% rename from hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device.h rename to hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/cmsis_nvic.h index a2031eabeb9..eb09b74d89c 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/cmsis_nvic.h @@ -1,6 +1,5 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. /* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors ******************************************************************************* * Copyright (c) 2014, STMicroelectronics * All rights reserved. @@ -28,27 +27,29 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H + */ +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H +// STM32F303RE +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to 0x193 +// Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM +#define NVIC_NUM_VECTORS 101 +#define NVIC_USER_IRQ_OFFSET 16 +#include "cmsis.h" +#ifdef __cplusplus +extern "C" { +#endif +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - -//#define DEVICE_ERROR_RED 0 - -#include "objects.h" +#ifdef __cplusplus +} +#endif #endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/hal_tick.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/hal_tick.c new file mode 100644 index 00000000000..e326cdcecdd --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/hal_tick.c @@ -0,0 +1,120 @@ +/** + ****************************************************************************** + * @file hal_tick.c + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "hal_tick.h" + +TIM_HandleTypeDef TimMasterHandle; +uint32_t PreviousVal = 0; + +void us_ticker_irq_handler(void); + +void timer_irq_handler(void) { + // Channel 1 for mbed timeout + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); + us_ticker_irq_handler(); + } + + // Channel 2 for HAL tick + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); + uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + if ((val - PreviousVal) >= HAL_TICK_DELAY) { + // Increment HAL variable + HAL_IncTick(); + // Prepare next interrupt + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + PreviousVal = val; +#if 0 // For DEBUG only + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6); +#endif + } + } +} + +// Reconfigure the HAL tick using a standard timer instead of systick. +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + // Enable timer clock + TIM_MST_RCC; + + // Reset timer + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; + + // Configure time base + TimMasterHandle.Instance = TIM_MST; + TimMasterHandle.Init.Period = 0xFFFFFFFF; + TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick + TimMasterHandle.Init.ClockDivision = 0; + TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + TimMasterHandle.Init.RepetitionCounter = 0; + HAL_TIM_OC_Init(&TimMasterHandle); + + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler); + NVIC_EnableIRQ(TIM_MST_IRQ); + + // Channel 1 for mbed timeout + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); + + // Channel 2 for HAL tick + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); + PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); + +#if 0 // For DEBUG only + __GPIOB_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/hal_tick.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/hal_tick.h new file mode 100644 index 00000000000..e8acd8c64b9 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/hal_tick.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f3xx.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM2 +#define TIM_MST_IRQ TIM2_IRQn +#define TIM_MST_RCC __TIM2_CLK_ENABLE() + +#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/stm32f303xe.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/stm32f303xe.h new file mode 100644 index 00000000000..b6e93fcb70c --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/stm32f303xe.h @@ -0,0 +1,15169 @@ +/** + ****************************************************************************** + * @file stm32f303xe.h + * @author MCD Application Team + * @version V2.3.0 + * @date 29-April-2015 + * @brief CMSIS STM32F303xE Devices Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f303xe + * @{ + */ + +#ifndef __STM32F303xE_H +#define __STM32F303xE_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001U /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1U /*!< STM32F303xE devices provide an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32F303xE devices use 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< STM32F303xE devices provide an FPU */ +#endif +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F303xE devices Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ + USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */ + USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */ + CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */ + CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ + USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ + USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */ + UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ADC4_IRQn = 61, /*!< ADC4 global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/ + COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/ + COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */ + USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */ + USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */ + USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */ + TIM20_BRK_IRQn = 77, /*!< TIM20 Break Interrupt */ + TIM20_UP_IRQn = 78, /*!< TIM20 Update Interrupt */ + TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger and Commutation Interrupt */ + TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare Interrupt */ + FPU_IRQn = 81, /*!< Floating point Interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f3xx.h" /* STM32F3xx System Header */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, 0x010 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x01C */ + __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1/3 base address + 0x30C */ +} ADC_Common_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief Analog Comparators + */ +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f3xx + * @{ + */ + +#ifndef __STM32F3xx_H +#define __STM32F3xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F3) +#define STM32F3 +#endif /* STM32F3 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F301x8) && !defined (STM32F302x8) && !defined (STM32F318xx) && \ + !defined (STM32F302xC) && !defined (STM32F303xC) && !defined (STM32F358xx) && \ + !defined (STM32F303x8) && !defined (STM32F334x8) && !defined (STM32F328xx) && \ + !defined (STM32F302xE) && !defined (STM32F303xE) && !defined (STM32F398xx) && \ + !defined (STM32F373xC) && !defined (STM32F378xx) + + /* #define STM32F301x8 */ /*!< STM32F301K6, STM32F301K8, STM32F301C6, STM32F301C8, + STM32F301R6 and STM32F301R8 Devices */ + /* #define STM32F302x8 */ /*!< STM32F302K6, STM32F302K8, STM32F302C6, STM32F302C8, + STM32F302R6 and STM32F302R8 Devices */ + /* #define STM32F302xC */ /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC, + STM32F302VB and STM32F302VC Devices */ + /* #define STM32F302xE */ /*!< STM32F302RE, STM32F302VE, STM32F302ZE, STM32F302RD, + STM32F302VD and STM32F302ZD Devices */ + /* #define STM32F303x8 */ /*!< STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8, + STM32F303R6 and STM32F303R8 Devices */ + /* #define STM32F303xC */ /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, + STM32F303VB and STM32F303VC Devices */ +#define STM32F303xE /*!< STM32F303RE, STM32F303VE, STM32F303ZE, STM32F303RD, + STM32F303VD and STM32F303ZD Devices */ + /* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC, + STM32F373R8, STM32F373RB, STM32F373RC, + STM32F373V8, STM32F373VB and STM32F373VC Devices */ + /* #define STM32F334x8 */ /*!< STM32F334K4, STM32F334K6, STM32F334K8, + STM32F334C4, STM32F334C6, STM32F334C8, + STM32F334R4, STM32F334R6 and STM32F334R8 Devices */ + /* #define STM32F318xx */ /*!< STM32F318K8, STM32F318C8: STM32F301x8 with regulator off: STM32F318xx Devices */ + /* #define STM32F328xx */ /*!< STM32F328C8, STM32F328R8: STM32F334x8 with regulator off: STM32F328xx Devices */ + /* #define STM32F358xx */ /*!< STM32F358CC, STM32F358RC, STM32F358VC: STM32F303xC with regulator off: STM32F358xx Devices */ + /* #define STM32F378xx */ /*!< STM32F378CC, STM32F378RC, STM32F378VC: STM32F373xC with regulator off: STM32F378xx Devices */ + /* #define STM32F398xx */ /*!< STM32F398VE: STM32F303xE with regulator off: STM32F398xx Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.3.0 + */ +#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32F3_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\ + |(__STM32F3_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32F3_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32F3_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F301x8) + #include "stm32f301x8.h" +#elif defined(STM32F302x8) + #include "stm32f302x8.h" +#elif defined(STM32F302xC) + #include "stm32f302xc.h" +#elif defined(STM32F302xE) + #include "stm32f302xe.h" +#elif defined(STM32F303x8) + #include "stm32f303x8.h" +#elif defined(STM32F303xC) + #include "stm32f303xc.h" +#elif defined(STM32F303xE) + #include "stm32f303xe.h" +#elif defined(STM32F373xC) + #include "stm32f373xc.h" +#elif defined(STM32F334x8) + #include "stm32f334x8.h" +#elif defined(STM32F318xx) + #include "stm32f318xx.h" +#elif defined(STM32F328xx) + #include "stm32f328xx.h" +#elif defined(STM32F358xx) + #include "stm32f358xx.h" +#elif defined(STM32F378xx) + #include "stm32f378xx.h" +#elif defined(STM32F398xx) + #include "stm32f398xx.h" +#else + #error "Please select first the target STM32F3xx device used in your application (in stm32f3xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +#if defined (USE_HAL_DRIVER) + #include "stm32f3xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F3xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/system_stm32f3xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/system_stm32f3xx.c new file mode 100644 index 00000000000..1bc7fef29c3 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/system_stm32f3xx.c @@ -0,0 +1,459 @@ +/** + ****************************************************************************** + * @file system_stm32f3xx.c + * @author MCD Application Team + * @version V2.3.0 + * @date 29-April-2015 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f3xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 8 MHz) + * | 2- PLL_HSE_XTAL | + * | (external 8 MHz xtal) | + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 72 | 64 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 72 | 64 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 36 | 32 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 72 | 64 + *----------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | NO | NO + *----------------------------------------------------------------------------- + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f3xx_system + * @{ + */ + +/** @addtogroup STM32F3xx_System_Private_Includes + * @{ + */ + +#include "stm32f3xx.h" +#include "hal_tick.h" + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_Macros + * @{ + */ + +/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ +#define USE_PLL_HSE_EXTC (1) /* Use external clock */ +#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock there is no need to + call the 2 first functions listed above, since SystemCoreClock variable is + updated automatically. + */ +uint32_t SystemCoreClock = 72000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes + * @{ + */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +uint8_t SetSysClock_PLL_HSI(void); + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and the PLL configuration is reset. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= 0x00000001U; + + /* Reset CFGR register */ + RCC->CFGR &= 0xF87FC00CU; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= 0xFEF6FFFFU; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ + RCC->CFGR &= 0xFF80FFFFU; + + /* Reset PREDIV1[3:0] bits */ + RCC->CFGR2 &= 0xFFFFFFF0U; + + /* Reset USARTSW[1:0], I2CSW and TIMs bits */ + RCC->CFGR3 &= 0xFF00FCCCU; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000U; + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + + /* Configure the Cube driver */ + SystemCoreClock = 8000000; // At this stage the HSI is used as system clock + HAL_Init(); + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + SetSysClock(); + + /* Reset the timer to avoid issues after the RAM initialization */ + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + +#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; + } + else + { + /* HSI oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull; + } +#else + if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; + } +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ + #if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) + #endif + { + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) + { + while(1) + { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Enable HSE oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) + { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } + else + { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //if (bypass == 0) + // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal + //else + // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz + + return 1; // OK +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/system_stm32f3xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/system_stm32f3xx.h new file mode 100644 index 00000000000..2107220bc15 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/system_stm32f3xx.h @@ -0,0 +1,126 @@ +/** + ****************************************************************************** + * @file system_stm32f3xx.h + * @author MCD Application Team + * @version V2.3.0 + * @date 29-April-2015 + * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f3xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F3XX_H +#define __SYSTEM_STM32F3XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F3xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F3xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 3) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) by calling HAL API function HAL_RCC_ClockConfig() + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F3XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_ARM_STD/startup_stm32f769xx.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_ARM_STD/startup_stm32f769xx.S new file mode 100644 index 00000000000..8521c8b3242 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_ARM_STD/startup_stm32f769xx.S @@ -0,0 +1,479 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f769xx.s +;* Author : MCD Application Team +;* Version : V1.1.0 +;* Date : 22-April-2016 +;* Description : STM32F769xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__initial_sp EQU 0x20080000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD DSI_IRQHandler ; DSI + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD CAN3_TX_IRQHandler ; CAN3 TX + DCD CAN3_RX0_IRQHandler ; CAN3 RX0 + DCD CAN3_RX1_IRQHandler ; CAN3 RX1 + DCD CAN3_SCE_IRQHandler ; CAN3 SCE + DCD JPEG_IRQHandler ; JPEG + DCD MDIOS_IRQHandler ; MDIOS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT CAN3_TX_IRQHandler [WEAK] + EXPORT CAN3_RX0_IRQHandler [WEAK] + EXPORT CAN3_RX1_IRQHandler [WEAK] + EXPORT CAN3_SCE_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +DSI_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SDMMC2_IRQHandler +CAN3_TX_IRQHandler +CAN3_RX0_IRQHandler +CAN3_RX1_IRQHandler +CAN3_SCE_IRQHandler +JPEG_IRQHandler +MDIOS_IRQHandler + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_ARM_STD/stm32f769ni.sct b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_ARM_STD/stm32f769ni.sct new file mode 100644 index 00000000000..1c2ba8fd8d6 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_ARM_STD/stm32f769ni.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2016, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F769NI: 2048 KB FLASH (0x200000) + 512 KB SRAM (0x80000) +LR_IROM1 0x08000000 0x200000 { ; load region size_region + + ER_IROM1 0x08000000 0x200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 126 vectors = 504 bytes (0x1F8) to be reserved in RAM + RW_IRAM1 (0x20000000+0x1F8) (0x80000-0x1F8) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_ARM_STD/sys.cpp b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 00000000000..bb665909b98 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_GCC_ARM/STM32F769NI.ld b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_GCC_ARM/STM32F769NI.ld new file mode 100644 index 00000000000..359b884aee5 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_GCC_ARM/STM32F769NI.ld @@ -0,0 +1,153 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + RAM (rwx) : ORIGIN = 0x200001F8, LENGTH = 512K - 0x1F8 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_GCC_ARM/startup_stm32f769xx.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_GCC_ARM/startup_stm32f769xx.S new file mode 100644 index 00000000000..3cb97ec6334 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_GCC_ARM/startup_stm32f769xx.S @@ -0,0 +1,644 @@ +/** + ****************************************************************************** + * @file startup_stm32f769xx.s + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief STM32F769xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M7 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system initialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M7. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word DSI_IRQHandler /* DSI */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */ + .word SDMMC2_IRQHandler /* SDMMC2 */ + .word CAN3_TX_IRQHandler /* CAN3 TX */ + .word CAN3_RX0_IRQHandler /* CAN3 RX0 */ + .word CAN3_RX1_IRQHandler /* CAN3 RX1 */ + .word CAN3_SCE_IRQHandler /* CAN3 SCE */ + .word JPEG_IRQHandler /* JPEG */ + .word MDIOS_IRQHandler /* MDIOS */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak DSI_IRQHandler + .thumb_set DSI_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak CAN3_TX_IRQHandler + .thumb_set CAN3_TX_IRQHandler,Default_Handler + + .weak CAN3_RX0_IRQHandler + .thumb_set CAN3_RX0_IRQHandler,Default_Handler + + .weak CAN3_RX1_IRQHandler + .thumb_set CAN3_RX1_IRQHandler,Default_Handler + + .weak CAN3_SCE_IRQHandler + .thumb_set CAN3_SCE_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_IAR/startup_stm32f769xx.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_IAR/startup_stm32f769xx.S new file mode 100644 index 00000000000..126ba462fe9 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_IAR/startup_stm32f769xx.S @@ -0,0 +1,804 @@ +;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f769xx.s +;* Author : MCD Application Team +;* Version : V1.0.1 +;* Date : 22-April-2016 +;* Description : STM32F769xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD DSI_IRQHandler ; DSI + DCD DFSDM0_IRQHandler ; DFSDM Filter1 + DCD DFSDM1_IRQHandler ; DFSDM Filter2 + DCD DFSDM2_IRQHandler ; DFSDM Filter3 + DCD DFSDM3_IRQHandler ; DFSDM Filter4 + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD CAN3_TX_IRQHandler ; CAN3 TX + DCD CAN3_RX0_IRQHandler ; CAN3 RX0 + DCD CAN3_RX1_IRQHandler ; CAN3 RX1 + DCD CAN3_SCE_IRQHandler ; CAN3 SCE + DCD JPEG_IRQHandler ; JPEG + DCD MDIOS_IRQHandler ; MDIOS +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + + PUBWEAK DSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DSI_IRQHandler + B DSI_IRQHandler + + PUBWEAK DFSDM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM0_IRQHandler + B DFSDM0_IRQHandler + + PUBWEAK DFSDM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_IRQHandler + B DFSDM1_IRQHandler + + PUBWEAK DFSDM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM2_IRQHandler + B DFSDM2_IRQHandler + + PUBWEAK DFSDM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM3_IRQHandler + B DFSDM3_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK CAN3_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN3_TX_IRQHandler + B CAN3_TX_IRQHandler + + PUBWEAK CAN3_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN3_RX0_IRQHandler + B CAN3_RX0_IRQHandler + + PUBWEAK CAN3_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN3_RX1_IRQHandler + B CAN3_RX1_IRQHandler + + PUBWEAK CAN3_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN3_SCE_IRQHandler + B CAN3_SCE_IRQHandler + + PUBWEAK JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler + B JPEG_IRQHandler + + PUBWEAK MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler + B MDIOS_IRQHandler + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_IAR/stm32f769ni.icf b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_IAR/stm32f769ni.icf new file mode 100644 index 00000000000..7af894aeb41 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/TOOLCHAIN_IAR/stm32f769ni.icf @@ -0,0 +1,35 @@ +/* [ROM = 2048kb = 0x200000] */ +define symbol __intvec_start__ = 0x08000000; +define symbol __region_ROM_start__ = 0x08000000; +define symbol __region_ROM_end__ = 0x081FFFFF; + +/* [RAM = 512kb = 0x80000] Vector table dynamic copy: 126 vectors = 504 bytes (0x1F8) to be reserved in RAM */ +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x200001F7; /* Aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x200001F8; +define symbol __region_RAM_end__ = 0x2007FFFF; + +define symbol __region_ITCMRAM_start__ = 0x00000000; +define symbol __region_ITCMRAM_end__ = 0x00003FFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; +define region ITCMRAM_region = mem:[from __region_ITCMRAM_start__ to __region_ITCMRAM_end__]; + +/* Stack and Heap */ +/*Heap 1/4 of ram and stack 1/8*/ +define symbol __size_cstack__ = 0x8000; +define symbol __size_heap__ = 0x8000; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block STACKHEAP }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/cmsis.h similarity index 83% rename from hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device.h rename to hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/cmsis.h index cfc391f58aa..ee3ba9007b7 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/cmsis.h @@ -1,6 +1,5 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. /* mbed Microcontroller Library + * A generic CMSIS include header ******************************************************************************* * Copyright (c) 2016, STMicroelectronics * All rights reserved. @@ -29,26 +28,11 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" +#include "stm32f7xx.h" +#include "cmsis_nvic.h" #endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/device.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/cmsis_nvic.c similarity index 65% rename from hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/device.h rename to hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/cmsis_nvic.c index aa30383f4d7..69a0fa58323 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/device.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/cmsis_nvic.c @@ -1,4 +1,5 @@ /* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors ******************************************************************************* * Copyright (c) 2016, STMicroelectronics * All rights reserved. @@ -27,46 +28,28 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 1 - -#define DEVICE_SERIAL 1 -#define DEVICE_SERIAL_FC 0 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_RTC 1 -#define DEVICE_RTC_LSI 0 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SLEEP 1 - -//======================================= - -#define DEVICE_SEMIHOST 0 -#define DEVICE_LOCALFILESYSTEM 0 -#define DEVICE_ID_LENGTH 24 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_RED 0 - -#include "objects.h" - -#endif +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/cmsis_nvic.h similarity index 76% rename from hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device.h rename to hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/cmsis_nvic.h index 374bdfde23d..0a26d73682f 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/cmsis_nvic.h @@ -1,6 +1,5 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. /* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors ******************************************************************************* * Copyright (c) 2016, STMicroelectronics * All rights reserved. @@ -28,28 +27,28 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H + */ +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 98 vectors = 392 bytes from 0x40 to 0x1C7 +// Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM +#define NVIC_NUM_VECTORS 114 +#define NVIC_USER_IRQ_OFFSET 16 +#include "cmsis.h" +#ifdef __cplusplus +extern "C" { +#endif +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - -#define LED_RED LED2 - -#include "objects.h" +#ifdef __cplusplus +} +#endif #endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/hal_tick.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/hal_tick.c new file mode 100644 index 00000000000..8c22bf69259 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/hal_tick.c @@ -0,0 +1,144 @@ +/** + ****************************************************************************** + * @file hal_tick.c + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "hal_tick.h" + +// 0=NO, 1=PG6 toggles at each tick +#define DEBUG_TICK 0 + +TIM_HandleTypeDef TimMasterHandle; +uint32_t PreviousVal = 0; + +void HAL_IncTick(void); +void us_ticker_irq_handler(void); + +void timer_irq_handler(void) { + // Channel 1 for mbed timeout + if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) { + if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC1) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); + us_ticker_irq_handler(); + } + } + + // Channel 2 for HAL tick + if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC2) == SET) { + if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC2) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); + uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + if ((val - PreviousVal) >= HAL_TICK_DELAY) { + // Increment HAL variable + HAL_IncTick(); + // Prepare next interrupt + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + PreviousVal = val; +#if DEBUG_TICK > 0 + HAL_GPIO_TogglePin(GPIOG, GPIO_PIN_6); +#endif + } + } + } +} + +// Reconfigure the HAL tick using a standard timer instead of systick. +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + RCC_ClkInitTypeDef RCC_ClkInitStruct; + uint32_t PclkFreq; + + // Get clock configuration + // Note: PclkFreq contains here the Latency (not used after) + HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &PclkFreq); + + // Get TIM5 clock value + PclkFreq = HAL_RCC_GetPCLK1Freq(); + + // Enable timer clock + TIM_MST_RCC; + + // Reset timer + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; + + // Configure time base + TimMasterHandle.Instance = TIM_MST; + TimMasterHandle.Init.Period = 0xFFFFFFFF; + + // TIMxCLK = PCLKx when the APB prescaler = 1 else TIMxCLK = 2 * PCLKx + if (RCC_ClkInitStruct.APB1CLKDivider == RCC_HCLK_DIV1) + TimMasterHandle.Init.Prescaler = (uint16_t)((PclkFreq) / 1000000) - 1; // 1 us tick + else + TimMasterHandle.Init.Prescaler = (uint16_t)((PclkFreq * 2) / 1000000) - 1; // 1 us tick + + TimMasterHandle.Init.ClockDivision = 0; + TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + TimMasterHandle.Init.RepetitionCounter = 0; + HAL_TIM_OC_Init(&TimMasterHandle); + + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler); + NVIC_EnableIRQ(TIM_MST_IRQ); + + // Channel 1 for mbed timeout + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); + + // Channel 2 for HAL tick + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); + PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); + +#if DEBUG_TICK > 0 + __GPIOG_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); +#endif + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/hal_tick.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/hal_tick.h new file mode 100644 index 00000000000..6501819b5d2 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/hal_tick.h @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f7xx.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM5 +#define TIM_MST_IRQ TIM5_IRQn +#define TIM_MST_RCC __TIM5_CLK_ENABLE() + +#define TIM_MST_RESET_ON __TIM5_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() + +#define HAL_TICK_DELAY (1000) // 1 ms + +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f769xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f769xx.h new file mode 100644 index 00000000000..69e99eda659 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f769xx.h @@ -0,0 +1,11332 @@ +/** + ****************************************************************************** + * @file stm32f769xx.h + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f769xx + * @{ + */ + +#ifndef __STM32F769xx_H +#define __STM32F769xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief STM32F7xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + DSI_IRQn = 98, /*!< DSI global Interrupt */ + DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */ + DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */ + DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */ + DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */ + SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */ + CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */ + CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */ + CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */ + CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */ + JPEG_IRQn = 108, /*!< JPEG global Interrupt */ + MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +/** + * @brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ +#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ +#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ + + +#include "system_stm32f7xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief HDMI-CEC + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */ +} FLASH_TypeDef; + + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5_6 + */ + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED; /*!< Reserved, 0x18 */ + __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ +} PWR_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ + __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */ + __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */ + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */ + +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ +} LPTIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ +} USART_TypeDef; + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */ + __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */ + __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */ + __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */ + __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */ + __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */ + __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */ + uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */ + __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */ + __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */ + __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */ + __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */ + __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */ + __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */ + __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */ + __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */ + __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */ + __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */ + __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */ + __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */ + __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */ + __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */ + __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */ + __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */ + __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */ + __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */ + __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */ + __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */ + __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */ + __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */ + __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */ + __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */ + __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */ + __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */ + __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */ + __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */ + __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */ + __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */ + __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */ + __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */ + __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */ + __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */ + __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */ + __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */ + __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */ + __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */ + __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */ + __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */ + __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */ + __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */ + __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */ + __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */ + __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */ + __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */ + __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */ + __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */ + __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */ + __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */ + __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */ + __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */ + __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */ + __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */ + __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */ + __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */ + __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */ + __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */ + __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */ + __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */ + __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */ + __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */ + __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */ + __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */ +} MDIOS_TypeDef; + +/** + * @brief DSI Controller + */ + +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED5; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */ + __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ + uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED9; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */ + uint32_t RESERVED10; /*!< Reserved, 0x42C */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ +} DSI_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */ +#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */ +#define RAMDTCM_BASE 0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM */ +#define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */ +#define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */ +#define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */ +#define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */ +#define SRAM1_BASE 0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */ +#define SRAM2_BASE 0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ +#define FLASH_END 0x081FFFFFU /*!< FLASH end address */ + +/* Legacy define */ +#define FLASH_BASE FLASHAXI_BASE + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) +#define CAN3_BASE (APB1PERIPH_BASE + 0x3400U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) +#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) +#define I2C4_BASE (APB1PERIPH_BASE + 0x6000U) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U) +#define CEC_BASE (APB1PERIPH_BASE + 0x6C00U) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800U) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000U) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400U) +#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300U) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U) +#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U) +#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U) +#define DSI_BASE (APB2PERIPH_BASE + 0x6C00U) +#define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U) +#define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U) +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U) +#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U) +#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) +#define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */ +#define PACKAGESIZE_BASE 0x1FFF7BF0U /*!< Package size register base address */ +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100U) +#define ETH_PTP_BASE (ETH_BASE + 0x0700U) +#define ETH_DMA_BASE (ETH_BASE + 0x1000U) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U) +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U) +#define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U) +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE 0xE0042000U + +/*!< USB registers base address */ +#define USB_OTG_HS_PERIPH_BASE 0x40040000U +#define USB_OTG_FS_PERIPH_BASE 0x50000000U + +#define USB_OTG_GLOBAL_BASE 0x000U +#define USB_OTG_DEVICE_BASE 0x800U +#define USB_OTG_IN_ENDPOINT_BASE 0x900U +#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U +#define USB_OTG_EP_REG_SIZE 0x20U +#define USB_OTG_HOST_BASE 0x400U +#define USB_OTG_HOST_PORT_BASE 0x440U +#define USB_OTG_HOST_CHANNEL_BASE 0x500U +#define USB_OTG_HOST_CHANNEL_SIZE 0x20U +#define USB_OTG_PCGCCTL_BASE 0xE00U +#define USB_OTG_FIFO_BASE 0x1000U +#define USB_OTG_FIFO_SIZE 0x1000U + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) +#define CAN3 ((CAN_TypeDef *) CAN3_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +#define JPEG ((JPEG_TypeDef *) JPEG_BASE) +#define DSI ((DSI_TypeDef *)DSI_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD 0x00000001U /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx + * @{ + */ + +#ifndef __STM32F7xx_H +#define __STM32F7xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F7) +#define STM32F7 +#endif /* STM32F7 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ +#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \ + !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) + /* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG, + STM32F756NG Devices */ + /* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG, + STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */ + /* #define STM32F745xx */ /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */ + /* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG, + STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */ + /* #define STM32F767xx */ /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI, + STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI, STM32F768AI Devices */ +#define STM32F769xx /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II, + STM32F769NG, STM32F769NI Devices */ + /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI, STM32F778AI Devices */ + /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V1.1.0 + */ +#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F7_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\ + |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32F7_CMSIS_VERSION)) +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ +#if defined(STM32F756xx) + #include "stm32f756xx.h" +#elif defined(STM32F746xx) + #include "stm32f746xx.h" +#elif defined(STM32F745xx) + #include "stm32f745xx.h" +#elif defined(STM32F765xx) + #include "stm32f765xx.h" +#elif defined(STM32F767xx) + #include "stm32f767xx.h" +#elif defined(STM32F769xx) + #include "stm32f769xx.h" +#elif defined(STM32F777xx) + #include "stm32f777xx.h" +#elif defined(STM32F779xx) + #include "stm32f779xx.h" +#else + #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + +/** + * @} + */ + +#ifdef USE_HAL_DRIVER + #include "stm32f7xx_hal_conf.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F7xx_H */ + +/** + * @} + */ + + /** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7xx_hal_conf.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7xx_hal_conf.h new file mode 100644 index 00000000000..a0e53e43513 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7xx_hal_conf.h @@ -0,0 +1,454 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf_template.h + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f7xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_CAN_MODULE_ENABLED +#define HAL_CEC_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED +#define HAL_DAC_MODULE_ENABLED +#define HAL_DCMI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_DMA2D_MODULE_ENABLED +#define HAL_ETH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_NAND_MODULE_ENABLED +#define HAL_NOR_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED +#define HAL_SDRAM_MODULE_ENABLED +#define HAL_HASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_LPTIM_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_QSPI_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SAI_MODULE_ENABLED +#define HAL_SD_MODULE_ENABLED +#define HAL_SPDIFRX_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED +#define HAL_DFSDM_MODULE_ENABLED +#define HAL_DSI_MODULE_ENABLED +#define HAL_JPEG_MODULE_ENABLED +#define HAL_MDIOS_MODULE_ENABLED + + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT 200U /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define ART_ACCLERATOR_ENABLE 1U /* To enable instruction cache and prefetch */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1 */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848 PHY Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY 0x000000FFU +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY 0x00000FFFU + +#define PHY_READ_TO 0x0000FFFFU +#define PHY_WRITE_TO 0x0000FFFFU + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x11U) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x12U) /*!< MII Interrupt Status and Misc. Control Register */ + +#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */ + +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 1U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32f7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32f7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/system_stm32f7xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/system_stm32f7xx.c new file mode 100644 index 00000000000..367ce072d45 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/system_stm32f7xx.c @@ -0,0 +1,852 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.c + * @author MCD Application Team + * @version V1.0.2 + * @date 21-September-2015 + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | [1] PLL_HSE_XTAL | [2] PLL_HSI if [1] fails + * | (external 25MHz xtal) | (internal 16MHz clock) + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 216 | 216 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 216 | 216 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 54 | 54 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 108 | 108 + *----------------------------------------------------------------------------- + * USB capable | YES | NO + * with 48 MHz precise clock | | + *----------------------------------------------------------------------------- + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** @addtogroup STM32F7xx_System_Private_Includes + * @{ + */ + +#include "stm32f7xx.h" +#include "hal_tick.h" + +HAL_StatusTypeDef HAL_Init(void); + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted + on STMicroelectronics EVAL/Discovery boards as data memory */ +/*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define + need to be added in the project preprocessor to avoid SDRAM multiple configuration + (the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */ +/* #define DATA_IN_ExtSRAM */ +/* #define DATA_IN_ExtSDRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Macros + * @{ + */ + +/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ +#define USE_PLL_HSE_EXTC (1) /* Use external clock */ +#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = HSI_VALUE; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes + * @{ + */ +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +uint8_t SetSysClock_PLL_HSI(void); + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + + /* Configure the Cube driver */ + SystemCoreClock = HSI_VALUE; // At this stage the HSI is used as system clock + HAL_Init(); + + // Enable CPU L1-Cache + SCB_EnableICache(); + SCB_EnableDCache(); + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + SetSysClock(); + + /* Reset the timer to avoid issues after the RAM initialization */ + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f7xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0; +#if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register uint32_t index; + + /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x55550545; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x55554145; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCCC000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xFF800FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x55400555; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CC00CC; + GPIOG->AFR[1] = 0xC00000CC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x80220AAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0x80320FFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x40110555; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x55550450; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00145555; + +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[4] = 0x00001091; + FMC_Bank1->BTCR[5] = 0x00110212; + FMC_Bank1E->BWTR[4] = 0x0FFFFFFF; + + /* Configure and enable SDRAM bank1 */ + FMC_Bank5_6->SDCR[0] = 0x000019E5; + FMC_Bank5_6->SDTR[0] = 0x01116361; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x000000F3; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#elif defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register uint32_t index; + + /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x50150005; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x55554005; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCCC000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x55400555; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CC00CC; + GPIOG->AFR[1] = 0xC000000C; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x80020A0A; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0x80020A0A; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x40010505; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x55550450; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00145555; + +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ + FMC_Bank5_6->SDCR[0] = 0x000019E5; + FMC_Bank5_6->SDTR[0] = 0x01116361; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x000000F3; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#elif defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x55550545; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x55554145; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x55000555; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00200AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x00300FFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00100555; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[4] = 0x00001091; + FMC_Bank1->BTCR[5] = 0x00110212; + FMC_Bank1E->BWTR[4] = 0x0FFFFFFF; + +#endif /* DATA_IN_ExtSRAM */ + + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ + #if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) + #endif + { + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) + { + while(1) + { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + // Output clock on MCO2 pin(PC9) for debugging purpose + // Can be visualized on CN8 connector pin 4 + //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + // Enable power clock + __PWR_CLK_ENABLE(); + + // Enable HSE oscillator and activate PLL with HSE as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) + { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */ + } + else + { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */ + } + // Warning: this configuration is for a 8 MHz xtal clock only + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 1 MHz (25 MHz / 25) + RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2) + RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + // Activate the OverDrive to reach the 216 MHz Frequency + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + return 0; // FAIL + } + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + // Enable CPU L1-Cache + SCB_EnableICache(); + SCB_EnableDCache(); + + // Enable power clock + __PWR_CLK_ENABLE(); + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) + RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2) + RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + // Activate the OverDrive to reach the 216 MHz Frequency + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + return 0; // FAIL + } + + return 1; // OK +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/system_stm32f7xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/system_stm32f7xx.h new file mode 100644 index 00000000000..f452d4d8e5a --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/system_stm32f7xx.h @@ -0,0 +1,126 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.h + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F7XX_H +#define __SYSTEM_STM32F7XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F7xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F7xx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F7XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c index a45e9e62134..c38165ec045 100755 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c @@ -40,6 +40,12 @@ enum _sai_transfer_state kSAI_Error /*!< Transfer error occured. */ }; +/*! @brief Typedef for sai tx interrupt handler. */ +typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/*! @brief Typedef for sai rx interrupt handler. */ +typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -98,6 +104,10 @@ static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; /* Clock name array */ static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_tx_isr_t s_saiTxIsr; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_rx_isr_t s_saiRxIsr; /******************************************************************************* * Code @@ -231,12 +241,13 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Configure Master clock output enable */ - base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); - /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ /* Configure audio protocol */ @@ -332,12 +343,13 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Configure Master clock output enable */ - base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); - /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ /* Configure audio protocol */ @@ -663,6 +675,9 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + /* Set the isr pointer */ + s_saiTxIsr = SAI_TransferTxHandleIRQ; + /* Enable Tx irq */ EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); } @@ -676,6 +691,9 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + /* Set the isr pointer */ + s_saiRxIsr = SAI_TransferRxHandleIRQ; + /* Enable Rx irq */ EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); } @@ -1011,24 +1029,24 @@ void I2S0_DriverIRQHandler(void) { if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag))) { - SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); } if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag))) { - SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); } } #else void I2S0_Tx_DriverIRQHandler(void) { assert(s_saiHandle[0][0]); - SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); } void I2S0_Rx_DriverIRQHandler(void) { assert(s_saiHandle[0][1]); - SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); } #endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */ #endif /* I2S0*/ @@ -1037,12 +1055,12 @@ void I2S0_Rx_DriverIRQHandler(void) void I2S1_Tx_DriverIRQHandler(void) { assert(s_saiHandle[1][0]); - SAI_TransferTxHandleIRQ(I2S1, s_saiHandle[1][0]); + s_saiTxIsr(I2S1, s_saiHandle[1][0]); } void I2S1_Rx_DriverIRQHandler(void) { assert(s_saiHandle[1][1]); - SAI_TransferRxHandleIRQ(I2S1, s_saiHandle[1][1]); + s_saiRxIsr(I2S1, s_saiHandle[1][1]); } #endif diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h index 72b6efd06bc..cb38688cd92 100755 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h @@ -38,7 +38,6 @@ * @{ */ -/*! @file */ /******************************************************************************* * Definitions @@ -46,7 +45,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */ /*@}*/ /*! @brief SAI return status*/ @@ -168,7 +167,7 @@ typedef enum _sai_fifo_packing } sai_fifo_packing_t; #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ -/*! @brief SAI user configure structure */ +/*! @brief SAI user configuration structure */ typedef struct _sai_config { sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ @@ -276,7 +275,7 @@ extern "C" { * because the clock is not enabled. * * @param base SAI base pointer - * @param config SAI configure structure. + * @param config SAI configuration structure. */ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); @@ -292,7 +291,7 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); * because the clock is not enabled. * * @param base SAI base pointer - * @param config SAI configure structure. + * @param config SAI configuration structure. */ void SAI_RxInit(I2S_Type *base, const sai_config_t *config); diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.c b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.c index 5a1028ba978..15e1f55f437 100644 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.c +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.c @@ -73,6 +73,9 @@ enum _flexcan_mb_code_tx kFLEXCAN_TxMbNotUsed = 0xF, /*!< Not used.*/ }; +/* Typedef for interrupt handler. */ +typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle); + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -86,23 +89,24 @@ enum _flexcan_mb_code_tx uint32_t FLEXCAN_GetInstance(CAN_Type *base); /*! - * @brief Enter FlexCAN Fraze Mode. + * @brief Enter FlexCAN Freeze Mode. * - * This function makes the FlexCAN work under Fraze Mode. + * This function makes the FlexCAN work under Freeze Mode. * * @param base FlexCAN peripheral base address. */ -static void FLEXCAN_EnterFrazeMode(CAN_Type *base); +static void FLEXCAN_EnterFreezeMode(CAN_Type *base); /*! - * @brief Exit FlexCAN Fraze Mode. + * @brief Exit FlexCAN Freeze Mode. * - * This function makes the FlexCAN leave Fraze Mode. + * This function makes the FlexCAN leave Freeze Mode. * * @param base FlexCAN peripheral base address. */ -static void FLEXCAN_ExitFrazeMode(CAN_Type *base); +static void FLEXCAN_ExitFreezeMode(CAN_Type *base); +#if !defined(NDEBUG) /*! * @brief Check if Message Buffer is occupied by Rx FIFO. * @@ -112,6 +116,19 @@ static void FLEXCAN_ExitFrazeMode(CAN_Type *base); * @param mbIdx The FlexCAN Message Buffer index. */ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +/*! + * @brief Get the first valid Message buffer ID of give FlexCAN instance. + * + * This function is a helper function for Errata 5641 workaround. + * + * @param base FlexCAN peripheral base address. + * @return The first valid Message Buffer Number. + */ +static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base); +#endif /*! * @brief Check if Message Buffer interrupt is enabled. @@ -165,6 +182,9 @@ static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS; /* Array of FlexCAN clock name. */ static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS; +/* FlexCAN ISR for transactional APIs. */ +static flexcan_isr_t s_flexcanIsr; + /******************************************************************************* * Code ******************************************************************************/ @@ -187,10 +207,10 @@ uint32_t FLEXCAN_GetInstance(CAN_Type *base) return instance; } -static void FLEXCAN_EnterFrazeMode(CAN_Type *base) +static void FLEXCAN_EnterFreezeMode(CAN_Type *base) { /* Set Freeze, Halt bits. */ - base->MCR |= CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK; + base->MCR |= CAN_MCR_HALT_MASK; /* Wait until the FlexCAN Module enter freeze mode. */ while (!(base->MCR & CAN_MCR_FRZACK_MASK)) @@ -198,10 +218,10 @@ static void FLEXCAN_EnterFrazeMode(CAN_Type *base) } } -static void FLEXCAN_ExitFrazeMode(CAN_Type *base) +static void FLEXCAN_ExitFreezeMode(CAN_Type *base) { /* Clear Freeze, Halt bits. */ - base->MCR &= ~(CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK); + base->MCR &= ~CAN_MCR_HALT_MASK; /* Wait until the FlexCAN Module exit freeze mode. */ while (base->MCR & CAN_MCR_FRZACK_MASK) @@ -209,6 +229,7 @@ static void FLEXCAN_ExitFrazeMode(CAN_Type *base) } } +#if !defined(NDEBUG) static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) { uint8_t lastOccupiedMb; @@ -221,7 +242,11 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) /* Calculate the number of last Message Buffer occupied by Rx FIFO. */ lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + if (mbIdx <= (lastOccupiedMb + 1)) +#else if (mbIdx <= lastOccupiedMb) +#endif { return true; } @@ -232,9 +257,40 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) } else { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + if (0 == mbIdx) + { + return true; + } + else + { + return false; + } +#else return false; +#endif } } +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base) +{ + uint32_t firstValidMbNum; + + if (base->MCR & CAN_MCR_RFEN_MASK) + { + firstValidMbNum = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + firstValidMbNum = ((firstValidMbNum + 1) * 2) + 6; + } + else + { + firstValidMbNum = 0; + } + + return firstValidMbNum; +} +#endif static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx) { @@ -296,7 +352,7 @@ static void FLEXCAN_Reset(CAN_Type *base) base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); #else - base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); + base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); #endif /* Reset CTRL1 and CTRL2 rigister. */ @@ -387,7 +443,7 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc /* Reset to known status. */ FLEXCAN_Reset(base); - /* Save current MCR value. */ + /* Save current MCR value and enable to enter Freeze mode(enabled by default). */ mcrTemp = base->MCR; /* Set the maximum number of Message Buffers */ @@ -448,8 +504,8 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf /* Assertion. */ assert(config); - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Cleaning previous Timing Setting. */ base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | @@ -460,59 +516,55 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) | CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg)); - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } -void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) { - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Setting Rx Message Buffer Global Mask value. */ base->RXMGMASK = mask; base->RX14MASK = mask; base->RX15MASK = mask; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } -void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) { - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Setting Rx FIFO Global Mask value. */ base->RXFGMASK = mask; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } -void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) { assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Setting Rx Individual Mask value. */ base->RXIMR[maskIdx] = mask; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) { /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Inactivate Message Buffer. */ if (enable) @@ -535,14 +587,10 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(((config) || (false == enable))); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp = 0; - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } - /* Inactivate Message Buffer. */ base->MB[mbIdx].CS = 0; @@ -574,7 +622,7 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co } } -void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable) +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable) { /* Assertion. */ assert((config) || (false == enable)); @@ -582,8 +630,8 @@ void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS); uint8_t setup_mb, i, rffn = 0; - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); if (enable) { @@ -675,8 +723,8 @@ void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con FLEXCAN_SetRxMbConfig(base, 5, NULL, false); } - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } #if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) @@ -684,25 +732,25 @@ void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) { if (enable) { - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Enable FlexCAN DMA. */ base->MCR |= CAN_MCR_DMA_MASK; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } else { - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Disable FlexCAN DMA. */ base->MCR &= ~CAN_MCR_DMA_MASK; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } } #endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ @@ -713,14 +761,10 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(txFrame); assert(txFrame->length <= 8); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp = 0; - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } - /* Check if Message Buffer is available. */ if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) { @@ -751,6 +795,11 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t /* Activate Tx Message Buffer. */ base->MB[mbIdx].CS = cs_temp; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif + return kStatus_Success; } else @@ -765,15 +814,11 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(rxFrame); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp; uint8_t rx_code; - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } - /* Read CS field of Rx Message Buffer to lock Message Buffer. */ cs_temp = base->MB[mbIdx].CS; /* Get Rx Message Buffer Code field. */ @@ -819,7 +864,7 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram } } -status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) { /* Assertion. */ assert(rxFrame); @@ -863,7 +908,7 @@ status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) } } -status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame) +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame) { /* Write Tx Message Buffer to initiate a data sending. */ if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame)) @@ -884,7 +929,7 @@ status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra } } -status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) { /* Wait until Rx Message Buffer non-empty. */ while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) @@ -898,7 +943,7 @@ status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_ return FLEXCAN_ReadRxMb(base, mbIdx, rxFrame); } -status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame) +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame) { status_t rxFifoStatus; @@ -908,7 +953,7 @@ status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rx } /* */ - rxFifoStatus = FlEXCAN_ReadRxFifo(base, rxFrame); + rxFifoStatus = FLEXCAN_ReadRxFifo(base, rxFrame); /* Clean Rx Fifo available flag. */ FLEXCAN_ClearMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag); @@ -938,6 +983,8 @@ void FLEXCAN_TransferCreateHandle(CAN_Type *base, handle->callback = callback; handle->userData = userData; + s_flexcanIsr = FLEXCAN_TransferHandleIRQ; + /* We Enable Error & Status interrupt here, because this interrupt just * report current status of FlexCAN module through Callback function. * It is insignificance without a available callback function. @@ -970,11 +1017,7 @@ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handl assert(handle); assert(xfer); assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); /* Check if Message Buffer is idle. */ if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) @@ -1017,11 +1060,7 @@ status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *ha assert(handle); assert(xfer); assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); /* Check if Message Buffer is idle. */ if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) @@ -1073,11 +1112,7 @@ void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t /* Assertion. */ assert(handle); assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Disable Message Buffer Interrupt. */ FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); @@ -1096,11 +1131,7 @@ void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint /* Assertion. */ assert(handle); assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Disable Message Buffer Interrupt. */ FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); @@ -1185,7 +1216,7 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) break; case kFLEXCAN_RxFifoFrameAvlFlag: - status = FlEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); + status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); if (kStatus_Success == status) { status = kStatus_FLEXCAN_RxFifoIdle; @@ -1273,7 +1304,7 @@ void CAN0_DriverIRQHandler(void) { assert(s_flexcanHandle[0]); - FLEXCAN_TransferHandleIRQ(CAN0, s_flexcanHandle[0]); + s_flexcanIsr(CAN0, s_flexcanHandle[0]); } #endif @@ -1282,7 +1313,7 @@ void CAN1_DriverIRQHandler(void) { assert(s_flexcanHandle[1]); - FLEXCAN_TransferHandleIRQ(CAN1, s_flexcanHandle[1]); + s_flexcanIsr(CAN1, s_flexcanHandle[1]); } #endif @@ -1291,7 +1322,7 @@ void CAN2_DriverIRQHandler(void) { assert(s_flexcanHandle[2]); - FLEXCAN_TransferHandleIRQ(CAN2, s_flexcanHandle[2]); + s_flexcanIsr(CAN2, s_flexcanHandle[2]); } #endif @@ -1300,7 +1331,7 @@ void CAN3_DriverIRQHandler(void) { assert(s_flexcanHandle[3]); - FLEXCAN_TransferHandleIRQ(CAN3, s_flexcanHandle[3]); + s_flexcanIsr(CAN3, s_flexcanHandle[3]); } #endif @@ -1309,6 +1340,6 @@ void CAN4_DriverIRQHandler(void) { assert(s_flexcanHandle[4]); - FLEXCAN_TransferHandleIRQ(CAN4, s_flexcanHandle[4]); + s_flexcanIsr(CAN4, s_flexcanHandle[4]); } #endif diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.h b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.h index b0dee77173d..13c28f357d4 100644 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.h +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.h @@ -37,7 +37,6 @@ * @{ */ -/*! @file*/ /****************************************************************************** * Definitions @@ -87,10 +86,8 @@ (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */ #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \ - ( \ - ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ - ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \ - << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \ (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \ @@ -296,13 +293,13 @@ typedef struct _flexcan_frame uint32_t length : 4; /*!< CAN frame payload length in bytes(Range: 0~8). */ uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ - uint32_t reserve1 : 1; /*!< Reserved for placeholder. */ + uint32_t : 1; /*!< Reserved. */ uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */ }; struct { uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ - uint32_t reserve2 : 3; /*!< Reserved for place holder. */ + uint32_t : 3; /*!< Reserved. */ }; union { @@ -366,7 +363,7 @@ typedef struct _flexcan_rx_mb_config flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */ } flexcan_rx_mb_config_t; -/*! @brief FlexCAN Rx FIFO configure structure. */ +/*! @brief FlexCAN Rx FIFO configuration structure. */ typedef struct _flexcan_rx_fifo_config { uint32_t *idFilterTable; /*!< Pointer to FlexCAN Rx FIFO identifier filter table. */ @@ -437,7 +434,7 @@ extern "C" { * to call the FLEXCAN_Init function by passing in these parameters: * @code * flexcan_config_t flexcanConfig; - * flexcanConfig.clkSrc = KFLEXCAN_ClkSrcOsc; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; * flexcanConfig.baudRate = 125000U; * flexcanConfig.maxMbNum = 16; * flexcanConfig.enableLoopBack = false; @@ -466,7 +463,7 @@ void FLEXCAN_Deinit(CAN_Type *base); /*! * @brief Get the default configuration structure. * - * This function initializes the FlexCAN configure structure to default value. The default + * This function initializes the FlexCAN configuration structure to default value. The default * value are: * flexcanConfig->clkSrc = KFLEXCAN_ClkSrcOsc; * flexcanConfig->baudRate = 125000U; @@ -512,7 +509,7 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf * @param base FlexCAN peripheral base address. * @param mask Rx Message Buffer Global Mask value. */ -void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); /*! * @brief Sets the FlexCAN receive FIFO global mask. @@ -522,7 +519,7 @@ void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); * @param base FlexCAN peripheral base address. * @param mask Rx Fifo Global Mask value. */ -void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); /*! * @brief Sets the FlexCAN receive individual mask. @@ -538,7 +535,7 @@ void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); * @param maskIdx The Index of individual Mask. * @param mask Rx Individual Mask value. */ -void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask); +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask); /*! * @brief Configures a FlexCAN transmit message buffer. @@ -580,7 +577,7 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co * - true: Enable Rx FIFO. * - false: Disable Rx FIFO. */ -void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable); +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable); /* @} */ @@ -629,7 +626,7 @@ static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask) * @param txErrBuf Buffer to store Tx Error Counter value. * @param rxErrBuf Buffer to store Rx Error Counter value. */ -static inline void FlEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf) +static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf) { if (txErrBuf) { @@ -890,7 +887,7 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram * @retval kStatus_Success - Read Message from Rx FIFO successfully. * @retval kStatus_Fail - Rx FIFO is not enabled. */ -status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); /* @} */ @@ -910,7 +907,7 @@ status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); * @retval kStatus_Success - Write Tx Message Buffer Successfully. * @retval kStatus_Fail - Tx Message Buffer is currently in use. */ -status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame); +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame); /*! * @brief Performs a polling receive transaction on the CAN bus. @@ -924,7 +921,7 @@ status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. * @retval kStatus_Fail - Rx Message Buffer is empty. */ -status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); /*! * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus. @@ -936,7 +933,7 @@ status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_ * @retval kStatus_Success - Read Message from Rx FIFO successfully. * @retval kStatus_Fail - Rx FIFO is not enabled. */ -status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame); +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame); /*! * @brief Initializes the FlexCAN handle. diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.c b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.c index a45e9e62134..c38165ec045 100644 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.c +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.c @@ -40,6 +40,12 @@ enum _sai_transfer_state kSAI_Error /*!< Transfer error occured. */ }; +/*! @brief Typedef for sai tx interrupt handler. */ +typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/*! @brief Typedef for sai rx interrupt handler. */ +typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -98,6 +104,10 @@ static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; /* Clock name array */ static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_tx_isr_t s_saiTxIsr; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_rx_isr_t s_saiRxIsr; /******************************************************************************* * Code @@ -231,12 +241,13 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Configure Master clock output enable */ - base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); - /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ /* Configure audio protocol */ @@ -332,12 +343,13 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Configure Master clock output enable */ - base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); - /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ /* Configure audio protocol */ @@ -663,6 +675,9 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + /* Set the isr pointer */ + s_saiTxIsr = SAI_TransferTxHandleIRQ; + /* Enable Tx irq */ EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); } @@ -676,6 +691,9 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + /* Set the isr pointer */ + s_saiRxIsr = SAI_TransferRxHandleIRQ; + /* Enable Rx irq */ EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); } @@ -1011,24 +1029,24 @@ void I2S0_DriverIRQHandler(void) { if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag))) { - SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); } if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag))) { - SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); } } #else void I2S0_Tx_DriverIRQHandler(void) { assert(s_saiHandle[0][0]); - SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); } void I2S0_Rx_DriverIRQHandler(void) { assert(s_saiHandle[0][1]); - SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); } #endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */ #endif /* I2S0*/ @@ -1037,12 +1055,12 @@ void I2S0_Rx_DriverIRQHandler(void) void I2S1_Tx_DriverIRQHandler(void) { assert(s_saiHandle[1][0]); - SAI_TransferTxHandleIRQ(I2S1, s_saiHandle[1][0]); + s_saiTxIsr(I2S1, s_saiHandle[1][0]); } void I2S1_Rx_DriverIRQHandler(void) { assert(s_saiHandle[1][1]); - SAI_TransferRxHandleIRQ(I2S1, s_saiHandle[1][1]); + s_saiRxIsr(I2S1, s_saiHandle[1][1]); } #endif diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.h b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.h index 72b6efd06bc..cb38688cd92 100644 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.h +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.h @@ -38,7 +38,6 @@ * @{ */ -/*! @file */ /******************************************************************************* * Definitions @@ -46,7 +45,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */ /*@}*/ /*! @brief SAI return status*/ @@ -168,7 +167,7 @@ typedef enum _sai_fifo_packing } sai_fifo_packing_t; #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ -/*! @brief SAI user configure structure */ +/*! @brief SAI user configuration structure */ typedef struct _sai_config { sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ @@ -276,7 +275,7 @@ extern "C" { * because the clock is not enabled. * * @param base SAI base pointer - * @param config SAI configure structure. + * @param config SAI configuration structure. */ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); @@ -292,7 +291,7 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); * because the clock is not enabled. * * @param base SAI base pointer - * @param config SAI configure structure. + * @param config SAI configuration structure. */ void SAI_RxInit(I2S_Type *base, const sai_config_t *config); diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.c b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.c index a45e9e62134..c38165ec045 100644 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.c +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.c @@ -40,6 +40,12 @@ enum _sai_transfer_state kSAI_Error /*!< Transfer error occured. */ }; +/*! @brief Typedef for sai tx interrupt handler. */ +typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/*! @brief Typedef for sai rx interrupt handler. */ +typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -98,6 +104,10 @@ static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; /* Clock name array */ static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_tx_isr_t s_saiTxIsr; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_rx_isr_t s_saiRxIsr; /******************************************************************************* * Code @@ -231,12 +241,13 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Configure Master clock output enable */ - base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); - /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ /* Configure audio protocol */ @@ -332,12 +343,13 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Configure Master clock output enable */ - base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); - /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ /* Configure audio protocol */ @@ -663,6 +675,9 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + /* Set the isr pointer */ + s_saiTxIsr = SAI_TransferTxHandleIRQ; + /* Enable Tx irq */ EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); } @@ -676,6 +691,9 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + /* Set the isr pointer */ + s_saiRxIsr = SAI_TransferRxHandleIRQ; + /* Enable Rx irq */ EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); } @@ -1011,24 +1029,24 @@ void I2S0_DriverIRQHandler(void) { if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag))) { - SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); } if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag))) { - SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); } } #else void I2S0_Tx_DriverIRQHandler(void) { assert(s_saiHandle[0][0]); - SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); } void I2S0_Rx_DriverIRQHandler(void) { assert(s_saiHandle[0][1]); - SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); } #endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */ #endif /* I2S0*/ @@ -1037,12 +1055,12 @@ void I2S0_Rx_DriverIRQHandler(void) void I2S1_Tx_DriverIRQHandler(void) { assert(s_saiHandle[1][0]); - SAI_TransferTxHandleIRQ(I2S1, s_saiHandle[1][0]); + s_saiTxIsr(I2S1, s_saiHandle[1][0]); } void I2S1_Rx_DriverIRQHandler(void) { assert(s_saiHandle[1][1]); - SAI_TransferRxHandleIRQ(I2S1, s_saiHandle[1][1]); + s_saiRxIsr(I2S1, s_saiHandle[1][1]); } #endif diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.h b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.h index 72b6efd06bc..cb38688cd92 100644 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.h +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.h @@ -38,7 +38,6 @@ * @{ */ -/*! @file */ /******************************************************************************* * Definitions @@ -46,7 +45,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */ /*@}*/ /*! @brief SAI return status*/ @@ -168,7 +167,7 @@ typedef enum _sai_fifo_packing } sai_fifo_packing_t; #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ -/*! @brief SAI user configure structure */ +/*! @brief SAI user configuration structure */ typedef struct _sai_config { sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ @@ -276,7 +275,7 @@ extern "C" { * because the clock is not enabled. * * @param base SAI base pointer - * @param config SAI configure structure. + * @param config SAI configuration structure. */ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); @@ -292,7 +291,7 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); * because the clock is not enabled. * * @param base SAI base pointer - * @param config SAI configure structure. + * @param config SAI configuration structure. */ void SAI_RxInit(I2S_Type *base, const sai_config_t *config); diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/TARGET_HEXIWEAR/PeripheralPins.c b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/TARGET_HEXIWEAR/PeripheralPins.c index a7a8cb961c5..86a8b70ad5d 100644 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/TARGET_HEXIWEAR/PeripheralPins.c +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/TARGET_HEXIWEAR/PeripheralPins.c @@ -99,6 +99,7 @@ const PinMap PinMap_UART_RTS[] = { /************SPI***************/ const PinMap PinMap_SPI_SCLK[] = { + {PTE2 , SPI_1, 2}, {PTB21, SPI_2, 2}, {PTC5 , SPI_0, 2}, {PTD5 , SPI_1, 7}, @@ -106,6 +107,8 @@ const PinMap PinMap_SPI_SCLK[] = { }; const PinMap PinMap_SPI_MOSI[] = { + {PTE1 , SPI_1, 2}, + {PTE3 , SPI_1, 7}, {PTB22, SPI_2, 2}, {PTC6 , SPI_0, 2}, {PTD6 , SPI_1, 7}, @@ -113,6 +116,8 @@ const PinMap PinMap_SPI_MOSI[] = { }; const PinMap PinMap_SPI_MISO[] = { + {PTE1 , SPI_1, 7}, + {PTE3 , SPI_1, 2}, {PTB23, SPI_2, 2}, {PTC7 , SPI_0, 2}, {PTD7 , SPI_1, 7}, @@ -120,6 +125,7 @@ const PinMap PinMap_SPI_MISO[] = { }; const PinMap PinMap_SPI_SSEL[] = { + {PTE4 , SPI_1, 2}, {PTB20, SPI_2, 2}, {PTC4 , SPI_0, 2}, {PTD4 , SPI_1, 7}, diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.c b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.c index 5a1028ba978..15e1f55f437 100755 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.c +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.c @@ -73,6 +73,9 @@ enum _flexcan_mb_code_tx kFLEXCAN_TxMbNotUsed = 0xF, /*!< Not used.*/ }; +/* Typedef for interrupt handler. */ +typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle); + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -86,23 +89,24 @@ enum _flexcan_mb_code_tx uint32_t FLEXCAN_GetInstance(CAN_Type *base); /*! - * @brief Enter FlexCAN Fraze Mode. + * @brief Enter FlexCAN Freeze Mode. * - * This function makes the FlexCAN work under Fraze Mode. + * This function makes the FlexCAN work under Freeze Mode. * * @param base FlexCAN peripheral base address. */ -static void FLEXCAN_EnterFrazeMode(CAN_Type *base); +static void FLEXCAN_EnterFreezeMode(CAN_Type *base); /*! - * @brief Exit FlexCAN Fraze Mode. + * @brief Exit FlexCAN Freeze Mode. * - * This function makes the FlexCAN leave Fraze Mode. + * This function makes the FlexCAN leave Freeze Mode. * * @param base FlexCAN peripheral base address. */ -static void FLEXCAN_ExitFrazeMode(CAN_Type *base); +static void FLEXCAN_ExitFreezeMode(CAN_Type *base); +#if !defined(NDEBUG) /*! * @brief Check if Message Buffer is occupied by Rx FIFO. * @@ -112,6 +116,19 @@ static void FLEXCAN_ExitFrazeMode(CAN_Type *base); * @param mbIdx The FlexCAN Message Buffer index. */ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +/*! + * @brief Get the first valid Message buffer ID of give FlexCAN instance. + * + * This function is a helper function for Errata 5641 workaround. + * + * @param base FlexCAN peripheral base address. + * @return The first valid Message Buffer Number. + */ +static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base); +#endif /*! * @brief Check if Message Buffer interrupt is enabled. @@ -165,6 +182,9 @@ static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS; /* Array of FlexCAN clock name. */ static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS; +/* FlexCAN ISR for transactional APIs. */ +static flexcan_isr_t s_flexcanIsr; + /******************************************************************************* * Code ******************************************************************************/ @@ -187,10 +207,10 @@ uint32_t FLEXCAN_GetInstance(CAN_Type *base) return instance; } -static void FLEXCAN_EnterFrazeMode(CAN_Type *base) +static void FLEXCAN_EnterFreezeMode(CAN_Type *base) { /* Set Freeze, Halt bits. */ - base->MCR |= CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK; + base->MCR |= CAN_MCR_HALT_MASK; /* Wait until the FlexCAN Module enter freeze mode. */ while (!(base->MCR & CAN_MCR_FRZACK_MASK)) @@ -198,10 +218,10 @@ static void FLEXCAN_EnterFrazeMode(CAN_Type *base) } } -static void FLEXCAN_ExitFrazeMode(CAN_Type *base) +static void FLEXCAN_ExitFreezeMode(CAN_Type *base) { /* Clear Freeze, Halt bits. */ - base->MCR &= ~(CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK); + base->MCR &= ~CAN_MCR_HALT_MASK; /* Wait until the FlexCAN Module exit freeze mode. */ while (base->MCR & CAN_MCR_FRZACK_MASK) @@ -209,6 +229,7 @@ static void FLEXCAN_ExitFrazeMode(CAN_Type *base) } } +#if !defined(NDEBUG) static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) { uint8_t lastOccupiedMb; @@ -221,7 +242,11 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) /* Calculate the number of last Message Buffer occupied by Rx FIFO. */ lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + if (mbIdx <= (lastOccupiedMb + 1)) +#else if (mbIdx <= lastOccupiedMb) +#endif { return true; } @@ -232,9 +257,40 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) } else { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + if (0 == mbIdx) + { + return true; + } + else + { + return false; + } +#else return false; +#endif } } +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base) +{ + uint32_t firstValidMbNum; + + if (base->MCR & CAN_MCR_RFEN_MASK) + { + firstValidMbNum = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + firstValidMbNum = ((firstValidMbNum + 1) * 2) + 6; + } + else + { + firstValidMbNum = 0; + } + + return firstValidMbNum; +} +#endif static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx) { @@ -296,7 +352,7 @@ static void FLEXCAN_Reset(CAN_Type *base) base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); #else - base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); + base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); #endif /* Reset CTRL1 and CTRL2 rigister. */ @@ -387,7 +443,7 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc /* Reset to known status. */ FLEXCAN_Reset(base); - /* Save current MCR value. */ + /* Save current MCR value and enable to enter Freeze mode(enabled by default). */ mcrTemp = base->MCR; /* Set the maximum number of Message Buffers */ @@ -448,8 +504,8 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf /* Assertion. */ assert(config); - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Cleaning previous Timing Setting. */ base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | @@ -460,59 +516,55 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) | CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg)); - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } -void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) { - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Setting Rx Message Buffer Global Mask value. */ base->RXMGMASK = mask; base->RX14MASK = mask; base->RX15MASK = mask; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } -void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) { - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Setting Rx FIFO Global Mask value. */ base->RXFGMASK = mask; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } -void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) { assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Setting Rx Individual Mask value. */ base->RXIMR[maskIdx] = mask; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) { /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Inactivate Message Buffer. */ if (enable) @@ -535,14 +587,10 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(((config) || (false == enable))); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp = 0; - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } - /* Inactivate Message Buffer. */ base->MB[mbIdx].CS = 0; @@ -574,7 +622,7 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co } } -void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable) +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable) { /* Assertion. */ assert((config) || (false == enable)); @@ -582,8 +630,8 @@ void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS); uint8_t setup_mb, i, rffn = 0; - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); if (enable) { @@ -675,8 +723,8 @@ void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con FLEXCAN_SetRxMbConfig(base, 5, NULL, false); } - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } #if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) @@ -684,25 +732,25 @@ void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) { if (enable) { - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Enable FlexCAN DMA. */ base->MCR |= CAN_MCR_DMA_MASK; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } else { - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Disable FlexCAN DMA. */ base->MCR &= ~CAN_MCR_DMA_MASK; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } } #endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ @@ -713,14 +761,10 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(txFrame); assert(txFrame->length <= 8); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp = 0; - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } - /* Check if Message Buffer is available. */ if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) { @@ -751,6 +795,11 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t /* Activate Tx Message Buffer. */ base->MB[mbIdx].CS = cs_temp; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif + return kStatus_Success; } else @@ -765,15 +814,11 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(rxFrame); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp; uint8_t rx_code; - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } - /* Read CS field of Rx Message Buffer to lock Message Buffer. */ cs_temp = base->MB[mbIdx].CS; /* Get Rx Message Buffer Code field. */ @@ -819,7 +864,7 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram } } -status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) { /* Assertion. */ assert(rxFrame); @@ -863,7 +908,7 @@ status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) } } -status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame) +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame) { /* Write Tx Message Buffer to initiate a data sending. */ if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame)) @@ -884,7 +929,7 @@ status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra } } -status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) { /* Wait until Rx Message Buffer non-empty. */ while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) @@ -898,7 +943,7 @@ status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_ return FLEXCAN_ReadRxMb(base, mbIdx, rxFrame); } -status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame) +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame) { status_t rxFifoStatus; @@ -908,7 +953,7 @@ status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rx } /* */ - rxFifoStatus = FlEXCAN_ReadRxFifo(base, rxFrame); + rxFifoStatus = FLEXCAN_ReadRxFifo(base, rxFrame); /* Clean Rx Fifo available flag. */ FLEXCAN_ClearMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag); @@ -938,6 +983,8 @@ void FLEXCAN_TransferCreateHandle(CAN_Type *base, handle->callback = callback; handle->userData = userData; + s_flexcanIsr = FLEXCAN_TransferHandleIRQ; + /* We Enable Error & Status interrupt here, because this interrupt just * report current status of FlexCAN module through Callback function. * It is insignificance without a available callback function. @@ -970,11 +1017,7 @@ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handl assert(handle); assert(xfer); assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); /* Check if Message Buffer is idle. */ if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) @@ -1017,11 +1060,7 @@ status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *ha assert(handle); assert(xfer); assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); /* Check if Message Buffer is idle. */ if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) @@ -1073,11 +1112,7 @@ void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t /* Assertion. */ assert(handle); assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Disable Message Buffer Interrupt. */ FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); @@ -1096,11 +1131,7 @@ void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint /* Assertion. */ assert(handle); assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Disable Message Buffer Interrupt. */ FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); @@ -1185,7 +1216,7 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) break; case kFLEXCAN_RxFifoFrameAvlFlag: - status = FlEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); + status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); if (kStatus_Success == status) { status = kStatus_FLEXCAN_RxFifoIdle; @@ -1273,7 +1304,7 @@ void CAN0_DriverIRQHandler(void) { assert(s_flexcanHandle[0]); - FLEXCAN_TransferHandleIRQ(CAN0, s_flexcanHandle[0]); + s_flexcanIsr(CAN0, s_flexcanHandle[0]); } #endif @@ -1282,7 +1313,7 @@ void CAN1_DriverIRQHandler(void) { assert(s_flexcanHandle[1]); - FLEXCAN_TransferHandleIRQ(CAN1, s_flexcanHandle[1]); + s_flexcanIsr(CAN1, s_flexcanHandle[1]); } #endif @@ -1291,7 +1322,7 @@ void CAN2_DriverIRQHandler(void) { assert(s_flexcanHandle[2]); - FLEXCAN_TransferHandleIRQ(CAN2, s_flexcanHandle[2]); + s_flexcanIsr(CAN2, s_flexcanHandle[2]); } #endif @@ -1300,7 +1331,7 @@ void CAN3_DriverIRQHandler(void) { assert(s_flexcanHandle[3]); - FLEXCAN_TransferHandleIRQ(CAN3, s_flexcanHandle[3]); + s_flexcanIsr(CAN3, s_flexcanHandle[3]); } #endif @@ -1309,6 +1340,6 @@ void CAN4_DriverIRQHandler(void) { assert(s_flexcanHandle[4]); - FLEXCAN_TransferHandleIRQ(CAN4, s_flexcanHandle[4]); + s_flexcanIsr(CAN4, s_flexcanHandle[4]); } #endif diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h index b0dee77173d..13c28f357d4 100755 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h @@ -37,7 +37,6 @@ * @{ */ -/*! @file*/ /****************************************************************************** * Definitions @@ -87,10 +86,8 @@ (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */ #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \ - ( \ - ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ - ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \ - << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \ (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \ @@ -296,13 +293,13 @@ typedef struct _flexcan_frame uint32_t length : 4; /*!< CAN frame payload length in bytes(Range: 0~8). */ uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ - uint32_t reserve1 : 1; /*!< Reserved for placeholder. */ + uint32_t : 1; /*!< Reserved. */ uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */ }; struct { uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ - uint32_t reserve2 : 3; /*!< Reserved for place holder. */ + uint32_t : 3; /*!< Reserved. */ }; union { @@ -366,7 +363,7 @@ typedef struct _flexcan_rx_mb_config flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */ } flexcan_rx_mb_config_t; -/*! @brief FlexCAN Rx FIFO configure structure. */ +/*! @brief FlexCAN Rx FIFO configuration structure. */ typedef struct _flexcan_rx_fifo_config { uint32_t *idFilterTable; /*!< Pointer to FlexCAN Rx FIFO identifier filter table. */ @@ -437,7 +434,7 @@ extern "C" { * to call the FLEXCAN_Init function by passing in these parameters: * @code * flexcan_config_t flexcanConfig; - * flexcanConfig.clkSrc = KFLEXCAN_ClkSrcOsc; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; * flexcanConfig.baudRate = 125000U; * flexcanConfig.maxMbNum = 16; * flexcanConfig.enableLoopBack = false; @@ -466,7 +463,7 @@ void FLEXCAN_Deinit(CAN_Type *base); /*! * @brief Get the default configuration structure. * - * This function initializes the FlexCAN configure structure to default value. The default + * This function initializes the FlexCAN configuration structure to default value. The default * value are: * flexcanConfig->clkSrc = KFLEXCAN_ClkSrcOsc; * flexcanConfig->baudRate = 125000U; @@ -512,7 +509,7 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf * @param base FlexCAN peripheral base address. * @param mask Rx Message Buffer Global Mask value. */ -void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); /*! * @brief Sets the FlexCAN receive FIFO global mask. @@ -522,7 +519,7 @@ void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); * @param base FlexCAN peripheral base address. * @param mask Rx Fifo Global Mask value. */ -void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); /*! * @brief Sets the FlexCAN receive individual mask. @@ -538,7 +535,7 @@ void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); * @param maskIdx The Index of individual Mask. * @param mask Rx Individual Mask value. */ -void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask); +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask); /*! * @brief Configures a FlexCAN transmit message buffer. @@ -580,7 +577,7 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co * - true: Enable Rx FIFO. * - false: Disable Rx FIFO. */ -void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable); +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable); /* @} */ @@ -629,7 +626,7 @@ static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask) * @param txErrBuf Buffer to store Tx Error Counter value. * @param rxErrBuf Buffer to store Rx Error Counter value. */ -static inline void FlEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf) +static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf) { if (txErrBuf) { @@ -890,7 +887,7 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram * @retval kStatus_Success - Read Message from Rx FIFO successfully. * @retval kStatus_Fail - Rx FIFO is not enabled. */ -status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); /* @} */ @@ -910,7 +907,7 @@ status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); * @retval kStatus_Success - Write Tx Message Buffer Successfully. * @retval kStatus_Fail - Tx Message Buffer is currently in use. */ -status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame); +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame); /*! * @brief Performs a polling receive transaction on the CAN bus. @@ -924,7 +921,7 @@ status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. * @retval kStatus_Fail - Rx Message Buffer is empty. */ -status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); /*! * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus. @@ -936,7 +933,7 @@ status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_ * @retval kStatus_Success - Read Message from Rx FIFO successfully. * @retval kStatus_Fail - Rx FIFO is not enabled. */ -status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame); +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame); /*! * @brief Initializes the FlexCAN handle. diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c index a45e9e62134..c38165ec045 100755 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c @@ -40,6 +40,12 @@ enum _sai_transfer_state kSAI_Error /*!< Transfer error occured. */ }; +/*! @brief Typedef for sai tx interrupt handler. */ +typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/*! @brief Typedef for sai rx interrupt handler. */ +typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -98,6 +104,10 @@ static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; /* Clock name array */ static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_tx_isr_t s_saiTxIsr; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_rx_isr_t s_saiRxIsr; /******************************************************************************* * Code @@ -231,12 +241,13 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Configure Master clock output enable */ - base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); - /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ /* Configure audio protocol */ @@ -332,12 +343,13 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Configure Master clock output enable */ - base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); - /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ /* Configure audio protocol */ @@ -663,6 +675,9 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + /* Set the isr pointer */ + s_saiTxIsr = SAI_TransferTxHandleIRQ; + /* Enable Tx irq */ EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); } @@ -676,6 +691,9 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + /* Set the isr pointer */ + s_saiRxIsr = SAI_TransferRxHandleIRQ; + /* Enable Rx irq */ EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); } @@ -1011,24 +1029,24 @@ void I2S0_DriverIRQHandler(void) { if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag))) { - SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); } if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag))) { - SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); } } #else void I2S0_Tx_DriverIRQHandler(void) { assert(s_saiHandle[0][0]); - SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); } void I2S0_Rx_DriverIRQHandler(void) { assert(s_saiHandle[0][1]); - SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); } #endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */ #endif /* I2S0*/ @@ -1037,12 +1055,12 @@ void I2S0_Rx_DriverIRQHandler(void) void I2S1_Tx_DriverIRQHandler(void) { assert(s_saiHandle[1][0]); - SAI_TransferTxHandleIRQ(I2S1, s_saiHandle[1][0]); + s_saiTxIsr(I2S1, s_saiHandle[1][0]); } void I2S1_Rx_DriverIRQHandler(void) { assert(s_saiHandle[1][1]); - SAI_TransferRxHandleIRQ(I2S1, s_saiHandle[1][1]); + s_saiRxIsr(I2S1, s_saiHandle[1][1]); } #endif diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.h b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.h index 72b6efd06bc..cb38688cd92 100755 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.h +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.h @@ -38,7 +38,6 @@ * @{ */ -/*! @file */ /******************************************************************************* * Definitions @@ -46,7 +45,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */ /*@}*/ /*! @brief SAI return status*/ @@ -168,7 +167,7 @@ typedef enum _sai_fifo_packing } sai_fifo_packing_t; #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ -/*! @brief SAI user configure structure */ +/*! @brief SAI user configuration structure */ typedef struct _sai_config { sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ @@ -276,7 +275,7 @@ extern "C" { * because the clock is not enabled. * * @param base SAI base pointer - * @param config SAI configure structure. + * @param config SAI configuration structure. */ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); @@ -292,7 +291,7 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); * because the clock is not enabled. * * @param base SAI base pointer - * @param config SAI configure structure. + * @param config SAI configuration structure. */ void SAI_RxInit(I2S_Type *base, const sai_config_t *config); diff --git a/hal/targets/hal/TARGET_Maxim/TARGET_MAX32600/serial_api.c b/hal/targets/hal/TARGET_Maxim/TARGET_MAX32600/serial_api.c index da2b10bc4d9..7ce61555323 100644 --- a/hal/targets/hal/TARGET_Maxim/TARGET_MAX32600/serial_api.c +++ b/hal/targets/hal/TARGET_Maxim/TARGET_MAX32600/serial_api.c @@ -250,27 +250,15 @@ int serial_getc(serial_t *obj) while(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY) {} c = obj->uart->tx_rx_fifo & 0xFF; - // Echo characters for stdio - if (obj->uart == (mxc_uart_regs_t*)STDIO_UART) { - obj->uart->tx_rx_fifo = c; - } - return c; } //****************************************************************************** void serial_putc(serial_t *obj, int c) { - // Append a carriage return for stdio - if ((c == (int)'\n') && (obj->uart == (mxc_uart_regs_t*)STDIO_UART)) { - while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {} - obj->uart->tx_rx_fifo = '\r'; - } - // Wait for TXFIFO to not be full while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {} obj->uart->tx_rx_fifo = c; - } //****************************************************************************** diff --git a/hal/targets/hal/TARGET_Maxim/TARGET_MAX32610/serial_api.c b/hal/targets/hal/TARGET_Maxim/TARGET_MAX32610/serial_api.c index da2b10bc4d9..7ce61555323 100644 --- a/hal/targets/hal/TARGET_Maxim/TARGET_MAX32610/serial_api.c +++ b/hal/targets/hal/TARGET_Maxim/TARGET_MAX32610/serial_api.c @@ -250,27 +250,15 @@ int serial_getc(serial_t *obj) while(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY) {} c = obj->uart->tx_rx_fifo & 0xFF; - // Echo characters for stdio - if (obj->uart == (mxc_uart_regs_t*)STDIO_UART) { - obj->uart->tx_rx_fifo = c; - } - return c; } //****************************************************************************** void serial_putc(serial_t *obj, int c) { - // Append a carriage return for stdio - if ((c == (int)'\n') && (obj->uart == (mxc_uart_regs_t*)STDIO_UART)) { - while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {} - obj->uart->tx_rx_fifo = '\r'; - } - // Wait for TXFIFO to not be full while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {} obj->uart->tx_rx_fifo = c; - } //****************************************************************************** diff --git a/hal/targets/hal/TARGET_Maxim/TARGET_MAX32620/serial_api.c b/hal/targets/hal/TARGET_Maxim/TARGET_MAX32620/serial_api.c index f213ab7b00d..105449bb7bf 100644 --- a/hal/targets/hal/TARGET_Maxim/TARGET_MAX32620/serial_api.c +++ b/hal/targets/hal/TARGET_Maxim/TARGET_MAX32620/serial_api.c @@ -303,29 +303,12 @@ int serial_getc(serial_t *obj) c = *obj->fifo->rx_8; - // Echo characters for stdio - if (obj->uart == (mxc_uart_regs_t*)STDIO_UART) { - *obj->fifo->tx_8 = (uint8_t)c; - } - return c; } //****************************************************************************** void serial_putc(serial_t *obj, int c) { - // Append a carriage return for stdio - if ((c == (int)'\n') && (obj->uart == (mxc_uart_regs_t*)STDIO_UART)) { - while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) - >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) - >= MXC_UART_FIFO_DEPTH ); - - // Must clear before every write to the buffer to know that the fifo - // is empty when the TX DONE bit is set - obj->uart->intfl = MXC_F_UART_INTFL_TX_DONE; - *obj->fifo->tx_8 = (uint8_t)'\r'; - } - // Wait for TXFIFO to not be full while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_MTM_MTCONNECT04S/PinNames.h b/hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_MTM_MTCONNECT04S/PinNames.h new file mode 100644 index 00000000000..5a834539c43 --- /dev/null +++ b/hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_MTM_MTCONNECT04S/PinNames.h @@ -0,0 +1,137 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 Nordic Semiconductor + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 3 + +typedef enum { + p0 = 0, + p1 = 1, + p2 = 2, + p3 = 3, + p4 = 4, + p5 = 5, + p6 = 6, + p7 = 7, + p8 = 8, + p9 = 9, + p10 = 10, + p11 = 11, + p12 = 12, + p13 = 13, + p14 = 14, + p15 = 15, + p16 = 16, + p17 = 17, + p18 = 18, + p19 = 19, + p20 = 20, + p21 = 21, + p22 = 22, + p23 = 23, + p24 = 24, + p25 = 25, + p26 = 26, + p27 = 27, + p28 = 28, + p29 = 29, + p30 = 30, + p31 = 31, + + P0_0 = p0, + P0_1 = p1, + P0_2 = p2, + P0_3 = p3, + P0_4 = p4, + P0_5 = p5, + P0_6 = p6, + P0_7 = p7, + + P0_8 = p8, + P0_9 = p9, + P0_10 = p10, + P0_11 = p11, + P0_12 = p12, + P0_13 = p13, + P0_14 = p14, + P0_15 = p15, + + P0_16 = p16, + P0_17 = p17, + P0_18 = p18, + P0_19 = p19, + P0_20 = p20, + P0_21 = p21, + P0_22 = p22, + P0_23 = p23, + + P0_24 = p24, + P0_25 = p25, + P0_26 = p26, + P0_27 = p27, + P0_28 = p28, + P0_29 = p29, + P0_30 = p30, + P0_31 = p31, + + LEDR = p16, + LEDG = p15, + LEDB = p6, + LED1 = LEDR, + LED2 = LEDG, + LED3 = LEDB, + LED4 = LEDB, + + RX_PIN_NUMBER = p4, + TX_PIN_NUMBER = p5, + CTS_PIN_NUMBER = p2, + RTS_PIN_NUMBER = p3, + + // mBed interface Pins + USBTX = TX_PIN_NUMBER, + USBRX = RX_PIN_NUMBER, + + I2C_SDA0 = p14, + I2C_SCL0 = p13, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_MTM_MTCONNECT04S/device.h b/hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_MTM_MTCONNECT04S/device.h new file mode 100644 index 00000000000..3b470c68647 --- /dev/null +++ b/hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_MTM_MTCONNECT04S/device.h @@ -0,0 +1,38 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + + + + + + + + + + + + + + + + +#include "objects.h" + +#endif diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_DELTA_DFBM_NQ620/PinNames.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_DELTA_DFBM_NQ620/PinNames.h new file mode 100644 index 00000000000..c9cb9317078 --- /dev/null +++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_DELTA_DFBM_NQ620/PinNames.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2016 Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA + * integrated circuit in a product or a software update for such product, must reproduce + * the above copyright notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be + * used to endorse or promote products derived from this software without specific prior + * written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary or object form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 3 + +typedef enum { + p0 = 0, + p1 = 1, + p2 = 2, + p3 = 3, + p4 = 4, + p5 = 5, + p6 = 6, + p7 = 7, + p8 = 8, + p9 = 9, + p10 = 10, + p11 = 11, + p12 = 12, + p13 = 13, + p14 = 14, + p15 = 15, + p16 = 16, + p17 = 17, + p18 = 18, + p19 = 19, + p20 = 20, + p21 = 21, + p22 = 22, + p23 = 23, + p24 = 24, + p25 = 25, + p26 = 26, + p27 = 27, + p28 = 28, + p29 = 29, + p30 = 30, + p31 = 31, + + P0_0 = p0, + P0_1 = p1, + P0_2 = p2, + P0_3 = p3, + P0_4 = p4, + P0_5 = p5, + P0_6 = p6, + P0_7 = p7, + + P0_8 = p8, + P0_9 = p9, + P0_10 = p10, + P0_11 = p11, + P0_12 = p12, + P0_13 = p13, + P0_14 = p14, + P0_15 = p15, + + P0_16 = p16, + P0_17 = p17, + P0_18 = p18, + P0_19 = p19, + P0_20 = p20, + P0_21 = p21, + P0_22 = p22, + P0_23 = p23, + + P0_24 = p24, + P0_25 = p25, + P0_26 = p26, + P0_27 = p27, + P0_28 = p28, + P0_29 = p29, + P0_30 = p30, + + LED1 = p17, + LED2 = p18, + LED3 = p19, + LED4 = p20, + + BUTTON1 = p13, + BUTTON2 = p14, + BUTTON3 = p15, + BUTTON4 = p16, + + RX_PIN_NUMBER = p11, + TX_PIN_NUMBER = p12, + CTS_PIN_NUMBER = p13, + RTS_PIN_NUMBER = p14, + + // mBed interface Pins + USBTX = TX_PIN_NUMBER, + USBRX = RX_PIN_NUMBER, + + SPI_PSELMOSI0 = p23, + SPI_PSELMISO0 = p24, + SPI_PSELSS0 = p22, + SPI_PSELSCK0 = p25, + + SPI_PSELMOSI1 = p12, + SPI_PSELMISO1 = p13, + SPI_PSELSS1 = p11, + SPI_PSELSCK1 = p14, + + SPIS_PSELMOSI = p12, + SPIS_PSELMISO = p13, + SPIS_PSELSS = p11, + SPIS_PSELSCK = p14, + + I2C_SDA0 = p26, + I2C_SCL0 = p27, + + D0 = p11, + D1 = p12, + D2 = p13, + D3 = p14, + D4 = p15, + D5 = p16, + D6 = p17, + D7 = p18, + + D8 = p19, + D9 = p20, + D10 = p22, + D11 = p23, + D12 = p24, + D13 = p25, + + D14 = p26, + D15 = p27, + + A0 = p3, + A1 = p4, + A2 = p28, + A3 = p29, + A4 = p30, + A5 = p31, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_DELTA_DFBM_NQ620/device.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_DELTA_DFBM_NQ620/device.h new file mode 100644 index 00000000000..2427e752ea9 --- /dev/null +++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_DELTA_DFBM_NQ620/device.h @@ -0,0 +1,38 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + + + + + + + + + + + + + + + + +#include "objects.h" + +#endif diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/Pad.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/Pad.c index d46dd78514f..47e54bbeb5c 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/Pad.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/Pad.c @@ -8,9 +8,15 @@ * $Rev: 2848 $ * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/PeripheralNames.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/PeripheralNames.h index 93af9371604..7306fa2e0b6 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/PeripheralNames.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/PeripheralNames.h @@ -7,9 +7,15 @@ * $Rev: 0.1 $ * $Date: 2015-11-07 $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h index 3e61f379659..49536724d84 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h @@ -7,9 +7,15 @@ * $Rev: 0.1 $ * $Date: 2015-11-06 $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h index c9e67440709..0f6cfc5bfa7 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h @@ -7,9 +7,15 @@ * $Date: 2015-06-15 16:46:35 +0530 (Mon, 15 Jun 2015) $ * @brief Definitions and API for the SAR ADC driver. ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h index c6522331135..95dc35b4d54 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h @@ -7,9 +7,15 @@ * $Rev: 3422 $ * $Date: 2015-06-09 11:01:43 +0530 (Tue, 09 Jun 2015) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/aes_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/aes_map.h index e585eb3bae1..d9de7e59e8a 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/aes_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/aes_map.h @@ -7,9 +7,15 @@ * $Rev: 2110 $ * $Date: 2013-07-16 20:13:03 +0530 (Tue, 16 Jul 2013) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/analogin_api.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/analogin_api.c index 3cd8e689d87..b28b77a73f8 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/analogin_api.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/analogin_api.c @@ -7,9 +7,15 @@ * $Rev: * $Date: ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/architecture.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/architecture.h index 2b23233bbe7..4306b8ed6ca 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/architecture.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/architecture.h @@ -7,9 +7,15 @@ * $Rev: $ * $Date: $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h index e1d3a43ac97..01ae0924240 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h @@ -7,9 +7,15 @@ * $Rev: 3823 $ * $Date: 2015-10-23 16:21:37 +0530 (Fri, 23 Oct 2015) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h index d3318ba50c7..bbb160635b6 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h @@ -7,9 +7,15 @@ * $Rev: 2607 $ * $Date: 2013-12-06 18:02:43 +0530 (Fri, 06 Dec 2013) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/clock.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/clock.h index 546afd7c57e..30f5f77b388 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/clock.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/clock.h @@ -7,9 +7,15 @@ * $Rev: 3414 $ * $Date: 2015-06-05 13:27:04 +0530 (Fri, 05 Jun 2015) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h index 8bef9ba56b9..dfc7056463f 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h @@ -7,9 +7,15 @@ * $Rev: 2848 $ * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/crossbar.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/crossbar.h index e9cac9d2323..e7347c39d4d 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/crossbar.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/crossbar.h @@ -7,9 +7,15 @@ * $Rev: 2033 $ * $Date: 2013-06-28 17:12:31 +0200 (Fri, 28 Jun 2013) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/crossbar_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/crossbar_map.h index a1c070d99ba..4f1f89c60a3 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/crossbar_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/crossbar_map.h @@ -7,9 +7,15 @@ * $Rev: 3318 $ * $Date: 2015-03-27 16:29:34 +0530 (Fri, 27 Mar 2015) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/device.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/device.h index 9c78dda34f4..1dd9b649de0 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/device.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/device.h @@ -7,9 +7,15 @@ * $Rev: 0.1 $ * $Date: 2015-11-06 $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h index c0ff8cfdae9..84ef37fea01 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h @@ -7,9 +7,15 @@ * $Rev: 3415 $ * $Date: 2015-06-05 13:29:52 +0530 (Fri, 05 Jun 2015) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/error.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/error.h index 81e7813b256..a76b7c17662 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/error.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/error.h @@ -7,9 +7,15 @@ * $Rev: 2074 $ * $Date: 2013-07-10 18:06:15 +0530 (Wed, 10 Jul 2013) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/exceptions.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/exceptions.c index b1dc6034b40..8ad8160873e 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/exceptions.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/exceptions.c @@ -7,9 +7,15 @@ * $Rev: 2074 $ * $Date: 2013-07-10 14:36:15 +0200 (Wed, 10 Jul 2013) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/fib.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/fib.h index 69e24b9f329..fb7a400fdf0 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/fib.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/fib.h @@ -7,9 +7,15 @@ * $Rev: 2074 $ * $Date: 2013-07-10 14:36:15 +0200 (Wed, 10 Jul 2013) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/flash_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/flash_map.h index 3429cbbcd4d..19849ad24c3 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/flash_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/flash_map.h @@ -7,9 +7,15 @@ * $Rev: 2686 $ * $Date: 2014-01-23 13:31:54 +0530 (Thu, 23 Jan 2014) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio.h index f75b7b5ab4f..8780f196c03 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio.h @@ -7,9 +7,15 @@ * $Rev: 3724 $ * $Date: 2015-09-14 14:35:42 +0530 (Mon, 14 Sep 2015) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_api.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_api.c index 6ece1879e44..d8f06c11de8 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_api.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_api.c @@ -7,9 +7,15 @@ * $Rev: * $Date: 2015-11-04 $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c index 4616ed29804..f8d6e7e6117 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c @@ -7,9 +7,15 @@ * $Rev: * $Date: 2015-11-04 $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h index b12d50cd341..0bc576e8fc1 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h @@ -7,9 +7,15 @@ * $Rev: 2115 $ * $Date: 2013-07-17 18:08:17 +0530 (Wed, 17 Jul 2013) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c.h index da4eae1e163..3467f5def7e 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c.h @@ -7,9 +7,15 @@ * $Rev: $ * $Date: 2016-04-20 $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c index ac1a84e9b66..e710399eea4 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c @@ -7,9 +7,15 @@ * $Rev: 3525 $ * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h index 7402fc37101..fc671c1a2be 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h @@ -7,9 +7,15 @@ * $Rev: 3324 $ * $Date: 2015-03-27 17:00:28 +0530 (Fri, 27 Mar 2015) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h index 271c7fa2dd6..8dca4371cee 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h @@ -7,9 +7,15 @@ * $Rev: 3390 $ * $Date: 2015-05-13 17:21:05 +0530 (Wed, 13 May 2015) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/macros.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/macros.h index ea6ce851e11..fff801ec85e 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/macros.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/macros.h @@ -7,9 +7,15 @@ * $Rev: 2076 $ * $Date: 2013-07-10 18:26:10 +0530 (Wed, 10 Jul 2013) $ ******************************************************************************* - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h index 22158af3f67..508fed1aa5c 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h @@ -7,9 +7,15 @@ * $Rev: 3525 $ * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/mib.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/mib.h index 7853980939d..bb63e928525 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/mib.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/mib.h @@ -7,9 +7,15 @@ * $Rev: 2284 $ * $Date: 2013-09-12 15:08:22 +0530 (Thu, 12 Sep 2013) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c index 71c63e9c2ce..2487de64132 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c @@ -7,9 +7,15 @@ * $Rev: * $Date: $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF @@ -28,7 +34,7 @@ * Header files * * * *************************************************************************************************/ -#include "NCS36510Init.h" +#include "ncs36510Init.h" void fPmuInit(void); /** diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.h index 67e14eabd30..953512aa16d 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.h @@ -7,9 +7,15 @@ * $Rev: * $Date: $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c index d4864b205bb..cc840d8215c 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c @@ -7,9 +7,15 @@ * $Rev: $ * $Date: 2016-04-12 $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c index 4c04397fced..b5f6a159dda 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c @@ -7,9 +7,15 @@ * $Rev: $ * $Date: $ ****************************************************************************** - * @copyright (c) 2015 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c index 04700aa0ae8..17e842ef4e5 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c @@ -7,9 +7,15 @@ * @version $Rev: $ * @date $Date: 2016-02-05 $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c index 89db27e62e7..16afcbcf930 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c @@ -7,9 +7,15 @@ * $Rev: $ * $Date: 2015-11-15 $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/objects.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/objects.h index 386d377e571..915197ef3dc 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/objects.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/objects.h @@ -7,9 +7,15 @@ * $Rev: 0.1 $ * $Date: 2015-11-06 $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pad.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pad.h index 8fda83912ad..26d3e5c7ec2 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pad.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pad.h @@ -8,9 +8,15 @@ * $Rev: 2848 $ * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h index 31791071d05..a41d693eb52 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h @@ -7,9 +7,15 @@ * $Rev: 3166 $ * $Date: 2015-01-19 11:28:08 +0530 (Mon, 19 Jan 2015) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h index 58d897f6f7b..33913ed3188 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h @@ -7,9 +7,15 @@ * $Rev: 3372 $ * $Date: 2015-04-22 12:18:18 +0530 (Wed, 22 Apr 2015) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/port_api.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/port_api.c index 5ed13439d3d..e0fb1c08584 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/port_api.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/port_api.c @@ -7,9 +7,15 @@ * $Rev: * $Date: ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h index c7c824bd5eb..455a8cb56b1 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h @@ -7,9 +7,15 @@ * $Rev: 3378 $ * $Date: 2015-04-28 13:38:36 +0530 (Tue, 28 Apr 2015) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pwmout_api.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pwmout_api.c index f168b2272a1..8940120fd68 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pwmout_api.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pwmout_api.c @@ -7,9 +7,15 @@ * $Rev: * $Date: ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/random_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/random_map.h index 267800ed7e6..db395cc58a8 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/random_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/random_map.h @@ -7,9 +7,15 @@ * $Rev: 3283 $ * $Date: 2015-02-26 18:52:22 +0530 (Thu, 26 Feb 2015) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/reset_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/reset_map.h index 5bc1c2f6d15..229d8e78a3e 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/reset_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/reset_map.h @@ -7,9 +7,15 @@ * $Rev: 2848 $ * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c index 775ac2124a0..12f5127935f 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c @@ -7,9 +7,15 @@ * $Rev: 3445 $ * $Date: 2015-06-22 13:51:24 +0530 (Mon, 22 Jun 2015) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h index 482bc6d7e6e..21b10652f61 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h @@ -7,9 +7,15 @@ * $Rev: 2848 $ * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h index ccf931c15ae..22ee1e48a67 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h @@ -7,9 +7,15 @@ * $Rev: 2953 $ * $Date: 2014-09-15 18:13:01 +0530 (Mon, 15 Sep 2014) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc.c index a98c5e6d2b0..aad86ca8ef5 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc.c @@ -7,9 +7,15 @@ * $Rev: 3525 $ * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc.h index 06af25b8f5b..2e7f210e84e 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc.h @@ -7,9 +7,15 @@ * $Rev: 3485 $ * $Date: 2015-07-14 15:20:11 +0530 (Tue, 14 Jul 2015) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc_api.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc_api.c index 8cff6fbc023..15cb73c8562 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc_api.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc_api.c @@ -7,9 +7,15 @@ * $Rev: 0.1 $ * $Date: 2016-01-20 12:09:00 +0530 (Wed, 20 Jan 2016) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h index c8ee311b555..64b06acbfdf 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h @@ -7,9 +7,15 @@ * $Rev: 3008 $ * $Date: 2014-10-16 18:42:48 +0530 (Thu, 16 Oct 2014) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c index 3e1d27ff7a3..1d57d654908 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c @@ -7,9 +7,15 @@ * $Rev: 0.1 $ * $Date: 2015-11-04 05:30:00 +0530 (Wed, 04 Nov 2015) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep.c index ab5669bd1bd..9fce0d8de29 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep.c @@ -7,9 +7,15 @@ * $Rev: 0.1 $ * $Date: 01-21-2016 $ ****************************************************************************** - * @copyright (c) 2015 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep.h index 6a6a4d55109..f7e6cb8f8c2 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep.h @@ -7,9 +7,15 @@ * $Rev: $ * $Date: $ ****************************************************************************** - * @copyright (c) 2015 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c index 18e1fda94d0..432c6e1ba16 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c @@ -7,9 +7,16 @@ * $Rev: $ * $Date: $ ****************************************************************************** - * @copyright (c) 2015 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. + * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi.h index e6ea31d82a8..7ca81c258fc 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi.h @@ -7,9 +7,15 @@ * @version $Rev: $ * @date $Date: 2016-02-05 $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c index 6f55c5f9a4d..614e0c73358 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c @@ -7,9 +7,15 @@ * $Rev: 0.1 $ * $Date: 02-05-2016 $ ****************************************************************************** - * @copyright (c) 2015 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi_ipc7207_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi_ipc7207_map.h index f59a6dc3799..507c1042359 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi_ipc7207_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi_ipc7207_map.h @@ -7,9 +7,15 @@ * $Rev: 2110 $ * $Date: 2013-07-16 20:13:03 +0530 (Tue, 16 Jul 2013) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/swversion.c b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/swversion.c index ab9511bf183..50f30ff12a5 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/swversion.c +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/swversion.c @@ -7,9 +7,15 @@ * $Rev: 2199 $ * $Date: 2013-08-07 12:17:27 +0200 (Wed, 07 Aug 2013) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sys.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sys.h index 617f65734c0..e55c0929a50 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sys.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sys.h @@ -7,9 +7,15 @@ * $Rev: 2074 $ * $Date: 2013-07-10 14:36:15 +0200 (Wed, 10 Jul 2013) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/test_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/test_map.h index 3bd6910c4d9..122a2434edc 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/test_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/test_map.h @@ -7,9 +7,15 @@ * $Rev: 2848 $ * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ticker.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ticker.h index 7ef1d99aa85..82f186d093c 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ticker.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ticker.h @@ -7,9 +7,15 @@ * $Rev: * $Date: ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/timer.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/timer.h index 0b96c1ba9ed..59b0d760625 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/timer.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/timer.h @@ -7,9 +7,15 @@ * $Rev: 3725 $ * $Date: 2015-09-14 14:36:27 +0530 (Mon, 14 Sep 2015) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h index 5d83156b7bc..28e172c2634 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h @@ -7,9 +7,15 @@ * $Rev: 3423 $ * $Date: 2015-06-09 11:16:49 +0530 (Tue, 09 Jun 2015) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h index ad64ae49464..560198916c3 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h @@ -7,9 +7,15 @@ * $Rev: 3727 $ * $Date: 2015-09-14 14:38:34 +0530 (Mon, 14 Sep 2015) $ ****************************************************************************** -* @copyright (c) 2012 ON Semiconductor. All rights reserved. -* ON Semiconductor is supplying this software for use with ON Semiconductor -* processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/types.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/types.h index af09cc32f2c..88153af0807 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/types.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/types.h @@ -7,9 +7,15 @@ * $Rev: 2074 $ * $Date: 2013-07-10 18:06:15 +0530 (Wed, 10 Jul 2013) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart.h index 3272d6eccb4..cdb92bc79d5 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart.h @@ -7,9 +7,15 @@ * $Rev: 2074 $ * $Date: 2013-07-10 18:06:15 +0530 (Wed, 10 Jul 2013) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h index 838e43bc0e7..dcba674cdd7 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h @@ -7,9 +7,15 @@ * $Rev: 2607 $ * $Date: 2013-12-06 18:02:43 +0530 (Fri, 06 Dec 2013) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h index 5381af73657..b26e37d8faf 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h @@ -7,9 +7,15 @@ * $Rev: 2615 $ * $Date: 2013-12-13 13:17:21 +0530 (Fri, 13 Dec 2013) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h index 7f8091ea1db..8b07f3adb48 100644 --- a/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h +++ b/hal/targets/hal/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h @@ -7,9 +7,15 @@ * $Rev: 3283 $ * $Date: 2015-02-26 18:52:22 +0530 (Thu, 26 Feb 2015) $ ****************************************************************************** - * @copyright (c) 2012 ON Semiconductor. All rights reserved. - * ON Semiconductor is supplying this software for use with ON Semiconductor - * processor based microcontrollers only. + * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). + * All rights reserved. This software and/or documentation is licensed by ON Semiconductor + * under limited terms and conditions. The terms and conditions pertaining to the software + * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf + * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and + * if applicable the software license agreement. Do not use this software and/or + * documentation unless you have carefully read and you agree to the limited terms and + * conditions. By using this software and/or documentation, you agree to the limited + * terms and conditions. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device.h deleted file mode 100644 index f0799e9083e..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device.h +++ /dev/null @@ -1,54 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F0/device.h similarity index 99% rename from hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device.h rename to hal/targets/hal/TARGET_STM/TARGET_STM32F0/device.h index bbb4b7513e6..b6131682750 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F0/device.h @@ -32,22 +32,9 @@ #ifndef MBED_DEVICE_H #define MBED_DEVICE_H - - - - - - - - - //======================================= - #define DEVICE_ID_LENGTH 24 - - - #include "objects.h" #endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device.h deleted file mode 100644 index f0799e9083e..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device.h +++ /dev/null @@ -1,54 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h index 8d371add2df..3fc3ed5c335 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h @@ -60,17 +60,6 @@ struct analogin_s { uint8_t channel; }; -struct serial_s { - UARTName uart; - int index; // Used by irq - uint32_t baudrate; - uint32_t databits; - uint32_t stopbits; - uint32_t parity; - PinName pin_tx; - PinName pin_rx; -}; - struct spi_s { SPIName spi; uint32_t bits; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h index e0d28cc3b98..fa4a7243520 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h @@ -60,17 +60,6 @@ struct analogin_s { uint8_t channel; }; -struct serial_s { - UARTName uart; - int index; // Used by irq - uint32_t baudrate; - uint32_t databits; - uint32_t stopbits; - uint32_t parity; - PinName pin_tx; - PinName pin_rx; -}; - struct spi_s { SPIName spi; uint32_t bits; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device.h deleted file mode 100644 index f0799e9083e..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device.h +++ /dev/null @@ -1,54 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h index 53e829b7769..e16970c065b 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h @@ -60,17 +60,6 @@ struct analogin_s { uint8_t channel; }; -struct serial_s { - UARTName uart; - int index; // Used by irq - uint32_t baudrate; - uint32_t databits; - uint32_t stopbits; - uint32_t parity; - PinName pin_tx; - PinName pin_rx; -}; - struct spi_s { SPIName spi; uint32_t bits; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F1/common_objects.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F1/common_objects.h index a3c3410cb3f..585d323084c 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F1/common_objects.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F1/common_objects.h @@ -49,6 +49,25 @@ struct pwmout_s { uint8_t inverted; }; +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +#if DEVICE_SERIAL_ASYNCH + uint32_t events; +#endif +#if DEVICE_SERIAL_FC + uint32_t hw_flow_ctl; + PinName pin_rts; + PinName pin_cts; +#endif +}; + #include "gpio_object.h" #ifdef __cplusplus diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F1/device.h similarity index 99% rename from hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device.h rename to hal/targets/hal/TARGET_STM/TARGET_STM32F1/device.h index bbb4b7513e6..b6131682750 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F1/device.h @@ -32,22 +32,9 @@ #ifndef MBED_DEVICE_H #define MBED_DEVICE_H - - - - - - - - - //======================================= - #define DEVICE_ID_LENGTH 24 - - - #include "objects.h" #endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F1/serial_api.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F1/serial_api.c index bfa025b96e2..e88f9885b85 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F1/serial_api.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F1/serial_api.c @@ -40,76 +40,93 @@ #define UART_NUM (3) -static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0}; +static uint32_t serial_irq_ids[UART_NUM] = {0}; +static UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; -UART_HandleTypeDef UartHandle; - int stdio_uart_inited = 0; serial_t stdio_uart; +#if DEVICE_SERIAL_ASYNCH + #define SERIAL_S(obj) (&((obj)->serial)) +#else + #define SERIAL_S(obj) (obj) +#endif + static void init_uart(serial_t *obj) { - - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - UartHandle.Init.BaudRate = obj->baudrate; - UartHandle.Init.WordLength = obj->databits; - UartHandle.Init.StopBits = obj->stopbits; - UartHandle.Init.Parity = obj->parity; - UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - - if (obj->pin_rx == NC) { - UartHandle.Init.Mode = UART_MODE_TX; - } else if (obj->pin_tx == NC) { - UartHandle.Init.Mode = UART_MODE_RX; + struct serial_s *obj_s = SERIAL_S(obj); + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; + huart->Instance = (USART_TypeDef *)(obj_s->uart); + + huart->Init.BaudRate = obj_s->baudrate; + huart->Init.WordLength = obj_s->databits; + huart->Init.StopBits = obj_s->stopbits; + huart->Init.Parity = obj_s->parity; +#if DEVICE_SERIAL_FC + huart->Init.HwFlowCtl = obj_s->hw_flow_ctl; +#else + huart->Init.HwFlowCtl = UART_HWCONTROL_NONE; +#endif + huart->TxXferCount = 0; + huart->TxXferSize = 0; + huart->RxXferCount = 0; + huart->RxXferSize = 0; + + if (obj_s->pin_rx == NC) { + huart->Init.Mode = UART_MODE_TX; + } else if (obj_s->pin_tx == NC) { + huart->Init.Mode = UART_MODE_RX; } else { - UartHandle.Init.Mode = UART_MODE_TX_RX; + huart->Init.Mode = UART_MODE_TX_RX; } - // Fix because HAL_RCC_GetHCLKFreq() don't update anymore SystemCoreClock + /* uAMR & ARM: Call to UART init is done between reset of pre-initialized variables */ + /* and before HAL Init. SystemCoreClock init required here */ SystemCoreClockUpdate(); - if (HAL_UART_Init(&UartHandle) != HAL_OK) { + if (HAL_UART_Init(huart) != HAL_OK) { error("Cannot initialize UART\n"); } - } void serial_init(serial_t *obj, PinName tx, PinName rx) { + struct serial_s *obj_s = SERIAL_S(obj); + // Determine the UART to use (UART_1, UART_2, ...) UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj->uart != (UARTName)NC); + obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT(obj_s->uart != (UARTName)NC); - // Enable UART clock - if (obj->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); + // Enable USART clock + if (obj_s->uart == UART_1) { + __HAL_RCC_USART1_FORCE_RESET(); + __HAL_RCC_USART1_RELEASE_RESET(); __HAL_RCC_USART1_CLK_ENABLE(); - obj->index = 0; + obj_s->index = 0; } - if (obj->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); + if (obj_s->uart == UART_2) { + __HAL_RCC_USART2_FORCE_RESET(); + __HAL_RCC_USART2_RELEASE_RESET(); __HAL_RCC_USART2_CLK_ENABLE(); - obj->index = 1; + obj_s->index = 1; } - if (obj->uart == UART_3) { - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); + if (obj_s->uart == UART_3) { + __HAL_RCC_USART3_FORCE_RESET(); + __HAL_RCC_USART3_RELEASE_RESET(); __HAL_RCC_USART3_CLK_ENABLE(); - obj->index = 2; + obj_s->index = 2; } // Configure UART pins pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); + if (tx != NC) { pin_mode(tx, PullUp); } @@ -118,18 +135,22 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) } // Configure UART - obj->baudrate = 9600; - obj->databits = UART_WORDLENGTH_8B; - obj->stopbits = UART_STOPBITS_1; - obj->parity = UART_PARITY_NONE; + obj_s->baudrate = 9600; + obj_s->databits = UART_WORDLENGTH_8B; + obj_s->stopbits = UART_STOPBITS_1; + obj_s->parity = UART_PARITY_NONE; + +#if DEVICE_SERIAL_FC + obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; +#endif - obj->pin_tx = tx; - obj->pin_rx = rx; + obj_s->pin_tx = tx; + obj_s->pin_rx = rx; init_uart(obj); // For stdio management - if (obj->uart == STDIO_UART) { + if (obj_s->uart == STDIO_UART) { stdio_uart_inited = 1; memcpy(&stdio_uart, obj, sizeof(serial_t)); } @@ -137,62 +158,68 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) void serial_free(serial_t *obj) { + struct serial_s *obj_s = SERIAL_S(obj); + // Reset UART and disable clock - if (obj->uart == UART_1) { + if (obj_s->uart == UART_1) { __USART1_FORCE_RESET(); __USART1_RELEASE_RESET(); __USART1_CLK_DISABLE(); } - if (obj->uart == UART_2) { + if (obj_s->uart == UART_2) { __USART2_FORCE_RESET(); __USART2_RELEASE_RESET(); __USART2_CLK_DISABLE(); } - if (obj->uart == UART_3) { + if (obj_s->uart == UART_3) { __USART3_FORCE_RESET(); __USART3_RELEASE_RESET(); __USART3_CLK_DISABLE(); } // Configure GPIOs - pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - serial_irq_ids[obj->index] = 0; + serial_irq_ids[obj_s->index] = 0; } void serial_baud(serial_t *obj, int baudrate) { - obj->baudrate = baudrate; + struct serial_s *obj_s = SERIAL_S(obj); + + obj_s->baudrate = baudrate; init_uart(obj); } void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { + struct serial_s *obj_s = SERIAL_S(obj); + if (data_bits == 9) { - obj->databits = UART_WORDLENGTH_9B; + obj_s->databits = UART_WORDLENGTH_9B; } else { - obj->databits = UART_WORDLENGTH_8B; + obj_s->databits = UART_WORDLENGTH_8B; } switch (parity) { case ParityOdd: - case ParityForced0: - obj->parity = UART_PARITY_ODD; + obj_s->parity = UART_PARITY_ODD; break; case ParityEven: - case ParityForced1: - obj->parity = UART_PARITY_EVEN; + obj_s->parity = UART_PARITY_EVEN; break; default: // ParityNone - obj->parity = UART_PARITY_NONE; + case ParityForced0: // unsupported! + case ParityForced1: // unsupported! + obj_s->parity = UART_PARITY_NONE; break; } if (stop_bits == 2) { - obj->stopbits = UART_STOPBITS_2; + obj_s->stopbits = UART_STOPBITS_2; } else { - obj->stopbits = UART_STOPBITS_1; + obj_s->stopbits = UART_STOPBITS_1; } init_uart(obj); @@ -202,91 +229,104 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b * INTERRUPTS HANDLING ******************************************************************************/ -static void uart_irq(UARTName name, int id) +static void uart_irq(int id) { - UartHandle.Instance = (USART_TypeDef *)name; + UART_HandleTypeDef * huart = &uart_handlers[id]; + if (serial_irq_ids[id] != 0) { - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) { - irq_handler(serial_irq_ids[id], TxIrq); - __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TC); + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { + if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) { + irq_handler(serial_irq_ids[id], TxIrq); + __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); + } + } + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { + if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET) { + irq_handler(serial_irq_ids[id], RxIrq); + __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE); + } } - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) { - irq_handler(serial_irq_ids[id], RxIrq); - __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_RXNE); + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { + if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET) { + volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag + } } } } static void uart1_irq(void) { - uart_irq(UART_1, 0); + uart_irq(0); } static void uart2_irq(void) { - uart_irq(UART_2, 1); + uart_irq(1); } static void uart3_irq(void) { - uart_irq(UART_3, 2); + uart_irq(2); } void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + struct serial_s *obj_s = SERIAL_S(obj); + irq_handler = handler; - serial_irq_ids[obj->index] = id; + serial_irq_ids[obj_s->index] = id; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + struct serial_s *obj_s = SERIAL_S(obj); + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; IRQn_Type irq_n = (IRQn_Type)0; uint32_t vector = 0; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - if (obj->uart == UART_1) { + if (obj_s->uart == UART_1) { irq_n = USART1_IRQn; vector = (uint32_t)&uart1_irq; } - if (obj->uart == UART_2) { + if (obj_s->uart == UART_2) { irq_n = USART2_IRQn; vector = (uint32_t)&uart2_irq; } - if (obj->uart == UART_3) { + if (obj_s->uart == UART_3) { irq_n = USART3_IRQn; vector = (uint32_t)&uart3_irq; } if (enable) { - if (irq == RxIrq) { - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE); + __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); } else { // TxIrq - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC); + __HAL_UART_ENABLE_IT(huart, UART_IT_TC); } - NVIC_SetVector(irq_n, vector); NVIC_EnableIRQ(irq_n); } else { // disable - int all_disabled = 0; - if (irq == RxIrq) { - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE); + __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); // Check if TxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1; + if ((huart->Instance->CR1 & USART_CR1_TXEIE) == 0) { + all_disabled = 1; + } } else { // TxIrq - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC); + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); // Check if RxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1; + if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) { + all_disabled = 1; + } } - if (all_disabled) NVIC_DisableIRQ(irq_n); - + if (all_disabled) { + NVIC_DisableIRQ(irq_n); + } } } @@ -296,49 +336,55 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) int serial_getc(serial_t *obj) { - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); + struct serial_s *obj_s = SERIAL_S(obj); + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; + while (!serial_readable(obj)); - if (obj->databits == UART_WORDLENGTH_8B) { - return (int)(uart->DR & (uint8_t)0xFF); + if (obj_s->databits == UART_WORDLENGTH_8B) { + return (int)(huart->Instance->DR & (uint8_t)0xFF); } else { - return (int)(uart->DR & (uint16_t)0x1FF); + return (int)(huart->Instance->DR & (uint16_t)0x1FF); } } void serial_putc(serial_t *obj, int c) { - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); + struct serial_s *obj_s = SERIAL_S(obj); + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; + while (!serial_writable(obj)); - if (obj->databits == UART_WORDLENGTH_8B) { - uart->DR = (uint8_t)(c & (uint8_t)0xFF); + if (obj_s->databits == UART_WORDLENGTH_8B) { + huart->Instance->DR = (uint8_t)(c & (uint8_t)0xFF); } else { - uart->DR = (uint16_t)(c & (uint16_t)0x1FF); + huart->Instance->DR = (uint16_t)(c & (uint16_t)0x1FF); } } int serial_readable(serial_t *obj) { - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); + struct serial_s *obj_s = SERIAL_S(obj); + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; + // Check if data is received - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0); - return status; + return (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) ? 1 : 0; } int serial_writable(serial_t *obj) { - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); + struct serial_s *obj_s = SERIAL_S(obj); + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; + // Check if data is transmitted - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0); - return status; + return (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) ? 1 : 0; } void serial_clear(serial_t *obj) { - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TXE); - __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_RXNE); + struct serial_s *obj_s = SERIAL_S(obj); + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; + + huart->TxXferCount = 0; + huart->RxXferCount = 0; } void serial_pinout_tx(PinName tx) @@ -348,12 +394,462 @@ void serial_pinout_tx(PinName tx) void serial_break_set(serial_t *obj) { - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - HAL_LIN_SendBreak(&UartHandle); + struct serial_s *obj_s = SERIAL_S(obj); + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; + + HAL_LIN_SendBreak(huart); } void serial_break_clear(serial_t *obj) { + (void)obj; +} + +#if DEVICE_SERIAL_ASYNCH + +/****************************************************************************** + * LOCAL HELPER FUNCTIONS + ******************************************************************************/ + +/** + * Configure the TX buffer for an asynchronous write serial transaction + * + * @param obj The serial object. + * @param tx The buffer for sending. + * @param tx_length The number of words to transmit. + */ +static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t width) +{ + (void)width; + + // Exit if a transmit is already on-going + if (serial_tx_active(obj)) { + return; + } + + obj->tx_buff.buffer = tx; + obj->tx_buff.length = tx_length; + obj->tx_buff.pos = 0; } + +/** + * Configure the RX buffer for an asynchronous write serial transaction + * + * @param obj The serial object. + * @param tx The buffer for sending. + * @param tx_length The number of words to transmit. + */ +static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t width) +{ + (void)width; + + // Exit if a reception is already on-going + if (serial_rx_active(obj)) { + return; + } + + obj->rx_buff.buffer = rx; + obj->rx_buff.length = rx_length; + obj->rx_buff.pos = 0; +} + +/** + * Configure events + * + * @param obj The serial object + * @param event The logical OR of the events to configure + * @param enable Set to non-zero to enable events, or zero to disable them + */ +static void serial_enable_event(serial_t *obj, int event, uint8_t enable) +{ + struct serial_s *obj_s = SERIAL_S(obj); + + // Shouldn't have to enable interrupt here, just need to keep track of the requested events. + if (enable) { + obj_s->events |= event; + } else { + obj_s->events &= ~event; + } +} + + +/** +* Get index of serial object TX IRQ, relating it to the physical peripheral. +* +* @param obj pointer to serial object +* @return internal NVIC TX IRQ index of U(S)ART peripheral +*/ +static IRQn_Type serial_get_irq_n(serial_t *obj) +{ + struct serial_s *obj_s = SERIAL_S(obj); + IRQn_Type irq_n; + + switch (obj_s->index) { + case 0: + irq_n = USART1_IRQn; + break; + + case 1: + irq_n = USART2_IRQn; + break; + + case 2: + irq_n = USART3_IRQn; + break; + + default: + irq_n = (IRQn_Type)0; + } + + return irq_n; +} + +/****************************************************************************** + * MBED API FUNCTIONS + ******************************************************************************/ + +/** + * Begin asynchronous TX transfer. The used buffer is specified in the serial + * object, tx_buff + * + * @param obj The serial object + * @param tx The buffer for sending + * @param tx_length The number of words to transmit + * @param tx_width The bit width of buffer word + * @param handler The serial handler + * @param event The logical OR of events to be registered + * @param hint A suggestion for how to use DMA with this transfer + * @return Returns number of data transfered, or 0 otherwise + */ +int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + // TODO: DMA usage is currently ignored + (void) hint; + + // Check buffer is ok + MBED_ASSERT(tx != (void*)0); + MBED_ASSERT(tx_width == 8); // support only 8b width + + struct serial_s *obj_s = SERIAL_S(obj); + UART_HandleTypeDef * huart = &uart_handlers[obj_s->index]; + + if (tx_length == 0) { + return 0; + } + + // Set up buffer + serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); + + // Set up events + serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events + serial_enable_event(obj, event, 1); // Set only the wanted events + + // Enable interrupt + IRQn_Type irq_n = serial_get_irq_n(obj); + NVIC_ClearPendingIRQ(irq_n); + NVIC_DisableIRQ(irq_n); + NVIC_SetPriority(irq_n, 1); + NVIC_SetVector(irq_n, (uint32_t)handler); + NVIC_EnableIRQ(irq_n); + + // the following function will enable UART_IT_TXE and error interrupts + if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) { + return 0; + } + + return tx_length; +} + +/** + * Begin asynchronous RX transfer (enable interrupt for data collecting) + * The used buffer is specified in the serial object, rx_buff + * + * @param obj The serial object + * @param rx The buffer for sending + * @param rx_length The number of words to transmit + * @param rx_width The bit width of buffer word + * @param handler The serial handler + * @param event The logical OR of events to be registered + * @param handler The serial handler + * @param char_match A character in range 0-254 to be matched + * @param hint A suggestion for how to use DMA with this transfer + */ +void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) +{ + // TODO: DMA usage is currently ignored + (void) hint; + + /* Sanity check arguments */ + MBED_ASSERT(obj); + MBED_ASSERT(rx != (void*)0); + MBED_ASSERT(rx_width == 8); // support only 8b width + + struct serial_s *obj_s = SERIAL_S(obj); + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; + + serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0); + serial_enable_event(obj, event, 1); + + // set CharMatch + obj->char_match = char_match; + + serial_rx_buffer_set(obj, rx, rx_length, rx_width); + + IRQn_Type irq_n = serial_get_irq_n(obj); + NVIC_ClearPendingIRQ(irq_n); + NVIC_DisableIRQ(irq_n); + NVIC_SetPriority(irq_n, 0); + NVIC_SetVector(irq_n, (uint32_t)handler); + NVIC_EnableIRQ(irq_n); + + // following HAL function will enable the RXNE interrupt + error interrupts + HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length); +} + +/** + * Attempts to determine if the serial peripheral is already in use for TX + * + * @param obj The serial object + * @return Non-zero if the TX transaction is ongoing, 0 otherwise + */ +uint8_t serial_tx_active(serial_t *obj) +{ + MBED_ASSERT(obj); + + struct serial_s *obj_s = SERIAL_S(obj); + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; + + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0); +} + +/** + * Attempts to determine if the serial peripheral is already in use for RX + * + * @param obj The serial object + * @return Non-zero if the RX transaction is ongoing, 0 otherwise + */ +uint8_t serial_rx_active(serial_t *obj) +{ + MBED_ASSERT(obj); + + struct serial_s *obj_s = SERIAL_S(obj); + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; + + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0); +} + +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { + __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); + } +} + +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { + volatile uint32_t tmpval = huart->Instance->DR; // Clear PE flag + } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { + volatile uint32_t tmpval = huart->Instance->DR; // Clear FE flag + } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) { + volatile uint32_t tmpval = huart->Instance->DR; // Clear NE flag + } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { + volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag + } +} + +/** + * The asynchronous TX and RX handler. + * + * @param obj The serial object + * @return Returns event flags if a TX/RX transfer termination condition was met or 0 otherwise + */ +int serial_irq_handler_asynch(serial_t *obj) +{ + struct serial_s *obj_s = SERIAL_S(obj); + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; + + volatile int return_event = 0; + uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer); + uint8_t i = 0; + + // TX PART: + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { + if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) { + // Return event SERIAL_EVENT_TX_COMPLETE if requested + if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) { + return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events); + } + } + } + + // Handle error events + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { + if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { + return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events); + } +} + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { + if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { + return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events); + } + } + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { + if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { + return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events); + } + } + + HAL_UART_IRQHandler(huart); + + // Abort if an error occurs + if (return_event & SERIAL_EVENT_RX_PARITY_ERROR || + return_event & SERIAL_EVENT_RX_FRAMING_ERROR || + return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) { + return return_event; + } + + //RX PART + if (huart->RxXferSize != 0) { + obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount; + } + if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) { + return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events); + } + + // Check if char_match is present + if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) { + if (buf != NULL) { + for (i = 0; i < obj->rx_buff.pos; i++) { + if (buf[i] == obj->char_match) { + obj->rx_buff.pos = i; + return_event |= (SERIAL_EVENT_RX_CHARACTER_MATCH & obj_s->events); + serial_rx_abort_asynch(obj); + break; + } + } + } + } + + return return_event; +} + +/** + * Abort the ongoing TX transaction. It disables the enabled interupt for TX and + * flush TX hardware buffer if TX FIFO is used + * + * @param obj The serial object + */ +void serial_tx_abort_asynch(serial_t *obj) +{ + struct serial_s *obj_s = SERIAL_S(obj); + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; + + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); + __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + + // clear flags + __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); + + // reset states + huart->TxXferCount = 0; + // update handle state + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { + huart->State = HAL_UART_STATE_BUSY_RX; + } else { + huart->State = HAL_UART_STATE_READY; + } +} + +/** + * Abort the ongoing RX transaction It disables the enabled interrupt for RX and + * flush RX hardware buffer if RX FIFO is used + * + * @param obj The serial object + */ +void serial_rx_abort_asynch(serial_t *obj) +{ + struct serial_s *obj_s = SERIAL_S(obj); + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; + + // disable interrupts + __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + // clear flags + __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE); + volatile uint32_t tmpval = huart->Instance->DR; // Clear errors flag + + // reset states + huart->RxXferCount = 0; + // update handle state + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { + huart->State = HAL_UART_STATE_BUSY_TX; + } else { + huart->State = HAL_UART_STATE_READY; + } +} + +#endif + +#if DEVICE_SERIAL_FC + +/** + * Set HW Control Flow + * @param obj The serial object + * @param type The Control Flow type (FlowControlNone, FlowControlRTS, FlowControlCTS, FlowControlRTSCTS) + * @param rxflow Pin for the rxflow + * @param txflow Pin for the txflow + */ +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + struct serial_s *obj_s = SERIAL_S(obj); + + // Determine the UART to use (UART_1, UART_2, ...) + UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); + UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); + + // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object + obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts); + MBED_ASSERT(obj_s->uart != (UARTName)NC); + + if(type == FlowControlNone) { + // Disable hardware flow control + obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; + } + if (type == FlowControlRTS) { + // Enable RTS + MBED_ASSERT(uart_rts != (UARTName)NC); + obj_s->hw_flow_ctl = UART_HWCONTROL_RTS; + obj_s->pin_rts = rxflow; + // Enable the pin for RTS function + pinmap_pinout(rxflow, PinMap_UART_RTS); + } + if (type == FlowControlCTS) { + // Enable CTS + MBED_ASSERT(uart_cts != (UARTName)NC); + obj_s->hw_flow_ctl = UART_HWCONTROL_CTS; + obj_s->pin_cts = txflow; + // Enable the pin for CTS function + pinmap_pinout(txflow, PinMap_UART_CTS); + } + if (type == FlowControlRTSCTS) { + // Enable CTS & RTS + MBED_ASSERT(uart_rts != (UARTName)NC); + MBED_ASSERT(uart_cts != (UARTName)NC); + obj_s->hw_flow_ctl = UART_HWCONTROL_RTS_CTS; + obj_s->pin_rts = rxflow; + obj_s->pin_cts = txflow; + // Enable the pin for CTS function + pinmap_pinout(txflow, PinMap_UART_CTS); + // Enable the pin for RTS function + pinmap_pinout(rxflow, PinMap_UART_RTS); + } + + init_uart(obj); +} + +#endif #endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device.h deleted file mode 100644 index 019149b16b8..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device.h +++ /dev/null @@ -1,48 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H -#define DEVICE_RTC_LSI 1 - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralNames.h index 1b2dd8f02d3..ff95fc7be8f 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralNames.h @@ -62,7 +62,8 @@ typedef enum { typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE } SPIName; typedef enum { @@ -79,7 +80,8 @@ typedef enum { PWM_8 = (int)TIM8_BASE, PWM_15 = (int)TIM15_BASE, PWM_16 = (int)TIM16_BASE, - PWM_17 = (int)TIM17_BASE + PWM_17 = (int)TIM17_BASE, + PWM_20 = (int)TIM20_BASE } PWMName; typedef enum { diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PortNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PortNames.h index 026326171c1..0d25c875132 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PortNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PortNames.h @@ -40,7 +40,9 @@ typedef enum { PortC = 2, PortD = 3, PortE = 4, - PortF = 5 + PortF = 5, + PortG = 6, + PortH = 7 } PortName; #ifdef __cplusplus diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PeripheralNames.h similarity index 60% rename from hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device.h rename to hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PeripheralNames.h index bdad16c6f18..6b86154e45a 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PeripheralNames.h @@ -1,5 +1,3 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. /* mbed Microcontroller Library ******************************************************************************* * Copyright (c) 2015, STMicroelectronics @@ -29,26 +27,71 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H +#include "cmsis.h" +#ifdef __cplusplus +extern "C" { +#endif -#include "objects.h" +typedef enum { + ADC_1 = (int)ADC1_BASE, + ADC_2 = (int)ADC2_BASE, + ADC_3 = (int)ADC3_BASE, + ADC_4 = (int)ADC4_BASE +} ADCName; + +typedef enum { + DAC_1 = (int)DAC_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE +} UARTName; + +#define STDIO_UART_TX SERIAL_TX +#define STDIO_UART_RX SERIAL_RX +#define STDIO_UART UART_3 + + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE + +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_15 = (int)TIM15_BASE, + PWM_16 = (int)TIM16_BASE, + PWM_17 = (int)TIM17_BASE, + PWM_20 = (int)TIM20_BASE +} PWMName; + +typedef enum { + CAN_1 = (int)CAN_BASE +} CANName; + +#ifdef __cplusplus +} +#endif #endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PeripheralPins.c new file mode 100644 index 00000000000..4b3c4c21ad2 --- /dev/null +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PeripheralPins.c @@ -0,0 +1,390 @@ +/* mbed Microcontroller Library + '******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 //- ARDUINO A0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 + {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 + {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + //{PB_0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 //(pin used by LED1) + {PB_1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 + {PB_2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + {PB_11, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + //{PB_11, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 + {PB_12, ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC4_IN3 + {PB_13, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 + //{PB_14, ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC4_IN4 //(pin used by LED3) + {PB_15, ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC4_IN5 + //{PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PC_0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 //- ARDUINO A1 + //{PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PC_1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 //- ARDUINO A3 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + //{PC_2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8*/ + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 //- ARDUINO A2 + //{PC_3, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9*/ + {PC_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 //- ARDUINO A4 + {PC_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 //- ARDUINO A5 + //{PD_8, ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC4_IN12 //(pin used by UART console) + //{PD_9, ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC4_IN13 //(pin used by UART console) + {PD_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 + //{PD_10, ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC4_IN7*/ + {PD_11, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 + //{PD_11, ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC4_IN8 + {PD_12, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9 + //{PD_12, ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC4_IN9 + //{PD_13, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 + {PD_13, ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC4_IN10 + {PD_14, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11 + //{PD_14, ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC4_IN11 + {PE_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13 + //{PE_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 + {PE_8, ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC4_IN6 + {PE_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 + {PE_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14 + {PE_11, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15 + {PE_12, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC3_IN16 + {PE_13, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 + {PE_14, ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC4_IN1 + {PE_15, ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC4_IN2 + //{PF_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PF_2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {PF_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + //{PA_10, I2C_2 , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, //(pin used for usb) + //{PA_14, I2C_1 , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},// (pin used for stmc) + // {PB_5, I2C_3 , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C3)},// I2C3 not useable with usb , no SCL available. + //{PB_7, I2C_1 , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},//(pin used by LED2) + {PB_9, I2C_1 , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, //- ARDUINO D14 + //{PC_9, I2C_3 , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C3)}, + //{PF_0, I2C_2 , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},// PF_0 not useable on board , need resistors changes I2C2 not useable + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + //{PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C3)}, //(pin used for usb) + //{PA_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, //(pin used for usb) + // {PA_15, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + // {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, //- ARDUINO D15 + //{PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},// I2C2 not useable due to PF_0 not useable + //{PF_6, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},// I2C2 not useable due to PF_0 not useable + {NC, NC, 0} +}; + +//*** PWM *** + +const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 1)}, // TIM15_CH1N + //{PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + //{PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 0)}, // TIM15_CH1 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 2, 0)}, // TIM15_CH2 + //{PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + //{PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + //{PA_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + //{PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + //{PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + //{PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 0)}, // TIM1_CH1 //(pin used for usb) + //{PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 0)}, // TIM1_CH2 //(pin used for usb) + //{PA_9, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 3, 0)}, // TIM2_CH3 //(pin used for usb) + //{PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 0)}, // TIM1_CH3 //(pin used for usb) + //{PA_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 4, 0)}, // TIM2_CH4 //(pin used for usb) + //{PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N //(pin used for usb) + //{PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 4, 0)}, // TIM1_CH4 //(pin used for usb) + //{PA_11, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 1, 0)}, // TIM4_CH1 //(pin used for usb) + //{PA_12, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 //(pin used for usb) + //{PA_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N //(pin used for usb) + //{PA_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 2, 0)}, // TIM4_CH2 //(pin used for usb) + //{PA_13, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + //{PA_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 3, 0)}, // TIM4_CH3 //(pin used SWD signals connected to ST-LINK/V2-1) + {PA_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 2, 0)}, // TIM8_CH2 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 + //{PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + //{PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + //{PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N + //{PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + //{PB_3, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + {PB_4, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + //{PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + //{PB_4, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + {PB_5, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + //{PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + //{PB_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + //{PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + //{PB_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 1, 0)}, // TIM8_CH1 + //{PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + //{PB_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + //{PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + //{PB_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 2, 0)}, // TIM8_CH2 + {PB_9, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + //{PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + //{PB_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 3, 0)}, // TIM8_CH3 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 1, 0)}, // TIM15_CH1 + //{PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + //{PB_15, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 1)}, // TIM15_CH1N + {PB_15, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 2, 0)}, // TIM15_CH2 + //{PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 3, 1)}, // TIM1_CH3N + {PC_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PC_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PC_2, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PC_3, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + //{PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 0)}, // TIM8_CH1 + //{PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + //{PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 0)}, // TIM8_CH3 + //{PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 4, 0)}, // TIM8_CH4 + {PC_10, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + {PC_11, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + {PC_12, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 1)}, // TIM8_CH3N + //{PC_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 1, 1)}, // TIM1_CH1N //(pin used USER BUTTON) + {PD_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 4, 0)}, // TIM8_CH4 + {PD_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 + {PD_4, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 + {PD_6, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 + {PD_7, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - ARDUINO D9 + {PE_0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM16, 1, 0)}, // TIM16_CH1 + // {PE_1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM17, 1, 0)}, // TIM17_CH1 + {PE_1, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 4, 0)}, // TIM20_CH4 + {PE_2, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 1, 0)}, // TIM20_CH1 + //{PE_2, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PE_3, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 2, 0)}, // TIM20_CH2 + //{PE_3, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + //{PE_4, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 1, 1)}, // TIM20_CH1N + {PE_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + //{PE_5, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 2, 1)}, // TIM20_CH2N + {PE_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PE_6, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 3, 1)}, // TIM20_CH3N + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + //{PF_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N //PF_0 not useable , need resitor changes on board + {PF_2, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 3, 0)}, // TIM20_CH3 + {PF_3, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 4, 0)}, // TIM20_CH4 + {PF_4, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM20, 1, 1)}, // TIM20_CH1N + {PF_5, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 2, 1)}, // TIM20_CH2N + {PF_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PF_9, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM15, 1, 0)}, // TIM15_CH1 + {PF_10, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM15, 2, 0)}, // TIM15_CH2 + {PF_12, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 1, 0)}, // TIM20_CH1 + {PF_13, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 2, 0)}, // TIM20_CH2 + {PF_14, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 3, 0)}, // TIM20_CH3 + {PF_15, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 4, 0)}, // TIM20_CH4 + {PG_0, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 1, 1)}, // TIM20_CH1N + {PG_1, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 2, 1)}, // TIM20_CH2N + {PG_2, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 3, 1)}, // TIM20_CH3N + {PH_0, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 1, 0)}, // TIM20_CH1 + {PH_1, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM20, 2, 0)}, // TIM20_CH2 + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + //{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, //(pin used for usb) + {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, + //{PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART5)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, //(pin used by uart console) + {PE_0, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + //{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, //(pin used for usb) + {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + //{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, //(pin used by LED2) + {PB_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_5, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, + //{PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},// (pin used by uart console) + {PE_1, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PE_15, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PF_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + //{PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, //(pin used by LED3) + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + //{PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, //(pin used for usb) + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + // {PA_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, //(pin used SWD signals connected to ST-LINK/V2-1) + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, //- ARDUINO D11 + //{PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, //(pin used for usb) + //{PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + //{PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},//SPI2 not useable with usb (no MISO pin) + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, //- ARDUINO D12 + //{PA_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, //(pin used for usb) + //{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + //{PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, //(pin used by LED3) + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},//- ARDUINO D13 + //{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + //{PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP,GPIO_AF5_SPI2)},//SPI2 not useable with usb + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + //{PF_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, //SPI2 not useable with usb (no MISO pin) + //{PF_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, //SPI2 not useable with usb (no MISO pin) + //{PF_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, //SPI2 not useable with usb (no MISO pin) + + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + // {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + //{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},//SPI2 not useable with usb (no MISO pin) + //{PD_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)},//SPI2 not useable with usb (no MISO pin) + {PE_3, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + //{PF_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},//SPI2 not useable with usb (no MISO pin) + + {NC, NC, 0} +}; + +//*** CAN *** + +const PinMap PinMap_CAN_RD[] = { + //{PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_CAN)}, //(pin used for usb) + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_CAN)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_CAN)}, + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_TD[] = { + //{PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_CAN)}, //(pin used for usb) + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_CAN)}, + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_CAN)}, + {NC, NC, 0} +}; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PinNames.h new file mode 100644 index 00000000000..80d1ced3097 --- /dev/null +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PinNames.h @@ -0,0 +1,255 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_MODE_INPUT (0) +#define STM_MODE_OUTPUT_PP (1) +#define STM_MODE_OUTPUT_OD (2) +#define STM_MODE_AF_PP (3) +#define STM_MODE_AF_OD (4) +#define STM_MODE_ANALOG (5) +#define STM_MODE_IT_RISING (6) +#define STM_MODE_IT_FALLING (7) +#define STM_MODE_IT_RISING_FALLING (8) +#define STM_MODE_EVT_RISING (9) +#define STM_MODE_EVT_FALLING (10) +#define STM_MODE_EVT_RISING_FALLING (11) +#define STM_MODE_IT_EVT_RESET (12) + +// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H) +// Low nibble = pin number +#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF) +#define STM_PIN(X) ((uint32_t)(X) & 0xF) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_5 = 0x55, + PF_6 = 0x56, + PF_7 = 0x57, + PF_8 = 0x58, + PF_9 = 0x59, + PF_10 = 0x5A, + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_15 = 0x5F, + + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + + PH_0 = 0x70, + PH_1 = 0x71, + PH_2 = 0x72, + + // Arduino connector namings + A0 = PA_3, + A1 = PC_0, + A2 = PC_3, + A3 = PC_1, + A4 = PC_4, + A5 = PC_5, + D0 = PG_9, + D1 = PG_14, + D2 = PF_15, + D3 = PE_13, + D4 = PF_14, + D5 = PE_11, + D6 = PE_9, + D7 = PF_13, + D8 = PF_12, + D9 = PD_15, + D10 = PD_14, + D11 = PA_7, + D12 = PA_6, + D13 = PA_5, + D14 = PB_9, + D15 = PB_8, + + // Generic signals namings + LED1 = PB_0, + LED2 = PB_7, + LED3 = PB_14, + LED4 = LED1, + USER_BUTTON = PC_13, + SERIAL_TX = PD_8, // Virtual Com Port + SERIAL_RX = PD_9, // Virtual Com Port + USBTX = SERIAL_TX, // Virtual Com Port + USBRX = SERIAL_RX, // Virtual Com Port + I2C_SCL = D15, + I2C_SDA = D14, + SPI_MOSI = D11, + SPI_MISO = D12, + SPI_SCK = D13, + SPI_CS = D10, + PWM_OUT = D9, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PortNames.h similarity index 83% rename from hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device.h rename to hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PortNames.h index 38e5143ddb2..af38196b848 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PortNames.h @@ -1,5 +1,3 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. /* mbed Microcontroller Library ******************************************************************************* * Copyright (c) 2015, STMicroelectronics @@ -29,25 +27,25 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H +#ifdef __cplusplus +extern "C" { +#endif - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortE = 4, + PortF = 5, + PortG = 6, + PortH = 7 +} PortName; + +#ifdef __cplusplus +} +#endif #endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device.h similarity index 100% rename from hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device.h rename to hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device.h diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h similarity index 57% rename from hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device.h rename to hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h index 38e5143ddb2..81ebc1d3710 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h @@ -1,5 +1,3 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. /* mbed Microcontroller Library ******************************************************************************* * Copyright (c) 2015, STMicroelectronics @@ -29,25 +27,94 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#ifdef __cplusplus +extern "C" { +#endif -#include "objects.h" +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; + uint32_t channel; +}; + +struct dac_s { + DACName dac; + PinName pin; + uint32_t channel; +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +}; + +struct spi_s { + SPIName spi; + uint32_t bits; + uint32_t cpol; + uint32_t cpha; + uint32_t mode; + uint32_t nss; + uint32_t br_presc; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +}; + +struct i2c_s { + I2CName i2c; + uint32_t slave; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t prescaler; + uint32_t period; + uint32_t pulse; + uint32_t channel; + uint32_t inverted; +}; + +struct can_s { + CANName can; + int index; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif #endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device.h deleted file mode 100644 index bdad16c6f18..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device.h +++ /dev/null @@ -1,54 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/device.h similarity index 99% rename from hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device.h rename to hal/targets/hal/TARGET_STM/TARGET_STM32F3/device.h index bbb4b7513e6..b6131682750 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/device.h @@ -32,22 +32,9 @@ #ifndef MBED_DEVICE_H #define MBED_DEVICE_H - - - - - - - - - //======================================= - #define DEVICE_ID_LENGTH 24 - - - #include "objects.h" #endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/pinmap.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/pinmap.c index 3532124c4c0..202891f1151 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/pinmap.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/pinmap.c @@ -71,16 +71,50 @@ uint32_t Set_GPIO_Clock(uint32_t port_idx) gpio_add = GPIOD_BASE; __GPIOD_CLK_ENABLE(); break; -#if defined(GPIOE_BASE) +#if defined GPIOE_BASE case PortE: gpio_add = GPIOE_BASE; __GPIOE_CLK_ENABLE(); break; #endif +#if defined GPIOF_BASE case PortF: gpio_add = GPIOF_BASE; __GPIOF_CLK_ENABLE(); break; +#endif +#if defined GPIOG_BASE + case PortG: + gpio_add = GPIOG_BASE; + __GPIOG_CLK_ENABLE(); + break; +#endif +#if defined GPIOH_BASE + case PortH: + gpio_add = GPIOH_BASE; + __GPIOH_CLK_ENABLE(); + break; +#endif +#if defined GPIOI_BASE + case PortI: + gpio_add = GPIOI_BASE; + __GPIOI_CLK_ENABLE(); + break; +#endif +#if defined GPIOJ_BASE + case PortJ: + gpio_add = GPIOJ_BASE; + __GPIOJ_CLK_ENABLE(); + break; +#endif +#if defined GPIOK_BASE + case PortK: + gpio_add = GPIOK_BASE; + __GPIOK_CLK_ENABLE(); + break; +#endif + + default: error("Pinmap error: wrong port number."); break; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/pwmout_api.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/pwmout_api.c index abd28ca2b0c..2f3c8a925b3 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/pwmout_api.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/pwmout_api.c @@ -50,18 +50,60 @@ void pwmout_init(pwmout_t* obj, PinName pin) obj->channel = STM_PIN_CHANNEL(function); obj->inverted = STM_PIN_INVERTED(function); - // Enable TIM clock - if (obj->pwm == PWM_1) __TIM1_CLK_ENABLE(); - if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE(); -#if defined(TIM3) - if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE(); -#endif -#if defined(TIM8) - if (obj->pwm == PWM_8) __TIM8_CLK_ENABLE(); -#endif - if (obj->pwm == PWM_15) __TIM15_CLK_ENABLE(); - if (obj->pwm == PWM_16) __TIM16_CLK_ENABLE(); - if (obj->pwm == PWM_17) __TIM17_CLK_ENABLE(); +#if defined(TIM1_BASE) + if (obj->pwm == PWM_1) __HAL_RCC_TIM1_CLK_ENABLE(); +#endif +#if defined(TIM2_BASE) + if (obj->pwm == PWM_2) __HAL_RCC_TIM2_CLK_ENABLE(); +#endif +#if defined(TIM3_BASE) + if (obj->pwm == PWM_3) __HAL_RCC_TIM3_CLK_ENABLE(); +#endif +#if defined(TIM4_BASE) + if (obj->pwm == PWM_4) __HAL_RCC_TIM4_CLK_ENABLE(); +#endif +#if defined(TIM5_BASE) + if (obj->pwm == PWM_5) __HAL_RCC_TIM5_CLK_ENABLE(); +#endif +#if defined(TIM8_BASE) + if (obj->pwm == PWM_8) __HAL_RCC_TIM8_CLK_ENABLE(); +#endif +#if defined(TIM9_BASE) + if (obj->pwm == PWM_9) __HAL_RCC_TIM9_CLK_ENABLE(); +#endif +#if defined(TIM10_BASE) + if (obj->pwm == PWM_10) __HAL_RCC_TIM10_CLK_ENABLE(); +#endif +#if defined(TIM11_BASE) + if (obj->pwm == PWM_11) __HAL_RCC_TIM11_CLK_ENABLE(); +#endif +#if defined(TIM12_BASE) + if (obj->pwm == PWM_12) __HAL_RCC_TIM12_CLK_ENABLE(); +#endif +#if defined(TIM13_BASE) + if (obj->pwm == PWM_13) __HAL_RCC_TIM13_CLK_ENABLE(); +#endif +#if defined(TIM14_BASE) + if (obj->pwm == PWM_14) __HAL_RCC_TIM14_CLK_ENABLE(); +#endif +#if defined(TIM15_BASE) + if (obj->pwm == PWM_15) __HAL_RCC_TIM15_CLK_ENABLE(); +#endif +#if defined(TIM16_BASE) + if (obj->pwm == PWM_16) __HAL_RCC_TIM16_CLK_ENABLE(); +#endif +#if defined(TIM17_BASE) + if (obj->pwm == PWM_17) __HAL_RCC_TIM17_CLK_ENABLE(); +#endif +#if defined(TIM18_BASE) + if (obj->pwm == PWM_18) __HAL_RCC_TIM18_CLK_ENABLE(); +#endif +#if defined(TIM19_BASE) + if (obj->pwm == PWM_19) __HAL_RCC_TIM19_CLK_ENABLE(); +#endif +#if defined(TIM20_BASE) + if (obj->pwm == PWM_20) __HAL_RCC_TIM20_CLK_ENABLE(); +#endif // Configure GPIO pinmap_pinout(pin, PinMap_PWM); diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c index d161679292e..674b0936455 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c @@ -96,6 +96,12 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel } #endif +#if defined(SPI4_BASE) + if (obj->spi == SPI_3) { + __SPI4_CLK_ENABLE(); + } +#endif + // Configure the SPI pins pinmap_pinout(mosi, PinMap_SPI_MOSI); pinmap_pinout(miso, PinMap_SPI_MISO); @@ -152,6 +158,14 @@ void spi_free(spi_t *obj) } #endif +#if defined(SPI4_BASE) + if (obj->spi == SPI_4) { + __SPI4_FORCE_RESET(); + __SPI4_RELEASE_RESET(); + __SPI4_CLK_DISABLE(); + } +#endif + // Configure GPIOs pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); @@ -223,6 +237,9 @@ void spi_frequency(spi_t *obj, int hz) #endif #if defined SPI3_BASE case SPI_3: +#endif +#if defined SPI4_BASE + case SPI_4: #endif /* SPI_2 and SPI_3. Source CLK is PCKL1 */ spi_hz = HAL_RCC_GetPCLK1Freq(); diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PinNames.h index 7905be583d4..bd77a3968c8 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PinNames.h @@ -37,13 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -222,6 +222,10 @@ typedef enum { PI_14 = 0x8E, PI_15 = 0x8F, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, // Arduino connector namings A0 = PA_0, diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PeripheralPins.c index 20a9d9d68b8..8ba96dec158 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PeripheralPins.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PeripheralPins.c @@ -55,6 +55,9 @@ const PinMap PinMap_ADC[] = { {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT) + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP) {NC, NC, 0} }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PinNames.h index 2cede5bd9b4..5162e53409f 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PinNames.h @@ -37,13 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -156,6 +156,11 @@ typedef enum { PH_0 = 0x70, PH_1 = 0x71, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + // Arduino connector namings A0 = PA_1, A1 = PA_2, @@ -185,6 +190,7 @@ typedef enum { LED2 = LED1, LED3 = PD_11, LED4 = PD_12, + LED_RED = LED1, USER_BUTTON = PD_13, SERIAL_TX = PC_10, SERIAL_RX = PC_11, diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/device.h deleted file mode 100644 index 766dbb9ccc1..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/device.h +++ /dev/null @@ -1,55 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - -#define LED_RED LED1 - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PeripheralPins.c index e8f335d2b6b..ed0dff5c245 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PeripheralPins.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PeripheralPins.c @@ -55,6 +55,9 @@ const PinMap PinMap_ADC[] = { {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT) + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP) {NC, NC, 0} }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PinNames.h index 8e0affe2226..bb2956a0a32 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PinNames.h @@ -37,13 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -139,11 +139,17 @@ typedef enum { PH_0 = 0x70, PH_1 = 0x71, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + // Generic signals namings LED1 = PD_12, LED2 = PD_13, LED3 = PD_14, LED4 = PD_15, + LED_RED = LED1, USER_BUTTON = PA_0, SERIAL_TX = PA_2, SERIAL_RX = PA_3, diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/device.h deleted file mode 100644 index ada82d8c640..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/device.h +++ /dev/null @@ -1,54 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - -#define LED_RED LED1 - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PeripheralPins.c index b02bd26ee49..55f36d5fb18 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PeripheralPins.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PeripheralPins.c @@ -55,6 +55,9 @@ const PinMap PinMap_ADC[] = { {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 {NC, NC, 0} }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PinNames.h index fd47fd86c8c..1fa7322b782 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PinNames.h @@ -37,13 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) -#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) -#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) -#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -222,6 +222,11 @@ typedef enum { PI_14 = 0x8E, PI_15 = 0x8F, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + // Generic signals namings LED1 = PD_13, LED2 = PD_12, @@ -229,6 +234,7 @@ typedef enum { LED4 = PD_12, LED5 = PD_14, LED6 = PD_15, + LED_RED = LED1, USER_BUTTON = PA_0, SERIAL_TX = PA_2, /* USART2 */ SERIAL_RX = PA_3, diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/device.h deleted file mode 100644 index ada82d8c640..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/device.h +++ /dev/null @@ -1,54 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - -#define LED_RED LED1 - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralPins.c index 2c0379c0992..a1c42f55602 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralPins.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralPins.c @@ -63,6 +63,9 @@ const PinMap PinMap_ADC[] = { {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 {PF_10,ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT) + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP) {NC, NC, 0} }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h index 439ff3f243c..e790e62c293 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h @@ -37,21 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\ - ((PUPD & 0x07) << 4) |\ - ((AFNUM & 0x0F) << 7))) - -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\ - ((PUPD & 0x07) << 4) |\ - ((AFNUM & 0x0F) << 7) |\ - ((CHANNEL & 0x0F) << 11) |\ - ((INVERTED & 0x01) << 15))) - -#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) -#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) -#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -162,7 +154,6 @@ typedef enum { PE_14 = 0x4E, PE_15 = 0x4F, - PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, @@ -180,7 +171,6 @@ typedef enum { PF_14 = 0x5E, PF_15 = 0x5F, - PG_0 = 0x60, PG_1 = 0x61, PG_2 = 0x62, @@ -198,15 +188,20 @@ typedef enum { PG_14 = 0x6E, PG_15 = 0x6F, - PH_0 = 0x70, PH_1 = 0x71, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + // Generic signals namings LED1 = PG_13, // Corresponds to LD3 on MB1075B LED2 = PG_14, // Corresponds to LD4 on MB1075B LED3 = PG_13, LED4 = PG_14, + LED_RED = LED2, USER_BUTTON = PA_0, SERIAL_TX = PA_9, SERIAL_RX = PA_10, diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/device.h deleted file mode 100644 index ca87126633e..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/device.h +++ /dev/null @@ -1,55 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - -#define LED_RED LED2 - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PeripheralPins.c index e57b41dd59f..2be79017397 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PeripheralPins.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PeripheralPins.c @@ -63,6 +63,9 @@ const PinMap PinMap_ADC[] = { {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 {PF_10,ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT) + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP) {NC, NC, 0} }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PinNames.h index 30967992f7b..c238cc38f6d 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PinNames.h @@ -37,13 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -154,7 +154,6 @@ typedef enum { PE_14 = 0x4E, PE_15 = 0x4F, - PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, @@ -172,7 +171,6 @@ typedef enum { PF_14 = 0x5E, PF_15 = 0x5F, - PG_0 = 0x60, PG_1 = 0x61, PG_2 = 0x62, @@ -190,7 +188,6 @@ typedef enum { PG_14 = 0x6E, PG_15 = 0x6F, - PH_0 = 0x70, PH_1 = 0x71, PH_2 = 0x72, @@ -208,7 +205,6 @@ typedef enum { PH_14 = 0x7E, PH_15 = 0x7F, - PI_0 = 0x80, PI_1 = 0x81, PI_2 = 0x82, @@ -226,7 +222,6 @@ typedef enum { PI_14 = 0x8E, PI_15 = 0x8F, - PJ_0 = 0x90, PJ_1 = 0x91, PJ_2 = 0x92, @@ -244,6 +239,10 @@ typedef enum { PK_6 = 0xA6, PK_7 = 0xA7, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, // Arduino connector namings A0 = PB_1, @@ -276,6 +275,7 @@ typedef enum { LED3 = PD_5, LED4 = PK_3, LED7 = PD_3, + LED_RED = LED1, USER_BUTTON = PA_0, SERIAL_TX = PB_10, SERIAL_RX = PB_11, diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/device.h deleted file mode 100644 index 1477050375c..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/device.h +++ /dev/null @@ -1,55 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - -#define LED_RED LED1 - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralPins.c index f1f50db2bda..7a3856479ea 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralPins.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralPins.c @@ -55,6 +55,9 @@ const PinMap PinMap_ADC[] = { {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT) + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP) {NC, NC, 0} }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PinNames.h index a36638356c5..fa4ab57468a 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PinNames.h @@ -37,13 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -124,6 +124,11 @@ typedef enum { PH_0 = 0x70, PH_1 = 0x71, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + // Not connected NC = (int)0xFFFFFFFF, diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/device.h deleted file mode 100644 index bbb4b7513e6..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/device.h +++ /dev/null @@ -1,53 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralPins.c index 5af48997840..5f05986b29d 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralPins.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralPins.c @@ -55,6 +55,9 @@ const PinMap PinMap_ADC[] = { {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT) + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP) {NC, NC, 0} }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h index a8076afcfa7..d5e693570df 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h @@ -37,13 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -124,6 +124,11 @@ typedef enum { PH_0 = 0x70, PH_1 = 0x71, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + // Arduino connector namings A0 = PC_2, A1 = PC_0, diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device.h deleted file mode 100644 index bbb4b7513e6..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device.h +++ /dev/null @@ -1,53 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralPins.c index 54c96ffdd73..8b02db2dc67 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralPins.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralPins.c @@ -55,6 +55,9 @@ const PinMap PinMap_ADC[] = { {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 {NC, NC, 0} }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PinNames.h index 8fe270b12de..831103cc0ec 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PinNames.h @@ -37,13 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -125,6 +125,11 @@ typedef enum { PH_0 = 0x70, PH_1 = 0x71, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + // Generic signals namings LED1 = PA_9, LED2 = PA_9, diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device.h deleted file mode 100644 index bbb4b7513e6..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device.h +++ /dev/null @@ -1,53 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralPins.c index 4d2118949dc..8922b85513a 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralPins.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralPins.c @@ -55,6 +55,9 @@ const PinMap PinMap_ADC[] = { {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT) + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP) {NC, NC, 0} }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h index 87189ccf74d..19825ece390 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h @@ -37,13 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -124,6 +124,11 @@ typedef enum { PH_0 = 0x70, PH_1 = 0x71, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + // Generic signals namings XBEE_DOUT = PA_2, XBEE_DIN = PA_3, diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device.h deleted file mode 100644 index bbb4b7513e6..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device.h +++ /dev/null @@ -1,53 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PeripheralPins.c index cd62675815b..aeff4e10351 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PeripheralPins.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PeripheralPins.c @@ -55,6 +55,9 @@ const PinMap PinMap_ADC[] = { {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 {NC, NC, 0} }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PinNames.h index c97b280041a..f663e7e0b73 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PinNames.h @@ -37,14 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -125,6 +124,11 @@ typedef enum { PH_0 = 0x70, PH_1 = 0x71, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + // Arduino connector namings A0 = PA_0, A1 = PA_1, @@ -154,6 +158,7 @@ typedef enum { LED2 = PA_5, LED3 = PA_5, LED4 = PA_5, + LED_RED = LED1, USER_BUTTON = PC_13, SERIAL_TX = PA_2, SERIAL_RX = PA_3, diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/device.h deleted file mode 100644 index ada82d8c640..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/device.h +++ /dev/null @@ -1,54 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - -#define LED_RED LED1 - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/PeripheralPins.c index e8f49c22880..685f091aa2f 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/PeripheralPins.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/PeripheralPins.c @@ -55,6 +55,9 @@ const PinMap PinMap_ADC[] = { {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT) + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP) {NC, NC, 0} }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/PinNames.h index 7d9f2d9a6b4..19b179f8a5e 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/PinNames.h @@ -37,13 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -124,6 +124,11 @@ typedef enum { PH_0 = 0x70, PH_1 = 0x71, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + // Arduino connector namings A0 = PA_0, A1 = PA_1, @@ -153,6 +158,7 @@ typedef enum { LED2 = PA_5, LED3 = PA_5, LED4 = PA_5, + LED_RED = LED1, USER_BUTTON = PC_13, SERIAL_TX = PA_2, SERIAL_RX = PA_3, diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/device.h deleted file mode 100644 index de47c39c286..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/device.h +++ /dev/null @@ -1,54 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - -#define LED_RED LED1 - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralPins.c index 5b729383768..822922786c9 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralPins.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralPins.c @@ -55,6 +55,9 @@ const PinMap PinMap_ADC[] = { {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT) + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP) {NC, NC, 0} }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PinNames.h index 60718d7a8d0..f663e7e0b73 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PinNames.h @@ -37,13 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -124,6 +124,11 @@ typedef enum { PH_0 = 0x70, PH_1 = 0x71, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + // Arduino connector namings A0 = PA_0, A1 = PA_1, @@ -153,6 +158,7 @@ typedef enum { LED2 = PA_5, LED3 = PA_5, LED4 = PA_5, + LED_RED = LED1, USER_BUTTON = PC_13, SERIAL_TX = PA_2, SERIAL_RX = PA_3, diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/device.h deleted file mode 100644 index de47c39c286..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/device.h +++ /dev/null @@ -1,54 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - -#define LED_RED LED1 - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PeripheralPins.c index 98c52c02a38..33e23aa783b 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PeripheralPins.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PeripheralPins.c @@ -87,6 +87,9 @@ const PinMap PinMap_ADC[] = { {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A5 + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT) + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP) {NC, NC, 0} }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PinNames.h index 3b6948b2aa5..ad4ac56e5da 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PinNames.h @@ -37,22 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\ - ((PUPD & 0x07) << 4) |\ - ((AFNUM & 0x0F) << 7))) - -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\ - ((PUPD & 0x07) << 4) |\ - ((AFNUM & 0x0F) << 7) |\ - ((CHANNEL & 0x0F) << 11) |\ - ((INVERTED & 0x01) << 15))) - -#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) -#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) -#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) - +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -200,6 +191,11 @@ typedef enum { PH_0 = 0x70, PH_1 = 0x71, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + // Arduino connector namings A0 = PA_3, A1 = PC_0, @@ -229,6 +225,7 @@ typedef enum { LED2 = PB_7, // Blue LED3 = PB_14, // Red LED4 = PB_0, + LED_RED = LED2, USER_BUTTON = PC_13, SERIAL_TX = PD_8, // Virtual Com Port SERIAL_RX = PD_9, // Virtual Com Port diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PeripheralPins.c index 53caab52c24..13bb9f75413 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PeripheralPins.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PeripheralPins.c @@ -55,6 +55,9 @@ const PinMap PinMap_ADC[] = { {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT) + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP) {NC, NC, 0} }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PinNames.h index 60718d7a8d0..f663e7e0b73 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PinNames.h @@ -37,13 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -124,6 +124,11 @@ typedef enum { PH_0 = 0x70, PH_1 = 0x71, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + // Arduino connector namings A0 = PA_0, A1 = PA_1, @@ -153,6 +158,7 @@ typedef enum { LED2 = PA_5, LED3 = PA_5, LED4 = PA_5, + LED_RED = LED1, USER_BUTTON = PC_13, SERIAL_TX = PA_2, SERIAL_RX = PA_3, diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/device.h deleted file mode 100644 index 1477050375c..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/device.h +++ /dev/null @@ -1,55 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - -#define LED_RED LED1 - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/PeripheralPins.c index a130339d3e7..90299409e8a 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/PeripheralPins.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/PeripheralPins.c @@ -89,6 +89,9 @@ const PinMap PinMap_ADC[] = { {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 //{PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A5 + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_VBAT) + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 (shared with ADC_TEMP) {NC, NC, 0} }; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/PinNames.h index c6cd114cba6..5933ae2fce0 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/PinNames.h @@ -37,13 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -192,6 +192,11 @@ typedef enum { PH_1 = 0x71, PH_2 = 0x72, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + // Arduino connector namings A0 = PA_3, A1 = PC_0, @@ -221,6 +226,7 @@ typedef enum { LED2 = PB_7, LED3 = PB_14, LED4 = LED1, + LED_RED = LED3, USER_BUTTON = PC_13, SERIAL_TX = PD_8, // Virtual Com Port SERIAL_RX = PD_9, // Virtual Com Port diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h index 844ae704e40..59442ceffbe 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h @@ -37,13 +37,13 @@ extern "C" { #endif // See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) #define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) #define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) #define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) -#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) +#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) #define STM_MODE_INPUT (0) #define STM_MODE_OUTPUT_PP (1) #define STM_MODE_OUTPUT_OD (2) @@ -109,6 +109,11 @@ typedef enum { PH_8 = 0x78, PH_9 = 0x79, PH_10 = 0x7A, PH_11 = 0x7B, PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + // Module Pins // A P_A5 = PC_2, // UART-DTR diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/device.h deleted file mode 100644 index bbb4b7513e6..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/device.h +++ /dev/null @@ -1,53 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/analogin_api.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/analogin_api.c index 8353da8bf29..6b289a6ea35 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/analogin_api.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/analogin_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2016, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -58,8 +58,10 @@ void analogin_init(analogin_t *obj, PinName pin) MBED_ASSERT(function != (uint32_t)NC); obj->channel = STM_PIN_CHANNEL(function); - // Configure GPIO - pinmap_pinout(pin, PinMap_ADC); + // Configure GPIO excepted for internal channels (Temperature, Vref, Vbat) + if ((obj->channel != 16) && (obj->channel != 17) && (obj->channel != 18)) { + pinmap_pinout(pin, PinMap_ADC); + } // Save pin number for the read function obj->pin = pin; @@ -101,6 +103,7 @@ void analogin_init(analogin_t *obj, PinName pin) AdcHandle.Init.NbrOfConversion = 1; AdcHandle.Init.DMAContinuousRequests = DISABLE; AdcHandle.Init.EOCSelection = DISABLE; + if (HAL_ADC_Init(&AdcHandle) != HAL_OK) { error("Cannot initialize ADC\n"); } @@ -114,7 +117,7 @@ static inline uint16_t adc_read(analogin_t *obj) // Configure ADC channel sConfig.Rank = 1; - sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + sConfig.SamplingTime = ADC_SAMPLETIME_15CYCLES; sConfig.Offset = 0; switch (obj->channel) { @@ -166,6 +169,15 @@ static inline uint16_t adc_read(analogin_t *obj) case 15: sConfig.Channel = ADC_CHANNEL_15; break; + case 16: + sConfig.Channel = ADC_CHANNEL_16; + break; + case 17: + sConfig.Channel = ADC_CHANNEL_17; + break; + case 18: + sConfig.Channel = ADC_CHANNEL_18; + break; default: return 0; } diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/device.h similarity index 99% rename from hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/device.h rename to hal/targets/hal/TARGET_STM/TARGET_STM32F4/device.h index bbb4b7513e6..b6131682750 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/device.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F4/device.h @@ -32,22 +32,9 @@ #ifndef MBED_DEVICE_H #define MBED_DEVICE_H - - - - - - - - - //======================================= - #define DEVICE_ID_LENGTH 24 - - - #include "objects.h" #endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/device.h deleted file mode 100644 index bdad16c6f18..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/device.h +++ /dev/null @@ -1,54 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PeripheralNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PeripheralNames.h new file mode 100644 index 00000000000..0dde5d66edf --- /dev/null +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PeripheralNames.h @@ -0,0 +1,104 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, + ADC_2 = (int)ADC2_BASE, + ADC_3 = (int)ADC3_BASE +} ADCName; + +typedef enum { + DAC_1 = DAC_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + UART_6 = (int)USART6_BASE, + UART_7 = (int)UART7_BASE, + UART_8 = (int)UART8_BASE +} UARTName; + +#define STDIO_UART_TX PA_9 +#define STDIO_UART_RX PA_10 +#define STDIO_UART UART_1 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE, + SPI_5 = (int)SPI5_BASE, + SPI_6 = (int)SPI6_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE, + I2C_4 = (int)I2C4_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE, + PWM_12 = (int)TIM12_BASE, + PWM_13 = (int)TIM13_BASE, + PWM_14 = (int)TIM14_BASE +} PWMName; + +typedef enum { + CAN_1 = (int)CAN1_BASE, + CAN_2 = (int)CAN2_BASE +} CANName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PeripheralPins.c new file mode 100644 index 00000000000..dd9c99a92cb --- /dev/null +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PeripheralPins.c @@ -0,0 +1,211 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ============================================================================= +// Notes: +// * Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// * Only the pins that are placed on the Arduino connector are described. +// ============================================================================= + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + // {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - ARDUINO A1 + {PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 - ARDUINO A1 + // {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - ARDUINO A0 + {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - ARDUINO A0 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,12, 0)}, // ADC1_IN12 - ARDUINO A2 + // {PC_2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,12, 0)}, // ADC2_IN12 - ARDUINO A2 + {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 - ARDUINO D3 + {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 - ARDUINO D6 + {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 - ARDUINO A4 + {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 - ARDUINO A5 + {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A3 + + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 1, 0)}, // DAC_OUT1 (ARDUINO A1) + // {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 2, 0)}, // DAC_OUT2 - used by USB3320C + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // used by Audio_SDA + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D14/SDA + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D14/SCL + {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // used by Audio_SCL + {NC, NC, 0} +}; + +//*** PWM *** + +const PinMap PinMap_PWM[] = { + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO A0 + // {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - ARDUINO A0 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - ARDUINO D10 + + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - ARDUINO D15 + // {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - ARDUINO D15 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - ARDUINO D14 + // {PB_9, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - ARDUINO D14 + // {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - ARDUINO D12 + // {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - ARDUINO D12 + {PB_14, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 - ARDUINO D12 + // {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - ARDUINO D11 + // {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - ARDUINO D11 + {PB_15, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 - ARDUINO D11 + + {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - ARDUINO D1 + // {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO D1 + {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - ARDUINO D0 + // {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO D0 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - ARDUINO D5 + // {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - ARDUINO D5 + + {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - ARDUINO D3 + {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - ARDUINO D6 + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - ARDUINO A4 + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - ARDUINO A5 + + {PH_6, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 - ARDUINO D9 + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by stlink usb) + // {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4 )}, // ARDUINO D13 - remove SB15 to use it + {PB_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, // ARDUINO D14 + {PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // ARDUINO D12 + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // ARDUINO D1 + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5 )}, // WIFI_RX + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7 )}, // ARDUINO D6 + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by st-link usb) + {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4 )}, // ARDUINO D10 + {PB_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5 )}, // ARDUINO D15 + {PB_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // ARDUINO D11 + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // ARDUINO D0 + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5 )}, // WIFI_TX + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7 )}, // ARDUINO D3 + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1 )}, // ARDUINO D13 + {PB_14, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4 )}, // ARDUINO D12 + // {PB_14, USART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3 )}, // ARDUINO D12 + {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5 )}, // ARDUINO D5 + {PF_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7 )}, // ARDUINO A4 + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // ARDUINO D10 + {PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4 )}, // ARDUINO D11 + {PF_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7 )}, // ARDUINO A5 + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO D11 + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, // SD card + {PD_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // SD card + {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // ARDUINO A5 + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // ARDUINO A0 + // {PA_6, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, // ARDUINO A0 + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // SD card + // {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // SD card + // {PB_4, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, // SD card + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO D12 + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO A2 + {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // ARDUINO A4 + {PG_9, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // SD card + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO D13 + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // SD card + // {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + // {PB_3, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // ARDUINO D6 + {PH_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // ARDUINO D9 + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // ARDUINO A1 + // {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO D10 + {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)}, // SD card + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO D14 + {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // ARDUINO D3 + {PG_10, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // SD card + {NC, NC, 0} +}; + +//*** CAN *** + +const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NC, 0} +}; \ No newline at end of file diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PinNames.h new file mode 100644 index 00000000000..157f900b802 --- /dev/null +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PinNames.h @@ -0,0 +1,317 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\ + ((PUPD & 0x07) << 4) |\ + ((AFNUM & 0x0F) << 7))) + +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\ + ((PUPD & 0x07) << 4) |\ + ((AFNUM & 0x0F) << 7) |\ + ((CHANNEL & 0x0F) << 11) |\ + ((INVERTED & 0x01) << 15))) + +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) + +#define STM_MODE_INPUT (0) +#define STM_MODE_OUTPUT_PP (1) +#define STM_MODE_OUTPUT_OD (2) +#define STM_MODE_AF_PP (3) +#define STM_MODE_AF_OD (4) +#define STM_MODE_ANALOG (5) +#define STM_MODE_IT_RISING (6) +#define STM_MODE_IT_FALLING (7) +#define STM_MODE_IT_RISING_FALLING (8) +#define STM_MODE_EVT_RISING (9) +#define STM_MODE_EVT_FALLING (10) +#define STM_MODE_EVT_RISING_FALLING (11) +#define STM_MODE_IT_EVT_RESET (12) + +// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H, 8=I, 9=J, A=K) +// Low nibble = pin number +#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF) +#define STM_PIN(X) ((uint32_t)(X) & 0xF) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_5 = 0x55, + PF_6 = 0x56, + PF_7 = 0x57, + PF_8 = 0x58, + PF_9 = 0x59, + PF_10 = 0x5A, + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_15 = 0x5F, + + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + + PH_0 = 0x70, + PH_1 = 0x71, + PH_2 = 0x72, + PH_3 = 0x73, + PH_4 = 0x74, + PH_5 = 0x75, + PH_6 = 0x76, + PH_7 = 0x77, + PH_8 = 0x78, + PH_9 = 0x79, + PH_10 = 0x7A, + PH_11 = 0x7B, + PH_12 = 0x7C, + PH_13 = 0x7D, + PH_14 = 0x7E, + PH_15 = 0x7F, + + PI_0 = 0x80, + PI_1 = 0x81, + PI_2 = 0x82, + PI_3 = 0x83, + PI_4 = 0x84, + PI_5 = 0x85, + PI_6 = 0x86, + PI_7 = 0x87, + PI_8 = 0x88, + PI_9 = 0x89, + PI_10 = 0x8A, + PI_11 = 0x8B, + PI_12 = 0x8C, + PI_13 = 0x8D, + PI_14 = 0x8E, + PI_15 = 0x8F, + + PJ_0 = 0x90, + PJ_1 = 0x91, + PJ_2 = 0x92, + PJ_3 = 0x93, + PJ_4 = 0x94, + PJ_5 = 0x95, + PJ_6 = 0x96, + PJ_7 = 0x97, + PJ_8 = 0x98, + PJ_9 = 0x99, + PJ_10 = 0x9A, + PJ_11 = 0x9B, + PJ_12 = 0x9C, + PJ_13 = 0x9D, + PJ_14 = 0x9E, + PJ_15 = 0x9F, + + PK_0 = 0xA0, + PK_1 = 0xA1, + PK_2 = 0xA2, + PK_3 = 0xA3, + PK_4 = 0xA4, + PK_5 = 0xA5, + PK_6 = 0xA6, + PK_7 = 0xA7, + + // Arduino connector namings + A0 = PA_6, + A1 = PA_4, + A2 = PC_2, + A3 = PF_10, + A4 = PF_8, + A5 = PF_9, + D0 = PC_7, + D1 = PC_6, + D2 = PJ_1, + D3 = PF_6, + D4 = PJ_0, + D5 = PC_8, + D6 = PF_7, + D7 = PJ_3, + D8 = PJ_4, + D9 = PH_6, + D10 = PA_11, + D11 = PB_15, + D12 = PB_14, + D13 = PA_12, + D14 = PB_9, + D15 = PB_8, + + // Generic signals namings + LED1 = PJ_13, // LD1 = RED + LED2 = PJ_5, // LD2 = GREEN + LED3 = PA_12, // LD3 = GREEN + LED4 = PJ_13, + USER_BUTTON = PA_0, + SERIAL_TX = PA_9, // Virtual Com Port + SERIAL_RX = PA_10, // Virtual Com Port + USBTX = PA_9, // Virtual Com Port + USBRX = PA_10, // Virtual Com Port + I2C_SCL = D15, + I2C_SDA = D14, + SPI_MOSI = D11, + SPI_MISO = D12, + SPI_SCK = D13, + SPI_CS = D10, + PWM_OUT = D9, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PortNames.h similarity index 82% rename from hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device.h rename to hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PortNames.h index 38e5143ddb2..e875a51cdc1 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device.h +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PortNames.h @@ -1,5 +1,3 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. /* mbed Microcontroller Library ******************************************************************************* * Copyright (c) 2015, STMicroelectronics @@ -29,25 +27,28 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H +#ifdef __cplusplus +extern "C" { +#endif - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortE = 4, + PortF = 5, + PortG = 6, + PortH = 7, + PortI = 8, // kept for compilation + PortJ = 9, // kept for compilation + PortK = 10 // kept for compilation +} PortName; + +#ifdef __cplusplus +} +#endif #endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device.h similarity index 100% rename from hal/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device.h rename to hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device.h diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/objects.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/objects.h new file mode 100644 index 00000000000..e63d9e72300 --- /dev/null +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/objects.h @@ -0,0 +1,116 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; + uint8_t channel; +}; + +struct dac_s { + DACName dac; + PinName pin; + uint32_t channel; +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +#if DEVICE_SERIAL_FC + uint32_t hw_flow_ctl; + PinName pin_rts; + PinName pin_cts; +#endif +}; + +struct spi_s { + SPIName spi; + uint32_t bits; + uint32_t cpol; + uint32_t cpha; + uint32_t mode; + uint32_t nss; + uint32_t br_presc; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +}; + +struct i2c_s { + I2CName i2c; + uint32_t slave; +}; + +struct can_s { + CANName can; + int index; +}; + +#include "gpio_object.h" +#include "common_objects.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/device.h new file mode 100644 index 00000000000..b6131682750 --- /dev/null +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/device.h @@ -0,0 +1,40 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +//======================================= +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" + +#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device.h deleted file mode 100644 index 38e5143ddb2..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device.h +++ /dev/null @@ -1,53 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device.h deleted file mode 100644 index 38e5143ddb2..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device.h +++ /dev/null @@ -1,53 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device.h deleted file mode 100644 index 38e5143ddb2..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device.h +++ /dev/null @@ -1,53 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device.h deleted file mode 100644 index 38e5143ddb2..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device.h +++ /dev/null @@ -1,53 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device.h deleted file mode 100644 index 38e5143ddb2..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device.h +++ /dev/null @@ -1,53 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L0/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32L0/device.h new file mode 100644 index 00000000000..b6131682750 --- /dev/null +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32L0/device.h @@ -0,0 +1,40 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +//======================================= +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" + +#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device.h deleted file mode 100644 index bbb4b7513e6..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device.h +++ /dev/null @@ -1,53 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device.h deleted file mode 100644 index bbb4b7513e6..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device.h +++ /dev/null @@ -1,53 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device.h deleted file mode 100644 index 17cd684d651..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device.h +++ /dev/null @@ -1,62 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - -//MODTRONIX BEGIN - mbed Defines ////////////////////////////////////////////// -//Provide place for adding mbed defines. Alternative to adding them in IDE project properties. -//Add project defines here, or add them to your toolchain compiler preprocessor - - -//MODTRONIX END /////////////////////////////////////////////////////////////// - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L1/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32L1/device.h new file mode 100644 index 00000000000..b6131682750 --- /dev/null +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32L1/device.h @@ -0,0 +1,40 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +//======================================= +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" + +#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/PeripheralPins.c index fd662fae2f2..319972f36b6 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/PeripheralPins.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/PeripheralPins.c @@ -192,6 +192,35 @@ const PinMap PinMap_UART_RX[] = { {NC, NC, 0} }; +const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, +// {PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {NC, NC, 0} +}; + //*** SPI *** const PinMap PinMap_SPI_MOSI[] = { diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/device.h deleted file mode 100644 index bdad16c6f18..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/device.h +++ /dev/null @@ -1,54 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/device.h deleted file mode 100644 index 38e5143ddb2..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/device.h +++ /dev/null @@ -1,53 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device.h deleted file mode 100644 index bdad16c6f18..00000000000 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device.h +++ /dev/null @@ -1,54 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L4/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32L4/device.h new file mode 100644 index 00000000000..b6131682750 --- /dev/null +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32L4/device.h @@ -0,0 +1,40 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +//======================================= +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" + +#endif diff --git a/libraries/USBDevice/USBAudio/USBAudio.h b/libraries/USBDevice/USBAudio/USBAudio.h index 5038f053c8e..f016ff0a0ec 100644 --- a/libraries/USBDevice/USBAudio/USBAudio.h +++ b/libraries/USBDevice/USBAudio/USBAudio.h @@ -25,7 +25,7 @@ #include "USBDevice_Types.h" #include "USBDevice.h" - +#include "Callback.h" /** * USBAudio example @@ -275,7 +275,7 @@ class USBAudio: public USBDevice { volatile uint8_t * buf_stream_out; // callback to update volume - FunctionPointer updateVol; + Callback updateVol; // boolean showing that the SOF handler has been called. Useful for readNB. volatile bool SOF_handler; diff --git a/libraries/USBDevice/USBSerial/USBSerial.h b/libraries/USBDevice/USBSerial/USBSerial.h index 164cf9bc7da..286b5a384d8 100644 --- a/libraries/USBDevice/USBSerial/USBSerial.h +++ b/libraries/USBDevice/USBSerial/USBSerial.h @@ -22,7 +22,7 @@ #include "USBCDC.h" #include "Stream.h" #include "CircBuffer.h" - +#include "Callback.h" /** * USBSerial example @@ -153,7 +153,7 @@ class USBSerial: public USBCDC, public Stream { } private: - FunctionPointer rx; + Callback rx; CircBuffer buf; void (*settingsChangedCallback)(int baud, int bits, int parity, int stop); }; diff --git a/libraries/USBHost/USBHost/USBDeviceConnected.h b/libraries/USBHost/USBHost/USBDeviceConnected.h index 22a4c1d3e91..f74c4b6e4b9 100644 --- a/libraries/USBHost/USBHost/USBDeviceConnected.h +++ b/libraries/USBHost/USBHost/USBDeviceConnected.h @@ -21,6 +21,7 @@ #include "USBEndpoint.h" #include "USBHostConf.h" #include "rtos.h" +#include "Callback.h" class USBHostHub; @@ -31,7 +32,7 @@ typedef struct { uint8_t intf_subclass; uint8_t intf_protocol; USBEndpoint * ep[MAX_ENDPOINT_PER_INTERFACE]; - FunctionPointer detach; + Callback detach; char name[10]; } INTERFACE; diff --git a/libraries/USBHost/USBHost/USBEndpoint.h b/libraries/USBHost/USBHost/USBEndpoint.h index 2ec90d729fd..64b320f2139 100644 --- a/libraries/USBHost/USBHost/USBEndpoint.h +++ b/libraries/USBHost/USBHost/USBEndpoint.h @@ -17,7 +17,7 @@ #ifndef USBENDPOINT_H #define USBENDPOINT_H -#include "FunctionPointer.h" +#include "Callback.h" #include "USBHostTypes.h" #include "rtos.h" @@ -153,7 +153,7 @@ class USBEndpoint int transferred; uint8_t * buf_start; - FunctionPointer rx; + Callback rx; USBEndpoint* nextEp; diff --git a/libraries/USBHost/USBHost/USBHost.cpp b/libraries/USBHost/USBHost/USBHost.cpp index d8b5c450e95..0ff47c5eeb0 100644 --- a/libraries/USBHost/USBHost/USBHost.cpp +++ b/libraries/USBHost/USBHost/USBHost.cpp @@ -247,11 +247,7 @@ void USBHost::usb_process() { } } -/* static */void USBHost::usb_process_static(void const * arg) { - ((USBHost *)arg)->usb_process(); -} - -USBHost::USBHost() : usbThread(USBHost::usb_process_static, (void *)this, osPriorityNormal, USB_THREAD_STACK) +USBHost::USBHost() : usbThread(osPriorityNormal, USB_THREAD_STACK) { headControlEndpoint = NULL; headBulkEndpoint = NULL; @@ -279,6 +275,8 @@ USBHost::USBHost() : usbThread(USBHost::usb_process_static, (void *)this, osPrio hub_in_use[i] = false; } #endif + + usbThread.start(this, &USBHost::usb_process); } USBHost::Lock::Lock(USBHost* pHost) : m_pHost(pHost) diff --git a/libraries/USBHost/USBHost/USBHost.h b/libraries/USBHost/USBHost/USBHost.h index 802ae993136..40c5664c408 100644 --- a/libraries/USBHost/USBHost/USBHost.h +++ b/libraries/USBHost/USBHost/USBHost.h @@ -278,7 +278,6 @@ class USBHost : public USBHALHost { Thread usbThread; void usb_process(); - static void usb_process_static(void const * arg); Mail mail_usb_event; Mutex usb_mutex; Mutex td_mutex; diff --git a/libraries/USBHost/USBHostMSD/USBHostMSD.cpp b/libraries/USBHost/USBHostMSD/USBHostMSD.cpp index 75d0f59d4b2..6b4ed828b2e 100644 --- a/libraries/USBHost/USBHostMSD/USBHostMSD.cpp +++ b/libraries/USBHost/USBHostMSD/USBHostMSD.cpp @@ -136,7 +136,7 @@ int USBHostMSD::readCapacity() { if (status == 0) { blockCount = (result[0] << 24) | (result[1] << 16) | (result[2] << 8) | result[3]; blockSize = (result[4] << 24) | (result[5] << 16) | (result[6] << 8) | result[7]; - USB_INFO("MSD [dev: %p] - blockCount: %lld, blockSize: %d, Capacity: %lld\r\n", dev, blockCount, blockSize, blockCount*blockSize); + USB_INFO("MSD [dev: %p] - blockCount: %u, blockSize: %d, Capacity: %d\r\n", dev, blockCount, blockSize, blockCount*blockSize); } return status; } diff --git a/libraries/USBHost/USBHostSerial/USBHostSerial.h b/libraries/USBHost/USBHostSerial/USBHostSerial.h index 94fc8ad7c54..816a0518c6d 100644 --- a/libraries/USBHost/USBHostSerial/USBHostSerial.h +++ b/libraries/USBHost/USBHostSerial/USBHostSerial.h @@ -24,6 +24,7 @@ #include "USBHost.h" #include "Stream.h" #include "MtxCircBuffer.h" +#include "Callback.h" /** * A class to communicate a USB virtual serial port @@ -137,8 +138,8 @@ class USBHostSerialPort : public Stream { void rxHandler(); void txHandler(); - FunctionPointer rx; - FunctionPointer tx; + Callback rx; + Callback tx; uint8_t serial_intf; }; diff --git a/libraries/tests/mbed/analog/main.cpp b/libraries/tests/mbed/analog/main.cpp index c5fdaa53220..d23121c65ff 100644 --- a/libraries/tests/mbed/analog/main.cpp +++ b/libraries/tests/mbed/analog/main.cpp @@ -64,6 +64,10 @@ AnalogOut out(PA_4); AnalogIn in(PC_5); AnalogOut out(PA_4); +#elif defined(TARGET_NUCLEO_F303ZE) +AnalogIn in(PC_5); +AnalogOut out(PA_5); + #elif defined(TARGET_DISCO_F429ZI) AnalogIn in(PC_3); AnalogOut out(PA_5); diff --git a/libraries/tests/mbed/can_loopback/main.cpp b/libraries/tests/mbed/can_loopback/main.cpp index 8e7935fd37e..3aea4ddcd8e 100644 --- a/libraries/tests/mbed/can_loopback/main.cpp +++ b/libraries/tests/mbed/can_loopback/main.cpp @@ -21,10 +21,11 @@ CAN can1(P5_9, P5_10); defined(TARGET_NUCLEO_F746ZG) || defined(TARGET_DISCO_L476VG) || \ defined(TARGET_NUCLEO_L476RG) || defined(TARGET_NUCLEO_L432KC) CAN can1(PA_11, PA_12); -#elif defined(TARGET_DISCO_F469NI) || defined(TARGET_DISCO_F746NG) || \ - defined(TARGET_NUCLEO_F446ZE) || \ - defined(TARGET_NUCLEO_F103RB) || \ - defined(TARGET_NUCLEO_F207ZG) + defined(TARGET_NUCLEO_F446ZE) || \ + defined(TARGET_NUCLEO_F103RB) || \ + defined(TARGET_NUCLEO_F207ZG) || \ + defined(TARGET_NUCLEO_F303ZE) || \ + defined(TARGET_DISCO_F769NI) CAN can1(PB_8, PB_9); #endif diff --git a/libraries/tests/utest/serial_asynch/serial_asynch.cpp b/libraries/tests/utest/serial_asynch/serial_asynch.cpp index b264587444c..d612f628048 100644 --- a/libraries/tests/utest/serial_asynch/serial_asynch.cpp +++ b/libraries/tests/utest/serial_asynch/serial_asynch.cpp @@ -51,6 +51,10 @@ #define TEST_SERIAL_ONE_TX_PIN PB_10 // UART3 #define TEST_SERIAL_TWO_RX_PIN PA_10 // UART1 +#elif defined(TARGET_NUCLEO_F103RB) +#define TEST_SERIAL_ONE_TX_PIN PB_10 // UART3 +#define TEST_SERIAL_TWO_RX_PIN PA_10 // UART1 + #elif defined(TARGET_NUCLEO_F207ZG) #define TEST_SERIAL_ONE_TX_PIN PC_12 // UART5 #define TEST_SERIAL_TWO_RX_PIN PC_11 // UART4 diff --git a/requirements.txt b/requirements.txt index 963bea20363..d01de683e98 100644 --- a/requirements.txt +++ b/requirements.txt @@ -3,8 +3,8 @@ PySerial>=2.7 PrettyTable>=0.7.2 Jinja2>=2.7.3 IntelHex>=1.3 -project-generator>=0.9.7,<0.10.0 -project-generator-definitions>=0.2.26,<0.3.0 +project-generator==0.9.10 +project_generator_definitions>=0.2.26,<0.3.0 junit-xml pyYAML requests diff --git a/rtos/rtos/Thread.cpp b/rtos/rtos/Thread.cpp index cb62d77165c..91e80afe2b5 100644 --- a/rtos/rtos/Thread.cpp +++ b/rtos/rtos/Thread.cpp @@ -101,11 +101,14 @@ osStatus Thread::terminate() { osStatus ret; _mutex.lock(); - ret = osThreadTerminate(_tid); + // Set the Thread's tid to NULL and + // release the semaphore before terminating + // since this thread could be terminating itself + osThreadId local_id = _tid; + _join_sem.release(); _tid = (osThreadId)NULL; - // Wake threads joining the terminated thread - _join_sem.release(); + ret = osThreadTerminate(local_id); _mutex.unlock(); return ret; @@ -116,6 +119,14 @@ osStatus Thread::join() { if (ret < 0) { return osErrorOS; } + + // The semaphore has been released so this thread is being + // terminated or has been terminated. Once the mutex has + // been locked it is ensured that the thread is deleted. + _mutex.lock(); + MBED_ASSERT(NULL == _tid); + _mutex.unlock(); + // Release sem so any other threads joining this thread wake up _join_sem.release(); return osOK; diff --git a/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h b/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h index 5bc6828fe83..944f7c7e0e7 100644 --- a/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h +++ b/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h @@ -511,7 +511,7 @@ osThreadDef_t os_thread_def_main = {(os_pthread)pre_main, osPriorityNormal, 1U, #elif defined(TARGET_STM32F401VC) #define INITIAL_SP (0x20010000UL) -#elif defined(TARGET_STM32F303RE) +#elif defined(TARGET_STM32F303RE) || defined(TARGET_STM32F303ZE) #define INITIAL_SP (0x20010000UL) #elif defined(TARGET_STM32F303K8) @@ -574,14 +574,17 @@ osThreadDef_t os_thread_def_main = {(os_pthread)pre_main, osPriorityNormal, 1U, #elif (defined(TARGET_STM32F767ZI)) #define INITIAL_SP (0x20080000UL) +#elif (defined(TARGET_STM32F769NI)) +#define INITIAL_SP (0x20080000UL) + #elif defined(TARGET_NUMAKER_PFM_NUC472) # if defined(__CC_ARM) -extern uint32_t Image$$ARM_LIB_HEAP$$Base[]; -extern uint32_t Image$$ARM_LIB_HEAP$$Length[]; +extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base[]; +extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Length[]; extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Length[]; -#define HEAP_START ((unsigned char*) Image$$ARM_LIB_HEAP$$Base) -#define HEAP_SIZE ((uint32_t) Image$$ARM_LIB_HEAP$$Length) +#define HEAP_START ((unsigned char*) Image$$ARM_LIB_HEAP$$ZI$$Base) +#define HEAP_SIZE ((uint32_t) Image$$ARM_LIB_HEAP$$ZI$$Length) #define ISR_STACK_START ((unsigned char*)Image$$ARM_LIB_STACK$$ZI$$Base) #define ISR_STACK_SIZE ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Length) # elif defined(__GNUC__) diff --git a/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c b/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c index 44618ef93a1..562f1addd09 100755 --- a/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c +++ b/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c @@ -52,10 +52,10 @@ || defined(TARGET_STM32F410RB) || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \ || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F207ZG) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) || defined(TARGET_MAX32600) || defined(TARGET_MAX32620) || defined(TARGET_TEENSY3_1) \ || defined(TARGET_STM32L152RE) || defined(TARGET_STM32F446RE) || defined(TARGET_STM32F446VE) || defined(TARGET_STM32F446ZE) || defined(TARGET_STM32L432KC) || defined(TARGET_STM32L476VG) || defined(TARGET_STM32L476RG) || defined(TARGET_STM32F469NI) || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG) || defined(TARGET_STM32L152RC) \ - || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800) || defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32PG_STK3401) || defined(TARGET_STM32F767ZI) \ + || defined(TARGET_EFM32GG_STK3700) || defined(TARGET_EFM32WG_STK3800) || defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32PG_STK3401) || defined(TARGET_STM32F767ZI) || defined(TARGET_STM32F769NI) \ || defined(TARGET_NUMAKER_PFM_NUC472) || defined(TARGET_NCS36510) # define OS_TASKCNT 14 -# elif defined(TARGET_LPC11U24) || defined(TARGET_STM32F303RE) || defined(TARGET_STM32F303K8) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ +# elif defined(TARGET_LPC11U24) || defined(TARGET_STM32F303RE) || defined(TARGET_STM32F303ZE) || defined(TARGET_STM32F303K8) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL26Z) || defined(TARGET_KL27Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) \ || defined(TARGET_STM32L031K6) || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32L073RZ) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32_SC151) \ @@ -88,7 +88,7 @@ || defined(TARGET_STM32F410RB) || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \ || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) || defined(TARGET_MAX32600) || defined(TARGET_MAX32620) || defined(TARGET_TEENSY3_1) \ || defined(TARGET_STM32L152RE) || defined(TARGET_STM32F446RE) || defined(TARGET_STM32F446VE) || defined(TARGET_STM32F446ZE) || defined(TARGET_STM32L432KC) || defined(TARGET_STM32L476VG) || defined(TARGET_STM32L476RG) || defined(TARGET_STM32F469NI) || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG) || defined(TARGET_STM32L152RC) \ - ||defined(TARGET_EFM32GG_STK3700) || defined(TARGET_STM32F767ZI) || defined(TARGET_STM32F207ZG) \ + ||defined(TARGET_EFM32GG_STK3700) || defined(TARGET_STM32F767ZI) || defined(TARGET_STM32F207ZG) || defined(TARGET_STM32F769NI) \ || defined(TARGET_NUMAKER_PFM_NUC472) || defined(TARGET_NCS36510) # define OS_MAINSTKSIZE 256 # elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ @@ -97,7 +97,7 @@ || defined(TARGET_SSCI824) || defined(TARGET_STM32F030R8) || defined(TARGET_STM32F070RB) \ || defined(TARGET_EFM32WG_STK3800) || defined(TARGET_EFM32LG_STK3600) || defined(TARGET_EFM32PG_STK3401) # define OS_MAINSTKSIZE 128 -# elif defined(TARGET_STM32F334R8) || defined(TARGET_STM32F303RE) || defined(TARGET_STM32F303K8) || defined(TARGET_STM32F334C8) \ +# elif defined(TARGET_STM32F334R8) || defined(TARGET_STM32F303RE)|| defined(TARGET_STM32F303ZE) || defined(TARGET_STM32F303K8) || defined(TARGET_STM32F334C8) \ || defined(TARGET_STM32L031K6) || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32L073RZ) \ || defined(TARGET_EFM32HG_STK3400) || defined(TARGET_BEETLE) # define OS_MAINSTKSIZE 112 @@ -169,7 +169,7 @@ # if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_TEENSY3_1) # define OS_CLOCK 96000000 -# elif defined(TARGET_LPC1347) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) || defined(TARGET_STM32F303RE) +# elif defined(TARGET_LPC1347) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) || defined(TARGET_STM32F303RE) || defined(TARGET_STM32F303ZE) # define OS_CLOCK 72000000 # elif defined(TARGET_STM32F303K8) @@ -227,7 +227,7 @@ #elif defined(TARGET_STM32F401VC) # define OS_CLOCK 84000000 -# elif defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG) || defined(TARGET_STM32F767ZI) +# elif defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG) || defined(TARGET_STM32F767ZI) || defined(TARGET_STM32F769NI) # define OS_CLOCK 216000000 #elif defined(TARGET_MAX32610) || defined(TARGET_MAX32600) diff --git a/tools/build.py b/tools/build.py index 6c65c7190dd..d988a0a6497 100644 --- a/tools/build.py +++ b/tools/build.py @@ -36,7 +36,7 @@ from tools.build_api import static_analysis_scan, static_analysis_scan_lib, static_analysis_scan_library from tools.build_api import print_build_results from tools.settings import CPPCHECK_CMD, CPPCHECK_MSG_FORMAT -from utils import argparse_filestring_type +from utils import argparse_filestring_type, args_error from tools.settings import CPPCHECK_CMD, CPPCHECK_MSG_FORMAT, CLI_COLOR_MAP from utils import argparse_filestring_type, argparse_dir_not_parent @@ -167,6 +167,9 @@ # Get toolchains list toolchains = options.tool if options.tool else TOOLCHAINS + if options.source_dir and not options.build_dir: + args_error(parser, "argument --build is required by argument --source") + if options.color: # This import happens late to prevent initializing colorization when we don't need it import colorize diff --git a/tools/build_api.py b/tools/build_api.py index be116eb8510..f38e484c967 100644 --- a/tools/build_api.py +++ b/tools/build_api.py @@ -1,6 +1,6 @@ """ mbed SDK -Copyright (c) 2011-2013 ARM Limited +Copyright (c) 2011-2016 ARM Limited Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -276,7 +276,8 @@ def get_mbed_official_release(version): def prepare_toolchain(src_paths, target, toolchain_name, macros=None, options=None, clean=False, jobs=1, notify=None, silent=False, verbose=False, - extra_verbose=False, config=None): + extra_verbose=False, config=None, + app_config=None): """ Prepares resource related objects - toolchain, target, config Positional arguments: @@ -294,6 +295,7 @@ def prepare_toolchain(src_paths, target, toolchain_name, verbose - Write the actual tools command lines used if True extra_verbose - even more output! config - a Config object to use instead of creating one + app_config - location of a chosen mbed_app.json file """ # We need to remove all paths which are repeated to avoid @@ -301,7 +303,7 @@ def prepare_toolchain(src_paths, target, toolchain_name, src_paths = [src_paths[0]] + list(set(src_paths[1:])) # If the configuration object was not yet created, create it now - config = config or Config(target, src_paths) + config = config or Config(target, src_paths, app_config=app_config) # If the 'target' argument is a string, convert it to a target instance if isinstance(target, basestring): @@ -326,7 +328,7 @@ def prepare_toolchain(src_paths, target, toolchain_name, return toolchain def scan_resources(src_paths, toolchain, dependencies_paths=None, - inc_dirs=None): + inc_dirs=None, base_path=None): """ Scan resources using initialized toolcain Positional arguments @@ -338,9 +340,9 @@ def scan_resources(src_paths, toolchain, dependencies_paths=None, """ # Scan src_path - resources = toolchain.scan_resources(src_paths[0]) + resources = toolchain.scan_resources(src_paths[0], base_path=base_path) for path in src_paths[1:]: - resources.add(toolchain.scan_resources(path)) + resources.add(toolchain.scan_resources(path, base_path=base_path)) # Scan dependency paths for include dirs if dependencies_paths is not None: @@ -369,7 +371,8 @@ def build_project(src_paths, build_path, target, toolchain_name, clean=False, notify=None, verbose=False, name=None, macros=None, inc_dirs=None, jobs=1, silent=False, report=None, properties=None, project_id=None, - project_description=None, extra_verbose=False, config=None): + project_description=None, extra_verbose=False, config=None, + app_config=None): """ Build a project. A project may be a test or a user program. Positional arguments: @@ -397,6 +400,7 @@ def build_project(src_paths, build_path, target, toolchain_name, project_description - the human-readable version of what this thing does extra_verbose - even more output! config - a Config object to use instead of creating one + app_config - location of a chosen mbed_app.json file """ # Convert src_path to a list if needed @@ -415,7 +419,7 @@ def build_project(src_paths, build_path, target, toolchain_name, toolchain = prepare_toolchain( src_paths, target, toolchain_name, macros=macros, options=options, clean=clean, jobs=jobs, notify=notify, silent=silent, verbose=verbose, - extra_verbose=extra_verbose, config=config) + extra_verbose=extra_verbose, config=config, app_config=app_config) # The first path will give the name to the library if name is None: @@ -489,7 +493,7 @@ def build_library(src_paths, build_path, target, toolchain_name, archive=True, notify=None, verbose=False, macros=None, inc_dirs=None, jobs=1, silent=False, report=None, properties=None, extra_verbose=False, project_id=None, - remove_config_header_file=False): + remove_config_header_file=False, app_config=None): """ Build a library Positional arguments: @@ -516,6 +520,7 @@ def build_library(src_paths, build_path, target, toolchain_name, extra_verbose - even more output! project_id - the name that goes in the report remove_config_header_file - delete config header file when done building + app_config - location of a chosen mbed_app.json file """ # Convert src_path to a list if needed @@ -539,7 +544,7 @@ def build_library(src_paths, build_path, target, toolchain_name, toolchain = prepare_toolchain( src_paths, target, toolchain_name, macros=macros, options=options, clean=clean, jobs=jobs, notify=notify, silent=silent, verbose=verbose, - extra_verbose=extra_verbose) + extra_verbose=extra_verbose, app_config=app_config) # The first path will give the name to the library if name is None: diff --git a/tools/build_travis.py b/tools/build_travis.py index 3ebfc67e304..fa107283ddb 100644 --- a/tools/build_travis.py +++ b/tools/build_travis.py @@ -49,6 +49,7 @@ { "target": "NUCLEO_F302R8", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F303K8", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F303RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, + { "target": "NUCLEO_F303ZE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F334R8", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F401RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F410RB", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, @@ -80,6 +81,7 @@ { "target": "DISCO_F429ZI", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "DISCO_F469NI", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "DISCO_F746NG", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "DISCO_F769NI", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "LPC1114", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "LPC11U35_401", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, diff --git a/tools/config.py b/tools/config.py index e6f8c638629..03ce5309a69 100644 --- a/tools/config.py +++ b/tools/config.py @@ -15,10 +15,12 @@ limitations under the License. """ +import os +import sys + # Implementation of mbed configuration mechanism from tools.utils import json_file_to_dict from tools.targets import Target -import os # Base class for all configuration exceptions class ConfigException(Exception): @@ -348,7 +350,7 @@ class Config(object): "UVISOR", "BLE", "CLIENT", "IPV4", "IPV6", "COMMON_PAL", "STORAGE" ] - def __init__(self, target, top_level_dirs=None): + def __init__(self, target, top_level_dirs=None, app_config=None): """Construct a mbed configuration Positional arguments: @@ -357,7 +359,8 @@ def __init__(self, target, top_level_dirs=None): Keyword argumets: top_level_dirs - a list of top level source directories (where - mbed_abb_config.json could be found) + mbed_app_config.json could be found) + app_config - location of a chosen mbed_app.json file NOTE: Construction of a Config object will look for the application configuration file in top_level_dirs. If found once, it'll parse it and @@ -366,18 +369,24 @@ def __init__(self, target, top_level_dirs=None): exception is raised. top_level_dirs may be None (in this case, the constructor will not search for a configuration file) """ - app_config_location = None - for directory in top_level_dirs or []: - full_path = os.path.join(directory, self.__mbed_app_config_name) - if os.path.isfile(full_path): - if app_config_location is not None: - raise ConfigException("Duplicate '%s' file in '%s' and '%s'" - % (self.__mbed_app_config_name, - app_config_location, full_path)) - else: - app_config_location = full_path - self.app_config_data = json_file_to_dict(app_config_location) \ - if app_config_location else {} + app_config_location = app_config + if app_config_location is None: + for directory in top_level_dirs or []: + full_path = os.path.join(directory, self.__mbed_app_config_name) + if os.path.isfile(full_path): + if app_config_location is not None: + raise ConfigException("Duplicate '%s' file in '%s' and '%s'" + % (self.__mbed_app_config_name, + app_config_location, full_path)) + else: + app_config_location = full_path + try: + self.app_config_data = json_file_to_dict(app_config_location) \ + if app_config_location else {} + except ValueError as exc: + sys.stderr.write(str(exc) + "\n") + self.app_config_data = {} + # Check the keys in the application configuration data unknown_keys = set(self.app_config_data.keys()) - \ self.__allowed_keys["application"] @@ -419,7 +428,12 @@ def add_config_files(self, flist): self.processed_configs[full_path] = True # Read the library configuration and add a "__full_config_path" # attribute to it - cfg = json_file_to_dict(config_file) + try: + cfg = json_file_to_dict(config_file) + except ValueError as exc: + sys.stderr.write(str(exc) + "\n") + continue + cfg["__config_path"] = full_path if "name" not in cfg: diff --git a/tools/export/__init__.py b/tools/export/__init__.py index 8ae7c69070e..301dc7117af 100644 --- a/tools/export/__init__.py +++ b/tools/export/__init__.py @@ -1,27 +1,28 @@ +"""The generic interface for all exporters. """ -mbed SDK -Copyright (c) 2011-2013 ARM Limited - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -""" +# mbed SDK +# Copyright (c) 2011-2016 ARM Limited +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. import os, tempfile from os.path import join, exists, basename from shutil import copytree, rmtree, copy import yaml -from tools.utils import mkdir -from tools.export import uvision4, uvision5, codered, gccarm, ds5_5, iar, emblocks, coide, kds, zip, simplicityv3, atmelstudio, sw4stm32, e2studio -from tools.export.exporters import zip_working_directory_and_clean_up, OldLibrariesException, FailedBuildException +from tools.export import uvision4, uvision5, codered, gccarm, ds5_5, iar +from tools.export import emblocks, coide, kds, simplicityv3, atmelstudio +from tools.export import sw4stm32, e2studio, zip +from tools.export.exporters import OldLibrariesException, FailedBuildException from tools.targets import TARGET_NAMES, EXPORT_MAP, TARGET_MAP from project_generator_definitions.definitions import ProGenDef @@ -41,6 +42,7 @@ 'atmelstudio' : atmelstudio.AtmelStudio, 'sw4stm32' : sw4stm32.Sw4STM32, 'e2studio' : e2studio.E2Studio, + 'zip' : zip.ZIP, } ERROR_MESSAGE_UNSUPPORTED_TOOLCHAIN = """ @@ -52,162 +54,25 @@ To export this project please import the export version of the mbed library. """ -def online_build_url_resolver(url): - # TODO: Retrieve the path and name of an online library build URL - return {'path':'', 'name':''} - - -def export(project_path, project_name, ide, target, destination='/tmp/', - tempdir=None, pgen_build = False, clean=True, extra_symbols=None, make_zip=True, sources_relative=False, - build_url_resolver=online_build_url_resolver, progen_build=False): - # Convention: we are using capitals for toolchain and target names - if target is not None: - target = target.upper() - - if tempdir is None: - tempdir = tempfile.mkdtemp() - - use_progen = False - supported = True - report = {'success': False, 'errormsg':'', 'skip': False} - - if ide is None or ide == "zip": - # Simple ZIP exporter - try: - ide = "zip" - exporter = zip.ZIP(target, tempdir, project_name, build_url_resolver, extra_symbols=extra_symbols) - exporter.scan_and_copy_resources(project_path, tempdir, sources_relative) - exporter.generate() - report['success'] = True - except OldLibrariesException, e: - report['errormsg'] = ERROR_MESSAGE_NOT_EXPORT_LIBS - else: - if ide not in EXPORTERS: - report['errormsg'] = ERROR_MESSAGE_UNSUPPORTED_TOOLCHAIN % (target, ide) - report['skip'] = True - else: - Exporter = EXPORTERS[ide] - target = EXPORT_MAP.get(target, target) - try: - if Exporter.PROGEN_ACTIVE: - use_progen = True - except AttributeError: - pass - - if target not in Exporter.TARGETS or Exporter.TOOLCHAIN not in TARGET_MAP[target].supported_toolchains: - supported = False - - if use_progen: - if not ProGenDef(ide).is_supported(TARGET_MAP[target].progen['target']): - supported = False - - if supported: - # target checked, export - try: - exporter = Exporter(target, tempdir, project_name, build_url_resolver, extra_symbols=extra_symbols, sources_relative=sources_relative) - exporter.scan_and_copy_resources(project_path, tempdir, sources_relative) - if progen_build: - #try to build with pgen ide builders - try: - exporter.generate(progen_build=True) - report['success'] = True - except FailedBuildException, f: - report['errormsg'] = "Build Failed" - else: - exporter.generate() - report['success'] = True - except OldLibrariesException, e: - report['errormsg'] = ERROR_MESSAGE_NOT_EXPORT_LIBS - - else: - report['errormsg'] = ERROR_MESSAGE_UNSUPPORTED_TOOLCHAIN % (target, ide) - report['skip'] = True +def mcu_ide_matrix(verbose_html=False): + """Shows target map using prettytable - zip_path = None - if report['success']: - # readme.txt to contain more exported data - exporter_yaml = { - 'project_generator': { - 'active' : False, - } - } - if use_progen: - try: - import pkg_resources - version = pkg_resources.get_distribution('project_generator').version - exporter_yaml['project_generator']['version'] = version - exporter_yaml['project_generator']['active'] = True; - exporter_yaml['project_generator_definitions'] = {} - version = pkg_resources.get_distribution('project_generator_definitions').version - exporter_yaml['project_generator_definitions']['version'] = version - except ImportError: - pass - with open(os.path.join(tempdir, 'exporter.yaml'), 'w') as outfile: - yaml.dump(exporter_yaml, outfile, default_flow_style=False) - # add readme file to every offline export. - open(os.path.join(tempdir, 'GettingStarted.htm'),'w').write(''% (ide)) - # copy .hgignore file to exported direcotry as well. - if exists(os.path.join(exporter.TEMPLATE_DIR,'.hgignore')): - copy(os.path.join(exporter.TEMPLATE_DIR,'.hgignore'), tempdir) - if make_zip: - zip_path = zip_working_directory_and_clean_up(tempdir, destination, project_name, clean) - else: - zip_path = destination - - return zip_path, report - - -############################################################################### -# Generate project folders following the online conventions -############################################################################### -def copy_tree(src, dst, clean=True): - if exists(dst): - if clean: - rmtree(dst) - else: - return - - copytree(src, dst) - - -def setup_user_prj(user_dir, prj_path, lib_paths=None): - """ - Setup a project with the same directory structure of the mbed online IDE + Keyword argumets: + verbose_html - print the matrix in html format """ - mkdir(user_dir) - - # Project Path - copy_tree(prj_path, join(user_dir, "src")) - - # Project Libraries - user_lib = join(user_dir, "lib") - mkdir(user_lib) - - if lib_paths is not None: - for lib_path in lib_paths: - copy_tree(lib_path, join(user_lib, basename(lib_path))) - -def mcu_ide_matrix(verbose_html=False, platform_filter=None): - """ Shows target map using prettytable """ - supported_ides = [] - for key in EXPORTERS.iterkeys(): - supported_ides.append(key) - supported_ides.sort() - from prettytable import PrettyTable, ALL # Only use it in this function so building works without extra modules + supported_ides = sorted(EXPORTERS.keys()) + # Only use it in this function so building works without extra modules + from prettytable import PrettyTable, ALL # All tests status table print - columns = ["Platform"] + supported_ides - pt = PrettyTable(columns) + table_printer = PrettyTable(["Platform"] + supported_ides) # Align table - for col in columns: - pt.align[col] = "c" - pt.align["Platform"] = "l" + for col in supported_ides: + table_printer.align[col] = "c" + table_printer.align["Platform"] = "l" perm_counter = 0 - target_counter = 0 for target in sorted(TARGET_NAMES): - target_counter += 1 - row = [target] # First column is platform name for ide in supported_ides: text = "-" @@ -218,20 +83,24 @@ def mcu_ide_matrix(verbose_html=False, platform_filter=None): text = "x" perm_counter += 1 row.append(text) - pt.add_row(row) + table_printer.add_row(row) - pt.border = True - pt.vrules = ALL - pt.hrules = ALL - # creates a html page suitable for a browser - # result = pt.get_html_string(format=True) if verbose_html else pt.get_string() + table_printer.border = True + table_printer.vrules = ALL + table_printer.hrules = ALL # creates a html page in a shorter format suitable for readme.md - result = pt.get_html_string() if verbose_html else pt.get_string() + if verbose_html: + result = table_printer.get_html_string() + else: + result = table_printer.get_string() result += "\n" result += "Total IDEs: %d\n"% (len(supported_ides)) - if verbose_html: result += "
" - result += "Total platforms: %d\n"% (target_counter) - if verbose_html: result += "
" + if verbose_html: + result += "
" + result += "Total platforms: %d\n"% (len(TARGET_NAMES)) + if verbose_html: + result += "
" result += "Total permutations: %d"% (perm_counter) - if verbose_html: result = result.replace("&", "&") + if verbose_html: + result = result.replace("&", "&") return result diff --git a/tools/export/atmelstudio.py b/tools/export/atmelstudio.py index f85a047b641..66c3c43020f 100644 --- a/tools/export/atmelstudio.py +++ b/tools/export/atmelstudio.py @@ -1,6 +1,6 @@ """ mbed SDK -Copyright (c) 2011-2015 ARM Limited +Copyright (c) 2011-2016 ARM Limited Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -61,7 +61,7 @@ def generate(self): ctx = { 'target': self.target, - 'name': self.program_name, + 'name': self.project_name, 'source_files': source_files, 'source_folders': source_folders, 'object_files': self.resources.objects, @@ -69,11 +69,11 @@ def generate(self): 'library_paths': self.resources.lib_dirs, 'linker_script': self.resources.linker_script, 'libraries': libraries, - 'symbols': self.get_symbols(), + 'symbols': self.toolchain.get_symbols(), 'solution_uuid': solution_uuid.upper(), 'project_uuid': project_uuid.upper() } - ctx.update(self.progen_flags) + ctx.update(self.flags) target = self.target.lower() - self.gen_file('atmelstudio6_2.atsln.tmpl', ctx, '%s.atsln' % self.program_name) - self.gen_file('atmelstudio6_2.cppproj.tmpl', ctx, '%s.cppproj' % self.program_name) + self.gen_file('atmelstudio6_2.atsln.tmpl', ctx, '%s.atsln' % self.project_name) + self.gen_file('atmelstudio6_2.cppproj.tmpl', ctx, '%s.cppproj' % self.project_name) diff --git a/tools/export/codered.py b/tools/export/codered.py index d7f815a8278..185e69a60dc 100644 --- a/tools/export/codered.py +++ b/tools/export/codered.py @@ -1,6 +1,6 @@ """ mbed SDK -Copyright (c) 2011-2013 ARM Limited +Copyright (c) 2011-2016 ARM Limited Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -48,13 +48,13 @@ def generate(self): libraries.append(l[3:]) ctx = { - 'name': self.program_name, + 'name': self.project_name, 'include_paths': self.resources.inc_dirs, 'linker_script': self.resources.linker_script, 'object_files': self.resources.objects, 'libraries': libraries, - 'symbols': self.get_symbols() + 'symbols': self.toolchain.get_symbols() } - ctx.update(self.progen_flags) + ctx.update(self.flags) self.gen_file('codered_%s_project.tmpl' % self.target.lower(), ctx, '.project') self.gen_file('codered_%s_cproject.tmpl' % self.target.lower(), ctx, '.cproject') diff --git a/tools/export/coide.py b/tools/export/coide.py index 77390afdd8a..cde592c0832 100644 --- a/tools/export/coide.py +++ b/tools/export/coide.py @@ -1,6 +1,6 @@ """ mbed SDK -Copyright (c) 2014 ARM Limited +Copyright (c) 2014-2016 ARM Limited Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -43,6 +43,7 @@ class CoIDE(Exporter): 'NUCLEO_F303K8', 'NUCLEO_F303RE', 'NUCLEO_F334R8', + 'NUCLEO_F303ZE', 'NUCLEO_F401RE', 'NUCLEO_F410RB', 'NUCLEO_F411RE', @@ -98,7 +99,7 @@ def generate(self): self.resources.linker_script = '' ctx = { - 'name': self.program_name, + 'name': self.project_name, 'source_files': source_files, 'header_files': header_files, 'include_paths': self.resources.inc_dirs, @@ -106,9 +107,9 @@ def generate(self): 'library_paths': self.resources.lib_dirs, 'object_files': self.resources.objects, 'libraries': libraries, - 'symbols': self.get_symbols() + 'symbols': self.toolchain.get_symbols() } target = self.target.lower() # Project file - self.gen_file('coide_%s.coproj.tmpl' % target, ctx, '%s.coproj' % self.program_name) + self.gen_file('coide_%s.coproj.tmpl' % target, ctx, '%s.coproj' % self.project_name) diff --git a/tools/export/ds5_5.py b/tools/export/ds5_5.py index 71242efdd73..9be2535867a 100644 --- a/tools/export/ds5_5.py +++ b/tools/export/ds5_5.py @@ -1,6 +1,6 @@ """ mbed SDK -Copyright (c) 2011-2013 ARM Limited +Copyright (c) 2011-2016 ARM Limited Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -54,12 +54,12 @@ def generate(self): }) ctx = { - 'name': self.program_name, + 'name': self.project_name, 'include_paths': self.resources.inc_dirs, 'scatter_file': self.resources.linker_script, 'object_files': self.resources.objects + self.resources.libraries, 'source_files': source_files, - 'symbols': self.get_symbols() + 'symbols': self.toolchain.get_symbols() } target = self.target.lower() diff --git a/tools/export/e2studio.py b/tools/export/e2studio.py index 66cd9dec9b3..205287089ad 100644 --- a/tools/export/e2studio.py +++ b/tools/export/e2studio.py @@ -1,6 +1,6 @@ """ mbed SDK -Copyright (c) 2011-2013 ARM Limited +Copyright (c) 2011-2016 ARM Limited Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -33,15 +33,15 @@ def generate(self): libraries.append(l[3:]) ctx = { - 'name': self.program_name, + 'name': self.project_name, 'include_paths': self.resources.inc_dirs, 'linker_script': self.resources.linker_script, 'object_files': self.resources.objects, 'libraries': libraries, - 'symbols': self.get_symbols() + 'symbols': self.toolchain.get_symbols() } self.gen_file('e2studio_%s_project.tmpl' % self.target.lower(), ctx, '.project') self.gen_file('e2studio_%s_cproject.tmpl' % self.target.lower(), ctx, '.cproject') self.gen_file('e2studio_%s_gdbinit.tmpl' % self.target.lower(), ctx, '.gdbinit') - self.gen_file('e2studio_launch.tmpl', ctx, '%s OpenOCD.launch' % self.program_name) + self.gen_file('e2studio_launch.tmpl', ctx, '%s OpenOCD.launch' % self.project_name) diff --git a/tools/export/emblocks.py b/tools/export/emblocks.py index a5f20d2c9d9..9e241994529 100644 --- a/tools/export/emblocks.py +++ b/tools/export/emblocks.py @@ -1,6 +1,6 @@ """ mbed SDK -Copyright (c) 2014 ARM Limited +Copyright (c) 2014-2016 ARM Limited Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -60,7 +60,7 @@ def generate(self): self.resources.linker_script = '' ctx = { - 'name': self.program_name, + 'name': self.project_name, 'target': self.target, 'toolchain': self.toolchain.name, 'source_files': source_files, @@ -68,13 +68,13 @@ def generate(self): 'script_file': self.resources.linker_script, 'library_paths': self.resources.lib_dirs, 'libraries': libraries, - 'symbols': self.get_symbols(), + 'symbols': self.toolchain.get_symbols(), 'object_files': self.resources.objects, 'sys_libs': self.toolchain.sys_libs, - 'cc_org': self.flags['common'] + self.flags['c'], - 'ld_org': self.flags['common'] + self.flags['ld'], - 'cppc_org': self.flags['common'] + self.flags['cxx'] + 'cc_org': self.flags['common_flags'] + self.flags['c_flags'], + 'ld_org': self.flags['common_flags'] + self.flags['ld_flags'], + 'cppc_org': self.flags['common_flags'] + self.flags['cxx_flags'] } # EmBlocks intermediate file template - self.gen_file('emblocks.eix.tmpl', ctx, '%s.eix' % self.program_name) + self.gen_file('emblocks.eix.tmpl', ctx, '%s.eix' % self.project_name) diff --git a/tools/export/exporters.py b/tools/export/exporters.py index d1846372e56..c3b381547c6 100644 --- a/tools/export/exporters.py +++ b/tools/export/exporters.py @@ -1,256 +1,219 @@ """Just a template for subclassing""" -import uuid, shutil, os, logging, fnmatch -from os import walk, remove -from os.path import join, dirname, isdir, split -from copy import copy -from jinja2 import Template, FileSystemLoader +import os +import sys +import logging +from os.path import join, dirname, relpath +from itertools import groupby +from jinja2 import FileSystemLoader from jinja2.environment import Environment -from contextlib import closing -from zipfile import ZipFile, ZIP_DEFLATED -from operator import add -from tools.utils import mkdir -from tools.toolchains import TOOLCHAIN_CLASSES from tools.targets import TARGET_MAP - -from project_generator.generate import Generator -from project_generator.project import Project +from project_generator.tools import tool +from project_generator.tools_supported import ToolsSupported from project_generator.settings import ProjectSettings +from project_generator_definitions.definitions import ProGenDef + -from tools.config import Config +class OldLibrariesException(Exception): + """Exception that indicates an export can not complete due to an out of date + library version. + """ + pass -class OldLibrariesException(Exception): pass +class FailedBuildException(Exception): + """Exception that indicates that a build failed""" + pass -class FailedBuildException(Exception) : pass +class TargetNotSupportedException(Exception): + """Indicates that an IDE does not support a particular MCU""" + pass -# Exporter descriptor for TARGETS -# TARGETS as class attribute for backward compatibility (allows: if in Exporter.TARGETS) class ExporterTargetsProperty(object): + """ Exporter descriptor for TARGETS + TARGETS as class attribute for backward compatibility + (allows: if in Exporter.TARGETS) + """ def __init__(self, func): self.func = func def __get__(self, inst, cls): return self.func(cls) class Exporter(object): + """Exporter base class + + This class is meant to be extended by individual exporters, and provides a + few helper methods for implementing an exporter with either jinja2 or + progen. + """ TEMPLATE_DIR = dirname(__file__) DOT_IN_RELATIVE_PATH = False - - def __init__(self, target, inputDir, program_name, build_url_resolver, extra_symbols=None, sources_relative=True): - self.inputDir = inputDir + NAME = None + TARGETS = None + TOOLCHAIN = None + + def __init__(self, target, export_dir, project_name, toolchain, + extra_symbols=None, resources=None): + """Initialize an instance of class exporter + Positional arguments: + target - the target mcu/board for this project + export_dir - the directory of the exported project files + project_name - the name of the project + toolchain - an instance of class toolchain + + Keyword arguments: + extra_symbols - a list of extra macros for the toolchain + resources - an instance of class Resources + """ + self.export_dir = export_dir self.target = target - self.program_name = program_name - self.toolchain = TOOLCHAIN_CLASSES[self.get_toolchain()](TARGET_MAP[target]) - self.build_url_resolver = build_url_resolver + self.project_name = project_name + self.toolchain = toolchain jinja_loader = FileSystemLoader(os.path.dirname(os.path.abspath(__file__))) self.jinja_environment = Environment(loader=jinja_loader) - self.extra_symbols = extra_symbols if extra_symbols else [] - self.config_macros = [] - self.sources_relative = sources_relative - self.config_header = None + self.resources = resources + self.generated_files = [] + self.builder_files_dict = {} def get_toolchain(self): + """A helper getter function that we should probably eliminate""" return self.TOOLCHAIN @property def flags(self): - return self.toolchain.flags - - @property - def progen_flags(self): - if not hasattr(self, "_progen_flag_cache") : - self._progen_flag_cache = dict([(key + "_flags", value) for key,value in self.flags.iteritems()]) - asm_defines = ["-D"+symbol for symbol in self.toolchain.get_symbols(True)] - c_defines = ["-D" + symbol for symbol in self.toolchain.get_symbols()] - self._progen_flag_cache['asm_flags'] += asm_defines - self._progen_flag_cache['c_flags'] += c_defines - self._progen_flag_cache['cxx_flags'] += c_defines - if self.config_header: - self._progen_flag_cache['c_flags'] += self.toolchain.get_config_option(self.config_header) - self._progen_flag_cache['cxx_flags'] += self.toolchain.get_config_option(self.config_header) - return self._progen_flag_cache - - def __scan_and_copy(self, src_path, trg_path): - resources = self.toolchain.scan_resources(src_path) - - for r_type in ['headers', 's_sources', 'c_sources', 'cpp_sources', - 'objects', 'libraries', 'linker_script', - 'lib_builds', 'lib_refs', 'hex_files', 'bin_files']: - r = getattr(resources, r_type) - if r: - self.toolchain.copy_files(r, trg_path, resources=resources) - return resources - - @staticmethod - def _get_dir_grouped_files(files): - """ Get grouped files based on the dirname """ - files_grouped = {} - for file in files: - rel_path = os.path.relpath(file, os.getcwd()) - dir_path = os.path.dirname(rel_path) - if dir_path == '': - # all files within the current dir go into Source_Files - dir_path = 'Source_Files' - if not dir_path in files_grouped.keys(): - files_grouped[dir_path] = [] - files_grouped[dir_path].append(file) - return files_grouped + """Returns a dictionary of toolchain flags. + Keys of the dictionary are: + cxx_flags - c++ flags + c_flags - c flags + ld_flags - linker flags + asm_flags - assembler flags + common_flags - common options + """ + config_header = self.toolchain.get_config_header() + flags = {key + "_flags": value for key, value + in self.toolchain.flags.iteritems()} + asm_defines = ["-D" + symbol for symbol in self.toolchain.get_symbols(True)] + c_defines = ["-D" + symbol for symbol in self.toolchain.get_symbols()] + flags['asm_flags'] += asm_defines + flags['c_flags'] += c_defines + flags['cxx_flags'] += c_defines + if config_header: + config_header = relpath(config_header, + self.resources.file_basepath[config_header]) + flags['c_flags'] += self.toolchain.get_config_option(config_header) + flags['cxx_flags'] += self.toolchain.get_config_option( + config_header) + return flags + + def get_source_paths(self): + """Returns a list of the directories where source files are contained""" + source_keys = ['s_sources', 'c_sources', 'cpp_sources', 'hex_files', + 'objects', 'libraries'] + source_files = [] + for key in source_keys: + source_files.extend(getattr(self.resources, key)) + return list(set([os.path.dirname(src) for src in source_files])) def progen_get_project_data(self): """ Get ProGen project data """ # provide default data, some tools don't require any additional # tool specific settings - code_files = [] - for r_type in ['c_sources', 'cpp_sources', 's_sources']: - for file in getattr(self.resources, r_type): - code_files.append(file) - - sources_files = code_files + self.resources.hex_files + self.resources.objects + \ - self.resources.libraries - sources_grouped = Exporter._get_dir_grouped_files(sources_files) - headers_grouped = Exporter._get_dir_grouped_files(self.resources.headers) - project_data = { - 'common': { - 'sources': sources_grouped, - 'includes': headers_grouped, - 'build_dir':'.build', - 'target': [TARGET_MAP[self.target].progen['target']], - 'macros': self.get_symbols(), - 'export_dir': [self.inputDir], - 'linker_file': [self.resources.linker_script], - } - } + def make_key(src): + """turn a source file into it's group name""" + key = os.path.basename(os.path.dirname(src)) + if not key: + key = os.path.basename(os.path.normpath(self.export_dir)) + return key + + def grouped(sources): + """Group the source files by their encompassing directory""" + data = sorted(sources, key=make_key) + return {k: list(g) for k, g in groupby(data, make_key)} + + if self.toolchain.get_config_header(): + config_header = self.toolchain.get_config_header() + config_header = relpath(config_header, + self.resources.file_basepath[config_header]) + else: + config_header = None + + # we want to add this to our include dirs + config_dir = os.path.dirname(config_header) if config_header else [] + + project_data = tool.get_tool_template() + + project_data['target'] = TARGET_MAP[self.target].progen['target'] + project_data['source_paths'] = self.get_source_paths() + project_data['include_paths'] = self.resources.inc_dirs + [config_dir] + project_data['include_files'] = grouped(self.resources.headers) + project_data['source_files_s'] = grouped(self.resources.s_sources) + project_data['source_files_c'] = grouped(self.resources.c_sources) + project_data['source_files_cpp'] = grouped(self.resources.cpp_sources) + project_data['source_files_obj'] = grouped(self.resources.objects) + project_data['source_files_lib'] = grouped(self.resources.libraries) + project_data['output_dir']['path'] = self.export_dir + project_data['linker_file'] = self.resources.linker_script + project_data['macros'] = [] + project_data['build_dir'] = 'build' + project_data['template'] = None + project_data['name'] = self.project_name + project_data['output_type'] = 'exe' + project_data['debugger'] = None return project_data - def progen_gen_file(self, tool_name, project_data, progen_build=False): - """ Generate project using ProGen Project API """ + def progen_gen_file(self, project_data): + """ Generate project using ProGen Project API + Positional arguments: + tool_name - the tool for which to generate project files + project_data - a dict whose base key, values are specified in + progen_get_project_data, the items will have been + modified by Exporter subclasses + + Keyword arguments: + progen_build - A boolean that determines if the tool will build the + project + """ + if not self.check_supported(self.NAME): + raise TargetNotSupportedException("Target not supported") settings = ProjectSettings() - project = Project(self.program_name, [project_data], settings) - # TODO: Fix this, the inc_dirs are not valid (our scripts copy files), therefore progen - # thinks it is not dict but a file, and adds them to workspace. - project.project['common']['include_paths'] = self.resources.inc_dirs - project.generate(tool_name, copied=not self.sources_relative) - if progen_build: - print("Project exported, building...") - result = project.build(tool_name) - if result == -1: - raise FailedBuildException("Build Failed") - - def __scan_all(self, path): - resources = [] - - for root, dirs, files in walk(path): - for d in copy(dirs): - if d == '.' or d == '..': - dirs.remove(d) - - for file in files: - file_path = join(root, file) - resources.append(file_path) - - return resources - - def scan_and_copy_resources(self, prj_paths, trg_path, relative=False): - # Copy only the file for the required target and toolchain - lib_builds = [] - # Create the configuration object - if isinstance(prj_paths, basestring): - prj_paths = [prj_paths] - config = Config(self.target, prj_paths) - for src in ['lib', 'src']: - resources = self.__scan_and_copy(join(prj_paths[0], src), trg_path) - for path in prj_paths[1:]: - resources.add(self.__scan_and_copy(join(path, src), trg_path)) - - lib_builds.extend(resources.lib_builds) - - # The repository files - #for repo_dir in resources.repo_dirs: - # repo_files = self.__scan_all(repo_dir) - # for path in prj_paths: - # self.toolchain.copy_files(repo_files, trg_path, rel_path=join(path, src)) - - # The libraries builds - for bld in lib_builds: - build_url = open(bld).read().strip() - lib_data = self.build_url_resolver(build_url) - lib_path = lib_data['path'].rstrip('\\/') - self.__scan_and_copy(lib_path, join(trg_path, lib_data['name'])) - - # Create .hg dir in mbed build dir so it's ignored when versioning - hgdir = join(trg_path, lib_data['name'], '.hg') - mkdir(hgdir) - fhandle = file(join(hgdir, 'keep.me'), 'a') - fhandle.close() - - if not relative: - # Final scan of the actual exported resources - resources = self.toolchain.scan_resources(trg_path) - resources.relative_to(trg_path, self.DOT_IN_RELATIVE_PATH) - else: - # use the prj_dir (source, not destination) - resources = self.toolchain.scan_resources(prj_paths[0]) - for path in prj_paths[1:]: - resources.add(toolchain.scan_resources(path)) - - # Loads the resources into the config system which might expand/modify resources based on config data - self.resources = config.load_resources(resources) - - if hasattr(self, "MBED_CONFIG_HEADER_SUPPORTED") and self.MBED_CONFIG_HEADER_SUPPORTED : - # Add the configuration file to the target directory - self.config_header = self.toolchain.MBED_CONFIG_FILE_NAME - config.get_config_data_header(join(trg_path, self.config_header)) - self.config_macros = [] - self.resources.inc_dirs.append(".") - else: - # And add the configuration macros to the toolchain - self.config_macros = config.get_config_data_macros() + exporter = ToolsSupported().get_tool(self.NAME) + self.builder_files_dict = {self.NAME:exporter(project_data, settings).export_project()} + for middle in self.builder_files_dict.values(): + for field, thing in middle.iteritems(): + if field == "files": + for filename in thing.values(): + self.generated_files.append(filename) + + def progen_build(self): + """Build a project that was already generated by progen""" + print("Project {} exported, building for {}...".format( + self.project_name, self.NAME)) + sys.stdout.flush() + builder = ToolsSupported().get_tool(self.NAME) + result = builder(self.builder_files_dict[self.NAME], ProjectSettings()).build_project() + if result == -1: + raise FailedBuildException("Build Failed") + + def check_supported(self, ide): + """Indicated if this combination of IDE and MCU is supported""" + if self.target not in self.TARGETS or \ + self.TOOLCHAIN not in TARGET_MAP[self.target].supported_toolchains: + return False + if not ProGenDef(ide).is_supported( + TARGET_MAP[self.target].progen['target']): + return False + return True def gen_file(self, template_file, data, target_file): - template_path = join(Exporter.TEMPLATE_DIR, template_file) - template = self.jinja_environment.get_template(template_file) + """Generates a project file from a template using jinja""" + jinja_loader = FileSystemLoader( + os.path.dirname(os.path.abspath(__file__))) + jinja_environment = Environment(loader=jinja_loader) + + template = jinja_environment.get_template(template_file) target_text = template.render(data) - target_path = join(self.inputDir, target_file) - logging.debug("Generating: %s" % target_path) + target_path = join(self.export_dir, target_file) + logging.debug("Generating: %s", target_path) open(target_path, "w").write(target_text) - - def get_symbols(self, add_extra_symbols=True): - """ This function returns symbols which must be exported. - Please add / overwrite symbols in each exporter separately - """ - - # We have extra symbols from e.g. libraries, we want to have them also added to export - extra = self.extra_symbols if add_extra_symbols else [] - if hasattr(self, "MBED_CONFIG_HEADER_SUPPORTED") and self.MBED_CONFIG_HEADER_SUPPORTED: - # If the config header is supported, we will preinclude it and do not not - # need the macros as preprocessor flags - return extra - - symbols = self.toolchain.get_symbols(True) + self.toolchain.get_symbols() \ - + self.config_macros + extra - return symbols - -def zip_working_directory_and_clean_up(tempdirectory=None, destination=None, program_name=None, clean=True): - uid = str(uuid.uuid4()) - zipfilename = '%s.zip'%uid - - logging.debug("Zipping up %s to %s" % (tempdirectory, join(destination, zipfilename))) - # make zip - def zipdir(basedir, archivename): - assert isdir(basedir) - fakeroot = program_name + '/' - with closing(ZipFile(archivename, "w", ZIP_DEFLATED)) as z: - for root, _, files in os.walk(basedir): - # NOTE: ignore empty directories - for fn in files: - absfn = join(root, fn) - zfn = fakeroot + '/' + absfn[len(basedir)+len(os.sep):] - z.write(absfn, zfn) - - zipdir(tempdirectory, join(destination, zipfilename)) - - if clean: - shutil.rmtree(tempdirectory) - - return join(destination, zipfilename) + self.generated_files += [target_path] diff --git a/tools/export/gcc_arm_disco_f769ni.tmpl b/tools/export/gcc_arm_disco_f769ni.tmpl new file mode 100644 index 00000000000..6e616cc8842 --- /dev/null +++ b/tools/export/gcc_arm_disco_f769ni.tmpl @@ -0,0 +1 @@ +{% extends "gcc_arm_common.tmpl" %} diff --git a/tools/export/gcc_arm_mtm_mtconnect04S.tmpl b/tools/export/gcc_arm_mtm_mtconnect04S.tmpl new file mode 100644 index 00000000000..a2d1df6b721 --- /dev/null +++ b/tools/export/gcc_arm_mtm_mtconnect04S.tmpl @@ -0,0 +1,14 @@ +{% extends "gcc_arm_common.tmpl" %} + +{% block additional_variables %} +SOFTDEVICE = mbed/TARGET_MTM_MTCONNECT04S/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s130_nrf51822_1_0_0/s130_nrf51_1.0.0_softdevice.hex +{% endblock %} + +{% block additional_executables %} +SREC_CAT = srec_cat +{% endblock %} + +{% block additional_targets %} +merge: + $(SREC_CAT) $(SOFTDEVICE) -intel $(PROJECT).hex -intel -o combined.hex -intel --line-length=44 +{% endblock %} diff --git a/tools/export/gcc_arm_nucleo_f303ke.tmpl b/tools/export/gcc_arm_nucleo_f303ke.tmpl new file mode 100644 index 00000000000..6e616cc8842 --- /dev/null +++ b/tools/export/gcc_arm_nucleo_f303ke.tmpl @@ -0,0 +1 @@ +{% extends "gcc_arm_common.tmpl" %} diff --git a/tools/export/gccarm.py b/tools/export/gccarm.py index 3cdb0477ff1..148fdd04e1b 100644 --- a/tools/export/gccarm.py +++ b/tools/export/gccarm.py @@ -1,6 +1,6 @@ """ mbed SDK -Copyright (c) 2011-2013 ARM Limited +Copyright (c) 2011-2016 ARM Limited Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -14,9 +14,9 @@ See the License for the specific language governing permissions and limitations under the License. """ -from exporters import Exporter -from os.path import splitext, basename, relpath, join, abspath +from os.path import splitext, basename, relpath, join, abspath, dirname from os import curdir, getcwd +from tools.export.exporters import Exporter class GccArm(Exporter): @@ -53,6 +53,7 @@ class GccArm(Exporter): 'DISCO_F469NI', 'DISCO_F303VC', 'DISCO_F746NG', + 'DISCO_F769NI', 'DISCO_L476VG', 'UBLOX_C027', 'ARCH_PRO', @@ -87,6 +88,7 @@ class GccArm(Exporter): 'NUCLEO_F303K8', 'NUCLEO_F303RE', 'NUCLEO_F334R8', + 'NUCLEO_F303ZE', 'NUCLEO_F746ZG', 'NUCLEO_F767ZI', 'DISCO_L053C8', @@ -106,6 +108,7 @@ class GccArm(Exporter): 'NRF51_DK', 'NRF51_DONGLE', 'NRF51_MICROBIT', + 'MTM_MTCONNECT04S', 'SEEED_TINY_BLE', 'DISCO_F401VC', 'DELTA_DFCM_NNN40', @@ -135,8 +138,6 @@ class GccArm(Exporter): def generate(self): # "make" wants Unix paths - if self.sources_relative: - self.resources.relative_to(self.prj_paths[0]) self.resources.win_to_unix() to_be_compiled = [] @@ -152,19 +153,20 @@ def generate(self): l, _ = splitext(basename(lib)) libraries.append(l[3:]) - build_dir = abspath(join(self.inputDir, ".build")) ctx = { - 'name': self.program_name, + 'name': self.project_name, 'to_be_compiled': to_be_compiled, 'object_files': self.resources.objects, 'include_paths': self.resources.inc_dirs, 'library_paths': self.resources.lib_dirs, 'linker_script': self.resources.linker_script, 'libraries': libraries, - 'symbols': self.get_symbols(), + 'symbols': self.toolchain.get_symbols(), 'cpu_flags': self.toolchain.cpu, - 'vpath': [relpath(s, build_dir) for s in self.prj_paths] if self.sources_relative else [".."], - 'hex_files': self.resources.hex_files + 'hex_files': self.resources.hex_files, + 'vpath': (["../../.."] + if basename(dirname(dirname(self.export_dir))) == "projectfiles" + else [".."]) } for key in ['include_paths', 'library_paths', 'linker_script', 'hex_files']: @@ -174,9 +176,5 @@ def generate(self): ctx[key] = ctx['vpath'][0] + "/" + ctx[key] if "../." not in ctx["include_paths"]: ctx["include_paths"] += ['../.'] - ctx.update(self.progen_flags) + ctx.update(self.flags) self.gen_file('gcc_arm_%s.tmpl' % self.target.lower(), ctx, 'Makefile') - - def scan_and_copy_resources(self, prj_paths, trg_path, relative=False): - self.prj_paths = prj_paths - Exporter.scan_and_copy_resources(self, prj_paths, trg_path, relative) diff --git a/tools/export/iar.py b/tools/export/iar.py index 5c52a3d1ec4..3ca488d6669 100644 --- a/tools/export/iar.py +++ b/tools/export/iar.py @@ -1,6 +1,6 @@ """ mbed SDK -Copyright (c) 2011-2015 ARM Limited +Copyright (c) 2011-2016 ARM Limited Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -28,7 +28,7 @@ class IAREmbeddedWorkbench(Exporter): Exporter class for IAR Systems. This class uses project generator. """ # These 2 are currently for exporters backward compatiblity - NAME = 'IAR' + NAME = 'iar_arm' TOOLCHAIN = 'IAR' # PROGEN_ACTIVE contains information for exporter scripts that this is using progen PROGEN_ACTIVE = True @@ -50,39 +50,23 @@ def TARGETS(cls): continue return cls._targets_supported - def generate(self, progen_build=False): + def generate(self): """ Generates the project files """ project_data = self.progen_get_project_data() - tool_specific = {} - # Expand tool specific settings by IAR specific settings which are required try: if TARGET_MAP[self.target].progen['iar']['template']: - tool_specific['iar'] = TARGET_MAP[self.target].progen['iar'] + project_data['template']=TARGET_MAP[self.target].progen['iar']['template'] except KeyError: # use default template # by the mbed projects - tool_specific['iar'] = { - # We currently don't use misc, template sets those for us - # 'misc': { - # 'cxx_flags': ['--no_rtti', '--no_exceptions'], - # 'c_flags': ['--diag_suppress=Pa050,Pa084,Pa093,Pa082'], - # 'ld_flags': ['--skip_dynamic_initialization'], - # }, - 'template': [os.path.join(os.path.dirname(__file__), 'iar_template.ewp.tmpl')], - } - - project_data['tool_specific'] = {} - project_data['tool_specific'].setdefault("iar", {}) - project_data['tool_specific']['iar'].setdefault("misc", {}) - project_data['tool_specific']['iar'].update(tool_specific['iar']) - project_data['tool_specific']['iar']['misc'].update(self.progen_flags) + project_data['template']=[os.path.join(os.path.dirname(__file__), 'iar_template.ewp.tmpl')] + + project_data['misc'] = self.flags # VLA is enabled via template IccAllowVLA - project_data['tool_specific']['iar']['misc']['c_flags'].remove("--vla") - project_data['common']['build_dir'] = os.path.join(project_data['common']['build_dir'], 'iar_arm') - if progen_build: - self.progen_gen_file('iar_arm', project_data, True) - else: - self.progen_gen_file('iar_arm', project_data) + project_data['misc']['c_flags'].remove("--vla") + project_data['misc']['asm_flags'] = list(set(project_data['misc']['asm_flags'])) + project_data['build_dir'] = os.path.join(project_data['build_dir'], 'iar_arm') + self.progen_gen_file(project_data) # Currently not used, we should reuse folder_name to create virtual folders class IarFolder(): diff --git a/tools/export/kds.py b/tools/export/kds.py index 13c038debaf..b77a507f176 100644 --- a/tools/export/kds.py +++ b/tools/export/kds.py @@ -1,6 +1,6 @@ """ mbed SDK -Copyright (c) 2011-2013 ARM Limited +Copyright (c) 2011-2016 ARM Limited Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -35,13 +35,13 @@ def generate(self): libraries.append(l[3:]) ctx = { - 'name': self.program_name, + 'name': self.project_name, 'include_paths': self.resources.inc_dirs, 'linker_script': self.resources.linker_script, 'object_files': self.resources.objects, 'libraries': libraries, - 'symbols': self.get_symbols() + 'symbols': self.toolchain.get_symbols() } self.gen_file('kds_%s_project.tmpl' % self.target.lower(), ctx, '.project') self.gen_file('kds_%s_cproject.tmpl' % self.target.lower(), ctx, '.cproject') - self.gen_file('kds_launch.tmpl', ctx, '%s.launch' % self.program_name) + self.gen_file('kds_launch.tmpl', ctx, '%s.launch' % self.project_name) diff --git a/tools/export/simplicityv3.py b/tools/export/simplicityv3.py index 3254152127b..ba6f6f185bf 100644 --- a/tools/export/simplicityv3.py +++ b/tools/export/simplicityv3.py @@ -1,6 +1,6 @@ """ mbed SDK -Copyright (c) 2014 ARM Limited +Copyright (c) 2014-2016 ARM Limited Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -147,7 +147,7 @@ def generate(self): libraries.append(l[3:]) defines = [] - for define in self.get_symbols(): + for define in self.toolchain.get_symbols(): if '=' in define: keyval = define.split('=') defines.append( (keyval[0], keyval[1]) ) @@ -157,7 +157,7 @@ def generate(self): self.check_and_add_path(split(self.resources.linker_script)[0]) ctx = { - 'name': self.program_name, + 'name': self.project_name, 'main_files': main_files, 'recursiveFolders': self.orderedPaths, 'object_files': self.resources.objects, @@ -165,13 +165,12 @@ def generate(self): 'library_paths': self.resources.lib_dirs, 'linker_script': self.resources.linker_script, 'libraries': libraries, - 'symbols': self.get_symbols(), 'defines': defines, 'part': self.PARTS[self.target], 'kit': self.KITS[self.target], 'loopcount': 0 } - ctx.update(self.progen_flags) + ctx.update(self.flags) ## Strip main folder from include paths because ssproj is not capable of handling it if '.' in ctx['include_paths']: @@ -191,4 +190,4 @@ def generate(self): print("\t" + bpath.name + "\n") ''' - self.gen_file('simplicityv3_slsproj.tmpl', ctx, '%s.slsproj' % self.program_name) + self.gen_file('simplicityv3_slsproj.tmpl', ctx, '%s.slsproj' % self.project_name) diff --git a/tools/export/sw4stm32.py b/tools/export/sw4stm32.py index bacc02260cc..11878cdfa91 100644 --- a/tools/export/sw4stm32.py +++ b/tools/export/sw4stm32.py @@ -44,6 +44,7 @@ class Sw4STM32(Exporter): 'NUCLEO_F302R8': {'name': 'NUCLEO-F302R8', 'mcuId': 'STM32F302R8Tx'}, 'NUCLEO_F303RE': {'name': 'NUCLEO-F303RE', 'mcuId': 'STM32F303RETx'}, 'NUCLEO_F334R8': {'name': 'NUCLEO-F334R8', 'mcuId': 'STM32F334R8Tx'}, + 'NUCLEO_F303ZE': {'name': 'NUCLEO-F303ZE', 'mcuId': 'STM32F303ZETx'}, 'NUCLEO_F401RE': {'name': 'NUCLEO-F401RE', 'mcuId': 'STM32F401RETx'}, 'NUCLEO_F429ZI': {'name': 'NUCLEO-F429ZI', 'mcuId': 'STM32F429ZITx'}, 'NUCLEO_F411RE': {'name': 'NUCLEO-F411RE', 'mcuId': 'STM32F411RETx'}, @@ -65,7 +66,7 @@ class Sw4STM32(Exporter): TARGETS = BOARDS.keys() def __gen_dir(self, dirname): - settings = join(self.inputDir, dirname) + settings = join(self.export_dir, dirname) mkdir(settings) def __generate_uid(self): @@ -78,13 +79,13 @@ def generate(self): libraries.append(l[3:]) ctx = { - 'name': self.program_name, + 'name': self.project_name, 'include_paths': self.resources.inc_dirs, 'linker_script': self.resources.linker_script, 'library_paths': self.resources.lib_dirs, 'object_files': self.resources.objects, 'libraries': libraries, - 'symbols': self.get_symbols(), + 'symbols': self.toolchain.get_symbols(), 'board_name': self.BOARDS[self.target.upper()]['name'], 'mcu_name': self.BOARDS[self.target.upper()]['mcuId'], 'debug_config_uid': self.__generate_uid(), diff --git a/tools/export/uvision4.py b/tools/export/uvision4.py index 0a76c89f824..5d3b548d742 100644 --- a/tools/export/uvision4.py +++ b/tools/export/uvision4.py @@ -1,6 +1,6 @@ """ mbed SDK -Copyright (c) 2011-2013 ARM Limited +Copyright (c) 2011-2016 ARM Limited Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -28,7 +28,7 @@ class Uvision4(Exporter): Exporter class for uvision. This class uses project generator. """ # These 2 are currently for exporters backward compatiblity - NAME = 'uVision4' + NAME = 'uvision' TOOLCHAIN = 'ARM' # PROGEN_ACTIVE contains information for exporter scripts that this is using progen PROGEN_ACTIVE = True @@ -53,7 +53,7 @@ def TARGETS(cls): def get_toolchain(self): return TARGET_MAP[self.target].default_toolchain - def generate(self, progen_build=False): + def generate(self): """ Generates the project files """ project_data = self.progen_get_project_data() tool_specific = {} @@ -72,25 +72,24 @@ def generate(self, progen_build=False): project_data['tool_specific'].update(tool_specific) # get flags from toolchain and apply - project_data['tool_specific']['uvision']['misc'] = {} + project_data['misc'] = {} # need to make this a string for progen. Only adds preprocessor when "macros" set asm_flag_string = '--cpreproc --cpreproc_opts=-D__ASSERT_MSG,' + ",".join( - list(set(self.progen_flags['asm_flags']))) - project_data['tool_specific']['uvision']['misc']['asm_flags'] = [asm_flag_string] + list(set(self.flags['asm_flags']))) + # asm flags only, common are not valid within uvision project, they are armcc specific + project_data['misc']['asm_flags'] = [asm_flag_string] # cxx flags included, as uvision have them all in one tab - project_data['tool_specific']['uvision']['misc']['c_flags'] = list(set( - ['-D__ASSERT_MSG'] + self.progen_flags['common_flags'] + self.progen_flags['c_flags'] + self.progen_flags[ - 'cxx_flags'])) + project_data['misc']['c_flags'] = list(set(['-D__ASSERT_MSG'] + + self.flags['common_flags'] + + self.flags['c_flags'] + + self.flags['cxx_flags'])) # not compatible with c99 flag set in the template - project_data['tool_specific']['uvision']['misc']['c_flags'].remove("--c99") + project_data['misc']['c_flags'].remove("--c99") # cpp is not required as it's implicit for cpp files - project_data['tool_specific']['uvision']['misc']['c_flags'].remove("--cpp") + project_data['misc']['c_flags'].remove("--cpp") # we want no-vla for only cxx, but it's also applied for C in IDE, thus we remove it - project_data['tool_specific']['uvision']['misc']['c_flags'].remove("--no_vla") - project_data['tool_specific']['uvision']['misc']['ld_flags'] = self.progen_flags['ld_flags'] + project_data['misc']['c_flags'].remove("--no_vla") + project_data['misc']['ld_flags'] = self.flags['ld_flags'] - project_data['common']['build_dir'] = project_data['common']['build_dir'] + '\\' + 'uvision4' - if progen_build: - self.progen_gen_file('uvision', project_data, True) - else: - self.progen_gen_file('uvision', project_data) + project_data['build_dir'] = project_data['build_dir'] + '\\' + 'uvision4' + self.progen_gen_file(project_data) diff --git a/tools/export/uvision5.py b/tools/export/uvision5.py index f985b3ff886..5eb08a58039 100644 --- a/tools/export/uvision5.py +++ b/tools/export/uvision5.py @@ -28,7 +28,7 @@ class Uvision5(Exporter): Exporter class for uvision5. This class uses project generator. """ # These 2 are currently for exporters backward compatiblity - NAME = 'uVision5' + NAME = 'uvision5' TOOLCHAIN = 'ARM' # PROGEN_ACTIVE contains information for exporter scripts that this is using progen PROGEN_ACTIVE = True @@ -53,7 +53,7 @@ def TARGETS(cls): def get_toolchain(self): return TARGET_MAP[self.target].default_toolchain - def generate(self, progen_build=False): + def generate(self): """ Generates the project files """ project_data = self.progen_get_project_data() tool_specific = {} @@ -68,27 +68,28 @@ def generate(self, progen_build=False): 'template': [join(dirname(__file__), 'uvision.uvproj.tmpl')], } + #project_data['template'] = [tool_specific['uvision5']['template']] project_data['tool_specific'] = {} project_data['tool_specific'].update(tool_specific) # get flags from toolchain and apply - project_data['tool_specific']['uvision5']['misc'] = {} - - # need to make this a string got progen. Only adds preprocessor when "macros" set - asm_flag_string = '--cpreproc --cpreproc_opts=-D__ASSERT_MSG,' + ",".join(list(set(self.progen_flags['asm_flags']))) - project_data['tool_specific']['uvision5']['misc']['asm_flags'] = [asm_flag_string] + project_data['misc'] = {} + asm_flag_string = '--cpreproc --cpreproc_opts=-D__ASSERT_MSG,' + ",".join(list(set(self.flags['asm_flags']))) + # asm flags only, common are not valid within uvision project, they are armcc specific + project_data['misc']['asm_flags'] = [asm_flag_string] # cxx flags included, as uvision have them all in one tab - project_data['tool_specific']['uvision5']['misc']['c_flags'] = list(set(['-D__ASSERT_MSG']+self.progen_flags['common_flags'] + self.progen_flags['c_flags'] + self.progen_flags['cxx_flags'])) + project_data['misc']['c_flags'] = list(set(['-D__ASSERT_MSG'] + + self.flags['common_flags'] + + self.flags['c_flags'] + + self.flags['cxx_flags'])) # not compatible with c99 flag set in the template - project_data['tool_specific']['uvision5']['misc']['c_flags'].remove("--c99") + project_data['misc']['c_flags'].remove("--c99") # cpp is not required as it's implicit for cpp files - project_data['tool_specific']['uvision5']['misc']['c_flags'].remove("--cpp") + project_data['misc']['c_flags'].remove("--cpp") # we want no-vla for only cxx, but it's also applied for C in IDE, thus we remove it - project_data['tool_specific']['uvision5']['misc']['c_flags'].remove("--no_vla") - project_data['tool_specific']['uvision5']['misc']['ld_flags'] = self.progen_flags['ld_flags'] + project_data['misc']['c_flags'].remove("--no_vla") + project_data['misc']['ld_flags'] = self.flags['ld_flags'] - project_data['common']['build_dir'] = project_data['common']['build_dir'] + '\\' + 'uvision5' - if progen_build: - self.progen_gen_file('uvision5', project_data, True) - else: - self.progen_gen_file('uvision5', project_data) + i = 0 + project_data['build_dir'] = project_data['build_dir'] + '\\' + 'uvision5' + self.progen_gen_file(project_data) diff --git a/tools/export/zip.py b/tools/export/zip.py index b9828a61a1c..3961eb0622c 100644 --- a/tools/export/zip.py +++ b/tools/export/zip.py @@ -33,9 +33,11 @@ class ZIP(Exporter): 's_sources':'2' } + TOOLCHAIN = 'ARM' + def get_toolchain(self): return 'uARM' if (self.target in self.USING_MICROLIB) else 'ARM' def generate(self): return True - \ No newline at end of file + diff --git a/tools/export_test.py b/tools/export_test.py index c668e79c240..35d59025d04 100644 --- a/tools/export_test.py +++ b/tools/export_test.py @@ -110,6 +110,7 @@ def test_export(toolchain, target, expected_error=None): ('coide', 'NUCLEO_F429ZI'), #('coide', 'DISCO_F469NI'), removed because template not available ('coide', 'NUCLEO_F334R8'), + ('coide', 'NUCLEO_F303ZE'), ('coide', 'MTS_MDOT_F405RG'), ('coide', 'MTS_MDOT_F411RE'), @@ -139,6 +140,7 @@ def test_export(toolchain, target, expected_error=None): ('uvision', 'NUCLEO_F303K8'), ('uvision', 'NUCLEO_F303RE'), ('uvision', 'NUCLEO_F334R8'), + ('uvision', 'NUCLEO_F303ZE'), ('uvision', 'NUCLEO_F401RE'), ('uvision', 'NUCLEO_F410RB'), ('uvision', 'NUCLEO_F411RE'), @@ -215,6 +217,7 @@ def test_export(toolchain, target, expected_error=None): ('gcc_arm', 'NUCLEO_F429ZI'), ('gcc_arm', 'NUCLEO_F446RE'), ('gcc_arm', 'NUCLEO_F446ZE'), + ('gcc_arm', 'NUCLEO_F303ZE'), ('gcc_arm', 'ELMO_F411RE'), ('gcc_arm', 'DISCO_F469NI'), ('gcc_arm', 'NUCLEO_F334R8'), @@ -265,6 +268,7 @@ def test_export(toolchain, target, expected_error=None): ('iar', 'NUCLEO_F303K8'), ('iar', 'NUCLEO_F303RE'), ('iar', 'NUCLEO_F334R8'), + ('iar', 'NUCLEO_F303ZE'), ('iar', 'NUCLEO_F401RE'), ('iar', 'NUCLEO_F410RB'), ('iar', 'NUCLEO_F411RE'), @@ -329,7 +333,7 @@ def test_export(toolchain, target, expected_error=None): ('sw4stm32', 'NUCLEO_L476RG'), ('sw4stm32', 'NUCLEO_F031K6'), ('sw4stm32', 'NUCLEO_F042K6'), - ('sw4stm32', 'NUCLEO_F303K8'), + ('sw4stm32', 'NUCLEO_F303ZE'), ('sw4stm32', 'NUCLEO_F410RB'), ('e2studio', 'RZ_A1H'), diff --git a/tools/get_config.py b/tools/get_config.py index c9b2a9bebc3..9782fc16aeb 100644 --- a/tools/get_config.py +++ b/tools/get_config.py @@ -37,7 +37,7 @@ if __name__ == '__main__': # Parse Options parser = get_default_options_parser(add_clean=False, add_options=False) - parser.add_argument("--source", dest="source_dir", type=argparse_filestring_type, + parser.add_argument("--source", dest="source_dir", type=argparse_filestring_type, required=True, default=[], help="The source (input) directory", action="append") parser.add_argument("--prefix", dest="prefix", action="append", default=[], help="Restrict listing to parameters that have this prefix") @@ -48,12 +48,12 @@ # Target if options.mcu is None : - args_error(parser, "[ERROR] You should specify an MCU") + args_error(parser, "argument -m/--mcu is required") target = options.mcu[0] # Toolchain if options.tool is None: - args_error(parser, "[ERROR] You should specify a TOOLCHAIN") + args_error(parser, "argument -t/--toolchain is required") toolchain = options.tool[0] options.prefix = options.prefix or [""] diff --git a/tools/make.py b/tools/make.py index 3dc5a63c3c6..0541d5e7608 100644 --- a/tools/make.py +++ b/tools/make.py @@ -52,7 +52,7 @@ if __name__ == '__main__': # Parse Options - parser = get_default_options_parser() + parser = get_default_options_parser(add_app_config=True) group = parser.add_mutually_exclusive_group(required=False) group.add_argument("-p", type=argparse_many(test_known), @@ -207,14 +207,20 @@ # Target if options.mcu is None : - args_error(parser, "[ERROR] You should specify an MCU") + args_error(parser, "argument -m/--mcu is required") mcu = options.mcu[0] # Toolchain if options.tool is None: - args_error(parser, "[ERROR] You should specify a TOOLCHAIN") + args_error(parser, "argument -t/--tool is required") toolchain = options.tool[0] + if (options.program is None) and (not options.source_dir): + args_error(parser, "one of -p, -n, or --source is required") + + if options.source_dir and not options.build_dir: + args_error(parser, "argument --build is required when argument --source is provided") + if options.color: # This import happens late to prevent initializing colorization when we don't need it import colorize @@ -268,7 +274,8 @@ silent=options.silent, macros=options.macros, jobs=options.jobs, - name=options.artifact_name) + name=options.artifact_name, + app_config=options.app_config) print 'Image: %s'% bin_file if options.disk: diff --git a/tools/options.py b/tools/options.py index 876e63ad7ac..c69d06f6b0c 100644 --- a/tools/options.py +++ b/tools/options.py @@ -18,9 +18,11 @@ from tools.toolchains import TOOLCHAINS from tools.targets import TARGET_NAMES from tools.utils import argparse_force_uppercase_type, \ - argparse_lowercase_hyphen_type, argparse_many + argparse_lowercase_hyphen_type, argparse_many, \ + argparse_filestring_type -def get_default_options_parser(add_clean=True, add_options=True): +def get_default_options_parser(add_clean=True, add_options=True, + add_app_config=False): """Create a new options parser with the default compiler options added Keyword arguments: @@ -78,4 +80,9 @@ def get_default_options_parser(add_clean=True, add_options=True): 'analyze'], "build option")) + if add_app_config: + parser.add_argument("--app-config", default=None, dest="app_config", + type=argparse_filestring_type, + help="Path of an app configuration file (Default is to look for 'mbed_app.json')") + return parser diff --git a/tools/project.py b/tools/project.py index 530def4093f..4fb905fbe14 100644 --- a/tools/project.py +++ b/tools/project.py @@ -1,3 +1,6 @@ +""" The CLI entry point for exporting projects from the mbed tools to any of the +supported IDEs or project structures. +""" import sys from os.path import join, abspath, dirname, exists, basename ROOT = abspath(join(dirname(__file__), "..")) @@ -5,21 +8,87 @@ from shutil import move, rmtree from argparse import ArgumentParser -from os import path +from os.path import normpath, realpath -from tools.paths import EXPORT_DIR -from tools.export import export, EXPORTERS, mcu_ide_matrix +from tools.paths import EXPORT_DIR, MBED_BASE, MBED_LIBRARIES +from tools.export import EXPORTERS, mcu_ide_matrix from tools.tests import TESTS, TEST_MAP -from tools.tests import test_known, test_name_known +from tools.tests import test_known, test_name_known, Test from tools.targets import TARGET_NAMES -from tools.libraries import LIBRARIES -from utils import argparse_filestring_type, argparse_many -from utils import argparse_force_lowercase_type, argparse_force_uppercase_type, argparse_dir_not_parent -from project_api import setup_project, perform_export, print_results, get_lib_symbols - - - -if __name__ == '__main__': +from tools.utils import argparse_filestring_type, argparse_many, args_error +from tools.utils import argparse_force_lowercase_type +from tools.utils import argparse_force_uppercase_type +from tools.project_api import export_project + + +def setup_project(ide, target, program=None, source_dir=None, build=None): + """Generate a name, if not provided, and find dependencies + + Positional arguments: + ide - IDE or project structure that will soon be exported to + target - MCU that the project will build for + + Keyword arguments: + program - the index of a test program + source_dir - the directory, or directories that contain all of the sources + build - a directory that will contain the result of the export + """ + # Some libraries have extra macros (called by exporter symbols) to we need + # to pass them to maintain compilation macros integrity between compiled + # library and header files we might use with it + if source_dir: + # --source is used to generate IDE files to toolchain directly + # in the source tree and doesn't generate zip file + project_dir = source_dir[0] + if program: + project_name = TESTS[program] + else: + project_name = basename(normpath(realpath(source_dir[0]))) + src_paths = source_dir + lib_paths = None + else: + test = Test(program) + if not build: + # Substitute the mbed library builds with their sources + if MBED_LIBRARIES in test.dependencies: + test.dependencies.remove(MBED_LIBRARIES) + test.dependencies.append(MBED_BASE) + + src_paths = [test.source_dir] + lib_paths = test.dependencies + project_name = "_".join([test.id, ide, target]) + project_dir = join(EXPORT_DIR, project_name) + + return project_dir, project_name, src_paths, lib_paths + + +def export(target, ide, build=None, src=None, macros=None, project_id=None, + clean=False, zip_proj=False, options=None): + """Do an export of a project. + + Positional arguments: + target - MCU that the project will compile for + ide - the IDE or project structure to export to + + Keyword arguments: + build - to use the compiled mbed libraries or not + src - directory or directories that contain the source to export + macros - extra macros to add to the project + project_id - the name of the project + clean - start from a clean state before exporting + zip_proj - create a zip file or not + """ + project_dir, name, src, lib = setup_project(ide, target, program=project_id, + source_dir=src, build=build) + + zip_name = name+".zip" if zip_proj else None + + export_project(src, project_dir, target, ide, clean=clean, name=name, + macros=macros, libraries_paths=lib, zip_proj=zip_name, options=options) + + +def main(): + """Entry point""" # Parse Options parser = ArgumentParser() @@ -29,32 +98,35 @@ toolchainlist.sort() parser.add_argument("-m", "--mcu", - metavar="MCU", - default='LPC1768', - type=argparse_many(argparse_force_uppercase_type(targetnames, "MCU")), - help="generate project for the given MCU (%s)"% ', '.join(targetnames)) + metavar="MCU", + default='LPC1768', + type=argparse_force_uppercase_type(targetnames, "MCU"), + help="generate project for the given MCU ({})".format( + ', '.join(targetnames))) parser.add_argument("-i", - dest="ide", - default='uvision', - type=argparse_force_lowercase_type(toolchainlist, "toolchain"), - help="The target IDE: %s"% str(toolchainlist)) + dest="ide", + default='uvision', + type=argparse_force_lowercase_type( + toolchainlist, "toolchain"), + help="The target IDE: %s"% str(toolchainlist)) parser.add_argument("-c", "--clean", - action="store_true", - default=False, - help="clean the export directory") + action="store_true", + default=False, + help="clean the export directory") group = parser.add_mutually_exclusive_group(required=False) - group.add_argument("-p", - type=test_known, - dest="program", - help="The index of the desired test program: [0-%d]"% (len(TESTS)-1)) + group.add_argument( + "-p", + type=test_known, + dest="program", + help="The index of the desired test program: [0-%s]"% (len(TESTS)-1)) group.add_argument("-n", - type=test_name_known, - dest="program", - help="The name of the desired test program") + type=test_name_known, + dest="program", + help="The name of the desired test program") parser.add_argument("-b", dest="build", @@ -63,40 +135,46 @@ help="use the mbed library build, instead of the sources") group.add_argument("-L", "--list-tests", - action="store_true", - dest="list_tests", - default=False, - help="list available programs in order and exit") + action="store_true", + dest="list_tests", + default=False, + help="list available programs in order and exit") group.add_argument("-S", "--list-matrix", - action="store_true", - dest="supported_ides", - default=False, - help="displays supported matrix of MCUs and IDEs") + action="store_true", + dest="supported_ides", + default=False, + help="displays supported matrix of MCUs and IDEs") parser.add_argument("-E", - action="store_true", - dest="supported_ides_html", - default=False, - help="writes tools/export/README.md") + action="store_true", + dest="supported_ides_html", + default=False, + help="writes tools/export/README.md") parser.add_argument("--source", - action="append", - type=argparse_filestring_type, - dest="source_dir", - default=[], - help="The source (input) directory") + action="append", + type=argparse_filestring_type, + dest="source_dir", + default=[], + help="The source (input) directory") parser.add_argument("-D", - action="append", - dest="macros", - help="Add a macro definition") + action="append", + dest="macros", + help="Add a macro definition") + + parser.add_argument("-o", + type=argparse_many(str), + dest="opts", + default=["debug-info"], + help="Toolchain options") options = parser.parse_args() # Print available tests in order and exit if options.list_tests is True: - print '\n'.join(map(str, sorted(TEST_MAP.values()))) + print '\n'.join([str(test) for test in sorted(TEST_MAP.values())]) sys.exit() # Only prints matrix of supported IDEs @@ -108,13 +186,13 @@ if options.supported_ides_html: html = mcu_ide_matrix(verbose_html=True) try: - with open("./export/README.md","w") as f: - f.write("Exporter IDE/Platform Support\n") - f.write("-----------------------------------\n") - f.write("\n") - f.write(html) - except IOError as e: - print "I/O error({0}): {1}".format(e.errno, e.strerror) + with open("./export/README.md", "w") as readme: + readme.write("Exporter IDE/Platform Support\n") + readme.write("-----------------------------------\n") + readme.write("\n") + readme.write(html) + except IOError as exc: + print "I/O error({0}): {1}".format(exc.errno, exc.strerror) except: print "Unexpected error:", sys.exc_info()[0] raise @@ -125,38 +203,25 @@ if exists(EXPORT_DIR): rmtree(EXPORT_DIR) - # Export results - successes = [] - failures = [] + for mcu in options.mcu: + zip_proj = not bool(options.source_dir) - # source_dir = use relative paths, otherwise sources are copied - sources_relative = True if options.source_dir else False + # Target + if not options.mcu: + args_error(parser, "argument -m/--mcu is required") + + # Toolchain + if not options.ide: + args_error(parser, "argument -i is required") + + if (options.program is None) and (not options.source_dir): + args_error(parser, "one of -p, -n, or --source is required") + # Export to selected toolchain + export(options.mcu, options.ide, build=options.build, + src=options.source_dir, macros=options.macros, + project_id=options.program, clean=options.clean, + zip_proj=zip_proj, options=options.opts) - for mcu in options.mcu: - # Program Number or name - p, src, ide = options.program, options.source_dir, options.ide - try: - project_dir, project_name, project_temp = setup_project(mcu, ide, p, src, options.build) - zip = not bool(src) # create zip when no src_dir provided - clean = not bool(src) # don't clean when source is provided, use acrual source tree for IDE files - - # Export to selected toolchain - lib_symbols = get_lib_symbols(options.macros, src, p) - tmp_path, report = export(project_dir, project_name, ide, mcu, project_dir[0], project_temp, clean=clean, make_zip=zip, extra_symbols=lib_symbols, sources_relative=sources_relative) - except OSError as e: - if e.errno == 2: - report = dict(success=False, errormsg="Library path '%s' does not exist. Ensure that the library is built." % (e.filename)) - else: - report = dict(success=False, errormsg="An OS error occured: errno #{}".format(e.errno)) - if report['success']: - if not zip: - zip_path = join(project_temp, project_name) - else: - zip_path = join(EXPORT_DIR, "%s_%s_%s.zip" % (project_name, ide, mcu)) - move(tmp_path, zip_path) - successes.append("%s::%s\t%s"% (mcu, ide, zip_path)) - else: - failures.append("%s::%s\t%s"% (mcu, ide, report['errormsg'])) - # Prints export results - print_results(successes, failures) +if __name__ == "__main__": + main() diff --git a/tools/project_api.py b/tools/project_api.py index f0bfb04795a..56ef18282ef 100644 --- a/tools/project_api.py +++ b/tools/project_api.py @@ -1,110 +1,255 @@ +""" The new way of doing exports """ import sys -from os.path import join, abspath, dirname, exists, basename +from os.path import join, abspath, dirname, exists +from os.path import basename, relpath, normpath +from os import makedirs, walk ROOT = abspath(join(dirname(__file__), "..")) sys.path.insert(0, ROOT) +import copy +from shutil import rmtree +import zipfile -from tools.paths import EXPORT_WORKSPACE, EXPORT_TMP -from tools.paths import MBED_BASE, MBED_LIBRARIES -from tools.export import export, setup_user_prj -from tools.utils import mkdir -from tools.tests import Test, TEST_MAP, TESTS -from tools.libraries import LIBRARIES +from tools.build_api import prepare_toolchain +from tools.build_api import scan_resources +from tools.export import EXPORTERS +from tools.toolchains import Resources -try: - import tools.private_settings as ps -except: - ps = object() +def get_exporter_toolchain(ide): + """ Return the exporter class and the toolchain string as a tuple -def get_program(n): - p = TEST_MAP[n].n - return p + Positional arguments: + ide - the ide name of an exporter + """ + return EXPORTERS[ide], EXPORTERS[ide].TOOLCHAIN -def get_test(p): - return Test(p) +def rewrite_basepath(file_name, resources, export_path, loc): + """ Replace the basepath of filename with export_path + Positional arguments: + file_name - the absolute path to a file + resources - the resources object that the file came from + export_path - the final destination of the file after export + """ + new_f = join(loc, relpath(file_name, resources.file_basepath[file_name])) + resources.file_basepath[join(export_path, new_f)] = export_path + return new_f -def get_test_from_name(n): - if not n in TEST_MAP.keys(): - # Check if there is an alias for this in private_settings.py - if getattr(ps, "test_alias", None) is not None: - alias = ps.test_alias.get(n, "") - if not alias in TEST_MAP.keys(): - return None + +def subtract_basepath(resources, export_path, loc=""): + """ Rewrite all of the basepaths with the export_path + + Positional arguments: + resources - the resource object to rewrite the basepaths of + export_path - the final destination of the resources with respect to the + generated project files + """ + keys = ['s_sources', 'c_sources', 'cpp_sources', 'hex_files', + 'objects', 'libraries', 'inc_dirs', 'headers', 'linker_script', + 'lib_dirs'] + for key in keys: + vals = getattr(resources, key) + if isinstance(vals, set): + vals = list(vals) + if isinstance(vals, list): + new_vals = [] + for val in vals: + new_vals.append(rewrite_basepath(val, resources, export_path, + loc)) + if isinstance(getattr(resources, key), set): + setattr(resources, key, set(new_vals)) else: - n = alias - else: - return None - return get_program(n) - - -def get_lib_symbols(macros, src, program): - # Some libraries have extra macros (called by exporter symbols) to we need to pass - # them to maintain compilation macros integrity between compiled library and - # header files we might use with it - lib_symbols = [] - if macros: - lib_symbols += macros - if src: - return lib_symbols - test = get_test(program) - for lib in LIBRARIES: - if lib['build_dir'] in test.dependencies: - lib_macros = lib.get('macros', None) - if lib_macros is not None: - lib_symbols.extend(lib_macros) - - -def setup_project(mcu, ide, program=None, source_dir=None, build=None): - - # Some libraries have extra macros (called by exporter symbols) to we need to pass - # them to maintain compilation macros integrity between compiled library and - # header files we might use with it - if source_dir: - # --source is used to generate IDE files to toolchain directly in the source tree and doesn't generate zip file - project_dir = source_dir - project_name = TESTS[program] if program else "Unnamed_Project" - project_temp = join(source_dir[0], 'projectfiles', '%s_%s' % (ide, mcu)) - mkdir(project_temp) + setattr(resources, key, new_vals) + elif vals: + setattr(resources, key, rewrite_basepath(vals, resources, + export_path, loc)) + + +def generate_project_files(resources, export_path, target, name, toolchain, ide, + macros=None): + """Generate the project files for a project + + Positional arguments: + resources - a Resources object containing all of the files needed to build + this project + export_path - location to place project files + name - name of the project + toolchain - a toolchain class that corresponds to the toolchain used by the + IDE or makefile + ide - IDE name to export to + + Optional arguments: + macros - additional macros that should be defined within the exported + project + """ + exporter_cls, _ = get_exporter_toolchain(ide) + exporter = exporter_cls(target, export_path, name, toolchain, + extra_symbols=macros, resources=resources) + exporter.generate() + files = exporter.generated_files + return files, exporter + + +def zip_export(file_name, prefix, resources, project_files): + """Create a zip file from an exported project. + + Positional Parameters: + file_name - the file name of the resulting zip file + prefix - a directory name that will prefix the entire zip file's contents + resources - a resources object with files that must be included in the zip + project_files - a list of extra files to be added to the root of the prefix + directory + """ + with zipfile.ZipFile(file_name, "w") as zip_file: + for prj_file in project_files: + zip_file.write(prj_file, join(prefix, basename(prj_file))) + for loc, resource in resources.iteritems(): + print resource.features + for res in [resource] + resource.features.values(): + extras = [] + for directory in res.repo_dirs: + for root, _, files in walk(directory): + for repo_file in files: + source = join(root, repo_file) + extras.append(source) + res.file_basepath[source] = res.base_path + for source in \ + res.headers + res.s_sources + res.c_sources +\ + res.cpp_sources + res.libraries + res.hex_files + \ + [res.linker_script] + res.bin_files + res.objects + \ + res.json_files + res.lib_refs + res.lib_builds + \ + res.repo_files + extras: + if source: + zip_file.write( + source, + join(prefix, loc, + relpath(source, res.file_basepath[source]))) + + + +def export_project(src_paths, export_path, target, ide, + libraries_paths=None, options=None, linker_script=None, + clean=False, notify=None, verbose=False, name=None, + inc_dirs=None, jobs=1, silent=False, extra_verbose=False, + config=None, macros=None, zip_proj=None): + """Generates a project file and creates a zip archive if specified + + Positional Arguments: + src_paths - a list of paths from which to find source files + export_path - a path specifying the location of generated project files + target - the mbed board/mcu for which to generate the executable + ide - the ide for which to generate the project fields + + Keyword Arguments: + libraries_paths - paths to additional libraries + options - build options passed by -o flag + linker_script - path to the linker script for the specified target + clean - removes the export_path if it exists + notify - function is passed all events, and expected to handle notification + of the user, emit the events to a log, etc. + verbose - assigns the notify function to toolchains print_notify_verbose + name - project name + inc_dirs - additional include directories + jobs - number of threads + silent - silent build - no output + extra_verbose - assigns the notify function to toolchains + print_notify_verbose + config - toolchain's config object + macros - User-defined macros + zip_proj - string name of the zip archive you wish to creat (exclude arg + if you do not wish to create an archive + """ + + # Convert src_path to a list if needed + if isinstance(src_paths, dict): + paths = sum(src_paths.values(), []) + elif isinstance(src_paths, list): + paths = src_paths[:] + else: + paths = [src_paths] + + # Extend src_paths wit libraries_paths + if libraries_paths is not None: + paths.extend(libraries_paths) + + if not isinstance(src_paths, dict): + src_paths = {"": paths} + + # Export Directory + if exists(export_path) and clean: + rmtree(export_path) + if not exists(export_path): + makedirs(export_path) + + _, toolchain_name = get_exporter_toolchain(ide) + + # Pass all params to the unified prepare_resources() + toolchain = prepare_toolchain(paths, target, toolchain_name, + macros=macros, options=options, clean=clean, + jobs=jobs, notify=notify, silent=silent, + verbose=verbose, extra_verbose=extra_verbose, + config=config) + # The first path will give the name to the library + if name is None: + name = basename(normpath(abspath(src_paths[0]))) + + # Call unified scan_resources + resource_dict = {loc: scan_resources(path, toolchain, inc_dirs=inc_dirs) + for loc, path in src_paths.iteritems()} + resources = Resources() + toolchain.build_dir = export_path + config_header = toolchain.get_config_header() + resources.headers.append(config_header) + resources.file_basepath[config_header] = dirname(config_header) + + if zip_proj: + subtract_basepath(resources, export_path) + for loc, res in resource_dict.iteritems(): + temp = copy.deepcopy(res) + subtract_basepath(temp, export_path, loc) + resources.add(temp) else: - test = get_test(program) - if not build: - # Substitute the library builds with the sources - # TODO: Substitute also the other library build paths - if MBED_LIBRARIES in test.dependencies: - test.dependencies.remove(MBED_LIBRARIES) - test.dependencies.append(MBED_BASE) + for _, res in resource_dict.iteritems(): + resources.add(res) - # Build the project with the same directory structure of the mbed online IDE - project_name = test.id - project_dir = [join(EXPORT_WORKSPACE, project_name)] - project_temp = EXPORT_TMP - setup_user_prj(project_dir[0], test.source_dir, test.dependencies) + # Change linker script if specified + if linker_script is not None: + resources.linker_script = linker_script - return project_dir, project_name, project_temp + files, exporter = generate_project_files(resources, export_path, + target, name, toolchain, ide, + macros=macros) + files.append(config_header) + if zip_proj: + if isinstance(zip_proj, basestring): + zip_export(join(export_path, zip_proj), name, resource_dict, files) + else: + zip_export(zip_proj, name, resource_dict, files) + return exporter -def perform_export(dir, name, ide, mcu, temp, clean=False, zip=False, lib_symbols='', - sources_relative=False, progen_build=False): - tmp_path, report = export(dir, name, ide, mcu, dir[0], temp, clean=clean, - make_zip=zip, extra_symbols=lib_symbols, sources_relative=sources_relative, - progen_build=progen_build) - return tmp_path, report +def print_results(successes, failures, skips=None): + """ Print out the results of an export process + Positional arguments: + successes - The list of exports that succeeded + failures - The list of exports that failed -def print_results(successes, failures, skips = []): + Keyword arguments: + skips - The list of exports that were skipped + """ print - if len(successes) > 0: + if successes: print "Successful: " for success in successes: print " * %s" % success - if len(failures) > 0: + if failures: print "Failed: " for failure in failures: print " * %s" % failure - if len(skips) > 0: + if skips: print "Skipped: " for skip in skips: print " * %s" % skip diff --git a/tools/test.py b/tools/test.py index 9b568a5d933..101af3fb336 100644 --- a/tools/test.py +++ b/tools/test.py @@ -41,7 +41,7 @@ if __name__ == '__main__': try: # Parse Options - parser = get_default_options_parser() + parser = get_default_options_parser(add_app_config=True) parser.add_argument("-D", action="append", @@ -107,17 +107,18 @@ # Target if options.mcu is None : - args_error(parser, "[ERROR] You should specify an MCU") + args_error(parser, "argument -m/--mcu is required") mcu = options.mcu[0] # Toolchain if options.tool is None: - args_error(parser, "[ERROR] You should specify a TOOLCHAIN") + args_error(parser, "argument -t/--tool is required") toolchain = options.tool[0] # Find all tests in the relevant paths for path in all_paths: - all_tests.update(find_tests(path, mcu, toolchain, options.options)) + all_tests.update(find_tests(path, mcu, toolchain, options.options, + app_config=options.app_config)) # Filter tests by name if specified if options.names: @@ -152,8 +153,7 @@ else: # Build all tests if not options.build_dir: - print "[ERROR] You must specify a build path" - sys.exit(1) + args_error(parser, "argument --build is required") base_source_paths = options.source_dir @@ -178,7 +178,8 @@ verbose=options.verbose, notify=notify, archive=False, - remove_config_header_file=True) + remove_config_header_file=True, + app_config=options.app_config) library_build_success = True except ToolException, e: @@ -204,7 +205,8 @@ verbose=options.verbose, notify=notify, jobs=options.jobs, - continue_on_build_fail=options.continue_on_build_fail) + continue_on_build_fail=options.continue_on_build_fail, + app_config=options.app_config) # If a path to a test spec is provided, write it to a file if options.test_spec: diff --git a/tools/test/build_api/build_api_test.py b/tools/test/build_api/build_api_test.py new file mode 100644 index 00000000000..97c2f1cf219 --- /dev/null +++ b/tools/test/build_api/build_api_test.py @@ -0,0 +1,188 @@ +""" +mbed SDK +Copyright (c) 2016 ARM Limited + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + +import unittest +from mock import patch +from tools.build_api import prepare_toolchain, build_project, build_library + +""" +Tests for build_api.py +""" + +class BuildApiTests(unittest.TestCase): + """ + Test cases for Build Api + """ + + def setUp(self): + """ + Called before each test case + + :return: + """ + self.target = "K64F" + self.src_paths = ['.'] + self.toolchain_name = "ARM" + self.build_path = "build_path" + + def tearDown(self): + """ + Called after each test case + + :return: + """ + pass + + @patch('tools.config.Config.__init__') + def test_prepare_toolchain_app_config(self, mock_config_init): + """ + Test that prepare_toolchain uses app_config correctly + + :param mock_config_init: mock of Config __init__ + :return: + """ + app_config = "app_config" + mock_config_init.return_value = None + + prepare_toolchain(self.src_paths, self.target, self.toolchain_name, + app_config=app_config) + + mock_config_init.assert_called_with(self.target, self.src_paths, + app_config=app_config) + + @patch('tools.config.Config.__init__') + def test_prepare_toolchain_no_app_config(self, mock_config_init): + """ + Test that prepare_toolchain correctly deals with no app_config + + :param mock_config_init: mock of Config __init__ + :return: + """ + mock_config_init.return_value = None + + prepare_toolchain(self.src_paths, self.target, self.toolchain_name) + + mock_config_init.assert_called_with(self.target, self.src_paths, + app_config=None) + + @patch('tools.build_api.scan_resources') + @patch('tools.build_api.mkdir') + @patch('os.path.exists') + @patch('tools.build_api.prepare_toolchain') + def test_build_project_app_config(self, mock_prepare_toolchain, mock_exists, _, __): + """ + Test that build_project uses app_config correctly + + :param mock_prepare_toolchain: mock of function prepare_toolchain + :param mock_exists: mock of function os.path.exists + :param _: mock of function mkdir (not tested) + :param __: mock of function scan_resources (not tested) + :return: + """ + app_config = "app_config" + mock_exists.return_value = False + mock_prepare_toolchain().link_program.return_value = 1, 2 + + build_project(self.src_paths, self.build_path, self.target, + self.toolchain_name, app_config=app_config) + + args = mock_prepare_toolchain.call_args + self.assertTrue('app_config' in args[1], + "prepare_toolchain was not called with app_config") + self.assertEqual(args[1]['app_config'], app_config, + "prepare_toolchain was called with an incorrect app_config") + + @patch('tools.build_api.scan_resources') + @patch('tools.build_api.mkdir') + @patch('os.path.exists') + @patch('tools.build_api.prepare_toolchain') + def test_build_project_no_app_config(self, mock_prepare_toolchain, mock_exists, _, __): + """ + Test that build_project correctly deals with no app_config + + :param mock_prepare_toolchain: mock of function prepare_toolchain + :param mock_exists: mock of function os.path.exists + :param _: mock of function mkdir (not tested) + :param __: mock of function scan_resources (not tested) + :return: + """ + mock_exists.return_value = False + # Needed for the unpacking of the returned value + mock_prepare_toolchain().link_program.return_value = 1, 2 + + build_project(self.src_paths, self.build_path, self.target, + self.toolchain_name) + + args = mock_prepare_toolchain.call_args + self.assertTrue('app_config' in args[1], + "prepare_toolchain was not called with app_config") + self.assertEqual(args[1]['app_config'], None, + "prepare_toolchain was called with an incorrect app_config") + + @patch('tools.build_api.scan_resources') + @patch('tools.build_api.mkdir') + @patch('os.path.exists') + @patch('tools.build_api.prepare_toolchain') + def test_build_library_app_config(self, mock_prepare_toolchain, mock_exists, _, __): + """ + Test that build_library uses app_config correctly + + :param mock_prepare_toolchain: mock of function prepare_toolchain + :param mock_exists: mock of function os.path.exists + :param _: mock of function mkdir (not tested) + :param __: mock of function scan_resources (not tested) + :return: + """ + app_config = "app_config" + mock_exists.return_value = False + + build_library(self.src_paths, self.build_path, self.target, + self.toolchain_name, app_config=app_config) + + args = mock_prepare_toolchain.call_args + self.assertTrue('app_config' in args[1], + "prepare_toolchain was not called with app_config") + self.assertEqual(args[1]['app_config'], app_config, + "prepare_toolchain was called with an incorrect app_config") + + @patch('tools.build_api.scan_resources') + @patch('tools.build_api.mkdir') + @patch('os.path.exists') + @patch('tools.build_api.prepare_toolchain') + def test_build_library_no_app_config(self, mock_prepare_toolchain, mock_exists, _, __): + """ + Test that build_library correctly deals with no app_config + + :param mock_prepare_toolchain: mock of function prepare_toolchain + :param mock_exists: mock of function os.path.exists + :param _: mock of function mkdir (not tested) + :param __: mock of function scan_resources (not tested) + :return: + """ + mock_exists.return_value = False + + build_library(self.src_paths, self.build_path, self.target, + self.toolchain_name) + + args = mock_prepare_toolchain.call_args + self.assertTrue('app_config' in args[1], + "prepare_toolchain was not called with app_config") + self.assertEqual(args[1]['app_config'], None, + "prepare_toolchain was called with an incorrect app_config") + +if __name__ == '__main__': + unittest.main() diff --git a/tools/test/config/config_test.py b/tools/test/config/config_test.py new file mode 100644 index 00000000000..114f088c28e --- /dev/null +++ b/tools/test/config/config_test.py @@ -0,0 +1,132 @@ +""" +mbed SDK +Copyright (c) 2016 ARM Limited + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + +import os.path +import unittest +from mock import patch +from tools.config import Config + +""" +Tests for config.py +""" + +class ConfigTests(unittest.TestCase): + """ + Test cases for Config class + """ + + def setUp(self): + """ + Called before each test case + + :return: + """ + self.target = "K64F" + + def tearDown(self): + """ + Called after each test case + + :return: + """ + pass + + @patch.object(Config, '_process_config_and_overrides') + @patch('tools.config.json_file_to_dict') + def test_init_app_config(self, mock_json_file_to_dict, _): + """ + Test that the initialisation correctly uses app_config + + :param mock_json_file_to_dict: mock of function json_file_to_dict + :param _: mock of function _process_config_and_overrides (not tested) + :return: + """ + app_config = "app_config" + mock_return = {'config': 'test'} + mock_json_file_to_dict.return_value = mock_return + + config = Config(self.target, app_config=app_config) + + mock_json_file_to_dict.assert_called_with(app_config) + self.assertEqual(config.app_config_data, mock_return, + "app_config_data should be set to the returned value") + + @patch.object(Config, '_process_config_and_overrides') + @patch('tools.config.json_file_to_dict') + def test_init_no_app_config(self, mock_json_file_to_dict, _): + """ + Test that the initialisation works without app config + + :param mock_json_file_to_dict: mock of function json_file_to_dict + :param _: patch of function _process_config_and_overrides (not tested) + :return: + """ + config = Config(self.target) + + mock_json_file_to_dict.assert_not_called() + self.assertEqual(config.app_config_data, {}, + "app_config_data should be set an empty dictionary") + + @patch.object(Config, '_process_config_and_overrides') + @patch('os.path.isfile') + @patch('tools.config.json_file_to_dict') + def test_init_no_app_config_with_dir(self, mock_json_file_to_dict, mock_isfile, _): + """ + Test that the initialisation works without app config and with a + specified top level directory + + :param mock_json_file_to_dict: mock of function json_file_to_dict + :param _: patch of function _process_config_and_overrides (not tested) + :return: + """ + directory = '.' + path = os.path.join('.', 'mbed_app.json') + mock_return = {'config': 'test'} + mock_json_file_to_dict.return_value = mock_return + mock_isfile.return_value = True + + config = Config(self.target, [directory]) + + mock_isfile.assert_called_with(path) + mock_json_file_to_dict.assert_called_once_with(path) + self.assertEqual(config.app_config_data, mock_return, + "app_config_data should be set to the returned value") + + @patch.object(Config, '_process_config_and_overrides') + @patch('tools.config.json_file_to_dict') + def test_init_override_app_config(self, mock_json_file_to_dict, _): + """ + Test that the initialisation uses app_config instead of top_level_dir + when both are specified + + :param mock_json_file_to_dict: mock of function json_file_to_dict + :param _: patch of function _process_config_and_overrides (not tested) + :return: + """ + app_config = "app_config" + directory = '.' + mock_return = {'config': 'test'} + mock_json_file_to_dict.return_value = mock_return + + config = Config(self.target, [directory], app_config=app_config) + + mock_json_file_to_dict.assert_called_once_with(app_config) + self.assertEqual(config.app_config_data, mock_return, + "app_config_data should be set to the returned value") + +if __name__ == '__main__': + unittest.main() diff --git a/tools/test/examples/examples.json b/tools/test/examples/examples.json new file mode 100644 index 00000000000..0beee5bda68 --- /dev/null +++ b/tools/test/examples/examples.json @@ -0,0 +1,12 @@ +{ + "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-blinky" : {}, + "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-Beacon" : + {"features": ["BLE"]}, + "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-HeartRate" : + {"features": ["BLE"]}, + "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-mesh-minimal" : + {"features": ["IPV6"]}, + "https://github.com/ARMmbed/mbed-os-example-client" : {"features": ["IPV6"]}, + "https://github.com/ARMmbed/mbed-os-example-sockets" : {"features": ["IPV6"]}, + "https://github.com/ARMmbed/mbed-os-example-uvisor" : {"targets": ["K64F"]} +} diff --git a/tools/test/examples/examples.py b/tools/test/examples/examples.py new file mode 100644 index 00000000000..50dafca931b --- /dev/null +++ b/tools/test/examples/examples.py @@ -0,0 +1,102 @@ +""" import and bulid a bunch of example programs """ + +from argparse import ArgumentParser +import os +from os.path import dirname, abspath, basename +import os.path +import sys +import subprocess +import json + +ROOT = abspath(dirname(dirname(dirname(dirname(__file__))))) +sys.path.insert(0, ROOT) + +from tools.build_api import get_mbed_official_release +from tools.targets import TARGET_MAP +from tools.utils import argparse_force_uppercase_type + + +EXAMPLES = json.load(open(os.path.join(os.path.dirname(__file__), + "examples.json"))) + +def print_stuff(name, lst): + if lst: + print("#"*80) + print("# {} example combinations".format(name)) + print("#") + for thing in lst: + print(thing) + + +SUPPORTED_TOOLCHAINS = ["ARM", "IAR", "GCC_ARM"] + + +def target_cross_toolchain(allowed_toolchains, + features=[], targets=TARGET_MAP.keys()): + """Generate pairs of target and toolchains + + Args: + allowed_toolchains - a list of all possible toolchains + + Kwargs: + features - the features that must be in the features array of a + target + targets - a list of available targets + """ + for target, toolchains in get_mbed_official_release("5"): + for toolchain in toolchains: + if (toolchain in allowed_toolchains and + target in targets and + all(feature in TARGET_MAP[target].features + for feature in features)): + yield target, toolchain + + +def main(): + """Entry point""" + parser = ArgumentParser() + subparsers = parser.add_subparsers() + import_cmd = subparsers.add_parser("import") + import_cmd.set_defaults(fn=do_import) + compile_cmd = subparsers.add_parser("compile") + compile_cmd.set_defaults(fn=do_compile) + compile_cmd.add_argument( + "toolchains", nargs="*", default=SUPPORTED_TOOLCHAINS, + type=argparse_force_uppercase_type(SUPPORTED_TOOLCHAINS, + "toolchain")) + args = parser.parse_args() + return args.fn(args) + + +def do_import(_): + """Do the import step of this process""" + for example, _ in EXAMPLES.iteritems(): + subprocess.call(["mbed-cli", "import", example]) + return 0 + + +def do_compile(args): + """Do the compile step""" + failures = [] + sucesses = [] + for example, requirements in EXAMPLES.iteritems(): + os.chdir(basename(example)) + for target, toolchain in target_cross_toolchain(args.toolchains, + **requirements): + proc = subprocess.Popen(["mbed-cli", "compile", "-t", toolchain, + "-m", target, "--silent"]) + proc.wait() + example_name = "{} {} {}".format(basename(example), target, + toolchain) + if proc.returncode: + failures.append(example_name) + else: + sucesses.append(example_name) + os.chdir("..") + + print_stuff("Passed", sucesses) + print_stuff("Failed", failures) + return len(failures) + +if __name__ == "__main__": + sys.exit(main()) diff --git a/tools/test/export/build_test.py b/tools/test/export/build_test.py index ec80fcfd004..e87b4875b15 100644 --- a/tools/test/export/build_test.py +++ b/tools/test/export/build_test.py @@ -1,7 +1,7 @@ #!/usr/bin/env python """ mbed SDK -Copyright (c) 2011-2013 ARM Limited +Copyright (c) 2011-2016 ARM Limited Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -16,154 +16,166 @@ limitations under the License. """ - import sys -import argparse -import os +from os import path, remove, rename import shutil -from os.path import join, abspath, dirname, exists, basename -r=dirname(__file__) -ROOT = abspath(join(r, "..","..","..")) +ROOT = path.abspath(path.join(path.dirname(__file__), "..", "..", "..")) sys.path.insert(0, ROOT) +import argparse from tools.export import EXPORTERS -from tools.targets import TARGET_NAMES, TARGET_MAP -from tools.project_api import setup_project, perform_export, print_results, get_test_from_name, get_lib_symbols -from project_generator_definitions.definitions import ProGenDef -from tools.utils import args_error - - -class ProgenBuildTest(): - def __init__(self, desired_ides, targets): - #map of targets and the ides that can build programs for them - self.target_ides = {} - for target in targets: - self.target_ides[target] =[] - for ide in desired_ides: - if target in EXPORTERS[ide].TARGETS: - #target is supported by ide - self.target_ides[target].append(ide) - if len(self.target_ides[target]) == 0: - del self.target_ides[target] - - - @staticmethod - def get_pgen_targets(ides): - #targets supported by pgen and desired ides for tests - targs = [] - for ide in ides: - for target in TARGET_NAMES: - if target not in targs and hasattr(TARGET_MAP[target],'progen') \ - and ProGenDef(ide).is_supported(TARGET_MAP[target].progen['target']): - targs.append(target) - return targs +from tools.targets import TARGET_NAMES +from tools.tests import TESTS +from tools.project import setup_project +from tools.project_api import print_results, export_project +from tools.tests import test_name_known, Test +from tools.export.exporters import FailedBuildException, \ + TargetNotSupportedException +from tools.utils import argparse_force_lowercase_type, \ + argparse_force_uppercase_type, argparse_many + + +class ProgenBuildTest(object): + """Object to encapsulate logic for progen build testing""" + def __init__(self, desired_ides, mcus, tests): + """ + Initialize an instance of class ProgenBuildTest + Args: + desired_ides: the IDEs you wish to make/build project files for + mcus: the mcus to specify in project files + tests: the test projects to make/build project files from + """ + self.ides = desired_ides + self.mcus = mcus + self.tests = tests + + @property + def mcu_ide_pairs(self): + """Yields tuples of valid mcu, ide combinations""" + for mcu in self.mcus: + for ide in self.ides: + if mcu in EXPORTERS[ide].TARGETS: + yield mcu, ide @staticmethod - def handle_project_files(project_dir, mcu, test, tool, clean=False): + def handle_log_files(project_dir, tool, name): + """ + Renames/moves log files + Args: + project_dir: the directory that contains project files + tool: the ide that created the project files + name: the name of the project + clean: a boolean value determining whether to remove the + created project files + """ log = '' if tool == 'uvision' or tool == 'uvision5': - log = os.path.join(project_dir,"build","build_log.txt") + log = path.join(project_dir, "build", "build_log.txt") elif tool == 'iar': - log = os.path.join(project_dir, 'build_log.txt') + log = path.join(project_dir, 'build_log.txt') try: - with open(log, 'r') as f: - print f.read() - except: - return - - prefix = "_".join([test, mcu, tool]) - log_name = os.path.join(os.path.dirname(project_dir), prefix+"_log.txt") - - #check if a log already exists for this platform+test+ide - if os.path.exists(log_name): - #delete it if so - os.remove(log_name) - os.rename(log, log_name) - - if clean: - shutil.rmtree(project_dir, ignore_errors=True) - return - - def generate_and_build(self, tests, clean=False): - - #build results + with open(log, 'r') as in_log: + print in_log.read() + log_name = path.join(path.dirname(project_dir), name + "_log.txt") + + # check if a log already exists for this platform+test+ide + if path.exists(log_name): + # delete it if so + remove(log_name) + rename(log, log_name) + except IOError: + pass + + def generate_and_build(self, clean=False): + """ + Generate the project file and build the project + Args: + clean: a boolean value determining whether to remove the + created project files + + Returns: + successes: a list of strings that contain the mcu, ide, test + properties of a successful build test + skips: a list of strings that contain the mcu, ide, test properties + of a skipped test (if the ide does not support mcu) + failures: a list of strings that contain the mcu, ide, test + properties of a failed build test + + """ successes = [] failures = [] skips = [] - for mcu, ides in self.target_ides.items(): - for test in tests: - #resolve name alias - test = get_test_from_name(test) - for ide in ides: - lib_symbols = get_lib_symbols(None, None, test) - project_dir, project_name, project_temp = setup_project(mcu, ide, test) - - dest_dir = os.path.dirname(project_temp) - destination = os.path.join(dest_dir,"_".join([project_name, mcu, ide])) - - tmp_path, report = perform_export(project_dir, project_name, ide, mcu, destination, - lib_symbols=lib_symbols, progen_build = True) - - if report['success']: - successes.append("build for %s::%s\t%s" % (mcu, ide, project_name)) - elif report['skip']: - skips.append("%s::%s\t%s" % (mcu, ide, project_name)) - else: - failures.append("%s::%s\t%s for %s" % (mcu, ide, report['errormsg'], project_name)) - - ProgenBuildTest.handle_project_files(destination, mcu, project_name, ide, clean) + for mcu, ide in self.mcu_ide_pairs: + for test in self.tests: + export_location, name, src, lib = setup_project(ide, mcu, + program=test) + test_name = Test(test).id + try: + exporter = export_project(src, export_location, mcu, ide, + clean=clean, name=name, + libraries_paths=lib) + exporter.progen_build() + successes.append("%s::%s\t%s" % (mcu, ide, test_name)) + except FailedBuildException: + failures.append("%s::%s\t%s" % (mcu, ide, test_name)) + except TargetNotSupportedException: + skips.append("%s::%s\t%s" % (mcu, ide, test_name)) + + ProgenBuildTest.handle_log_files(export_location, ide, name) + if clean: + shutil.rmtree(export_location, ignore_errors=True) return successes, failures, skips -if __name__ == '__main__': - accepted_ides = ["iar", "uvision", "uvision5"] - accepted_targets = sorted(ProgenBuildTest.get_pgen_targets(accepted_ides)) - default_tests = ["MBED_BLINKY"] - - parser = argparse.ArgumentParser(description = "Test progen builders. Leave any flag off to run with all possible options.") - parser.add_argument("-i", "--IDEs", - nargs = '+', - dest="ides", - help="tools you wish to perfrom build tests. (%s)" % ', '.join(accepted_ides), - default = accepted_ides) +def main(): + """Entry point""" + toolchainlist = ["iar", "uvision", "uvision5"] + default_tests = [test_name_known("MBED_BLINKY")] + targetnames = TARGET_NAMES + targetnames.sort() + + parser = argparse.ArgumentParser(description= + "Test progen builders. Leave any flag off" + " to run with all possible options.") + parser.add_argument("-i", + dest="ides", + default=toolchainlist, + type=argparse_many(argparse_force_lowercase_type( + toolchainlist, "toolchain")), + help="The target IDE: %s"% str(toolchainlist)) + + parser.add_argument( + "-p", + type=argparse_many(test_name_known), + dest="programs", + help="The index of the desired test program: [0-%d]" % (len(TESTS) - 1), + default=default_tests) parser.add_argument("-n", - nargs='+', - dest="tests", - help="names of desired test programs", - default = default_tests) - - parser.add_argument("-m", "--mcus", - nargs='+', - dest ="targets", - help="generate project for the given MCUs (%s)" % '\n '.join(accepted_targets), - default = accepted_targets) + type=argparse_many(test_name_known), + dest="programs", + help="The name of the desired test program", + default=default_tests) + + parser.add_argument( + "-m", "--mcu", + metavar="MCU", + default='LPC1768', + nargs="+", + type=argparse_force_uppercase_type(targetnames, "MCU"), + help="generate project for the given MCU (%s)" % ', '.join(targetnames)) parser.add_argument("-c", "--clean", dest="clean", - action = "store_true", + action="store_true", help="clean up the exported project files", default=False) options = parser.parse_args() - - tests = options.tests - ides = [ide.lower() for ide in options.ides] - targets = [target.upper() for target in options.targets] - - if any(get_test_from_name(test) is None for test in tests): - args_error(parser, "[ERROR] test name not recognized") - - if any(target not in accepted_targets for target in targets): - args_error(parser, "[ERROR] mcu must be one of the following:\n %s" % '\n '.join(accepted_targets)) - - if any(ide not in accepted_ides for ide in ides): - args_error(parser, "[ERROR] ide must be in %s" % ', '.join(accepted_ides)) - - build_test = ProgenBuildTest(ides, targets) - successes, failures, skips = build_test.generate_and_build(tests, options.clean) + test = ProgenBuildTest(options.ides, options.mcu, options.programs) + successes, failures, skips = test.generate_and_build(clean=options.clean) print_results(successes, failures, skips) sys.exit(len(failures)) - - +if __name__ == "__main__": + main() diff --git a/tools/test/test_api/test_api_test.py b/tools/test/test_api/test_api_test.py new file mode 100644 index 00000000000..9f16941b04d --- /dev/null +++ b/tools/test/test_api/test_api_test.py @@ -0,0 +1,141 @@ +""" +mbed SDK +Copyright (c) 2016 ARM Limited + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + +import unittest +from mock import patch +from tools.test_api import find_tests, build_tests + +""" +Tests for test_api.py +""" + +class TestApiTests(unittest.TestCase): + """ + Test cases for Test Api + """ + + def setUp(self): + """ + Called before each test case + + :return: + """ + self.base_dir = 'base_dir' + self.target = "K64F" + self.toolchain_name = "ARM" + + def tearDown(self): + """ + Called after each test case + + :return: + """ + pass + + @patch('tools.test_api.scan_resources') + @patch('tools.test_api.prepare_toolchain') + def test_find_tests_app_config(self, mock_prepare_toolchain, mock_scan_resources): + """ + Test find_tests for correct use of app_config + + :param mock_prepare_toolchain: mock of function prepare_toolchain + :param mock_scan_resources: mock of function scan_resources + :return: + """ + app_config = "app_config" + mock_scan_resources().inc_dirs.return_value = [] + + find_tests(self.base_dir, self.target, self.toolchain_name, app_config=app_config) + + args = mock_prepare_toolchain.call_args + self.assertTrue('app_config' in args[1], + "prepare_toolchain was not called with app_config") + self.assertEqual(args[1]['app_config'], app_config, + "prepare_toolchain was called with an incorrect app_config") + + @patch('tools.test_api.scan_resources') + @patch('tools.test_api.prepare_toolchain') + def test_find_tests_no_app_config(self, mock_prepare_toolchain, mock_scan_resources): + """ + Test find_tests correctly deals with no app_config + + :param mock_prepare_toolchain: mock of function prepare_toolchain + :param mock_scan_resources: mock of function scan_resources + :return: + """ + mock_scan_resources().inc_dirs.return_value = [] + + find_tests(self.base_dir, self.target, self.toolchain_name) + + args = mock_prepare_toolchain.call_args + self.assertTrue('app_config' in args[1], + "prepare_toolchain was not called with app_config") + self.assertEqual(args[1]['app_config'], None, + "prepare_toolchain was called with an incorrect app_config") + + @patch('tools.test_api.scan_resources') + @patch('tools.test_api.build_project') + def test_build_tests_app_config(self, mock_build_project, mock_scan_resources): + """ + Test build_tests for correct use of app_config + + :param mock_prepare_toolchain: mock of function prepare_toolchain + :param mock_scan_resources: mock of function scan_resources + :return: + """ + tests = {'test1': 'test1_path','test2': 'test2_path'} + src_paths = ['.'] + build_path = "build_path" + app_config = "app_config" + mock_build_project.return_value = "build_project" + + build_tests(tests, src_paths, build_path, self.target, self.toolchain_name, + app_config=app_config) + + arg_list = mock_build_project.call_args_list + for args in arg_list: + self.assertTrue('app_config' in args[1], + "build_tests was not called with app_config") + self.assertEqual(args[1]['app_config'], app_config, + "build_tests was called with an incorrect app_config") + + @patch('tools.test_api.scan_resources') + @patch('tools.test_api.build_project') + def test_build_tests_no_app_config(self, mock_build_project, mock_scan_resources): + """ + Test build_tests correctly deals with no app_config + + :param mock_prepare_toolchain: mock of function prepare_toolchain + :param mock_scan_resources: mock of function scan_resources + :return: + """ + tests = {'test1': 'test1_path', 'test2': 'test2_path'} + src_paths = ['.'] + build_path = "build_path" + mock_build_project.return_value = "build_project" + + build_tests(tests, src_paths, build_path, self.target, self.toolchain_name) + + arg_list = mock_build_project.call_args_list + for args in arg_list: + self.assertTrue('app_config' in args[1], + "build_tests was not called with app_config") + self.assertEqual(args[1]['app_config'], None, + "build_tests was called with an incorrect app_config") + +if __name__ == '__main__': + unittest.main() diff --git a/tools/test_api.py b/tools/test_api.py index d995e1bf469..3c05788e2b4 100644 --- a/tools/test_api.py +++ b/tools/test_api.py @@ -1978,33 +1978,35 @@ def get_default_test_options_parser(): help='Prints script version and exits') return parser -def test_path_to_name(path): +def test_path_to_name(path, base): """Change all slashes in a path into hyphens This creates a unique cross-platform test name based on the path This can eventually be overriden by a to-be-determined meta-data mechanism""" name_parts = [] - head, tail = os.path.split(path) + head, tail = os.path.split(relpath(path,base)) while (tail and tail != "."): name_parts.insert(0, tail) head, tail = os.path.split(head) return "-".join(name_parts).lower() -def find_tests(base_dir, target_name, toolchain_name, options=None): +def find_tests(base_dir, target_name, toolchain_name, options=None, app_config=None): """ Finds all tests in a directory recursively base_dir: path to the directory to scan for tests (ex. 'path/to/project') target_name: name of the target to use for scanning (ex. 'K64F') toolchain_name: name of the toolchain to use for scanning (ex. 'GCC_ARM') options: Compile options to pass to the toolchain (ex. ['debug-info']) + app_config - location of a chosen mbed_app.json file """ tests = {} # Prepare the toolchain - toolchain = prepare_toolchain(base_dir, target_name, toolchain_name, options=options, silent=True) + toolchain = prepare_toolchain([base_dir], target_name, toolchain_name, options=options, + silent=True, app_config=app_config) # Scan the directory for paths to probe for 'TESTS' folders - base_resources = scan_resources(base_dir, toolchain) + base_resources = scan_resources([base_dir], toolchain) dirs = base_resources.inc_dirs for directory in dirs: @@ -2028,7 +2030,7 @@ def find_tests(base_dir, target_name, toolchain_name, options=None): # Check to make sure discoverd folder is not in a host test directory if test_case_directory != 'host_tests' and test_group_directory != 'host_tests': - test_name = test_path_to_name(d) + test_name = test_path_to_name(d, base_dir) tests[test_name] = d return tests @@ -2060,7 +2062,7 @@ def norm_relative_path(path, start): def build_tests(tests, base_source_paths, build_path, target, toolchain_name, options=None, clean=False, notify=None, verbose=False, jobs=1, macros=None, silent=False, report=None, properties=None, - continue_on_build_fail=False): + continue_on_build_fail=False, app_config=None): """Given the data structure from 'find_tests' and the typical build parameters, build all the tests @@ -2101,7 +2103,8 @@ def build_tests(tests, base_source_paths, build_path, target, toolchain_name, project_id=test_name, report=report, properties=properties, - verbose=verbose) + verbose=verbose, + app_config=app_config) except Exception, e: if not isinstance(e, NotSupportedException): diff --git a/tools/tests.py b/tools/tests.py index 66da1249ef5..2033dd53a06 100644 --- a/tools/tests.py +++ b/tools/tests.py @@ -182,7 +182,7 @@ "peripherals": ["analog_loop"], "mcu": ["LPC1768", "LPC2368", "LPC2460", "KL25Z", "K64F", "K66F", "K22F", "LPC4088", "LPC1549", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_F302R8", "NUCLEO_F303K8", "NUCLEO_F303RE", "NUCLEO_F207ZG", - "NUCLEO_F334R8", "NUCLEO_L053R8", "NUCLEO_L073RZ", "NUCLEO_L152RE", + "NUCLEO_F334R8", "NUCLEO_F303ZE", "NUCLEO_L053R8", "NUCLEO_L073RZ", "NUCLEO_L152RE", "NUCLEO_F410RB", "NUCLEO_F411RE", "NUCLEO_F446RE", "NUCLEO_F446ZE", "DISCO_F407VG", "DISCO_F746NG", "NUCLEO_F746ZG", "ARCH_MAX", "MAX32600MBED", "MOTE_L152RC", "B96B_F446VE"] @@ -325,7 +325,8 @@ "NUCLEO_F091RC", "NUCLEO_F072RB", "NUCLEO_F042K6", "NUCLEO_F334R8", "NUCLEO_F207ZG", "NUCLEO_F303RE", "NUCLEO_F303K8", "NUCLEO_F302R8", "NUCLEO_F446RE","NUCLEO_F446ZE", "DISCO_F469NI", "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG", - "DISCO_F746NG", "DISCO_L476VG", "NUCLEO_L476RG", "NUCLEO_L432KC"] + "DISCO_F746NG", "DISCO_L476VG", "NUCLEO_L476RG", "NUCLEO_L432KC", + "DISCO_F769NI"] }, { "id": "MBED_A28", "description": "CAN loopback test", @@ -335,9 +336,10 @@ "duration": 20, "mcu": ["B96B_F446VE", "NUCLEO_F091RC", "NUCLEO_F072RB", "NUCLEO_F042K6", "NUCLEO_F334R8", "NUCLEO_F207ZG", - "NUCLEO_F303RE", "NUCLEO_F303K8", "NUCLEO_F302R8", "NUCLEO_F446RE","NUCLEO_F446ZE", + "NUCLEO_F303RE", "NUCLEO_F303K8", "NUCLEO_F302R8", "NUCLEO_F303ZE", "NUCLEO_F446RE","NUCLEO_F446ZE", "DISCO_F469NI", "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG", - "DISCO_F746NG", "DISCO_L476VG", "NUCLEO_L476RG", "NUCLEO_L432KC"] + "DISCO_F746NG", "DISCO_L476VG", "NUCLEO_L476RG", "NUCLEO_L432KC", + "DISCO_F769NI"] }, { "id": "MBED_BLINKY", "description": "Blinky", @@ -745,9 +747,9 @@ "RZ_A1H", "VK_RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "DISCO_F469NI", "NUCLEO_F410RB", "NUCLEO_F429ZI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F070RB", "NUCLEO_F207ZG", "NUCLEO_L031K6", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", - "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", + "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303ZE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", "EFM32HG_STK3400", "EFM32PG_STK3401", "EFM32LG_STK3600", "EFM32GG_STK3700", "EFM32WG_STK3800", - "NRF51822", "NRF51_DK", "SEEED_TINY_BLE", "ARM_BEETLE_SOC", "NUCLEO_F767ZI"], + "NRF51822", "NRF51_DK", "SEEED_TINY_BLE", "ARM_BEETLE_SOC", "NUCLEO_F767ZI", "DISCO_F769NI"], }, { "id": "RTOS_2", "description": "Mutex resource lock", @@ -758,12 +760,12 @@ "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "K66F", "KL46Z", "HEXIWEAR", "RZ_A1H", "VK_RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "DISCO_F469NI", "NUCLEO_F410RB", "NUCLEO_F429ZI", - "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F070RB", "NUCLEO_F207ZG", + "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F303ZE", "NUCLEO_F070RB", "NUCLEO_F207ZG", "NUCLEO_L031K6", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F446ZE", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", "EFM32HG_STK3400", "EFM32PG_STK3401", "EFM32LG_STK3600", "EFM32GG_STK3700", "EFM32WG_STK3800", - "NRF51822", "NRF51_DK", "SEEED_TINY_BLE", "ARM_BEETLE_SOC", "NUCLEO_F767ZI"], + "NRF51822", "NRF51_DK", "SEEED_TINY_BLE", "ARM_BEETLE_SOC", "NUCLEO_F767ZI", "DISCO_F769NI"], }, { "id": "RTOS_3", "description": "Semaphore resource lock", @@ -774,13 +776,13 @@ "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "K66F", "KL46Z", "HEXIWEAR", "RZ_A1H", "VK_RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "DISCO_F469NI", "NUCLEO_F410RB", "NUCLEO_F429ZI", - "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F070RB", "NUCLEO_F207ZG", + "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F303ZE", "NUCLEO_F070RB", "NUCLEO_F207ZG", "NUCLEO_L031K6", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", "EFM32HG_STK3400", "EFM32PG_STK3401", "EFM32LG_STK3600", "EFM32GG_STK3700", "EFM32WG_STK3800", - "NRF51822", "NRF51_DK", "SEEED_TINY_BLE", "ARM_BEETLE_SOC", "NUCLEO_F767ZI"], + "NRF51822", "NRF51_DK", "SEEED_TINY_BLE", "ARM_BEETLE_SOC", "NUCLEO_F767ZI", "DISCO_F769NI"], }, { "id": "RTOS_4", "description": "Signals messaging", @@ -790,13 +792,13 @@ "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "K66F", "KL46Z", "HEXIWEAR", "RZ_A1H", "VK_RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "DISCO_F469NI", "NUCLEO_F410RB", "NUCLEO_F429ZI", - "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F070RB", "NUCLEO_F207ZG", + "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F303ZE", "NUCLEO_F070RB", "NUCLEO_F207ZG", "NUCLEO_L031K6", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", "EFM32HG_STK3400", "EFM32PG_STK3401", "EFM32LG_STK3600", "EFM32GG_STK3700", "EFM32WG_STK3800", - "NRF51822", "NRF51_DK", "SEEED_TINY_BLE", "ARM_BEETLE_SOC", "NUCLEO_F767ZI"], + "NRF51822", "NRF51_DK", "SEEED_TINY_BLE", "ARM_BEETLE_SOC", "NUCLEO_F767ZI", "DISCO_F769NI"], }, { "id": "RTOS_5", "description": "Queue messaging", @@ -806,12 +808,12 @@ "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "K66F", "KL46Z", "HEXIWEAR", "RZ_A1H", "VK_RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "DISCO_F469NI", "NUCLEO_F410RB", "NUCLEO_F429ZI", - "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F070RB", "NUCLEO_F207ZG", + "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F303ZE", "NUCLEO_F070RB", "NUCLEO_F207ZG", "NUCLEO_L031K6", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", "EFM32HG_STK3400", "EFM32PG_STK3401", "EFM32LG_STK3600", "EFM32GG_STK3700", "EFM32WG_STK3800", - "NRF51822", "NRF51_DK", "SEEED_TINY_BLE", "ARM_BEETLE_SOC", "NUCLEO_F767ZI"], + "NRF51822", "NRF51_DK", "SEEED_TINY_BLE", "ARM_BEETLE_SOC", "NUCLEO_F767ZI", "DISCO_F769NI"], }, { "id": "RTOS_6", "description": "Mail messaging", @@ -821,12 +823,12 @@ "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "K66F", "KL46Z", "HEXIWEAR", "RZ_A1H", "VK_RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "DISCO_F469NI", "NUCLEO_F410RB", "NUCLEO_F429ZI", - "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F070RB", "NUCLEO_F207ZG", + "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F303ZE", "NUCLEO_F070RB", "NUCLEO_F207ZG", "NUCLEO_L031K6", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", "EFM32HG_STK3400", "EFM32PG_STK3401", "EFM32LG_STK3600", "EFM32GG_STK3700", "EFM32WG_STK3800", - "NRF51822", "NRF51_DK", "SEEED_TINY_BLE", "ARM_BEETLE_SOC", "NUCLEO_F767ZI"], + "NRF51822", "NRF51_DK", "SEEED_TINY_BLE", "ARM_BEETLE_SOC", "NUCLEO_F767ZI", "DISCO_F769NI"], }, { "id": "RTOS_7", "description": "Timer", @@ -838,12 +840,12 @@ "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "K66F", "KL46Z", "HEXIWEAR", "RZ_A1H", "VK_RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "DISCO_F469NI", "NUCLEO_F410RB", "NUCLEO_F429ZI", - "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F070RB", "NUCLEO_F207ZG", + "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F303ZE", "NUCLEO_F070RB", "NUCLEO_F207ZG", "NUCLEO_L031K6", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", "EFM32HG_STK3400", "EFM32PG_STK3401", "EFM32LG_STK3600", "EFM32GG_STK3700", "EFM32WG_STK3800", - "NRF51822", "NRF51_DK", "SEEED_TINY_BLE", "ARM_BEETLE_SOC", "NUCLEO_F767ZI"], + "NRF51822", "NRF51_DK", "SEEED_TINY_BLE", "ARM_BEETLE_SOC", "NUCLEO_F767ZI", "DISCO_F769NI"], }, { "id": "RTOS_8", "description": "ISR (Queue)", @@ -853,12 +855,12 @@ "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "K66F", "KL46Z", "HEXIWEAR", "RZ_A1H", "VK_RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "DISCO_F469NI", "NUCLEO_F410RB", "NUCLEO_F429ZI", - "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F070RB", "NUCLEO_F207ZG", + "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F303ZE", "NUCLEO_F070RB", "NUCLEO_F207ZG", "NUCLEO_L031K6", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", "EFM32HG_STK3400", "EFM32PG_STK3401", "EFM32LG_STK3600", "EFM32GG_STK3700", "EFM32WG_STK3800", - "NRF51822", "NRF51_DK", "SEEED_TINY_BLE", "ARM_BEETLE_SOC", "NUCLEO_F767ZI"], + "NRF51822", "NRF51_DK", "SEEED_TINY_BLE", "ARM_BEETLE_SOC", "NUCLEO_F767ZI", "DISCO_F769NI"], }, { "id": "RTOS_9", "description": "SD File write-read", @@ -1253,7 +1255,7 @@ def test_known(string): def test_name_known(string): if string not in TEST_MAP.keys() and \ (getattr(ps, "test_alias", None) is None or \ - ps.test_alias.get(test_id, "") not in TEST_MAP.keys()): + ps.test_alias.get(string, "") not in TEST_MAP.keys()): raise ArgumentTypeError("Program with name '{0}' not found. Supported tests are: \n{1}".format(string, columnate([t['id'] for t in TESTS]))) return TEST_MAP[string].n diff --git a/tools/toolchains/__init__.py b/tools/toolchains/__init__.py index 1bb892cf8c7..ed351006da5 100644 --- a/tools/toolchains/__init__.py +++ b/tools/toolchains/__init__.py @@ -564,6 +564,7 @@ def _add_dir(self, path, resources, base_path, exclude_paths=None): # Add root to include paths resources.inc_dirs.append(root) + resources.file_basepath[root] = base_path for file in files: file_path = join(root, file) @@ -953,6 +954,7 @@ def link_program(self, r, tmp_path, name): bin = join(tmp_path, filename) map = join(tmp_path, name + '.map') + r.objects = sorted(set(r.objects)) if self.need_update(elf, r.objects + r.libraries + [r.linker_script]): needed_update = True self.progress("link", name) diff --git a/tools/toolchains/gcc.py b/tools/toolchains/gcc.py index 30281e8d340..b7cb7d68bc0 100644 --- a/tools/toolchains/gcc.py +++ b/tools/toolchains/gcc.py @@ -40,7 +40,7 @@ class GCC(mbedToolchain): 'c': ["-std=gnu99"], 'cxx': ["-std=gnu++98", "-fno-rtti", "-Wvla"], 'ld': ["-Wl,--gc-sections", "-Wl,--wrap,main", - "-Wl,--wrap,_malloc_r", "-Wl,--wrap,_free_r", "-Wl,--wrap,_realloc_r"], + "-Wl,--wrap,_malloc_r", "-Wl,--wrap,_free_r", "-Wl,--wrap,_realloc_r", "-Wl,--wrap,_calloc_r"], } def __init__(self, target, options=None, notify=None, macros=None, silent=False, tool_path="", extra_verbose=False): diff --git a/tools/utils.py b/tools/utils.py index db103d7c117..b250491dc0c 100644 --- a/tools/utils.py +++ b/tools/utils.py @@ -282,9 +282,8 @@ def args_error(parser, message): parser - the ArgumentParser object that parsed the command line message - what went wrong """ - print "\n\n%s\n\n" % message - parser.print_help() - sys.exit() + parser.error(message) + sys.exit(2) def construct_enum(**enums):