diff --git a/TESTS/integration/COMMON/target_extended.json b/TESTS/integration/COMMON/target_extended.json index c708a827093..5a6c4c3e1b6 100644 --- a/TESTS/integration/COMMON/target_extended.json +++ b/TESTS/integration/COMMON/target_extended.json @@ -197,13 +197,6 @@ "nanostack.configuration" : "thread_router", "nanostack-hal.event_loop_thread_stack_size": 8192 }, - "MTB_USI_WM_BN_BM_22": { - "target.components_add" : ["SPIF"], - "spif-driver.SPI_MOSI" : "PC_3", - "spif-driver.SPI_MISO" : "PC_2", - "spif-driver.SPI_CLK" : "PB_13", - "spif-driver.SPI_CS" : "PA_6" - }, "MTB_ADV_WISE_1570": { "target.components_add" : ["SPIF"], "spif-driver.SPI_FREQ" : 20000000, @@ -214,15 +207,6 @@ "platform.default-serial-baud-rate" : 115200, "nsapi.dns-response-wait-time" : 30000 }, - "MTB_ADV_WISE_1530": { - "target.components_add" : ["SPIF"], - "spif-driver.SPI_MOSI" : "PC_3", - "spif-driver.SPI_MISO" : "PC_2", - "spif-driver.SPI_CLK" : "PB_13", - "spif-driver.SPI_CS" : "PC_12", - "no_led" : "1", - "tests-fs-size" : "2*1024*1024" - }, "MCU_PSOC6": { "tests-fs-size" : "8*1024*1024" }, diff --git a/TESTS/lorawan/loraradio/template_mbed_app.txt b/TESTS/lorawan/loraradio/template_mbed_app.txt index da5d12d0a7b..86558435168 100644 --- a/TESTS/lorawan/loraradio/template_mbed_app.txt +++ b/TESTS/lorawan/loraradio/template_mbed_app.txt @@ -69,28 +69,6 @@ "lora-tcxo": "PA_12" }, - "MTB_MURATA_ABZ": { - "lora-radio": "SX1276", - "lora-spi-mosi": "PA_7", - "lora-spi-miso": "PA_6", - "lora-spi-sclk": "PB_3", - "lora-cs": "PA_15", - "lora-reset": "PC_0", - "lora-dio0": "PB_4", - "lora-dio1": "PB_1", - "lora-dio2": "PB_0", - "lora-dio3": "PC_13", - "lora-dio4": "NC", - "lora-dio5": "NC", - "lora-rf-switch-ctl1": "NC", - "lora-rf-switch-ctl2": "NC", - "lora-txctl": "PC_2", - "lora-rxctl": "PA_1", - "lora-ant-switch": "NC", - "lora-pwr-amp-ctl": "PC_1", - "lora-tcxo": "PA_12" - }, - "XDOT_L151CC": { "lora-radio": "SX1272", "lora-spi-mosi": "LORA_MOSI", @@ -113,28 +91,6 @@ "lora-tcxo": "NC" }, - "MTB_MTS_XDOT": { - "lora-radio": "SX1272", - "lora-spi-mosi": "LORA_MOSI", - "lora-spi-miso": "LORA_MISO", - "lora-spi-sclk": "LORA_SCK", - "lora-cs": "LORA_NSS", - "lora-reset": "LORA_RESET", - "lora-dio0": "LORA_DIO0", - "lora-dio1": "LORA_DIO1", - "lora-dio2": "LORA_DIO2", - "lora-dio3": "LORA_DIO3", - "lora-dio4": "LORA_DIO4", - "lora-dio5": "NC", - "lora-rf-switch-ctl1": "NC", - "lora-rf-switch-ctl2": "NC", - "lora-txctl": "NC", - "lora-rxctl": "NC", - "lora-ant-switch": "NC", - "lora-pwr-amp-ctl": "NC", - "lora-tcxo": "NC" - }, - "LTEK_FF1705": { "lora-radio": "SX1272", "lora-spi-mosi": "LORA_MOSI", @@ -199,28 +155,6 @@ "lora-ant-switch": "ANT_SWITCH", "lora-pwr-amp-ctl": "NC", "lora-tcxo": "NC" - }, - - "MTB_RAK811": { - "lora-radio": "SX1276", - "lora-spi-mosi": "SPI_RF_MOSI", - "lora-spi-miso": "SPI_RF_MISO", - "lora-spi-sclk": "SPI_RF_SCK", - "lora-cs": "SPI_RF_CS", - "lora-reset": "SPI_RF_RESET", - "lora-dio0": "DIO0", - "lora-dio1": "DIO1", - "lora-dio2": "DIO2", - "lora-dio3": "DIO3", - "lora-dio4": "DIO4", - "lora-dio5": "NC", - "lora-rf-switch-ctl1": "NC", - "lora-rf-switch-ctl2": "NC", - "lora-txctl": "ANT_CTX_PA", - "lora-rxctl": "ANT_CRX_RX", - "lora-ant-switch": "NC", - "lora-pwr-amp-ctl": "NC", - "lora-tcxo": "RF_TCXO_EN" } } } diff --git a/TESTS/network/emac/main.cpp b/TESTS/network/emac/main.cpp index bbc98d06134..6baa8b6fc76 100644 --- a/TESTS/network/emac/main.cpp +++ b/TESTS/network/emac/main.cpp @@ -32,14 +32,6 @@ #error [NOT_SUPPORTED] Either wifi or ethernet testing need to be enabled #else -#if (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI) && \ - !defined(TARGET_MTB_ADV_WISE_1530) && \ - !defined(TARGET_MTB_USI_WM_BN_BM_22) && \ - !defined(TARGET_WIO_EMW3166) -#error [NOT_SUPPORTED] Wifi tests are not valid for the target -#else - - #include "greentea-client/test_env.h" #include "unity.h" diff --git a/TESTS/network/emac/mbed_lib.json b/TESTS/network/emac/mbed_lib.json index 08b4f457a7b..95791153052 100644 --- a/TESTS/network/emac/mbed_lib.json +++ b/TESTS/network/emac/mbed_lib.json @@ -7,12 +7,6 @@ "target_overrides": { "WIO_EMW3166": { "NO_SUPPORT_FOR_IPV4_MULTICAST_FILTER": true - }, - "MTB_ADV_WISE_1530": { - "NO_SUPPORT_FOR_IPV4_MULTICAST_FILTER": true - }, - "MTB_USI_WM_BN_BM_22": { - "NO_SUPPORT_FOR_IPV4_MULTICAST_FILTER": true } } } diff --git a/components/802.15.4_RF/stm-s2lp-rf-driver/mbed_lib.json b/components/802.15.4_RF/stm-s2lp-rf-driver/mbed_lib.json index ada37130b07..a820f4f18fa 100644 --- a/components/802.15.4_RF/stm-s2lp-rf-driver/mbed_lib.json +++ b/components/802.15.4_RF/stm-s2lp-rf-driver/mbed_lib.json @@ -4,11 +4,6 @@ "provide-default": { "help": "Provide default NanostackRfpy. [true/false]", "value": false - }, - "target_overrides": { - "MTB_STM_S2LP": { - "s2lp.provide-default": true - } } } } diff --git a/components/802.15.4_RF/stm-s2lp-rf-driver/stm-s2lp-rf-driver/NanostackRfPhys2lp.h b/components/802.15.4_RF/stm-s2lp-rf-driver/stm-s2lp-rf-driver/NanostackRfPhys2lp.h index 2b9038a84e9..614518b95d5 100644 --- a/components/802.15.4_RF/stm-s2lp-rf-driver/stm-s2lp-rf-driver/NanostackRfPhys2lp.h +++ b/components/802.15.4_RF/stm-s2lp-rf-driver/stm-s2lp-rf-driver/NanostackRfPhys2lp.h @@ -28,42 +28,6 @@ // Uncomment to use testing gpios attached to TX/RX processes // #define TEST_GPIOS_ENABLED -#if defined(TARGET_MTB_STM_S2LP) -#if !defined(S2LP_SPI_SDI) -#define S2LP_SPI_SDI PA_7 -#endif -#if !defined(S2LP_SPI_SDO) -#define S2LP_SPI_SDO PA_6 -#endif -#if !defined(S2LP_SPI_SCLK) -#define S2LP_SPI_SCLK PA_5 -#endif -#if !defined(S2LP_SPI_CS) -#define S2LP_SPI_CS PC_0 -#endif -#if !defined(S2LP_SPI_SDN) -#define S2LP_SPI_SDN PF_13 -#endif -#if !defined(S2LP_SPI_GPIO0) -#define S2LP_SPI_GPIO0 PA_3 -#endif -#if !defined(S2LP_SPI_GPIO1) -#define S2LP_SPI_GPIO1 PC_3 -#endif -#if !defined(S2LP_SPI_GPIO2) -#define S2LP_SPI_GPIO2 PF_3 -#endif -#if !defined(S2LP_SPI_GPIO3) -#define S2LP_SPI_GPIO3 PF_10 -#endif -#if !defined(S2LP_I2C_SDA) -#define S2LP_I2C_SDA PB_7 -#endif -#if !defined(S2LP_I2C_SCL) -#define S2LP_I2C_SCL PB_6 -#endif -#define AT24MAC -#else #if !defined(S2LP_SPI_SDI) #define S2LP_SPI_SDI D11 #endif @@ -106,7 +70,6 @@ #if !defined(S2LP_SPI_GPIO3) #define S2LP_SPI_GPIO3 A5 #endif -#endif #include "at24mac_s2lp.h" @@ -116,11 +79,11 @@ class TestPins_S2LP; class NanostackRfPhys2lp : public NanostackRfPhy { public: NanostackRfPhys2lp(PinName spi_sdi, PinName spi_sdo, PinName spi_sclk, PinName spi_cs, PinName spi_sdn - ,PinName spi_gpio0, PinName spi_gpio1, PinName spi_gpio2, PinName spi_gpio3 + , PinName spi_gpio0, PinName spi_gpio1, PinName spi_gpio2, PinName spi_gpio3 #ifdef AT24MAC - ,PinName i2c_sda, PinName i2c_scl + , PinName i2c_sda, PinName i2c_scl #endif //AT24MAC - ); + ); virtual ~NanostackRfPhys2lp(); virtual int8_t rf_register(); virtual void rf_unregister(); diff --git a/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json b/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json index cead28a9a59..fa991fe35aa 100644 --- a/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json +++ b/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json @@ -71,12 +71,6 @@ "SPI_CLK": "PTE2", "SPI_CS": "PTE4" }, - "LPC11U37H_401": { - "SPI_MOSI": "SDMOSI", - "SPI_MISO": "SDMISO", - "SPI_CLK": "SDSCLK", - "SPI_CS": "SDSSEL" - }, "LPC2368": { "SPI_MOSI": "p11", "SPI_MISO": "p12", @@ -131,12 +125,6 @@ "SPI_CLK": "PTE2", "SPI_CS": "PTE4" }, - "MTB_MTS_DRAGONFLY": { - "SPI_MOSI": "SPI2_MOSI", - "SPI_MISO": "SPI2_MISO", - "SPI_CLK": "SPI2_SCK", - "SPI_CS": "SPI_CS2" - }, "TB_SENSE_12": { "SPI_MOSI": "PC6", "SPI_MISO": "PC7", diff --git a/components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json b/components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json index cfb7b79ef4f..6c63c96f388 100644 --- a/components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json +++ b/components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json @@ -37,24 +37,12 @@ "SPI_CLK": "PTD5", "SPI_CS": "PTD4" }, - "MTB_ADV_WISE_1530": { - "SPI_MOSI": "PC_3", - "SPI_MISO": "PC_2", - "SPI_CLK": "PB_13", - "SPI_CS": "PC_12" - }, "WIO_EMW3166": { "SPI_MOSI": "PB_15", "SPI_MISO": "PB_14", "SPI_CLK": "PB_13", "SPI_CS": "PA_10" }, - "MTB_USI_WM_BN_BM_22": { - "SPI_MOSI": "PC_3", - "SPI_MISO": "PC_2", - "SPI_CLK": "PB_13", - "SPI_CS": "PA_6" - }, "MTB_ADV_WISE_1570": { "SPI_MOSI": "PA_7", "SPI_MISO": "PA_6", diff --git a/features/cellular/framework/targets/QUECTEL/BG96/mbed_lib.json b/features/cellular/framework/targets/QUECTEL/BG96/mbed_lib.json index 00b85f3de82..d72b2fba46e 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/mbed_lib.json +++ b/features/cellular/framework/targets/QUECTEL/BG96/mbed_lib.json @@ -37,13 +37,5 @@ "help": "Provide as default CellularDevice [true/false]", "value": false } - }, - "target_overrides": { - "MTB_STM_L475": { - "tx": "SERIAL_TX", - "rx": "SERIAL_RX", - "pwr": "PE_15", - "rst": "PE_9" - } } } diff --git a/features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32F4/TARGET_OLIMEX_STM32E407_F407ZG/stm32f4_eth_conf.c b/features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32F4/TARGET_OLIMEX_STM32E407_F407ZG/stm32f4_eth_conf.c deleted file mode 100644 index a11be4a4f72..00000000000 --- a/features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32F4/TARGET_OLIMEX_STM32E407_F407ZG/stm32f4_eth_conf.c +++ /dev/null @@ -1,60 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2017 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "stm32f4xx_hal.h" - -void _eth_config_mac(ETH_HandleTypeDef *heth) -{ - ETH_MACInitTypeDef macconf = { - .Watchdog = ETH_WATCHDOG_ENABLE, - .Jabber = ETH_JABBER_ENABLE, - .InterFrameGap = ETH_INTERFRAMEGAP_96BIT, - .CarrierSense = ETH_CARRIERSENCE_ENABLE, - .ReceiveOwn = ETH_RECEIVEOWN_ENABLE, - .LoopbackMode = ETH_LOOPBACKMODE_DISABLE, - .ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE, - .RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE, - .AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE, - .BackOffLimit = ETH_BACKOFFLIMIT_10, - .DeferralCheck = ETH_DEFFERRALCHECK_DISABLE, - .ReceiveAll = ETH_RECEIVEAll_DISABLE, - .SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE, - .PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL, - .BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE, - .DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL, - .PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE, - .MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_NONE, // Disable multicast filter - .UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT, - .HashTableHigh = 0x0U, - .HashTableLow = 0x0U, - .PauseTime = 0x0U, - .ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE, - .PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4, - .UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE, - .ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE, - .TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE, - .VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT, - .VLANTagIdentifier = 0x0U, - }; - - if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) { - macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; - } else { - macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; - } - - (void) HAL_ETH_ConfigMAC(heth, &macconf); -} diff --git a/features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32F4/TARGET_OLIMEX_STM32E407_F407ZG/stm32f4_eth_init.c b/features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32F4/TARGET_OLIMEX_STM32E407_F407ZG/stm32f4_eth_init.c deleted file mode 100644 index fba4a5bbfe8..00000000000 --- a/features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32F4/TARGET_OLIMEX_STM32E407_F407ZG/stm32f4_eth_init.c +++ /dev/null @@ -1,114 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT - -#include "stm32f4xx_hal.h" - -/** - * Override HAL Eth Init function - */ -void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) -{ - GPIO_InitTypeDef GPIO_InitStructure; - if (heth->Instance == ETH) { - - /* Enable GPIOs clocks */ - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOG_CLK_ENABLE(); - - /** ETH GPIO Configuration - RMII_REF_CLK ----------------------> PA1 - RMII_MDIO -------------------------> PA2 - RMII_MDC --------------------------> PC1 - RMII_MII_CRS_DV -------------------> PA7 - RMII_MII_RXD0 ---------------------> PC4 - RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> none - RMII_MII_TX_EN --------------------> PG11 - RMII_MII_TXD0 ---------------------> PG13 - RMII_MII_TXD1 ---------------------> PG14 - */ - /* Configure PA1, PA2 and PA7 */ - GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; - GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; - GPIO_InitStructure.Pull = GPIO_NOPULL; - GPIO_InitStructure.Alternate = GPIO_AF11_ETH; - GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7; - HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); - - /* Configure PC1, PC4 and PC5 */ - GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; - HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); - - /* Configure PG2, PG11 and PG13 */ - GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14; - HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); - - /* Enable the Ethernet global Interrupt */ - HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); - HAL_NVIC_EnableIRQ(ETH_IRQn); - - /* Enable ETHERNET clock */ - __HAL_RCC_ETH_CLK_ENABLE(); - } -} - -/** - * Override HAL Eth DeInit function - */ -void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) -{ - if (heth->Instance == ETH) { - /* Peripheral clock disable */ - __HAL_RCC_ETH_CLK_DISABLE(); - - /** ETH GPIO Configuration - RMII_REF_CLK ----------------------> PA1 - RMII_MDIO -------------------------> PA2 - RMII_MDC --------------------------> PC1 - RMII_MII_CRS_DV -------------------> PA7 - RMII_MII_RXD0 ---------------------> PC4 - RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> none - RMII_MII_TX_EN --------------------> PG11 - RMII_MII_TXD0 ---------------------> PG13 - RMII_MII_TXD1 ---------------------> PG14 - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14); - - /* Disable the Ethernet global Interrupt */ - NVIC_DisableIRQ(ETH_IRQn); - } -} - -#endif /* USE_USER_DEFINED_HAL_ETH_MSPINIT */ diff --git a/features/storage/TESTS/blockdevice/heap_block_device/main.cpp b/features/storage/TESTS/blockdevice/heap_block_device/main.cpp index 6567e4dcd1c..1e5ea878ec1 100644 --- a/features/storage/TESTS/blockdevice/heap_block_device/main.cpp +++ b/features/storage/TESTS/blockdevice/heap_block_device/main.cpp @@ -23,11 +23,6 @@ using namespace utest::v1; -// TODO HACK, replace with available ram/heap property -#if defined(TARGET_MTB_MTS_XDOT) -#error [NOT_SUPPORTED] Insufficient heap for heap block device tests -#else - #define TEST_BLOCK_SIZE 128 #define TEST_BLOCK_DEVICE_SIZE 32*TEST_BLOCK_SIZE #define TEST_BLOCK_COUNT 10 @@ -186,5 +181,3 @@ int main() { return !Harness::run(specification); } - -#endif // defined(TARGET_MTB_MTS_XDOT) diff --git a/features/storage/TESTS/blockdevice/mbr_block_device/main.cpp b/features/storage/TESTS/blockdevice/mbr_block_device/main.cpp index 5569f73a2f3..e050decf5e8 100644 --- a/features/storage/TESTS/blockdevice/mbr_block_device/main.cpp +++ b/features/storage/TESTS/blockdevice/mbr_block_device/main.cpp @@ -24,11 +24,6 @@ using namespace utest::v1; -// TODO HACK, replace with available ram/heap property -#if defined(TARGET_MTB_MTS_XDOT) -#error [NOT_SUPPORTED] Insufficient heap for heap block device tests -#else - #define BLOCK_COUNT 16 #define BLOCK_SIZE 512 @@ -250,5 +245,3 @@ int main() { return !Harness::run(specification); } - -#endif // defined(TARGET_MTB_MTS_XDOT) diff --git a/features/storage/TESTS/blockdevice/util_block_device/main.cpp b/features/storage/TESTS/blockdevice/util_block_device/main.cpp index ddc6e989b5d..bc2794c5612 100644 --- a/features/storage/TESTS/blockdevice/util_block_device/main.cpp +++ b/features/storage/TESTS/blockdevice/util_block_device/main.cpp @@ -26,11 +26,6 @@ using namespace utest::v1; -// TODO HACK, replace with available ram/heap property -#if defined(TARGET_MTB_MTS_XDOT) -#error [NOT_SUPPORTED] Insufficient heap for heap block device tests -#else - #define BLOCK_COUNT 16 #define BLOCK_SIZE 512 @@ -308,5 +303,3 @@ int main() { return !Harness::run(specification); } - -#endif // defined(TARGET_MTB_MTS_XDOT) diff --git a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralNames.h b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralNames.h deleted file mode 100644 index 3cbb1530a94..00000000000 --- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralNames.h +++ /dev/null @@ -1,86 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)UART0_BASE, - UART_1 = (int)UART1_BASE, - UART_2 = (int)UART2_BASE -} UARTName; -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_0 - -typedef enum { - I2C_0 = (int)I2C0_BASE, - I2C_1 = (int)I2C1_BASE, -} I2CName; - -#define TPM_SHIFT 8 -typedef enum { - PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 - PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 - PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 - PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 - PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 - PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 - PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 - PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 - PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 - PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 -} PWMName; - -typedef enum { - ADC0_SE4b = 4, - ADC0_SE5b = 5, - ADC0_SE6b = 6, - ADC0_SE7b = 7, - ADC0_SE8 = 8, - ADC0_SE9 = 9, - ADC0_SE12 = 12, - ADC0_SE13 = 13, - ADC0_SE14 = 14, - ADC0_SE15 = 15, - ADC1_SE4b = 16, - ADC1_SE5b = 17, - ADC1_SE6b = 18, - ADC1_SE7b = 19, -} ADCName; - -typedef enum { - DAC_0 = 0 -} DACName; - -typedef enum { - SPI_0 = (int)SPI0_BASE, - SPI_1 = (int)SPI0_BASE, - SPI_2 = (int)SPI0_BASE, - SPI_3 = (int)SPI0_BASE, - SPI_4 = (int)SPI0_BASE, -} SPIName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralPins.c b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralPins.c deleted file mode 100644 index 90a5b1eadb9..00000000000 --- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralPins.c +++ /dev/null @@ -1,137 +0,0 @@ - -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {PTC2, ADC0_SE4b, 0}, - {PTD1, ADC0_SE5b, 0}, - {PTD5, ADC0_SE6b, 0}, - {PTD6, ADC0_SE7b, 0}, - {PTB0, ADC0_SE8, 0}, - {PTB1, ADC0_SE9, 0}, - {PTB2, ADC0_SE12, 0}, - {PTB3, ADC0_SE13, 0}, - {PTC0, ADC0_SE14, 0}, - {PTC1, ADC0_SE15, 0}, - {PTC8, ADC1_SE4b, 0}, - {PTC9, ADC1_SE5b, 0}, - {PTC10,ADC1_SE6b, 0}, - {PTC11,ADC1_SE7b, 0}, - {NC, NC, 0} -}; - -/************DAC***************/ -const PinMap PinMap_DAC[] = { - {DAC0_OUT, DAC_0, 0}, - {NC , NC , 0} -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {PTB1, I2C_0, 2}, - {PTB3, I2C_0, 2}, - {PTE0, I2C_1, 2}, - {PTC11, I2C_1, 2}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PTB0, I2C_0, 2}, - {PTB2, I2C_0, 2}, - {PTE1, I2C_1, 2}, - {PTC10, I2C_1, 2}, - {NC , NC, 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {PTB17, UART_0, 3}, - {PTC4 , UART_1, 3}, - {PTD3 , UART_2, 3}, - {PTD7 , UART_0, 3}, - {PTE0 , UART_1, 3}, - {NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PTB16, UART_0, 3}, - {PTC3 , UART_1, 3}, - {PTD2 , UART_2, 3}, - {PTD6 , UART_0, 3}, - {PTE1 , UART_1, 3}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { // SCK - {PTC5, SPI_0, 2}, - {PTD1, SPI_0, 2}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { // DOUT - {PTD2, SPI_0, 2}, - {PTC6, SPI_0, 2}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { // DIN - {PTD3, SPI_0, 2}, - {PTC7, SPI_0, 2}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { // CS - {PTD0, SPI_0, 2}, - {PTC4, SPI_0, 2}, - {PTD4, SPI_0, 2}, - {PTC3, SPI_0, 2}, - {PTC2, SPI_0, 2}, - {PTD5, SPI_0, 2}, - {PTD6, SPI_0, 2}, - {PTC1, SPI_0, 2}, - {PTC0, SPI_0, 2} -}; - -/************PWM***************/ -const PinMap PinMap_PWM[] = { - // LEDs - {LED_RED , PWM_3 , 4}, // PTC3, FTM0 CH2 - {LED_GREEN, PWM_5, 4}, // PTD4, FTM0 CH4 - {LED_BLUE , PWM_8 , 3}, // PTA2, FTM0 CH7 - - {PTA0, PWM_6 , 3}, // PTA0, FTM0 CH5 - {PTA1, PWM_7 , 3}, // PTA1, FTM0 CH6 - {PTA3, PWM_1 , 3}, // PTA3, FTM0 CH0 - {PTA4, PWM_2 , 3}, // PTA4, FTM0 CH1 - {PTA5, PWM_3 , 3}, // PTA5, FTM0 CH2 - {PTA12, PWM_9 , 3}, // PTA12, FTM1 CH0 - {PTA13, PWM_10, 3}, // PTA13, FTM1 CH1 - {PTB0, PWM_9 , 3}, // PTB0, FTM1 CH0 - {PTB1, PWM_10, 3}, // PTB1, FTM1 CH1 - {PTC1, PWM_1 , 4}, // PTC1, FTM0 CH0 - {PTC2, PWM_2 , 4}, // PTC2, FTM0 CH1 - {PTC3, PWM_3 , 4}, // PTC3, FTM0 CH2 - {PTD4, PWM_4 , 4}, // PTD4, FTM0 CH3 - {PTD5, PWM_6 , 4}, // PTD5, FTM0 CH6 - {PTD6, PWM_7 , 4}, // PTD6, FTM0 CH6 - {PTD7, PWM_8 , 4}, // PTD7, FTM0 CH7 - - {NC , NC , 0} -}; diff --git a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h deleted file mode 100644 index bdb55e80656..00000000000 --- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h +++ /dev/null @@ -1,310 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -/* PCR - 0x1000 */ -#define PORT_SHIFT 12 - -typedef enum { - PTA0 = 0x0, - PTA1 = 0x4, - PTA2 = 0x8, - PTA3 = 0xc, - PTA4 = 0x10, - PTA5 = 0x14, - PTA6 = 0x18, - PTA7 = 0x1c, - PTA8 = 0x20, - PTA9 = 0x24, - PTA10 = 0x28, - PTA11 = 0x2c, - PTA12 = 0x30, - PTA13 = 0x34, - PTA14 = 0x38, - PTA15 = 0x3c, - PTA16 = 0x40, - PTA17 = 0x44, - PTA18 = 0x48, - PTA19 = 0x4c, - PTA20 = 0x50, - PTA21 = 0x54, - PTA22 = 0x58, - PTA23 = 0x5c, - PTA24 = 0x60, - PTA25 = 0x64, - PTA26 = 0x68, - PTA27 = 0x6c, - PTA28 = 0x70, - PTA29 = 0x74, - PTA30 = 0x78, - PTA31 = 0x7c, - PTB0 = 0x1000, - PTB1 = 0x1004, - PTB2 = 0x1008, - PTB3 = 0x100c, - PTB4 = 0x1010, - PTB5 = 0x1014, - PTB6 = 0x1018, - PTB7 = 0x101c, - PTB8 = 0x1020, - PTB9 = 0x1024, - PTB10 = 0x1028, - PTB11 = 0x102c, - PTB12 = 0x1030, - PTB13 = 0x1034, - PTB14 = 0x1038, - PTB15 = 0x103c, - PTB16 = 0x1040, - PTB17 = 0x1044, - PTB18 = 0x1048, - PTB19 = 0x104c, - PTB20 = 0x1050, - PTB21 = 0x1054, - PTB22 = 0x1058, - PTB23 = 0x105c, - PTB24 = 0x1060, - PTB25 = 0x1064, - PTB26 = 0x1068, - PTB27 = 0x106c, - PTB28 = 0x1070, - PTB29 = 0x1074, - PTB30 = 0x1078, - PTB31 = 0x107c, - PTC0 = 0x2000, - PTC1 = 0x2004, - PTC2 = 0x2008, - PTC3 = 0x200c, - PTC4 = 0x2010, - PTC5 = 0x2014, - PTC6 = 0x2018, - PTC7 = 0x201c, - PTC8 = 0x2020, - PTC9 = 0x2024, - PTC10 = 0x2028, - PTC11 = 0x202c, - PTC12 = 0x2030, - PTC13 = 0x2034, - PTC14 = 0x2038, - PTC15 = 0x203c, - PTC16 = 0x2040, - PTC17 = 0x2044, - PTC18 = 0x2048, - PTC19 = 0x204c, - PTC20 = 0x2050, - PTC21 = 0x2054, - PTC22 = 0x2058, - PTC23 = 0x205c, - PTC24 = 0x2060, - PTC25 = 0x2064, - PTC26 = 0x2068, - PTC27 = 0x206c, - PTC28 = 0x2070, - PTC29 = 0x2074, - PTC30 = 0x2078, - PTC31 = 0x207c, - PTD0 = 0x3000, - PTD1 = 0x3004, - PTD2 = 0x3008, - PTD3 = 0x300c, - PTD4 = 0x3010, - PTD5 = 0x3014, - PTD6 = 0x3018, - PTD7 = 0x301c, - PTD8 = 0x3020, - PTD9 = 0x3024, - PTD10 = 0x3028, - PTD11 = 0x302c, - PTD12 = 0x3030, - PTD13 = 0x3034, - PTD14 = 0x3038, - PTD15 = 0x303c, - PTD16 = 0x3040, - PTD17 = 0x3044, - PTD18 = 0x3048, - PTD19 = 0x304c, - PTD20 = 0x3050, - PTD21 = 0x3054, - PTD22 = 0x3058, - PTD23 = 0x305c, - PTD24 = 0x3060, - PTD25 = 0x3064, - PTD26 = 0x3068, - PTD27 = 0x306c, - PTD28 = 0x3070, - PTD29 = 0x3074, - PTD30 = 0x3078, - PTD31 = 0x307c, - PTE0 = 0x4000, - PTE1 = 0x4004, - PTE2 = 0x4008, - PTE3 = 0x400c, - PTE4 = 0x4010, - PTE5 = 0x4014, - PTE6 = 0x4018, - PTE7 = 0x401c, - PTE8 = 0x4020, - PTE9 = 0x4024, - PTE10 = 0x4028, - PTE11 = 0x402c, - PTE12 = 0x4030, - PTE13 = 0x4034, - PTE14 = 0x4038, - PTE15 = 0x403c, - PTE16 = 0x4040, - PTE17 = 0x4044, - PTE18 = 0x4048, - PTE19 = 0x404c, - PTE20 = 0x4050, - PTE21 = 0x4054, - PTE22 = 0x4058, - PTE23 = 0x405c, - PTE24 = 0x4060, - PTE25 = 0x4064, - PTE26 = 0x4068, - PTE27 = 0x406c, - PTE28 = 0x4070, - PTE29 = 0x4074, - PTE30 = 0x4078, - PTE31 = 0x407c, - - LED_RED = PTC5, // set these to the only led on board - LED_GREEN = PTC5, // - LED_BLUE = PTC5, // - - // mbed original LED naming - LED1 = LED_RED, - LED2 = LED_GREEN, - LED3 = LED_BLUE, - LED4 = LED_BLUE, - - // USB Pins - USBTX = PTB17, - USBRX = PTB16, - - // DAC Pins - DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ - - // Teensy3.1 Headers - D0 = PTB16, - D1 = PTB17, - D2 = PTD0, - D3 = PTA12, - D4 = PTA13, - D5 = PTD7, - D6 = PTD4, - D7 = PTD2, - D8 = PTD3, - D9 = PTC3, - D10 = PTC4, - D11 = PTC6, - D12 = PTC7, - D13 = PTC5, - D14 = PTD1, - D15 = PTC0, - D16 = PTB0, - D17 = PTB1, - D18 = PTB3, - D19 = PTB2, - D20 = PTD5, - D21 = PTD6, - D22 = PTC1, - D23 = PTC2, - D24 = PTA5, - D25 = PTB19, - D26 = PTE1, - D27 = PTC9, - D28 = PTC8, - D29 = PTC10, - D30 = PTC11, - D31 = PTE0, - D32 = PTB18, - D33 = PTA4, - - A0 = PTD1, - A1 = PTC0, - A2 = PTB0, - A3 = PTB1, - A4 = PTB3, - A5 = PTB2, - A6 = PTD5, - A7 = PTD6, - A8 = PTC1, - A9 = PTC2, - A15 = PTE1, - A16 = PTC9, - A17 = PTC8, - A18 = PTC10, - A19 = PTC11, - A20 = PTE0, - - I2C_SCL = PTB2, - I2C_SDA = PTB3, - - SPI_SCK = PTC5, // sclk - SPI_DOUT = PTC6, // mosi - SPI_DIN = PTC7, // miso - SPI_CS = PTC4, // ssel - - SERIAL_TX = PTB17, - SERIAL_RX = PTB16, - - PWM = PTA12, - PWM1 = PTA13, - PWM2 = PTD7, - PWM3 = PTD4, - PWM4 = PTC3, - PWM5 = PTC4, - PWM6 = PTD5, - PWM7 = PTD6, - PWM8 = PTC1, - PWM9 = PTC2, - PWM10 = PTB19, - PWM11 = PTB18, - - DAC = DAC0_OUT, - - TSI_ELEC0 = PTC1, - TSI_ELEC1 = PTC2, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - - -typedef enum { - PullNone = 0, - PullDown = 2, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device.h b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device.h deleted file mode 100644 index 939393fe9b8..00000000000 --- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device.h +++ /dev/null @@ -1,39 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 24 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/MK20DX256.h b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/MK20DX256.h deleted file mode 100644 index 82bb6fd929f..00000000000 --- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/MK20DX256.h +++ /dev/null @@ -1,6034 +0,0 @@ -/* -** ################################################################### -** Processors: MK20DX64VLH7 -** MK20DX128VLH7 -** MK20DX256VLH7 -** MK20DX64VLK7 -** MK20DX128VLK7 -** MK20DX256VLK7 -** MK20DX128VLL7 -** MK20DX256VLL7 -** MK20DX64VMB7 -** MK20DX128VMB7 -** MK20DX256VMB7 -** MK20DX128VML7 -** MK20DX256VML7 -** -** Compilers: ARM Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: Kxx (P1 silicon) Sub-Family Reference Manual Rev. 0, draft A Oct 2011 -** Version: rev. 1.0, 2012-01-15 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2012-01-15) -** Initial public version. -** -** ################################################################### -*/ - -/** - * @file MK20DX256.h - * @version 2.0 - * @date 2012-03-19 - * @brief CMSIS Peripheral Access Layer for MK20DX256 - * - * CMSIS Peripheral Access Layer for MK20DX256 - */ - -#if !defined(MK20DX256_H_) -#define MK20DX256_H_ /**< Symbol preventing repeated inclusion */ -#define MCU_MK20DX256 -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0200u -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0000u - -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -typedef enum IRQn { - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ - - /* Device specific interrupts */ - - DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */ - DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */ - DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */ - DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */ - DMA4_IRQn = 4, - DMA5_IRQn = 5, - DMA6_IRQn = 6, - DMA7_IRQn = 7, - DMA8_IRQn = 8, - DMA9_IRQn = 9, - DMA10_IRQn = 10, - DMA11_IRQn = 11, - DMA12_IRQn = 12, - DMA13_IRQn = 13, - DMA14_IRQn = 14, - DMA15_IRQn = 15, - DMA_Error_IRQn = 16, /**< DMA error interrupt */ - Reserved33_IRQn = 17, - FTFL_IRQn = 18, /**< FTFL interrupt */ - Read_Collision_IRQn = 19, /**< Read collision interrupt */ - LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ - LLW_IRQn = 21, /**< Low Leakage Wakeup */ - Watchdog_IRQn = 22, /**< WDOG interrupt */ - Reserved39_IRQn = 23, - I2C0_IRQn = 24, /**< I2C0 interrupt */ - I2C1_IRQn = 25, - SPI0_IRQn = 26, /**< SPI0 interrupt */ - SPI1_IRQn = 27, - Reserved44_IRQn = 28, - CAN0_ORed_Message_buffer_IRQn = 29, /**< CAN0 OR'd message buffers interrupt */ - CAN0_Bus_Off_IRQn = 30, /**< CAN0 bus off interrupt */ - CAN0_Error_IRQn = 31, /**< CAN0 error interrupt */ - CAN0_Tx_Warning_IRQn = 32, /**< CAN0 Tx warning interrupt */ - CAN0_Rx_Warning_IRQn = 33, /**< CAN0 Rx warning interrupt */ - CAN0_Wake_Up_IRQn = 34, /**< CAN0 wake up interrupt */ - I2S0_Tx_IRQn = 35, /**< I2S0 transmit interrupt */ - I2S0_Rx_IRQn = 36, /**< I2S0 receive interrupt */ - Reserved53_IRQn = 37, - Reserved54_IRQn = 38, - Reserved55_IRQn = 39, - Reserved56_IRQn = 40, - Reserved57_IRQn = 41, - Reserved58_IRQn = 42, - Reserved59_IRQn = 43, - UART0_LON_IRQn = 44, /**< UART0 LON interrupt */ - UART0_RX_TX_IRQn = 45, /**< UART0 receive/transmit interrupt */ - UART0_ERR_IRQn = 46, /**< UART0 error interrupt */ - UART1_RX_TX_IRQn = 47, /**< UART1 receive/transmit interrupt */ - UART1_ERR_IRQn = 48, /**< UART1 error interrupt */ - UART2_RX_TX_IRQn = 49, /**< UART2 receive/transmit interrupt */ - UART2_ERR_IRQn = 50, /**< UART2 error interrupt */ - Reserved67_IRQn = 51, - Reserved68_IRQn = 52, - Reserved69_IRQn = 53, - Reserved70_IRQn = 54, - Reserved71_IRQn = 55, - Reserved72_IRQn = 56, - ADC0_IRQn = 57, /**< ADC0 interrupt */ - ADC1_IRQn = 58, - CMP0_IRQn = 59, /**< CMP0 interrupt */ - CMP1_IRQn = 60, /**< CMP1 interrupt */ - CMP2_IRQn = 61, - FTM0_IRQn = 62, /**< FTM0 fault, overflow and channels interrupt */ - FTM1_IRQn = 63, /**< FTM1 fault, overflow and channels interrupt */ - FTM2_IRQn = 64, - CMT_IRQn = 65, /**< CMT interrupt */ - RTC_IRQn = 66, /**< RTC interrupt */ - RTC_Seconds_IRQn = 67, /**< RTC seconds interrupt */ - PIT0_IRQn = 68, /**< PIT timer channel 0 interrupt */ - PIT1_IRQn = 69, /**< PIT timer channel 1 interrupt */ - PIT2_IRQn = 70, /**< PIT timer channel 2 interrupt */ - PIT3_IRQn = 71, /**< PIT timer channel 3 interrupt */ - PDB0_IRQn = 72, /**< PDB0 interrupt */ - USB0_IRQn = 73, /**< USB0 interrupt */ - USBDCD_IRQn = 74, /**< USBDCD interrupt */ - Reserved91_IRQn = 75, - Reserved92_IRQn = 76, - Reserved93_IRQn = 77, - Reserved94_IRQn = 78, - Reserved95_IRQn = 79, - Reserved96_IRQn = 80, - DAC0_IRQn = 81, - Reserved98_IRQn = 82, - TSI0_IRQn = 83, /**< TSI0 interrupt */ - MCG_IRQn = 84, /**< MCG interrupt */ - LPTimer_IRQn = 85, /**< LPTimer interrupt */ - Reserved102_IRQn = 86, - PORTA_IRQn = 87, /**< Port A interrupt */ - PORTB_IRQn = 88, /**< Port B interrupt */ - PORTC_IRQn = 89, /**< Port C interrupt */ - PORTD_IRQn = 90, /**< Port D interrupt */ - PORTE_IRQn = 91, /**< Port E interrupt */ - Reserved108_IRQn = 92, - Reserved109_IRQn = 93, - SWI_IRQn = 94 /**< Software interrupt */ - -} IRQn_Type; - -/** - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M4 Core Configuration - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ - -#include "core_cm4.h" /* Core Peripheral Access Layer */ -#include "system_MK20DX256.h" /* Device specific configuration file */ - -/** - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */ - __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */ - __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */ - __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */ - __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */ - __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */ - __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */ - __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */ - __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */ - __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */ - __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */ - __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */ - __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */ - __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */ - __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */ - __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */ - __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */ - __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */ - __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */ - __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */ - __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */ - __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */ - __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */ - __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/* SC1 Bit Fields */ -#define ADC_SC1_ADCH_MASK 0x1Fu -#define ADC_SC1_ADCH_SHIFT 0 -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<>> ------------------ -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt - DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt - DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt - DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt - DCD DMA4_IRQHandler ; DMA channel 4 transfer complete interrupt - DCD DMA5_IRQHandler ; DMA channel 5 transfer complete interrupt - DCD DMA6_IRQHandler ; DMA channel 6 transfer complete interrupt - DCD DMA7_IRQHandler ; DMA channel 7 transfer complete interrupt - DCD DMA8_IRQHandler ; DMA channel 8 transfer complete interrupt - DCD DMA9_IRQHandler ; DMA channel 9 transfer complete interrupt - DCD DMA10_IRQHandler ; DMA channel 10 transfer complete interrupt - DCD DMA11_IRQHandler ; DMA channel 11 transfer complete interrupt - DCD DMA12_IRQHandler ; DMA channel 12 transfer complete interrupt - DCD DMA13_IRQHandler ; DMA channel 13 transfer complete interrupt - DCD DMA14_IRQHandler ; DMA channel 14 transfer complete interrupt - DCD DMA15_IRQHandler ; DMA channel 15 transfer complete interrupt - DCD DMA_Error_IRQHandler ; DMA error interrupt - DCD Reserved33_IRQHandler ; Reserved interrupt 33 - DCD FTFL_IRQHandler ; FTFL interrupt - DCD Read_Collision_IRQHandler ; Read collision interrupt - DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning - DCD LLW_IRQHandler ; Low Leakage Wakeup - DCD Watchdog_IRQHandler ; WDOG interrupt - DCD Reserved39_IRQHandler ; Reserved interrupt 39 - DCD I2C0_IRQHandler ; I2C0 interrupt - DCD I2C1_IRQHandler ; I2C1 interrupt - DCD SPI0_IRQHandler ; SPI0 interrupt - DCD SPI1_IRQHandler ; SPI1 interrupt - DCD Reserved44_IRQHandler ; Reserved interrupt 44 - DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt - DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt - DCD CAN0_Error_IRQHandler ; CAN0 error interrupt - DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt - DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt - DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt - DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt - DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt - DCD Reserved53_IRQHandler ; Reserved interrupt 53 - DCD Reserved54_IRQHandler ; Reserved interrupt 54 - DCD Reserved55_IRQHandler ; Reserved interrupt 55 - DCD Reserved56_IRQHandler ; Reserved interrupt 56 - DCD Reserved57_IRQHandler ; Reserved interrupt 57 - DCD Reserved58_IRQHandler ; Reserved interrupt 58 - DCD Reserved59_IRQHandler ; Reserved interrupt 59 - DCD UART0_LON_IRQHandler ; UART0 LON interrupt - DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt - DCD UART0_ERR_IRQHandler ; UART0 error interrupt - DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt - DCD UART1_ERR_IRQHandler ; UART1 error interrupt - DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt - DCD UART2_ERR_IRQHandler ; UART2 error interrupt - DCD Reserved67_IRQHandler ; Reserved interrupt 67 - DCD Reserved68_IRQHandler ; Reserved interrupt 68 - DCD Reserved69_IRQHandler ; Reserved interrupt 69 - DCD Reserved70_IRQHandler ; Reserved interrupt 70 - DCD Reserved71_IRQHandler ; Reserved interrupt 71 - DCD Reserved72_IRQHandler ; Reserved interrupt 72 - DCD ADC0_IRQHandler ; ADC0 interrupt - DCD ADC1_IRQHandler ; ADC1 interrupt - DCD CMP0_IRQHandler ; CMP0 interrupt - DCD CMP1_IRQHandler ; CMP1 interrupt - DCD CMP2_IRQHandler ; CMP2 interrupt - DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt - DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt - DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt - DCD CMT_IRQHandler ; CMT interrupt - DCD RTC_IRQHandler ; RTC interrupt - DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt - DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt - DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt - DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt - DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt - DCD PDB0_IRQHandler ; PDB0 interrupt - DCD USB0_IRQHandler ; USB0 interrupt - DCD USBDCD_IRQHandler ; USBDCD interrupt - DCD Reserved91_IRQHandler ; Reserved interrupt 91 - DCD Reserved92_IRQHandler ; Reserved interrupt 92 - DCD Reserved93_IRQHandler ; Reserved interrupt 93 - DCD Reserved94_IRQHandler ; Reserved interrupt 94 - DCD Reserved95_IRQHandler ; Reserved interrupt 95 - DCD Reserved96_IRQHandler ; Reserved interrupt 96 - DCD DAC0_IRQHandler ; DAC0 interrupt - DCD Reserved98_IRQHandler ; Reserved interrupt 98 - DCD TSI0_IRQHandler ; TSI0 interrupt - DCD MCG_IRQHandler ; MCG interrupt - DCD LPTimer_IRQHandler ; LPTimer interrupt - DCD Reserved102_IRQHandler ; Reserved interrupt 102 - DCD PORTA_IRQHandler ; Port A interrupt - DCD PORTB_IRQHandler ; Port B interrupt - DCD PORTC_IRQHandler ; Port C interrupt - DCD PORTD_IRQHandler ; Port D interrupt - DCD PORTE_IRQHandler ; Port E interrupt - DCD Reserved108_IRQHandler ; Reserved interrupt 108 - DCD Reserved109_IRQHandler ; Reserved interrupt 109 - DCD SWI_IRQHandler ; Software interrupt -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -; Flash Configuration -; 16-byte flash configuration field that stores default protection settings (loaded on reset) -; and security information that allows the MCU to restrict acces to the FTFL module. -; Backdoor Comparison Key -; Backdoor Key 0 <0x0-0xFF:2> -; Backdoor Key 1 <0x0-0xFF:2> -; Backdoor Key 2 <0x0-0xFF:2> -; Backdoor Key 3 <0x0-0xFF:2> -; Backdoor Key 4 <0x0-0xFF:2> -; Backdoor Key 5 <0x0-0xFF:2> -; Backdoor Key 6 <0x0-0xFF:2> -; Backdoor Key 7 <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF -; -; Program flash protection bytes (FPROT) -; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. -; Each bit protects a 1/32 region of the program flash memory. -; FPROT0 -; Program flash protection bytes -; 1/32 - 8/32 region -; FPROT0.0 -; FPROT0.1 -; FPROT0.2 -; FPROT0.3 -; FPROT0.4 -; FPROT0.5 -; FPROT0.6 -; FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; -; FPROT1 -; Program Flash Region Protect Register 1 -; 9/32 - 16/32 region -; FPROT1.0 -; FPROT1.1 -; FPROT1.2 -; FPROT1.3 -; FPROT1.4 -; FPROT1.5 -; FPROT1.6 -; FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF -; -; FPROT2 -; Program Flash Region Protect Register 2 -; 17/32 - 24/32 region -; FPROT2.0 -; FPROT2.1 -; FPROT2.2 -; FPROT2.3 -; FPROT2.4 -; FPROT2.5 -; FPROT2.6 -; FPROT2.7 -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2:EOR:0xFF -; -; FPROT3 -; Program Flash Region Protect Register 3 -; 25/32 - 32/32 region -; FPROT3.0 -; FPROT3.1 -; FPROT3.2 -; FPROT3.3 -; FPROT3.4 -; FPROT3.5 -; FPROT3.6 -; FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF -; -; -; Data flash protection byte (FDPROT) -; Each bit protects a 1/8 region of the data flash memory. -; (Program flash only devices: Reserved) -; FDPROT.0 -; FDPROT.1 -; FDPROT.2 -; FDPROT.3 -; FDPROT.4 -; FDPROT.5 -; FDPROT.6 -; FDPROT.7 -nFDPROT EQU 0x00 -FDPROT EQU nFDPROT:EOR:0xFF -; -; EEPROM protection byte (FEPROT) -; FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. -; (Program flash only devices: Reserved) -; FEPROT.0 -; FEPROT.1 -; FEPROT.2 -; FEPROT.3 -; FEPROT.4 -; FEPROT.5 -; FEPROT.6 -; FEPROT.7 -nFEPROT EQU 0x00 -FEPROT EQU nFEPROT:EOR:0xFF -; -; Flash nonvolatile option byte (FOPT) -; Allows the user to customize the operation of the MCU at boot time. -; LPBOOT -; <0=> Low-power boot -; <1=> normal boot -; EZPORT_DIS -; <0=> EzPort operation is enabled -; <1=> EzPort operation is disabled -FOPT EQU 0xFF -; -; Flash security byte (FSEC) -; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", -; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! -; SEC -; <2=> MCU security status is unsecure -; <3=> MCU security status is secure -; Flash Security -; This bits define the security state of the MCU. -; FSLACC -; <2=> Freescale factory access denied -; <3=> Freescale factory access granted -; Freescale Failure Analysis Access Code -; This bits define the security state of the MCU. -; MEEN -; <2=> Mass erase is disabled -; <3=> Mass erase is enabled -; Mass Erase Enable Bits -; Enables and disables mass erase capability of the FTFL module -; KEYEN -; <2=> Backdoor key access enabled -; <3=> Backdoor key access disabled -; Backdoor key Security Enable -; These bits enable and disable backdoor key access to the FTFL module. -FSEC EQU 0xFE -; -; - IF :LNOT::DEF:RAM_TARGET - AREA |.ARM.__at_0x400|, CODE, READONLY - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0, FPROT1, FPROT2, FPROT3 - DCB FSEC, FOPT, FEPROT, FDPROT - ENDIF - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT DMA0_IRQHandler [WEAK] - EXPORT DMA1_IRQHandler [WEAK] - EXPORT DMA2_IRQHandler [WEAK] - EXPORT DMA3_IRQHandler [WEAK] - EXPORT DMA4_IRQHandler [WEAK] - EXPORT DMA5_IRQHandler [WEAK] - EXPORT DMA6_IRQHandler [WEAK] - EXPORT DMA7_IRQHandler [WEAK] - EXPORT DMA8_IRQHandler [WEAK] - EXPORT DMA9_IRQHandler [WEAK] - EXPORT DMA10_IRQHandler [WEAK] - EXPORT DMA11_IRQHandler [WEAK] - EXPORT DMA12_IRQHandler [WEAK] - EXPORT DMA13_IRQHandler [WEAK] - EXPORT DMA14_IRQHandler [WEAK] - EXPORT DMA15_IRQHandler [WEAK] - EXPORT DMA_Error_IRQHandler [WEAK] - EXPORT Reserved33_IRQHandler [WEAK] - EXPORT FTFL_IRQHandler [WEAK] - EXPORT Read_Collision_IRQHandler [WEAK] - EXPORT LVD_LVW_IRQHandler [WEAK] - EXPORT LLW_IRQHandler [WEAK] - EXPORT Watchdog_IRQHandler [WEAK] - EXPORT Reserved39_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT Reserved44_IRQHandler [WEAK] - EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK] - EXPORT CAN0_Bus_Off_IRQHandler [WEAK] - EXPORT CAN0_Error_IRQHandler [WEAK] - EXPORT CAN0_Tx_Warning_IRQHandler [WEAK] - EXPORT CAN0_Rx_Warning_IRQHandler [WEAK] - EXPORT CAN0_Wake_Up_IRQHandler [WEAK] - EXPORT I2S0_Tx_IRQHandler [WEAK] - EXPORT I2S0_Rx_IRQHandler [WEAK] - EXPORT Reserved53_IRQHandler [WEAK] - EXPORT Reserved54_IRQHandler [WEAK] - EXPORT Reserved55_IRQHandler [WEAK] - EXPORT Reserved56_IRQHandler [WEAK] - EXPORT Reserved57_IRQHandler [WEAK] - EXPORT Reserved58_IRQHandler [WEAK] - EXPORT Reserved59_IRQHandler [WEAK] - EXPORT UART0_LON_IRQHandler [WEAK] - EXPORT UART0_RX_TX_IRQHandler [WEAK] - EXPORT UART0_ERR_IRQHandler [WEAK] - EXPORT UART1_RX_TX_IRQHandler [WEAK] - EXPORT UART1_ERR_IRQHandler [WEAK] - EXPORT UART2_RX_TX_IRQHandler [WEAK] - EXPORT UART2_ERR_IRQHandler [WEAK] - EXPORT Reserved67_IRQHandler [WEAK] - EXPORT Reserved68_IRQHandler [WEAK] - EXPORT Reserved69_IRQHandler [WEAK] - EXPORT Reserved70_IRQHandler [WEAK] - EXPORT Reserved71_IRQHandler [WEAK] - EXPORT Reserved72_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT CMP0_IRQHandler [WEAK] - EXPORT CMP1_IRQHandler [WEAK] - EXPORT CMP2_IRQHandler [WEAK] - EXPORT FTM0_IRQHandler [WEAK] - EXPORT FTM1_IRQHandler [WEAK] - EXPORT FTM2_IRQHandler [WEAK] - EXPORT CMT_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT RTC_Seconds_IRQHandler [WEAK] - EXPORT PIT0_IRQHandler [WEAK] - EXPORT PIT1_IRQHandler [WEAK] - EXPORT PIT2_IRQHandler [WEAK] - EXPORT PIT3_IRQHandler [WEAK] - EXPORT PDB0_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT USBDCD_IRQHandler [WEAK] - EXPORT Reserved91_IRQHandler [WEAK] - EXPORT Reserved92_IRQHandler [WEAK] - EXPORT Reserved93_IRQHandler [WEAK] - EXPORT Reserved94_IRQHandler [WEAK] - EXPORT Reserved95_IRQHandler [WEAK] - EXPORT Reserved96_IRQHandler [WEAK] - EXPORT DAC0_IRQHandler [WEAK] - EXPORT Reserved98_IRQHandler [WEAK] - EXPORT TSI0_IRQHandler [WEAK] - EXPORT MCG_IRQHandler [WEAK] - EXPORT LPTimer_IRQHandler [WEAK] - EXPORT Reserved102_IRQHandler [WEAK] - EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTB_IRQHandler [WEAK] - EXPORT PORTC_IRQHandler [WEAK] - EXPORT PORTD_IRQHandler [WEAK] - EXPORT PORTE_IRQHandler [WEAK] - EXPORT Reserved108_IRQHandler [WEAK] - EXPORT Reserved109_IRQHandler [WEAK] - EXPORT SWI_IRQHandler [WEAK] - EXPORT DefaultISR [WEAK] - -DMA0_IRQHandler -DMA1_IRQHandler -DMA2_IRQHandler -DMA3_IRQHandler -DMA4_IRQHandler -DMA5_IRQHandler -DMA6_IRQHandler -DMA7_IRQHandler -DMA8_IRQHandler -DMA9_IRQHandler -DMA10_IRQHandler -DMA11_IRQHandler -DMA12_IRQHandler -DMA13_IRQHandler -DMA14_IRQHandler -DMA15_IRQHandler -DMA_Error_IRQHandler -Reserved33_IRQHandler -FTFL_IRQHandler -Read_Collision_IRQHandler -LVD_LVW_IRQHandler -LLW_IRQHandler -Watchdog_IRQHandler -Reserved39_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -Reserved44_IRQHandler -CAN0_ORed_Message_buffer_IRQHandler -CAN0_Bus_Off_IRQHandler -CAN0_Error_IRQHandler -CAN0_Tx_Warning_IRQHandler -CAN0_Rx_Warning_IRQHandler -CAN0_Wake_Up_IRQHandler -I2S0_Tx_IRQHandler -I2S0_Rx_IRQHandler -Reserved53_IRQHandler -Reserved54_IRQHandler -Reserved55_IRQHandler -Reserved56_IRQHandler -Reserved57_IRQHandler -Reserved58_IRQHandler -Reserved59_IRQHandler -UART0_LON_IRQHandler -UART0_RX_TX_IRQHandler -UART0_ERR_IRQHandler -UART1_RX_TX_IRQHandler -UART1_ERR_IRQHandler -UART2_RX_TX_IRQHandler -UART2_ERR_IRQHandler -Reserved67_IRQHandler -Reserved68_IRQHandler -Reserved69_IRQHandler -Reserved70_IRQHandler -Reserved71_IRQHandler -Reserved72_IRQHandler -ADC0_IRQHandler -ADC1_IRQHandler -CMP0_IRQHandler -CMP1_IRQHandler -CMP2_IRQHandler -FTM0_IRQHandler -FTM1_IRQHandler -FTM2_IRQHandler -CMT_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT0_IRQHandler -PIT1_IRQHandler -PIT2_IRQHandler -PIT3_IRQHandler -PDB0_IRQHandler -USB0_IRQHandler -USBDCD_IRQHandler -Reserved91_IRQHandler -Reserved92_IRQHandler -Reserved93_IRQHandler -Reserved94_IRQHandler -Reserved95_IRQHandler -Reserved96_IRQHandler -DAC0_IRQHandler -Reserved98_IRQHandler -TSI0_IRQHandler -MCG_IRQHandler -LPTimer_IRQHandler -Reserved102_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -Reserved108_IRQHandler -Reserved109_IRQHandler -SWI_IRQHandler -DefaultISR - - B . - - ENDP - - - ALIGN - END diff --git a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/TOOLCHAIN_GCC_ARM/MK20DX256.ld b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/TOOLCHAIN_GCC_ARM/MK20DX256.ld deleted file mode 100644 index 243b82a6efb..00000000000 --- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/TOOLCHAIN_GCC_ARM/MK20DX256.ld +++ /dev/null @@ -1,171 +0,0 @@ -/* - * K20DX256 ARM GCC linker script file - */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 - FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010 - FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x00000410 - RAM (rwx) : ORIGIN = 0x1FFF81C0, LENGTH = 64K - 0x1C0 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * _reset_init : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .isr_vector : - { - . = 0; - __isr_vector = .; - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - *(.text.SystemInit) - . = ALIGN(8); - } > VECTORS - - .flash_protect : - { - KEEP(*(.kinetis_flash_config_field)) - . = ALIGN(8); - } > FLASH_PROTECTION - - .text : - { - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/TOOLCHAIN_GCC_ARM/startup_MK20DX256.S b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/TOOLCHAIN_GCC_ARM/startup_MK20DX256.S deleted file mode 100644 index e54559a4dc5..00000000000 --- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/TOOLCHAIN_GCC_ARM/startup_MK20DX256.S +++ /dev/null @@ -1,366 +0,0 @@ -/* File: startup_MK20DX256.s - * Purpose: startup file for Cortex-M4 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.3 - * Date: 08 Feb 2012 - * - * Copyright (c) 2015, ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the ARM Limited nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - .syntax unified - .arch armv7-m - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x400 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0xC00 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector - .align 2 - .globl __isr_vector - -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts */ - .long DMA0_IRQHandler // DMA channel 0 transfer complete interrupt - .long DMA1_IRQHandler // DMA channel 0 transfer complete interrupt - .long DMA2_IRQHandler // DMA channel 0 transfer complete interrupt - .long DMA3_IRQHandler // DMA channel 0 transfer complete interrupt - .long DMA4_IRQHandler // DMA channel 0 transfer complete interrupt - .long DMA5_IRQHandler // DMA channel 0 transfer complete interrupt - .long DMA6_IRQHandler // DMA channel 0 transfer complete interrupt - .long DMA7_IRQHandler // DMA channel 0 transfer complete interrupt - .long DMA8_IRQHandler // DMA channel 0 transfer complete interrupt - .long DMA9_IRQHandler // DMA channel 0 transfer complete interrupt - .long DMA10_IRQHandler // DMA channel 0 transfer complete interrupt - .long DMA11_IRQHandler // DMA channel 0 transfer complete interrupt - .long DMA12_IRQHandler // DMA channel 0 transfer complete interrupt - .long DMA13_IRQHandler // DMA channel 0 transfer complete interrupt - .long DMA14_IRQHandler // DMA channel 0 transfer complete interrupt - .long DMA15_IRQHandler // DMA channel 0 transfer complete interrupt - .long DMA_Error_IRQHandler // DMA error interrupt - .long Reserved33_IRQHandler // Reserved interrupt 33 - .long FTFL_IRQHandler // FTFL interrupt - .long Read_Collision_IRQHandler // Read collision interrupt - .long LVD_LVW_IRQHandler // Low Voltage Detect, Low Voltage Warning - .long LLW_IRQHandler // Low Leakage Wakeup - .long Watchdog_IRQHandler // WDOG interrupt - .long Reserved39_IRQHandler // Reserved interrupt 39 - .long I2C0_IRQHandler // I2C0 interrupt - .long I2C1_IRQHandler // I2C1 interrupt - .long SPI0_IRQHandler // SPI0 interrupt - .long SPI1_IRQHandler // SPI1 interrupt - .long Reserved44_IRQHandler // Reserved interrupt 44 - .long CAN0_ORed_Message_buffer_IRQHandler // CAN0 OR'd message buffers interrupt - .long CAN0_Bus_Off_IRQHandler // CAN0 bus off interrupt - .long CAN0_Error_IRQHandler // CAN0 error interrupt - .long CAN0_Tx_Warning_IRQHandler // CAN0 Tx warning interrupt - .long CAN0_Rx_Warning_IRQHandler // CAN0 Rx warning interrupt - .long CAN0_Wake_Up_IRQHandler // CAN0 wake up interrupt - .long I2S0_Tx_IRQHandler // I2S0 transmit interrupt - .long I2S0_Rx_IRQHandler // I2S0 receive interrupt - .long Reserved53_IRQHandler // Reserved interrupt 53 - .long Reserved54_IRQHandler // Reserved interrupt 54 - .long Reserved55_IRQHandler // Reserved interrupt 55 - .long Reserved56_IRQHandler // Reserved interrupt 56 - .long Reserved57_IRQHandler // Reserved interrupt 57 - .long Reserved58_IRQHandler // Reserved interrupt 58 - .long Reserved59_IRQHandler // Reserved interrupt 59 - .long UART0_LON_IRQHandler // UART0 LON interrupt - .long UART0_RX_TX_IRQHandler // UART0 receive/transmit interrupt - .long UART0_ERR_IRQHandler // UART0 error interrupt - .long UART1_RX_TX_IRQHandler // UART1 receive/transmit interrupt - .long UART1_ERR_IRQHandler // UART1 error interrupt - .long UART2_RX_TX_IRQHandler // UART2 receive/transmit interrupt - .long UART2_ERR_IRQHandler // UART2 error interrupt - .long Reserved67_IRQHandler // Reserved interrupt 67 - .long Reserved68_IRQHandler // Reserved interrupt 68 - .long Reserved69_IRQHandler // Reserved interrupt 69 - .long Reserved70_IRQHandler // Reserved interrupt 70 - .long Reserved71_IRQHandler // Reserved interrupt 71 - .long Reserved72_IRQHandler // Reserved interrupt 72 - .long ADC0_IRQHandler // ADC0 interrupt - .long ADC1_IRQHandler // ADC1 interrupt - .long CMP0_IRQHandler // CMP0 interrupt - .long CMP1_IRQHandler // CMP1 interrupt - .long CMP2_IRQHandler // CMP2 interrupt - .long FTM0_IRQHandler // FTM0 fault, overflow and channels interrupt - .long FTM1_IRQHandler // FTM1 fault, overflow and channels interrupt - .long FTM2_IRQHandler // FTM2 fault, overflow and channels interrupt - .long CMT_IRQHandler // CMT interrupt - .long RTC_IRQHandler // RTC interrupt - .long RTC_Seconds_IRQHandler // RTC seconds interrupt - .long PIT0_IRQHandler // PIT timer channel 0 interrupt - .long PIT1_IRQHandler // PIT timer channel 1 interrupt - .long PIT2_IRQHandler // PIT timer channel 2 interrupt - .long PIT3_IRQHandler // PIT timer channel 3 interrupt - .long PDB0_IRQHandler // PDB0 interrupt - .long USB0_IRQHandler // USB0 interrupt - .long USBDCD_IRQHandler // USBDCD interrupt - .long Reserved91_IRQHandler // Reserved interrupt 91 - .long Reserved92_IRQHandler // Reserved interrupt 92 - .long Reserved93_IRQHandler // Reserved interrupt 93 - .long Reserved94_IRQHandler // Reserved interrupt 94 - .long Reserved95_IRQHandler // Reserved interrupt 95 - .long Reserved96_IRQHandler // Reserved interrupt 96 - .long DAC0_IRQHandler // DAC0 interrupt - .long Reserved98_IRQHandler // Reserved interrupt 98 - .long TSI0_IRQHandler // TSI0 interrupt - .long MCG_IRQHandler // MCG interrupt - .long LPTimer_IRQHandler // LPTimer interrupt - .long Reserved102_IRQHandler // Reserved interrupt 102 - .long PORTA_IRQHandler // Port A interrupt - .long PORTB_IRQHandler // Port B interrupt - .long PORTC_IRQHandler // Port C interrupt - .long PORTD_IRQHandler // Port D interrupt - .long PORTE_IRQHandler // Port E interrupt - .long Reserved108_IRQHandler // Reserved interrupt 108 - .long Reserved109_IRQHandler // Reserved interrupt 109 - .long SWI_IRQHandler // Software interrupt - - .size __isr_vector, . - __isr_vector - - .section .text.Reset_Handler - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* - * Call SystemInit before loading the .data section to prevent the watchdog - * from resetting the board. - */ - ldr r0, =SystemInit - blx r0 - -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.Lflash_to_ram_loop: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .Lflash_to_ram_loop - -.Lflash_to_ram_loop_end: - - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler MemManage_Handler - def_default_handler BusFault_Handler - def_default_handler UsageFault_Handler - def_default_handler SVC_Handler - def_default_handler DebugMon_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - - def_irq_default_handler DMA0_IRQHandler - def_irq_default_handler DMA1_IRQHandler - def_irq_default_handler DMA2_IRQHandler - def_irq_default_handler DMA3_IRQHandler - def_irq_default_handler DMA4_IRQHandler - def_irq_default_handler DMA5_IRQHandler - def_irq_default_handler DMA6_IRQHandler - def_irq_default_handler DMA7_IRQHandler - def_irq_default_handler DMA8_IRQHandler - def_irq_default_handler DMA9_IRQHandler - def_irq_default_handler DMA10_IRQHandler - def_irq_default_handler DMA11_IRQHandler - def_irq_default_handler DMA12_IRQHandler - def_irq_default_handler DMA13_IRQHandler - def_irq_default_handler DMA14_IRQHandler - def_irq_default_handler DMA15_IRQHandler - def_irq_default_handler DMA_Error_IRQHandler - def_irq_default_handler Reserved33_IRQHandler - def_irq_default_handler FTFL_IRQHandler - def_irq_default_handler Read_Collision_IRQHandler - def_irq_default_handler LVD_LVW_IRQHandler - def_irq_default_handler LLW_IRQHandler - def_irq_default_handler Watchdog_IRQHandler - def_irq_default_handler Reserved39_IRQHandler - def_irq_default_handler I2C0_IRQHandler - def_irq_default_handler I2C1_IRQHandler - def_irq_default_handler SPI0_IRQHandler - def_irq_default_handler SPI1_IRQHandler - def_irq_default_handler Reserved44_IRQHandler - def_irq_default_handler CAN0_ORed_Message_buffer_IRQHandler - def_irq_default_handler CAN0_Bus_Off_IRQHandler - def_irq_default_handler CAN0_Error_IRQHandler - def_irq_default_handler CAN0_Tx_Warning_IRQHandler - def_irq_default_handler CAN0_Rx_Warning_IRQHandler - def_irq_default_handler CAN0_Wake_Up_IRQHandler - def_irq_default_handler I2S0_Tx_IRQHandler - def_irq_default_handler I2S0_Rx_IRQHandler - def_irq_default_handler Reserved53_IRQHandler - def_irq_default_handler Reserved54_IRQHandler - def_irq_default_handler Reserved55_IRQHandler - def_irq_default_handler Reserved56_IRQHandler - def_irq_default_handler Reserved57_IRQHandler - def_irq_default_handler Reserved58_IRQHandler - def_irq_default_handler Reserved59_IRQHandler - def_irq_default_handler UART0_LON_IRQHandler - def_irq_default_handler UART0_RX_TX_IRQHandler - def_irq_default_handler UART0_ERR_IRQHandler - def_irq_default_handler UART1_RX_TX_IRQHandler - def_irq_default_handler UART1_ERR_IRQHandler - def_irq_default_handler UART2_RX_TX_IRQHandler - def_irq_default_handler UART2_ERR_IRQHandler - def_irq_default_handler Reserved67_IRQHandler - def_irq_default_handler Reserved68_IRQHandler - def_irq_default_handler Reserved69_IRQHandler - def_irq_default_handler Reserved70_IRQHandler - def_irq_default_handler Reserved71_IRQHandler - def_irq_default_handler Reserved72_IRQHandler - def_irq_default_handler ADC0_IRQHandler - def_irq_default_handler ADC1_IRQHandler - def_irq_default_handler CMP0_IRQHandler - def_irq_default_handler CMP1_IRQHandler - def_irq_default_handler CMP2_IRQHandler - def_irq_default_handler FTM0_IRQHandler - def_irq_default_handler FTM1_IRQHandler - def_irq_default_handler FTM2_IRQHandler - def_irq_default_handler CMT_IRQHandler - def_irq_default_handler RTC_IRQHandler - def_irq_default_handler RTC_Seconds_IRQHandler - def_irq_default_handler PIT0_IRQHandler - def_irq_default_handler PIT1_IRQHandler - def_irq_default_handler PIT2_IRQHandler - def_irq_default_handler PIT3_IRQHandler - def_irq_default_handler PDB0_IRQHandler - def_irq_default_handler USB0_IRQHandler - def_irq_default_handler USBDCD_IRQHandler - def_irq_default_handler Reserved91_IRQHandler - def_irq_default_handler Reserved92_IRQHandler - def_irq_default_handler Reserved93_IRQHandler - def_irq_default_handler Reserved94_IRQHandler - def_irq_default_handler Reserved95_IRQHandler - def_irq_default_handler Reserved96_IRQHandler - def_irq_default_handler DAC0_IRQHandler - def_irq_default_handler Reserved98_IRQHandler - def_irq_default_handler TSI0_IRQHandler - def_irq_default_handler MCG_IRQHandler - def_irq_default_handler LPTimer_IRQHandler - def_irq_default_handler Reserved102_IRQHandler - def_irq_default_handler PORTA_IRQHandler - def_irq_default_handler PORTB_IRQHandler - def_irq_default_handler PORTC_IRQHandler - def_irq_default_handler PORTD_IRQHandler - def_irq_default_handler PORTE_IRQHandler - def_irq_default_handler Reserved108_IRQHandler - def_irq_default_handler Reserved109_IRQHandler - def_irq_default_handler SWI_IRQHandler - def_irq_default_handler DefaultISR - -/* Flash protection region, placed at 0x400 */ - .text - .thumb - .align 2 - .section .kinetis_flash_config_field,"a",%progbits -kinetis_flash_config: - .long 0xffffffff - .long 0xffffffff - .long 0xffffffff - .long 0xfffffffe - - .end diff --git a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/cmsis.h b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/cmsis.h deleted file mode 100644 index 86440692b3c..00000000000 --- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2015 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC11U24 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "MK20DX256.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/cmsis_nvic.h b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/cmsis_nvic.h deleted file mode 100644 index c835de230c4..00000000000 --- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/cmsis_nvic.h +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 95) // CORE + MCU Peripherals -#define NVIC_RAM_VECTOR_ADDRESS 0x1FFF8000 // Vectors positioned at start of RAM - -#endif diff --git a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/system_MK20DX256.c b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/system_MK20DX256.c deleted file mode 100644 index 9b851b44dff..00000000000 --- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/system_MK20DX256.c +++ /dev/null @@ -1,280 +0,0 @@ -/* -** ################################################################### -** Compilers: ARM Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** -** -** Version: rev. 1.0, 2011-12-15 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2011-12-15) -** Initial version -** -** ################################################################### -*/ - -/** - * @file MK20DX256 - * @version 1.0 - * @date 2011-12-15 - * @brief Device specific configuration file for MK20DX256 (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "MK20DX256.h" - -#define DISABLE_WDOG 1 - -#define CLOCK_SETUP 1 -/* Predefined clock setups - 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode - Reference clock source for MCG module is the slow internal clock source 32.768kHz - Core clock = 41.94MHz, BusClock = 41.94MHz - Works on Teensy3.1 but no USB support - 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode - Reference clock source for MCG module is an external crystal 16MHz - Core clock = 96MHz, BusClock = 48MHz - Default high speed Teensy3.1 96Mhz set up - 2 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode - Reference clock source for MCG module is an external crystal 16MHz - Core clock = 72MHz, BusClock = 36MHz - Alternative standard 'slower' Teensy3.1 72Mhz set up -*/ - -/*---------------------------------------------------------------------------- - Define clock source values - *----------------------------------------------------------------------------*/ -#if (CLOCK_SETUP == 0) - #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ - #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ - #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ - #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ - #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */ -#elif (CLOCK_SETUP == 1) - #define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */ - #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ - #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ - #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ - #define DEFAULT_SYSTEM_CLOCK 96000000u /* Default System clock value */ -#elif (CLOCK_SETUP == 2) - #define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */ - #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ - #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ - #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ - #define DEFAULT_SYSTEM_CLOCK 72000000u /* Default System clock value */ -#endif /* (CLOCK_SETUP == 2) */ - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ -void SystemInit (void) { - /* SystemInit MUST NOT use any variables from the .data section, as this section is not loaded yet! */ - -#if (DISABLE_WDOG) - /* Disable the WDOG module */ - /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */ - WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */ - /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */ - WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */ - /* WDOG_STCTRLH: DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ - WDOG->STCTRLH = (uint16_t)0x01D2u; -#endif /* (DISABLE_WDOG) */ - -#if (CLOCK_SETUP == 0) - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 41.94MHz cpu, 41.94MHz system, 20.97MHz flash*/ - SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1); - /* Switch to FEI Mode */ - /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK; - /* MCG->C2: LOCKRE0=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */ - MCG->C2 = (uint8_t)0x00u; - /* MCG_C4: DMX32=0,DRST_DRS=1 */ - MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u); - /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ - MCG->C5 = (uint8_t)0x00u; - /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ - MCG->C6 = (uint8_t)0x00u; - while((MCG->S & MCG_S_IREFST_MASK) == 0u) { } /* Check that the source of the FLL reference clock is the internal reference clock. */ - while((MCG->S & 0x0Cu) != 0x00u) { } /* Wait until output of the FLL is selected */ - -#elif (CLOCK_SETUP == 1) - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=3 Set Prescalers 96MHz cpu, 48MHz bus, 24MHz flash*/ - SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3); - /* SIM->CLKDIV2: USBDIV=2, Divide 96MHz system clock for USB 48MHz */ - SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1); - /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/ - OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK; - /* Switch to FBE Mode */ - /* MCG->C7: OSCSEL=0 */ - MCG->C7 = (uint8_t)0x00u; - /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK; - //MCG->C2 = (uint8_t)0x24u; - /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; - /* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; - /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */ - MCG->C5 = MCG_C5_PRDIV0(7); - /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ - MCG->C6 = (uint8_t)0x00u; - while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */ - while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */ - /* Switch to PBE Mode */ - /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */ - MCG->C5 = MCG_C5_PRDIV0(3); // config PLL input for 16 MHz Crystal / 4 = 4 MHz - /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */ - MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0);// config PLL for 96 MHz output - while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */ - while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ - /* Switch to PEE Mode */ - /* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK; - while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */ - while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ - -#elif (CLOCK_SETUP == 2) - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 72MHz cpu, 36MHz bus, 24MHz flash*/ - SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(2); - /* SIM->CLKDIV2: USBDIV=2,USBFRAC=1 Divide 72MHz system clock for USB 48MHz */ - SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC_MASK; - /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/ - OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK; - /* Switch to FBE Mode */ - /* MCG->C7: OSCSEL=0 */ - MCG->C7 = (uint8_t)0x00u; - /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK; - //MCG->C2 = (uint8_t)0x24u; - /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; - /* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; - /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */ - MCG->C5 = MCG_C5_PRDIV0(7); - /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ - MCG->C6 = (uint8_t)0x00u; - while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */ - while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */ - /* Switch to PBE Mode */ - /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */ - MCG->C5 = MCG_C5_PRDIV0(5); - /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */ - MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3); - while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */ - while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ - /* Switch to PEE Mode */ - /* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK; - while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */ - while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ -#endif /* (CLOCK_SETUP) */ -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ - uint8_t Divider; - - if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { - /* Output of FLL or PLL is selected */ - if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { - /* FLL is selected */ - if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { - /* External reference clock is selected */ - if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ - MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ - } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ - Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); - MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ - if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) { - MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */ - } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */ - } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ - } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ - /* Select correct multiplier to calculate the MCG output clock */ - switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { - case 0x0u: - MCGOUTClock *= 640u; - break; - case 0x20u: - MCGOUTClock *= 1280u; - break; - case 0x40u: - MCGOUTClock *= 1920u; - break; - case 0x60u: - MCGOUTClock *= 2560u; - break; - case 0x80u: - MCGOUTClock *= 732u; - break; - case 0xA0u: - MCGOUTClock *= 1464u; - break; - case 0xC0u: - MCGOUTClock *= 2197u; - break; - case 0xE0u: - MCGOUTClock *= 2929u; - break; - default: - break; - } - } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ - /* PLL is selected */ - Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); - MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ - Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); - MCGOUTClock *= Divider; /* Calculate the MCG output clock */ - } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ - } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) { - /* Internal reference clock is selected */ - if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ - } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ - MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */ - } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ - } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) { - /* External reference clock is selected */ - if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ - MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ - } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ - } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ - /* Reserved value */ - return; - } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ - SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); -} \ No newline at end of file diff --git a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/system_MK20DX256.h b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/system_MK20DX256.h deleted file mode 100644 index 3c916d03897..00000000000 --- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/system_MK20DX256.h +++ /dev/null @@ -1,85 +0,0 @@ -/* -** ################################################################### -** Compilers: ARM Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** -** -** Version: rev. 2.0, 2012-03-19 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2011-12-15) -** Initial version -** - rev. 2.0 (2012-03-19) -** PDB Peripheral register structure updated. -** DMA Registers and bits for unsupported DMA channels removed. -** -** ################################################################### -*/ - -/** - * @file MK20DX256 - * @version 2.0 - * @date 2012-03-19 - * @brief Device specific configuration file for MK20DX256 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef SYSTEM_MK20DX256_H_ -#define SYSTEM_MK20DX256_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* #if !defined(SYSTEM_MK20DX256_H_) */ diff --git a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/us_ticker.c b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/us_ticker.c deleted file mode 100644 index 8995ad72051..00000000000 --- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/us_ticker.c +++ /dev/null @@ -1,88 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" -#include "clk_freqs.h" - -static int us_ticker_inited = 0; - -void us_ticker_init(void) { - if (us_ticker_inited) - return; - us_ticker_inited = 1; - - SIM->SCGC6 |= SIM_SCGC6_PIT_MASK; // Clock PIT - PIT->MCR = 0; // Enable PIT - - //Timer on PIT0+1, ticker on PIT 2+3 - //Init timer - PIT->CHANNEL[1].LDVAL = 0xFFFFFFFF; - PIT->CHANNEL[1].TCTRL = PIT_TCTRL_CHN_MASK | PIT_TCTRL_TEN_MASK; // Start timer 1, chained to timer 0 - - // Use channel 0 as a prescaler for channel 1 - uint32_t ldval = (bus_frequency() + 500000) / 1000000 - 1; - PIT->CHANNEL[0].LDVAL = ldval; - PIT->CHANNEL[0].TCTRL = PIT_TCTRL_TEN_MASK; // Start timer - - //Init ticker - PIT->CHANNEL[2].LDVAL = ldval; - PIT->CHANNEL[2].TCTRL = PIT_TCTRL_TEN_MASK; // Start timer 2 as prescaler - - NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler); - NVIC_EnableIRQ(PIT3_IRQn); -} - -/****************************************************************************** - * Timer for us timing. - ******************************************************************************/ - -uint32_t us_ticker_read() { - if (!us_ticker_inited) - us_ticker_init(); - - return ~(PIT->CHANNEL[1].CVAL); -} - -/****************************************************************************** - * Ticker Event - ******************************************************************************/ - -void us_ticker_disable_interrupt(void) { - PIT->CHANNEL[3].TCTRL &= ~PIT_TCTRL_TIE_MASK; -} - -void us_ticker_clear_interrupt(void) { - PIT->CHANNEL[3].TFLG = 1; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) { - uint32_t delta = timestamp - us_ticker_read(); - PIT->CHANNEL[3].TCTRL = 0; - PIT->CHANNEL[3].LDVAL = delta; - PIT->CHANNEL[3].TCTRL = PIT_TCTRL_TIE_MASK | PIT_TCTRL_TEN_MASK | PIT_TCTRL_CHN_MASK; - -} - -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(PIT3_IRQn); -} - -void us_ticker_free(void) -{ - -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PeripheralNames.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PeripheralNames.h deleted file mode 100644 index 64906433721..00000000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PeripheralNames.h +++ /dev/null @@ -1,113 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - OSC32KCLK = 0, -} RTCName; - -typedef enum { - LPUART_0 = 0, - LPUART_1 = 1, - LPUART_2 = 2, - LPUART_3 = 3, - LPUART_4 = 4, -} UARTName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART LPUART_0 - -/* LPTMR interrupt is defined differently in K82F */ -#define LPTMR0_IRQn LPTMR0_LPTMR1_IRQn - -typedef enum { - I2C_0 = 0, - I2C_1 = 1, - I2C_2 = 2, - I2C_3 = 3, -} I2CName; - -#define TPM_SHIFT 8 -typedef enum { - PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 - PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 - PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 - PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 - PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 - PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 - PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 - PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 - PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 - PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 - PWM_11 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 - PWM_12 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 - PWM_13 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 - PWM_14 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 - PWM_15 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 - PWM_16 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 - PWM_17 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 - PWM_18 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 - PWM_19 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 - PWM_20 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 -} PWMName; - -#define ADC_INSTANCE_SHIFT 8 -#define ADC_B_CHANNEL_SHIFT 5 -typedef enum { - ADC0_SE4a = (0 << ADC_INSTANCE_SHIFT) | 4, - ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, - ADC0_SE5a = (0 << ADC_INSTANCE_SHIFT) | 5, - ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, - ADC0_SE6a = (0 << ADC_INSTANCE_SHIFT) | 6, - ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, - ADC0_SE7a = (0 << ADC_INSTANCE_SHIFT) | 7, - ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, - ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8, - ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9, - ADC0_SE10 = (0 << ADC_INSTANCE_SHIFT) | 10, - ADC0_SE11 = (0 << ADC_INSTANCE_SHIFT) | 11, - ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12, - ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13, - ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14, - ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15, - ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22, - ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23, -} ADCName; - -typedef enum { - DAC_0 = 0 -} DACName; - - -typedef enum { - SPI_0 = 0, - SPI_1 = 1, - SPI_2 = 2, -} SPIName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PeripheralPins.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PeripheralPins.c deleted file mode 100644 index 8eab4d62df6..00000000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PeripheralPins.c +++ /dev/null @@ -1,267 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************RTC***************/ -const PinMap PinMap_RTC[] = { - {NC, OSC32KCLK, 0}, -}; - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {PTE16, ADC0_SE4a, 0}, - {PTE17, ADC0_SE5a, 0}, - {PTE18, ADC0_SE6a, 0}, - {PTE19, ADC0_SE7a, 0}, - {PTB0, ADC0_SE8, 0}, - {PTB1, ADC0_SE9, 0}, - {PTA7, ADC0_SE10, 0}, - {PTA8, ADC0_SE11, 0}, - {PTB2, ADC0_SE12, 0}, - {PTB3, ADC0_SE13, 0}, - {PTC0, ADC0_SE14, 0}, - {PTC1, ADC0_SE15, 0}, - {PTC2, ADC0_SE4b, 0}, - {PTD1, ADC0_SE5b, 0}, - {PTD5, ADC0_SE6b, 0}, - {PTD6, ADC0_SE7b, 0}, - {NC , NC , 0} -}; - -/************DAC***************/ -const PinMap PinMap_DAC[] = { - {DAC0_OUT, DAC_0, 0}, - {NC , NC , 0} -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {PTE0, I2C_1, 6}, - {PTE10, I2C_3, 2}, - {PTE18, I2C_0, 4}, - {PTA21, I2C_0, 2}, - {PTA1, I2C_3, 4}, - {PTA7, I2C_2, 2}, - {PTA10, I2C_2, 2}, - {PTB1, I2C_0, 2}, - {PTB3, I2C_0, 2}, - {PTB11, I2C_2, 4}, - {PTC11, I2C_1, 2}, - {PTD3, I2C_0, 7}, - {PTD9, I2C_0, 2}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PTE1, I2C_1, 6}, - {PTE11, I2C_3, 2}, - {PTE19, I2C_0, 4}, - {PTA20, I2C_0, 2}, - {PTA2, I2C_3, 4}, - {PTA6, I2C_2, 2}, - {PTA11, I2C_2, 2}, - {PTB0, I2C_0, 2}, - {PTB2, I2C_0, 2}, - {PTB10, I2C_2, 4}, - {PTC10, I2C_1, 2}, - {PTD2, I2C_0, 7}, - {PTD8, I2C_0, 2}, - {NC , NC , 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {PTE0, LPUART_1, 3}, - {PTE4, LPUART_3, 3}, - {PTE12, LPUART_2, 3}, - {PTE16, LPUART_2, 3}, - {PTA20, LPUART_4, 3}, - {PTA2, LPUART_0, 2}, - {PTA14, LPUART_0, 3}, - {PTB11, LPUART_3, 3}, - {PTB17, LPUART_0, 3}, - {PTC4, LPUART_1, 3}, - {PTC15, LPUART_4, 3}, - {PTC17, LPUART_3, 3}, - {PTD3, LPUART_2, 3}, - {PTD7, LPUART_0, 3}, - {NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PTE1, LPUART_1, 3}, - {PTE5, LPUART_3, 3}, - {PTE13, LPUART_2, 3}, - {PTE17, LPUART_2, 3}, - {PTA21, LPUART_4, 3}, - {PTA1, LPUART_0, 2}, - {PTA15, LPUART_0, 3}, - {PTB10, LPUART_3, 3}, - {PTB16, LPUART_0, 3}, - {PTC3, LPUART_1, 3}, - {PTC14, LPUART_4, 3}, - {PTC16, LPUART_3, 3}, - {PTD2, LPUART_2, 3}, - {PTD6, LPUART_0, 3}, - {NC , NC , 0} -}; - -const PinMap PinMap_UART_CTS[] = { - {PTE2, LPUART_1, 3}, - {PTE6, LPUART_3, 3}, - {PTE18, LPUART_2, 3}, - {PTA0, LPUART_0, 2}, - {PTA16, LPUART_0, 3}, - {PTB3, LPUART_0, 3}, - {PTB9, LPUART_3, 3}, - {PTC2, LPUART_1, 3}, - {PTC13, LPUART_4, 3}, - {PTC19, LPUART_3, 3}, - {PTD1, LPUART_2, 3}, - {PTD5, LPUART_0, 3}, - {NC , NC , 0} -}; - -const PinMap PinMap_UART_RTS[] = { - {PTE3, LPUART_1, 3}, - {PTE7, LPUART_3, 3}, - {PTE19, LPUART_2, 3}, - {PTA3, LPUART_0, 2}, - {PTA17, LPUART_0, 3}, - {PTB2, LPUART_0, 3}, - {PTB8, LPUART_3, 3}, - {PTC1, LPUART_1, 3}, - {PTC12, LPUART_4, 3}, - {PTC18, LPUART_3, 3}, - {PTD0, LPUART_2, 3}, - {PTD4, LPUART_0, 3}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {PTE1, SPI_1, 2}, - {PTE2, SPI_1, 7}, - {PTE7, SPI_2, 2}, - {PTE17, SPI_0, 2}, - {PTA15, SPI_0, 2}, - {PTB11, SPI_1, 2}, - {PTB21, SPI_2, 2}, - {PTC5, SPI_0, 2}, - {PTD1, SPI_0, 2}, - {PTD5, SPI_1, 7}, - {PTD12, SPI_2, 2}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {PTE2, SPI_1, 2}, - {PTE3, SPI_1, 7}, - {PTE8, SPI_2, 3}, - {PTE18, SPI_0, 2}, - {PTA16, SPI_0, 2}, - {PTB16, SPI_1, 2}, - {PTB16, SPI_1, 2}, - {PTB22, SPI_2, 2}, - {PTC6, SPI_0, 2}, - {PTD2, SPI_0, 2}, - {PTD6, SPI_1, 7}, - {PTD13, SPI_2, 2}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PTE1, SPI_1, 7}, - {PTE4, SPI_1, 2}, - {PTE10, SPI_2, 3}, - {PTE19, SPI_0, 2}, - {PTA17, SPI_0, 2}, - {PTB17, SPI_1, 2}, - {PTB23, SPI_2, 2}, - {PTC7, SPI_0, 2}, - {PTD3, SPI_0, 2}, - {PTD7, SPI_1, 7}, - {PTD14, SPI_2, 2}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PTE5, SPI_1, 2}, - {PTE11, SPI_2, 3}, - {PTE16, SPI_0, 2}, - {PTA14, SPI_0, 2}, - {PTB10, SPI_1, 2}, - {PTB20, SPI_2, 2}, - {PTC4, SPI_0, 2}, - {PTD0, SPI_0, 2}, - {PTD4, SPI_1, 7}, - {PTD11, SPI_2, 2}, - {NC , NC , 0} -}; - -/************PWM***************/ -const PinMap PinMap_PWM[] = { - /* FTM 0 */ - {PTA0, PWM_6, 3}, - {PTA1, PWM_7, 3}, - {PTA2, PWM_8, 3}, - {PTA3, PWM_1, 3}, - {PTA4, PWM_2, 3}, - {PTA5, PWM_3, 3}, - {PTA6, PWM_4, 3}, - {PTA7, PWM_5, 3}, - {PTC1, PWM_1, 4}, - {PTC2, PWM_2, 4}, - {PTC3, PWM_3, 4}, - {PTC4, PWM_4, 4}, - {PTC5, PWM_3, 7}, - {PTD4, PWM_5, 4}, - {PTD5, PWM_6, 4}, - {PTD6, PWM_7, 4}, - {PTD7, PWM_8, 4}, - /* FTM 1 */ - {PTA8, PWM_9, 3}, - {PTA9, PWM_10, 3}, - {PTA12, PWM_9, 3}, - {PTA13, PWM_10, 3}, - {PTB0, PWM_9, 3}, - {PTB1, PWM_10, 3}, - /* FTM 2 */ - {PTA10, PWM_11, 3}, - {PTA11, PWM_12, 3}, - {PTB18, PWM_11, 3}, - {PTB19, PWM_12, 3}, - /* FTM 3 */ - {PTE5, PWM_13, 6}, - {PTE6, PWM_14, 6}, - {PTE7, PWM_15, 6}, - {PTE8, PWM_16, 6}, - {PTE9, PWM_17, 6}, - {PTE10, PWM_18, 6}, - {PTE11, PWM_19, 6}, - {PTE12, PWM_20, 6}, - {PTC8, PWM_17, 3}, - {PTC9, PWM_18, 3}, - {PTC10, PWM_19, 3}, - {PTC11, PWM_20, 3}, - {PTD0, PWM_13, 4}, - {PTD1, PWM_14, 4}, - {PTD2, PWM_15, 4}, - {PTD3, PWM_16, 4}, - - {NC , NC , 0} -}; diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PinNames.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PinNames.h deleted file mode 100644 index a10b156206c..00000000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PinNames.h +++ /dev/null @@ -1,180 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define GPIO_PORT_SHIFT 12 - -typedef enum { - PTA0 = (0 << GPIO_PORT_SHIFT | 0), - PTA1 = (0 << GPIO_PORT_SHIFT | 1), - PTA2 = (0 << GPIO_PORT_SHIFT | 2), - PTA3 = (0 << GPIO_PORT_SHIFT | 3), - PTA4 = (0 << GPIO_PORT_SHIFT | 4), - PTA5 = (0 << GPIO_PORT_SHIFT | 5), - PTA6 = (0 << GPIO_PORT_SHIFT | 6), - PTA7 = (0 << GPIO_PORT_SHIFT | 7), - PTA8 = (0 << GPIO_PORT_SHIFT | 8), - PTA9 = (0 << GPIO_PORT_SHIFT | 9), - PTA10 = (0 << GPIO_PORT_SHIFT | 10), - PTA11 = (0 << GPIO_PORT_SHIFT | 11), - PTA12 = (0 << GPIO_PORT_SHIFT | 12), - PTA13 = (0 << GPIO_PORT_SHIFT | 13), - PTA14 = (0 << GPIO_PORT_SHIFT | 14), - PTA15 = (0 << GPIO_PORT_SHIFT | 15), - PTA16 = (0 << GPIO_PORT_SHIFT | 16), - PTA17 = (0 << GPIO_PORT_SHIFT | 17), - PTA18 = (0 << GPIO_PORT_SHIFT | 18), - PTA19 = (0 << GPIO_PORT_SHIFT | 19), - PTA20 = (0 << GPIO_PORT_SHIFT | 20), - PTA21 = (0 << GPIO_PORT_SHIFT | 21), - PTB0 = (1 << GPIO_PORT_SHIFT | 0), - PTB1 = (1 << GPIO_PORT_SHIFT | 1), - PTB2 = (1 << GPIO_PORT_SHIFT | 2), - PTB3 = (1 << GPIO_PORT_SHIFT | 3), - PTB8 = (1 << GPIO_PORT_SHIFT | 8), - PTB9 = (1 << GPIO_PORT_SHIFT | 9), - PTB10 = (1 << GPIO_PORT_SHIFT | 10), - PTB11 = (1 << GPIO_PORT_SHIFT | 11), - PTB16 = (1 << GPIO_PORT_SHIFT | 16), - PTB17 = (1 << GPIO_PORT_SHIFT | 17), - PTB18 = (1 << GPIO_PORT_SHIFT | 18), - PTB19 = (1 << GPIO_PORT_SHIFT | 19), - PTB20 = (1 << GPIO_PORT_SHIFT | 20), - PTB21 = (1 << GPIO_PORT_SHIFT | 21), - PTB22 = (1 << GPIO_PORT_SHIFT | 22), - PTB23 = (1 << GPIO_PORT_SHIFT | 23), - PTC0 = (2 << GPIO_PORT_SHIFT | 0), - PTC1 = (2 << GPIO_PORT_SHIFT | 1), - PTC2 = (2 << GPIO_PORT_SHIFT | 2), - PTC3 = (2 << GPIO_PORT_SHIFT | 3), - PTC4 = (2 << GPIO_PORT_SHIFT | 4), - PTC5 = (2 << GPIO_PORT_SHIFT | 5), - PTC6 = (2 << GPIO_PORT_SHIFT | 6), - PTC7 = (2 << GPIO_PORT_SHIFT | 7), - PTC8 = (2 << GPIO_PORT_SHIFT | 8), - PTC9 = (2 << GPIO_PORT_SHIFT | 9), - PTC10 = (2 << GPIO_PORT_SHIFT | 10), - PTC11 = (2 << GPIO_PORT_SHIFT | 11), - PTC12 = (2 << GPIO_PORT_SHIFT | 12), - PTC13 = (2 << GPIO_PORT_SHIFT | 13), - PTC14 = (2 << GPIO_PORT_SHIFT | 14), - PTC15 = (2 << GPIO_PORT_SHIFT | 15), - PTC16 = (2 << GPIO_PORT_SHIFT | 16), - PTC17 = (2 << GPIO_PORT_SHIFT | 17), - PTC18 = (2 << GPIO_PORT_SHIFT | 18), - PTC19 = (2 << GPIO_PORT_SHIFT | 19), - PTD0 = (3 << GPIO_PORT_SHIFT | 0), - PTD1 = (3 << GPIO_PORT_SHIFT | 1), - PTD2 = (3 << GPIO_PORT_SHIFT | 2), - PTD3 = (3 << GPIO_PORT_SHIFT | 3), - PTD4 = (3 << GPIO_PORT_SHIFT | 4), - PTD5 = (3 << GPIO_PORT_SHIFT | 5), - PTD6 = (3 << GPIO_PORT_SHIFT | 6), - PTD7 = (3 << GPIO_PORT_SHIFT | 7), - PTD8 = (3 << GPIO_PORT_SHIFT | 8), - PTD9 = (3 << GPIO_PORT_SHIFT | 9), - PTD11 = (3 << GPIO_PORT_SHIFT | 11), - PTD12 = (3 << GPIO_PORT_SHIFT | 12), - PTD13 = (3 << GPIO_PORT_SHIFT | 13), - PTD14 = (3 << GPIO_PORT_SHIFT | 14), - PTE0 = (4 << GPIO_PORT_SHIFT | 0), - PTE1 = (4 << GPIO_PORT_SHIFT | 1), - PTE2 = (4 << GPIO_PORT_SHIFT | 2), - PTE3 = (4 << GPIO_PORT_SHIFT | 3), - PTE4 = (4 << GPIO_PORT_SHIFT | 4), - PTE5 = (4 << GPIO_PORT_SHIFT | 5), - PTE6 = (4 << GPIO_PORT_SHIFT | 6), - PTE7 = (4 << GPIO_PORT_SHIFT | 7), - PTE8 = (4 << GPIO_PORT_SHIFT | 8), - PTE9 = (4 << GPIO_PORT_SHIFT | 9), - PTE10 = (4 << GPIO_PORT_SHIFT | 10), - PTE11 = (4 << GPIO_PORT_SHIFT | 11), - PTE12 = (4 << GPIO_PORT_SHIFT | 12), - PTE13 = (4 << GPIO_PORT_SHIFT | 13), - PTE16 = (4 << GPIO_PORT_SHIFT | 16), - PTE17 = (4 << GPIO_PORT_SHIFT | 17), - PTE18 = (4 << GPIO_PORT_SHIFT | 18), - PTE19 = (4 << GPIO_PORT_SHIFT | 19), - - LED_RED = PTD4, - LED_RGB = PTA14, - - // mbed original LED naming - LED1 = LED_RED, - LED2 = LED_RED, - LED3 = LED_RED, - LED4 = LED_RED, - - //Push buttons - SW0 = PTD0, - - // Console Pins - USBTX = PTA2, - USBRX = PTA1, - - // GSM modem Pins - GSM_UART_TX = PTC15, - GSM_UART_RX = PTC14, - GSM_UART_CMD_TX = PTC4, - GSM_UART_CMD_RX = PTC3, - GSM_POWER = PTD7, - GSM_STATUS = PTE6, - GSM_PWRKEY = PTE8, - GSM_RI = PTE9, - GSM_DCD = PTE10, - - I2C_SCL = PTB10, - I2C_SDA = PTB11, - - SDHC_D0 = PTE1, - SDHC_D1 = PTE0, - SDHC_D2 = PTE5, - SDHC_D3 = PTE4, - SDHC_DCLK = PTE2, - SDHC_CMD = PTE3, - SHDC_DETECT = PTE7, - - DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ - - // Not connected - NC = (int) 0xFFFFFFFF -} PinName; - - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 2, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/device.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/device.h deleted file mode 100644 index 29a4e7a0b18..00000000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/device.h +++ /dev/null @@ -1,39 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 24 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/fsl_clock_config.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/fsl_clock_config.c deleted file mode 100644 index ae5657490a0..00000000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/fsl_clock_config.c +++ /dev/null @@ -1,506 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * How to setup clock using clock driver functions: - * - * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock - * and flash clock are in allowed range during clock mode switch. - * - * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. - * - * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and - * internal reference clock(MCGIRCLK). Follow the steps to setup: - * - * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. - * - * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured - * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig - * explicitly to setup MCGIRCLK. - * - * 3). Don't need to configure FLL explicitly, because if target mode is FLL - * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, - * if the target mode is not FLL mode, the FLL is disabled. - * - * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been - * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could - * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. - * - * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. - */ - -/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** -!!ClocksProfile -product: Clocks v1.0 -processor: MK82FN256xxx15 -package_id: MK82FN256VLL15 -mcu_data: ksdk2_0 -processor_version: 1.0.1 - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ - -#include "fsl_smc.h" -#include "fsl_rtc.h" -#include "fsl_clock_config.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */ -#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */ -#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */ -#define RTC_OSC_CAP_LOAD_0PF 0x0U /*!< RTC oscillator capacity load: 0pF */ -#define RTC_RTC32KCLK_PERIPHERALS_ENABLED 1U /*!< RTC32KCLK to other peripherals: enabled */ -#define SIM_FLEXIO_CLK_SEL_CORE_SYSTEM_CLK 0U /*!< FLEXIO clock select: Core/system clock */ -#define SIM_FLEXIO_CLK_SEL_MCGIRCLK_CLK 3U /*!< FLEXIO clock select: MCGIRCLK clock */ -#define SIM_LPUART_CLK_SEL_MCGIRCLK_CLK 3U /*!< LPUART clock select: MCGIRCLK clock */ -#define SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK 1U /*!< LPUART clock select: PLLFLLSEL output clock */ -#define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ -#define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */ -#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; - -/******************************************************************************* - * Code - ******************************************************************************/ -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_CONFIG_SetRtcClock - * Description : This function is used to configuring RTC clock including - * enabling RTC oscillator. - * Param capLoad : RTC oscillator capacity load - * Param enableOutPeriph : Enable (1U)/Disable (0U) clock to peripherals - * - *END**************************************************************************/ -static void CLOCK_CONFIG_SetRtcClock(uint32_t capLoad, uint8_t enableOutPeriph) -{ - /* RTC clock gate enable */ - CLOCK_EnableClock(kCLOCK_Rtc0); - if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the Rtc oscillator is not already enabled */ - /* Set the specified capacitor configuration for the RTC oscillator */ - RTC_SetOscCapLoad(RTC, capLoad); - /* Enable the RTC 32KHz oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; - } - /* Output to other peripherals */ - if (enableOutPeriph) { - RTC->CR &= ~RTC_CR_CLKO_MASK; - } - else { - RTC->CR |= RTC_CR_CLKO_MASK; - } - /* Set the XTAL32/RTC_CLKIN frequency based on board setting. */ - CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ); - /* Set RTC_TSR if there is fault value in RTC */ - if (RTC->SR & RTC_SR_TIF_MASK) { - RTC -> TSR = RTC -> TSR; - } - /* RTC clock gate disable */ - CLOCK_DisableClock(kCLOCK_Rtc0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_CONFIG_SetFllExtRefDiv - * Description : Configure FLL external reference divider (FRDIV). - * Param frdiv : The value to set FRDIV. - * - *END**************************************************************************/ -static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv) -{ - MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); -} - -/******************************************************************************* - ********************* Configuration BOARD_BootClockHSRUN ********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** -!!Configuration -name: BOARD_BootClockHSRUN -outputs: -- {id: Bus_clock.outFreq, value: 75 MHz} -- {id: Core_clock.outFreq, value: 150 MHz} -- {id: ERCLK32K.outFreq, value: 32.768 kHz} -- {id: FLEXIOCLK.outFreq, value: 150 MHz} -- {id: Flash_clock.outFreq, value: 25 MHz} -- {id: FlexBus_clock.outFreq, value: 75 MHz} -- {id: IRC48MCLK.outFreq, value: 48 MHz} -- {id: LPO_clock.outFreq, value: 1 kHz} -- {id: LPUARTCLK.outFreq, value: 75 MHz} -- {id: MCGFFCLK.outFreq, value: 1.5 MHz} -- {id: MCGIRCLK.outFreq, value: 2 MHz} -- {id: MCGPLLCLK.outFreq, value: 150 MHz} -- {id: MCGPLLCLK2X.outFreq, value: 300 MHz} -- {id: PLLFLLCLK.outFreq, value: 150 MHz} -- {id: System_clock.outFreq, value: 150 MHz} -settings: -- {id: MCGMode, value: PEE} -- {id: powerMode, value: HSRUN} -- {id: FLEXIOClkConfig, value: 'yes'} -- {id: LPUARTClkConfig, value: 'yes'} -- {id: MCG.FLL_mul.scale, value: '2929', locked: true} -- {id: MCG.FRDIV.scale, value: '32', locked: true} -- {id: MCG.IRCS.sel, value: MCG.FCRDIV} -- {id: MCG.IREFS.sel, value: MCG.FRDIV} -- {id: MCG.OSCSEL.sel, value: SIM.IRC48MCLK} -- {id: MCG.OSCSEL_PLL.sel, value: SIM.IRC48MCLK} -- {id: MCG.PLLS.sel, value: MCG.PLL_DIV2} -- {id: MCG.PRDIV.scale, value: '4', locked: true} -- {id: MCG.VDIV.scale, value: '25', locked: true} -- {id: MCG_C1_IRCLKEN_CFG, value: Enabled} -- {id: MCG_C2_RANGE0_CFG, value: Very_high} -- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high} -- {id: MCG_C5_PLLCLKEN0_CFG, value: Enabled} -- {id: RTC_CR_OSCE_CFG, value: Enabled} -- {id: SIM.LPUARTSRCSEL.sel, value: SIM.PLLFLLDIV} -- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK} -- {id: SIM.OUTDIV2.scale, value: '2'} -- {id: SIM.OUTDIV4.scale, value: '6'} -- {id: SIM.PLLFLLDIV.scale, value: '2', locked: true} -- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK} -- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK} -- {id: SIM.USBDIV.scale, value: '1', locked: true} -- {id: SIM.USBFRAC.scale, value: '1', locked: true} -sources: -- {id: IRC48M.IRC48M.outFreq, value: 48 MHz} -- {id: RTC.RTC32kHz.outFreq, value: 32.768 kHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ - -/******************************************************************************* - * Variables for BOARD_BootClockHSRUN configuration - ******************************************************************************/ -const mcg_config_t mcgConfig_BOARD_BootClockHSRUN = - { - .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */ - .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ - .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */ - .fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */ - .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */ - .drs = kMCG_DrsHigh, /* High frequency range */ - .dmx32 = kMCG_Dmx32Fine, /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ - .oscsel = kMCG_OscselIrc, /* Selects 48 MHz IRC Oscillator */ - .pll0Config = - { - .enableMode = kMCG_PllEnableIndependent,/* MCGPLLCLK enabled independent of MCG clock mode, MCGPLLCLK disabled in STOP mode */ - .prdiv = 0x3U, /* PLL Reference divider: divided by 4 */ - .vdiv = 0x9U, /* VCO divider: multiplied by 25 */ - }, - }; -const sim_clock_config_t simConfig_BOARD_BootClockHSRUN = - { - .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */ - .pllFllDiv = 1, /* PLLFLLSEL clock divider divisor: divided by 2 */ - .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */ - .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ - .clkdiv1 = 0x1150000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /6 */ - }; -const osc_config_t oscConfig_BOARD_BootClockHSRUN = - { - .freq = 0U, /* Oscillator frequency: 0Hz */ - .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ - .workMode = kOSC_ModeExt, /* Use external clock */ - .oscerConfig = - { - .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */ - .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */ - } - }; - -/******************************************************************************* - * Code for BOARD_BootClockHSRUN configuration - ******************************************************************************/ -void BOARD_BootClockHSRUN(void) -{ - /* Set HSRUN power mode */ - SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); - SMC_SetPowerModeHsrun(SMC); - while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun) - { - } - /* Set the system clock dividers in SIM to safe value. */ - CLOCK_SetSimSafeDivs(); - /* Configure RTC clock including enabling RTC oscillator. */ - CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_0PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED); - /* Configure the Internal Reference clock (MCGIRCLK). */ - CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode, - mcgConfig_BOARD_BootClockHSRUN.ircs, - mcgConfig_BOARD_BootClockHSRUN.fcrdiv); - /* Configure FLL external reference divider (FRDIV). */ - CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockHSRUN.frdiv); - /* Set MCG to PEE mode. */ - CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockHSRUN.oscsel, - kMCG_PllClkSelPll0, - &mcgConfig_BOARD_BootClockHSRUN.pll0Config); - /* Set the clock configuration in SIM module. */ - CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN); - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK; - /* Set LPUART clock source. */ - CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK); - /* Set FLEXIO clock source. */ - CLOCK_SetFlexio0Clock(SIM_FLEXIO_CLK_SEL_CORE_SYSTEM_CLK); -} - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** -!!Configuration -name: BOARD_BootClockRUN -outputs: -- {id: Bus_clock.outFreq, value: 60 MHz} -- {id: Core_clock.outFreq, value: 120 MHz} -- {id: ERCLK32K.outFreq, value: 32.768 kHz} -- {id: FLEXIOCLK.outFreq, value: 120 MHz} -- {id: Flash_clock.outFreq, value: 20 MHz} -- {id: FlexBus_clock.outFreq, value: 60 MHz} -- {id: IRC48MCLK.outFreq, value: 48 MHz} -- {id: LPO_clock.outFreq, value: 1 kHz} -- {id: LPUARTCLK.outFreq, value: 60 MHz} -- {id: MCGFFCLK.outFreq, value: 1.5 MHz} -- {id: MCGIRCLK.outFreq, value: 2 MHz} -- {id: MCGPLLCLK.outFreq, value: 120 MHz} -- {id: MCGPLLCLK2X.outFreq, value: 240 MHz} -- {id: PLLFLLCLK.outFreq, value: 120 MHz} -- {id: System_clock.outFreq, value: 120 MHz} -settings: -- {id: MCGMode, value: PEE} -- {id: FLEXIOClkConfig, value: 'yes'} -- {id: LPUARTClkConfig, value: 'yes'} -- {id: MCG.FLL_mul.scale, value: '2929', locked: true} -- {id: MCG.FRDIV.scale, value: '32', locked: true} -- {id: MCG.IRCS.sel, value: MCG.FCRDIV} -- {id: MCG.IREFS.sel, value: MCG.FRDIV} -- {id: MCG.OSCSEL.sel, value: SIM.IRC48MCLK} -- {id: MCG.OSCSEL_PLL.sel, value: SIM.IRC48MCLK} -- {id: MCG.PLLS.sel, value: MCG.PLL_DIV2} -- {id: MCG.PRDIV.scale, value: '4', locked: true} -- {id: MCG.VDIV.scale, value: '20', locked: true} -- {id: MCG_C1_IRCLKEN_CFG, value: Enabled} -- {id: MCG_C2_RANGE0_CFG, value: Very_high} -- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high} -- {id: MCG_C5_PLLCLKEN0_CFG, value: Enabled} -- {id: RTC_CR_OSCE_CFG, value: Enabled} -- {id: SIM.LPUARTSRCSEL.sel, value: SIM.PLLFLLDIV} -- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK} -- {id: SIM.OUTDIV2.scale, value: '2'} -- {id: SIM.OUTDIV4.scale, value: '6'} -- {id: SIM.PLLFLLDIV.scale, value: '2', locked: true} -- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK} -- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK} -- {id: SIM.USBDIV.scale, value: '1', locked: true} -- {id: SIM.USBFRAC.scale, value: '1', locked: true} -sources: -- {id: IRC48M.IRC48M.outFreq, value: 48 MHz} -- {id: RTC.RTC32kHz.outFreq, value: 32.768 kHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -const mcg_config_t mcgConfig_BOARD_BootClockRUN = - { - .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */ - .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ - .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */ - .fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */ - .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */ - .drs = kMCG_DrsHigh, /* High frequency range */ - .dmx32 = kMCG_Dmx32Fine, /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ - .oscsel = kMCG_OscselIrc, /* Selects 48 MHz IRC Oscillator */ - .pll0Config = - { - .enableMode = kMCG_PllEnableIndependent,/* MCGPLLCLK enabled independent of MCG clock mode, MCGPLLCLK disabled in STOP mode */ - .prdiv = 0x3U, /* PLL Reference divider: divided by 4 */ - .vdiv = 0x4U, /* VCO divider: multiplied by 20 */ - }, - }; -const sim_clock_config_t simConfig_BOARD_BootClockRUN = - { - .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */ - .pllFllDiv = 1, /* PLLFLLSEL clock divider divisor: divided by 2 */ - .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */ - .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ - .clkdiv1 = 0x1150000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /6 */ - }; -const osc_config_t oscConfig_BOARD_BootClockRUN = - { - .freq = 0U, /* Oscillator frequency: 0Hz */ - .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ - .workMode = kOSC_ModeExt, /* Use external clock */ - .oscerConfig = - { - .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */ - .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */ - } - }; - -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /* Set the system clock dividers in SIM to safe value. */ - CLOCK_SetSimSafeDivs(); - /* Configure RTC clock including enabling RTC oscillator. */ - CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_0PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED); - /* Configure the Internal Reference clock (MCGIRCLK). */ - CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, - mcgConfig_BOARD_BootClockRUN.ircs, - mcgConfig_BOARD_BootClockRUN.fcrdiv); - /* Configure FLL external reference divider (FRDIV). */ - CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv); - /* Set MCG to PEE mode. */ - CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, - kMCG_PllClkSelPll0, - &mcgConfig_BOARD_BootClockRUN.pll0Config); - /* Set the clock configuration in SIM module. */ - CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; - /* Set LPUART clock source. */ - CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK); - /* Set FLEXIO clock source. */ - CLOCK_SetFlexio0Clock(SIM_FLEXIO_CLK_SEL_CORE_SYSTEM_CLK); -} - -/******************************************************************************* - ********************* Configuration BOARD_BootClockVLPR *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** -!!Configuration -name: BOARD_BootClockVLPR -outputs: -- {id: Bus_clock.outFreq, value: 4 MHz} -- {id: Core_clock.outFreq, value: 4 MHz} -- {id: ERCLK32K.outFreq, value: 32.768 kHz} -- {id: FLEXIOCLK.outFreq, value: 4 MHz} -- {id: Flash_clock.outFreq, value: 800 kHz} -- {id: FlexBus_clock.outFreq, value: 4 MHz} -- {id: LPO_clock.outFreq, value: 1 kHz} -- {id: LPUARTCLK.outFreq, value: 4 MHz} -- {id: MCGIRCLK.outFreq, value: 4 MHz} -- {id: System_clock.outFreq, value: 4 MHz} -settings: -- {id: MCGMode, value: BLPI} -- {id: powerMode, value: VLPR} -- {id: FLEXIOClkConfig, value: 'yes'} -- {id: LPUARTClkConfig, value: 'yes'} -- {id: MCG.CLKS.sel, value: MCG.IRCS} -- {id: MCG.FCRDIV.scale, value: '1'} -- {id: MCG.IRCS.sel, value: MCG.FCRDIV} -- {id: MCG_C1_IRCLKEN_CFG, value: Enabled} -- {id: RTC_CR_OSCE_CFG, value: Enabled} -- {id: SIM.FLEXIOSRCSEL.sel, value: MCG.MCGIRCLK} -- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK} -- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK} -- {id: SIM.OUTDIV3.scale, value: '1'} -- {id: SIM.OUTDIV4.scale, value: '5'} -sources: -- {id: RTC.RTC32kHz.outFreq, value: 32.768 kHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ - -/******************************************************************************* - * Variables for BOARD_BootClockVLPR configuration - ******************************************************************************/ -const mcg_config_t mcgConfig_BOARD_BootClockVLPR = - { - .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */ - .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ - .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */ - .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */ - .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */ - .drs = kMCG_DrsLow, /* Low frequency range */ - .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ - .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */ - .pll0Config = - { - .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */ - .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */ - .vdiv = 0x0U, /* VCO divider: multiplied by 16 */ - }, - }; -const sim_clock_config_t simConfig_BOARD_BootClockVLPR = - { - .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */ - .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */ - .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */ - .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ - .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */ - }; -const osc_config_t oscConfig_BOARD_BootClockVLPR = - { - .freq = 0U, /* Oscillator frequency: 0Hz */ - .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ - .workMode = kOSC_ModeExt, /* Use external clock */ - .oscerConfig = - { - .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */ - .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */ - } - }; - -/******************************************************************************* - * Code for BOARD_BootClockVLPR configuration - ******************************************************************************/ -void BOARD_BootClockVLPR(void) -{ - /* Set the system clock dividers in SIM to safe value. */ - CLOCK_SetSimSafeDivs(); - /* Configure RTC clock including enabling RTC oscillator. */ - CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_0PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED); - /* Set MCG to BLPI mode. */ - CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, - mcgConfig_BOARD_BootClockVLPR.ircs, - mcgConfig_BOARD_BootClockVLPR.irclkEnableMode); - /* Set the clock configuration in SIM module. */ - CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR); - /* Set VLPR power mode. */ - SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); -#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) - SMC_SetPowerModeVlpr(SMC, false); -#else - SMC_SetPowerModeVlpr(SMC); -#endif - while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) - { - } - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK; - /* Set LPUART clock source. */ - CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK); - /* Set FLEXIO clock source. */ - CLOCK_SetFlexio0Clock(SIM_FLEXIO_CLK_SEL_MCGIRCLK_CLK); -} - diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/fsl_clock_config.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/fsl_clock_config.h deleted file mode 100644 index df0bede6e3c..00000000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/fsl_clock_config.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board RTC xtal frequency in Hz */ - -/******************************************************************************* - ********************* Configuration BOARD_BootClockHSRUN ********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockHSRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ - -/*! @brief MCG set for BOARD_BootClockHSRUN configuration. - */ -extern const mcg_config_t mcgConfig_BOARD_BootClockHSRUN; -/*! @brief SIM module set for BOARD_BootClockHSRUN configuration. - */ -extern const sim_clock_config_t simConfig_BOARD_BootClockHSRUN; -/*! @brief OSC set for BOARD_BootClockHSRUN configuration. - */ -extern const osc_config_t oscConfig_BOARD_BootClockHSRUN; - -/******************************************************************************* - * API for BOARD_BootClockHSRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockHSRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 120000000U /*!< Core clock frequency: 120000000Hz */ - -/*! @brief MCG set for BOARD_BootClockRUN configuration. - */ -extern const mcg_config_t mcgConfig_BOARD_BootClockRUN; -/*! @brief SIM module set for BOARD_BootClockRUN configuration. - */ -extern const sim_clock_config_t simConfig_BOARD_BootClockRUN; -/*! @brief OSC set for BOARD_BootClockRUN configuration. - */ -extern const osc_config_t oscConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************* Configuration BOARD_BootClockVLPR *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockVLPR configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 2000000U /*!< Core clock frequency: 2000000Hz */ - -/*! @brief MCG set for BOARD_BootClockVLPR configuration. - */ -extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR; -/*! @brief SIM module set for BOARD_BootClockVLPR configuration. - */ -extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR; -/*! @brief OSC set for BOARD_BootClockVLPR configuration. - */ -extern const osc_config_t oscConfig_BOARD_BootClockVLPR; - -/******************************************************************************* - * API for BOARD_BootClockVLPR configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockVLPR(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ - diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/mbed_overrides.c deleted file mode 100644 index 5295be6fd9b..00000000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/mbed_overrides.c +++ /dev/null @@ -1,85 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "fsl_smc.h" -#include "fsl_rcm.h" -#include "fsl_pmc.h" -#include "fsl_rtc.h" -#include "fsl_clock_config.h" - -//!< this contains the wakeup source -rcm_reset_source_t kinetisResetSource; - -// called before main -void mbed_sdk_init() -{ - rtc_config_t rtc_basic_config; - uint32_t u32cTPR_counter = 0; - - SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); - - // check the power mode source - kinetisResetSource = (rcm_reset_source_t) (RCM_GetPreviousResetSources(RCM)); - // if waking up from VLLS, do some cleanup - if (kinetisResetSource & kRCM_SourceWakeup) { - PMC_ClearPeriphIOIsolationFlag(PMC); - NVIC_ClearPendingIRQ(LLWU_IRQn); - } - - BOARD_BootClockRUN(); - - CLOCK_EnableClock(kCLOCK_Rtc0); - - /* Check if the Rtc oscillator is enabled */ - if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { - /*Init the RTC with default configuration*/ - RTC_GetDefaultConfig(&rtc_basic_config); - - /* Setup the 32K RTC OSC */ - RTC_Init(RTC, &rtc_basic_config); - - /* Enable the RTC 32KHz oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; - - /* Start the RTC time counter */ - RTC_StartTimer(RTC); - - /* Verify TPR register reaches 4096 counts */ - while (u32cTPR_counter < 4096) { - u32cTPR_counter = RTC->TPR; - } - /* 32kHz Oscillator is ready. */ - RTC_Deinit(RTC); - } - - CLOCK_DisableClock(kCLOCK_Rtc0); -} - -// Change the NMI pin to an input. This allows NMI pin to -// be used as a low power mode wakeup. The application will -// need to change the pin back to NMI_b or wakeup only occurs once! -void NMI_Handler(void) -{ - gpio_t gpio; - gpio_init_in(&gpio, PTA4); -} - -// Set the UART clock source -void serial_clock_init(void) -{ - CLOCK_SetLpuartClock(1U); -} - diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PeripheralNames.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PeripheralNames.h deleted file mode 100644 index 373051da51e..00000000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PeripheralNames.h +++ /dev/null @@ -1,102 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - OSC32KCLK = 0, -} RTCName; - -/* LPUART */ -typedef enum { - LPUART_0 = 0, - LPUART_1 = 1, - LPUART_2 = 2, -} UARTName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART LPUART_0 - -typedef enum { - I2C_0 = 0, - I2C_1 = 1, -} I2CName; - -#define TPM_SHIFT 8 -typedef enum { - PWM_1 = (0 << TPM_SHIFT) | (0), // TPM0 CH0 - PWM_2 = (0 << TPM_SHIFT) | (1), // TPM0 CH1 - PWM_3 = (0 << TPM_SHIFT) | (2), // TPM0 CH2 - PWM_4 = (0 << TPM_SHIFT) | (3), // TPM0 CH3 - PWM_5 = (0 << TPM_SHIFT) | (4), // TPM0 CH4 - PWM_6 = (0 << TPM_SHIFT) | (5), // TPM0 CH5 - PWM_7 = (1 << TPM_SHIFT) | (0), // TPM1 CH0 - PWM_8 = (1 << TPM_SHIFT) | (1), // TPM1 CH1 - PWM_9 = (2 << TPM_SHIFT) | (0), // TPM2 CH0 - PWM_10 = (2 << TPM_SHIFT) | (1), // TPM2 CH1 -} PWMName; - -#define ADC_INSTANCE_SHIFT 8 -#define ADC_B_CHANNEL_SHIFT 5 -typedef enum { - ADC0_SE0 = (0 << ADC_INSTANCE_SHIFT) | 0, - ADC0_SE1 = (0 << ADC_INSTANCE_SHIFT) | 1, - ADC0_SE2 = (0 << ADC_INSTANCE_SHIFT) | 2, - ADC0_SE3 = (0 << ADC_INSTANCE_SHIFT) | 3, - ADC0_SE4a = (0 << ADC_INSTANCE_SHIFT) | 4, - ADC0_SE5a = (0 << ADC_INSTANCE_SHIFT) | 5, - ADC0_SE6a = (0 << ADC_INSTANCE_SHIFT) | 6, - ADC0_SE7a = (0 << ADC_INSTANCE_SHIFT) | 7, - ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, - ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, - ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, - ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, - ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8, - ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9, - ADC0_SE11 = (0 << ADC_INSTANCE_SHIFT) | 11, - ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12, - ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13, - ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14, - ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15, - ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16, - ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17, - ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18, - ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21, - ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22, - ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23, -} ADCName; - -typedef enum { - SPI_0 = 0, - SPI_1 = 1, -} SPIName; - -typedef enum { - DAC_0 = 0 -} DACName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PeripheralPins.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PeripheralPins.c deleted file mode 100644 index 3cbfd04c6b2..00000000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PeripheralPins.c +++ /dev/null @@ -1,159 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************RTC***************/ -const PinMap PinMap_RTC[] = { - {NC, OSC32KCLK, 0}, -}; - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {PTB0, ADC0_SE8, 0}, - {PTB1, ADC0_SE9, 0}, - {PTB2, ADC0_SE12, 0}, - {PTB3, ADC0_SE13, 0}, - {PTC0, ADC0_SE14, 0}, - {PTC1, ADC0_SE15, 0}, - {PTC2, ADC0_SE4b, 0}, - {PTD1, ADC0_SE5b, 0}, - {PTD5, ADC0_SE6b, 0}, - {PTD6, ADC0_SE7b, 0}, - {NC , NC , 0} -}; - -/************DAC***************/ -const PinMap PinMap_DAC[] = { - {DAC0_OUT, DAC_0, 0}, - {NC , NC , 0} -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {PTB1, I2C_0, 2}, - {PTB3, I2C_0, 2}, - {PTC11, I2C_1, 2}, - {PTD3, I2C_0, 7}, - {PTD9, I2C_0, 2}, - {PTE0, I2C_1, 6}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PTB0, I2C_0, 2}, - {PTB2, I2C_0, 2}, - {PTC10, I2C_1, 2}, - {PTD2, I2C_0, 7}, - {PTD8, I2C_0, 2}, - {PTE1, I2C_1, 6}, - {NC , NC , 0} -}; - -/************LPUART***************/ -const PinMap PinMap_UART_TX[] = { - {PTA2, LPUART_0, 2}, - {PTA14, LPUART_0, 3}, - {PTB17, LPUART_0, 3}, - {PTC4, LPUART_1, 3}, - {PTD3, LPUART_2, 3}, - {PTD7, LPUART_0, 3}, - {PTE0, LPUART_1, 3}, - {NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PTA1, LPUART_0, 2}, - {PTA15, LPUART_0, 3}, - {PTB16, LPUART_0, 3}, - {PTC3, LPUART_1, 3}, - {PTD2, LPUART_2, 3}, - {PTD6, LPUART_0, 3}, - {PTE1, LPUART_1, 3}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {PTE1, SPI_1, 2}, - {PTE2, SPI_1, 7}, - {PTA15, SPI_1, 2}, - {PTB11, SPI_1, 2}, - {PTC5, SPI_0, 2}, - {PTD1, SPI_0, 2}, - {PTD5, SPI_1, 7}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {PTE2, SPI_1, 2}, - {PTE3, SPI_1, 7}, - {PTA16, SPI_1, 2}, - {PTB16, SPI_1, 2}, - {PTC6, SPI_0, 2}, - {PTD2, SPI_0, 2}, - {PTD6, SPI_1, 7}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PTE1, SPI_1, 7}, - {PTE4, SPI_1, 2}, - {PTA17, SPI_1, 2}, - {PTB17, SPI_1, 2}, - {PTC7, SPI_0, 2}, - {PTD3, SPI_0, 2}, - {PTD7, SPI_1, 7}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PTE5, SPI_1, 2}, - {PTA14, SPI_1, 2}, - {PTB10, SPI_1, 2}, - {PTC4, SPI_0, 2}, - {PTD0, SPI_0, 2}, - {PTD4, SPI_1, 7}, - {NC , NC , 0} -}; - -/************PWM***************/ -const PinMap PinMap_PWM[] = { - {PTA0, PWM_6, 3}, // PTA0 , TPM0 CH5 - {PTA3, PWM_1, 3}, // PTA3 , TPM0 CH0 - {PTA4, PWM_2 , 3}, // PTA4 , TPM0 CH1 - {PTA5, PWM_3 , 3}, // PTA5 , TPM0 CH2 - {PTA10, PWM_9, 3}, // PTA10, TPM2 CH0 - {PTA11, PWM_10, 3}, // PTA11, TPM2 CH1 - {PTA12, PWM_7 , 3}, // PTA12, TPM1 CH0 - {PTA13, PWM_8 , 3}, // PTA13, TPM1 CH1 - - {PTB0, PWM_7, 3}, // PTB0 , TPM1 CH0 - {PTB1, PWM_8, 3}, // PTB1 , TPM1 CH1 - {PTB18, PWM_9, 3}, // PTB18, TPM2 CH0 - {PTB19, PWM_10, 3}, // PTB18, TPM2 CH1 - - {PTC1, PWM_1, 4}, // PTC1 , TPM0 CH0 - {PTC2, PWM_2, 4}, // PTC2 , TPM0 CH1 - {PTC3, PWM_3, 4}, // PTC3 , TPM0 CH2 - {PTC4, PWM_4, 4}, // PTC4 , TPM0 CH3 - {PTC5, PWM_3, 7}, // PTC4 , TPM0 CH2 - - {PTD4, PWM_5 , 4}, // PTD4 , TPM0 CH4 - {PTD5, PWM_6 , 4}, // PTD5 , TPM0 CH5 - - {NC , NC , 0} -}; diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PinNames.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PinNames.h deleted file mode 100644 index 62a8495befe..00000000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PinNames.h +++ /dev/null @@ -1,147 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define GPIO_PORT_SHIFT 12 - -typedef enum { - PTA0 = (0 << GPIO_PORT_SHIFT | 0), - PTA1 = (0 << GPIO_PORT_SHIFT | 1), - PTA2 = (0 << GPIO_PORT_SHIFT | 2), - PTA3 = (0 << GPIO_PORT_SHIFT | 3), - PTA4 = (0 << GPIO_PORT_SHIFT | 4), - PTA5 = (0 << GPIO_PORT_SHIFT | 5), - PTA10 = (0 << GPIO_PORT_SHIFT | 10), - PTA11 = (0 << GPIO_PORT_SHIFT | 11), - PTA12 = (0 << GPIO_PORT_SHIFT | 12), - PTA13 = (0 << GPIO_PORT_SHIFT | 13), - PTA14 = (0 << GPIO_PORT_SHIFT | 14), - PTA15 = (0 << GPIO_PORT_SHIFT | 15), - PTA16 = (0 << GPIO_PORT_SHIFT | 16), - PTA17 = (0 << GPIO_PORT_SHIFT | 17), - PTA18 = (0 << GPIO_PORT_SHIFT | 18), - PTA19 = (0 << GPIO_PORT_SHIFT | 19), - - PTB0 = (1 << GPIO_PORT_SHIFT | 0), - PTB1 = (1 << GPIO_PORT_SHIFT | 1), - PTB2 = (1 << GPIO_PORT_SHIFT | 2), - PTB3 = (1 << GPIO_PORT_SHIFT | 3), - PTB9 = (1 << GPIO_PORT_SHIFT | 9), - PTB10 = (1 << GPIO_PORT_SHIFT | 10), - PTB11 = (1 << GPIO_PORT_SHIFT | 11), - PTB16 = (1 << GPIO_PORT_SHIFT | 16), - PTB17 = (1 << GPIO_PORT_SHIFT | 17), - PTB18 = (1 << GPIO_PORT_SHIFT | 18), - PTB19 = (1 << GPIO_PORT_SHIFT | 19), - PTB20 = (1 << GPIO_PORT_SHIFT | 20), - PTB21 = (1 << GPIO_PORT_SHIFT | 21), - PTB22 = (1 << GPIO_PORT_SHIFT | 22), - PTB23 = (1 << GPIO_PORT_SHIFT | 23), - PTC0 = (2 << GPIO_PORT_SHIFT | 0), - PTC1 = (2 << GPIO_PORT_SHIFT | 1), - PTC2 = (2 << GPIO_PORT_SHIFT | 2), - PTC3 = (2 << GPIO_PORT_SHIFT | 3), - PTC4 = (2 << GPIO_PORT_SHIFT | 4), - PTC5 = (2 << GPIO_PORT_SHIFT | 5), - PTC6 = (2 << GPIO_PORT_SHIFT | 6), - PTC7 = (2 << GPIO_PORT_SHIFT | 7), - PTC8 = (2 << GPIO_PORT_SHIFT | 8), - PTC9 = (2 << GPIO_PORT_SHIFT | 9), - PTC10 = (2 << GPIO_PORT_SHIFT | 10), - PTC11 = (2 << GPIO_PORT_SHIFT | 11), - PTC12 = (2 << GPIO_PORT_SHIFT | 12), - PTC13 = (2 << GPIO_PORT_SHIFT | 13), - PTC14 = (2 << GPIO_PORT_SHIFT | 14), - PTC15 = (2 << GPIO_PORT_SHIFT | 15), - PTC17 = (2 << GPIO_PORT_SHIFT | 17), - - PTD0 = (3 << GPIO_PORT_SHIFT | 0), - PTD1 = (3 << GPIO_PORT_SHIFT | 1), - PTD2 = (3 << GPIO_PORT_SHIFT | 2), - PTD3 = (3 << GPIO_PORT_SHIFT | 3), - PTD4 = (3 << GPIO_PORT_SHIFT | 4), - PTD5 = (3 << GPIO_PORT_SHIFT | 5), - PTD6 = (3 << GPIO_PORT_SHIFT | 6), - PTD7 = (3 << GPIO_PORT_SHIFT | 7), - PTD8 = (3 << GPIO_PORT_SHIFT | 8), - PTD9 = (3 << GPIO_PORT_SHIFT | 9), - - PTE0 = (4 << GPIO_PORT_SHIFT | 0), - PTE1 = (4 << GPIO_PORT_SHIFT | 1), - PTE2 = (4 << GPIO_PORT_SHIFT | 2), - PTE3 = (4 << GPIO_PORT_SHIFT | 3), - PTE4 = (4 << GPIO_PORT_SHIFT | 4), - PTE5 = (4 << GPIO_PORT_SHIFT | 5), - PTE6 = (4 << GPIO_PORT_SHIFT | 6), - PTE7 = (4 << GPIO_PORT_SHIFT | 7), - PTE8 = (4 << GPIO_PORT_SHIFT | 9), - PTE9 = (4 << GPIO_PORT_SHIFT | 9), - PTE10 = (4 << GPIO_PORT_SHIFT | 10), - PTE11 = (4 << GPIO_PORT_SHIFT | 11), - - LED_RED = PTE1, - - // mbed original LED naming - LED1 = LED_RED, - LED2 = LED_RED, - LED3 = LED_RED, - LED4 = LED_RED, - - //Push buttons - SW0 = PTE2, - - USBRX = PTA1, - USBTX = PTA2, - - UART_RTS = PTC1, - UART_CTS = PTC2, - UART_RX = PTC3, - UART_TX = PTC4, - - I2C_SCL = PTC10, - I2C_SDA = PTC11, - - DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ - - // Not connected - NC = (int) 0xFFFFFFFF -} PinName; - - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 2, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/device.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/device.h deleted file mode 100644 index 29a4e7a0b18..00000000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/device.h +++ /dev/null @@ -1,39 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 24 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/fsl_clock_config.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/fsl_clock_config.c deleted file mode 100755 index d89cf89c389..00000000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/fsl_clock_config.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * How to setup clock using clock driver functions: - * - * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock - * and flash clock are in allowed range during clock mode switch. - * - * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. - * - * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and - * internal reference clock(MCGIRCLK). Follow the steps to setup: - * - * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. - * - * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured - * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig - * explicitly to setup MCGIRCLK. - * - * 3). Don't need to configure FLL explicitly, because if target mode is FLL - * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, - * if the target mode is not FLL mode, the FLL is disabled. - * - * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been - * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could - * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. - * - * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. - */ - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Clocks v3.0 -processor: MKL82Z128xxx7 -package_id: MKL82Z128VLL7 -mcu_data: ksdk2_0 -processor_version: 2.0.0 - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -#include "fsl_clock_config.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define MCG_IRCLK_DISABLE 0U /*!< MCGIRCLK disabled */ -#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */ -#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */ -#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */ -#define SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK 1U /*!< LPUART clock select: PLLFLLSEL output clock */ -#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */ -#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; - -/******************************************************************************* - * Code - ******************************************************************************/ -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_CONFIG_SetFllExtRefDiv - * Description : Configure FLL external reference divider (FRDIV). - * Param frdiv : The value to set FRDIV. - * - *END**************************************************************************/ -static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv) -{ - MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); -} - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ - BOARD_BootClockRUN(); -} - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockRUN -called_from_default_init: true -outputs: -- {id: Bus_clock.outFreq, value: 16 MHz} -- {id: Core_clock.outFreq, value: 48 MHz} -- {id: Fast_bus_clock.outFreq, value: 48 MHz} -- {id: Flash_clock.outFreq, value: 16 MHz} -- {id: IRC48MCLK.outFreq, value: 48 MHz} -- {id: LPO_clock.outFreq, value: 1 kHz} -- {id: LPUARTCLK.outFreq, value: 48 MHz} -- {id: MCGPLLCLK.outFreq, value: 96 MHz} -- {id: MCGPLLCLK2X.outFreq, value: 192 MHz} -- {id: PLLFLLCLK.outFreq, value: 96 MHz} -- {id: System_clock.outFreq, value: 48 MHz} -settings: -- {id: MCGMode, value: PEE} -- {id: LPUARTClkConfig, value: 'yes'} -- {id: MCG.IREFS.sel, value: MCG.FRDIV} -- {id: MCG.OSCSEL.sel, value: SIM.IRC48MCLK} -- {id: MCG.OSCSEL_PLL.sel, value: SIM.IRC48MCLK} -- {id: MCG.PLLS.sel, value: MCG.PLL_DIV2} -- {id: MCG.PRDIV.scale, value: '4'} -- {id: RTC_CR_OSCE_CFG, value: Enabled} -- {id: SIM.FLEXIOSRCSEL.sel, value: SIM.PLLFLLDIV} -- {id: SIM.LPUARTSRCSEL.sel, value: SIM.PLLFLLDIV} -- {id: SIM.OUTDIV1.scale, value: '2'} -- {id: SIM.OUTDIV2.scale, value: '6'} -- {id: SIM.OUTDIV4.scale, value: '6'} -- {id: SIM.OUTDIV5.scale, value: '2'} -- {id: SIM.PLLFLLDIV.scale, value: '2'} -- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK} -sources: -- {id: IRC48M.IRC48M.outFreq, value: 48 MHz} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -const mcg_config_t mcgConfig_BOARD_BootClockRUN = - { - .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */ - .irclkEnableMode = MCG_IRCLK_DISABLE, /* MCGIRCLK disabled */ - .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */ - .fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */ - .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */ - .drs = kMCG_DrsLow, /* Low frequency range */ - .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ - .oscsel = kMCG_OscselIrc, /* Selects 48 MHz IRC Oscillator */ - .pll0Config = - { - .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */ - .prdiv = 0x3U, /* PLL Reference divider: divided by 4 */ - .vdiv = 0x0U, /* VCO divider: multiplied by 16 */ - }, - }; -const sim_clock_config_t simConfig_BOARD_BootClockRUN = - { - .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */ - .pllFllDiv = 1, /* PLLFLLSEL clock divider divisor: divided by 2 */ - .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */ - .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */ - .clkdiv1 = 0x15051000U, /* SIM_CLKDIV1 - OUTDIV1: /2, OUTDIV2: /6, OUTDIV4: /6, OUTDIV5: /2 */ - }; -const osc_config_t oscConfig_BOARD_BootClockRUN = - { - .freq = 0U, /* Oscillator frequency: 0Hz */ - .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ - .workMode = kOSC_ModeExt, /* Use external clock */ - .oscerConfig = - { - .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */ - .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */ - } - }; - -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /* Set the system clock dividers in SIM to safe value. */ - CLOCK_SetSimSafeDivs(); - /* Configure FLL external reference divider (FRDIV). */ - CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv); - /* Set MCG to PEE mode. */ - CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, - kMCG_PllClkSelPll0, - &mcgConfig_BOARD_BootClockRUN.pll0Config); - /* Set the clock configuration in SIM module. */ - CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; - /* Set LPUART clock source. */ - CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK); -} - diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/fsl_clock_config.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/fsl_clock_config.h deleted file mode 100755 index 85363ad469a..00000000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/fsl_clock_config.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ - -/*! @brief MCG set for BOARD_BootClockRUN configuration. - */ -extern const mcg_config_t mcgConfig_BOARD_BootClockRUN; -/*! @brief SIM module set for BOARD_BootClockRUN configuration. - */ -extern const sim_clock_config_t simConfig_BOARD_BootClockRUN; -/*! @brief OSC set for BOARD_BootClockRUN configuration. - */ -extern const osc_config_t oscConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ - diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/mbed_overrides.c deleted file mode 100644 index 3c72d889eaf..00000000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/mbed_overrides.c +++ /dev/null @@ -1,84 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "fsl_smc.h" -#include "fsl_rcm.h" -#include "fsl_pmc.h" -#include "fsl_rtc.h" -#include "fsl_clock_config.h" - -//!< this contains the wakeup source -rcm_reset_source_t kinetisResetSource; - -// called before main -void mbed_sdk_init() -{ - rtc_config_t rtc_basic_config; - uint32_t u32cTPR_counter = 0; - - SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); - - // check the power mode source - kinetisResetSource = (rcm_reset_source_t) (RCM_GetPreviousResetSources(RCM)); - // if waking up from VLLS, do some cleanup - if (kinetisResetSource & kRCM_SourceWakeup) { - PMC_ClearPeriphIOIsolationFlag(PMC); - NVIC_ClearPendingIRQ(LLWU_IRQn); - } - - BOARD_BootClockRUN(); - - CLOCK_EnableClock(kCLOCK_Rtc0); - - /* Check if the Rtc oscillator is enabled */ - if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { - /*Init the RTC with default configuration*/ - RTC_GetDefaultConfig(&rtc_basic_config); - - /* Setup the 32K RTC OSC */ - RTC_Init(RTC, &rtc_basic_config); - - /* Enable the RTC 32KHz oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; - - /* Start the RTC time counter */ - RTC_StartTimer(RTC); - - /* Verify TPR register reaches 4096 counts */ - while (u32cTPR_counter < 4096) { - u32cTPR_counter = RTC->TPR; - } - /* 32kHz Oscillator is ready. */ - RTC_Deinit(RTC); - } - - CLOCK_DisableClock(kCLOCK_Rtc0); -} - -// Change the NMI pin to an input. This allows NMI pin to -// be used as a low power mode wakeup. The application will -// need to change the pin back to NMI_b or wakeup only occurs once! -void NMI_Handler(void) -{ - gpio_t gpio; - gpio_init_in(&gpio, PTA4); -} - -// Set the UART clock source -void serial_clock_init(void) -{ - CLOCK_SetLpuartClock(2U); -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_MTB_LAIRD_BL600/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_MTB_LAIRD_BL600/PinNames.h deleted file mode 100644 index 9faa5133716..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_MTB_LAIRD_BL600/PinNames.h +++ /dev/null @@ -1,255 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -typedef enum { - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, - p31 = 31, - - - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_4 = p4, - P0_5 = p5, - P0_6 = p6, - P0_7 = p7, - - P0_8 = p8, - P0_9 = p9, - P0_10 = p10, - P0_11 = p11, - P0_12 = p12, - P0_13 = p13, - P0_14 = p14, - P0_15 = p15, - - P0_16 = p16, - P0_17 = p17, - P0_18 = p18, - P0_19 = p19, - P0_20 = p20, - P0_21 = p21, - P0_22 = p22, - P0_23 = p23, - - P0_24 = p24, - P0_25 = p25, - P0_26 = p26, - P0_27 = p27, - P0_28 = p28, - P0_29 = p29, - P0_30 = p30, - - // Module pins. Refer datasheet for pin numbers. - SIO_1 = P0_1, - SIO_2 = P0_2, - SIO_3 = P0_3, - SIO_4 = P0_4, - SIO_5 = P0_5, - SIO_6 = P0_6, - SIO_7 = P0_7, - SIO_8 = P0_8, - SIO_9 = P0_9, - SIO_10 = P0_10, - SIO_11 = P0_11, - SIO_12 = P0_12, - SIO_13 = P0_13, - SIO_14 = P0_14, - SIO_15 = P0_15, - SIO_16 = P0_16, - SIO_17 = P0_17, - SIO_18 = P0_18, - SIO_19 = P0_19, - SIO_20 = P0_20, - SIO_21 = P0_21, - SIO_22 = P0_22, - SIO_23 = P0_23, - SIO_24 = P0_24, - SIO_25 = P0_25, - SIO_26 = P0_26, - SIO_27 = P0_27, - SIO_28 = P0_28, - SIO_29 = P0_29, - SIO_30 = P0_30, - SIO_0 = P0_0, - - // Not connected - NC = (int)0xFFFFFFFF, - - //Mbed MTB pin defines. - P_1 = NC, - P_2 = SIO_1, - P_3 = NC, - P_4 = SIO_2, - P_5 = SIO_3, - P_6 = SIO_4, - P_7 = SIO_5, - P_8 = SIO_6, - P_9 = SIO_7, - P_10 = NC, - P_11 = NC, - P_12 = SIO_8, - P_13 = SIO_9, - P_14 = SIO_10, - P_15 = SIO_11, - P_16 = SIO_12, - P_17 = NC, - P_18 = SIO_13, - P_19 = SIO_14, - P_20 = SIO_15, - P_21 = SIO_16, - P_22 = NC, - P_23 = NC, - P_24 = SIO_17, - P_25 = SIO_18, - P_26 = SIO_19, - P_27 = SIO_20, - P_28 = NC, - P_29 = NC, - P_30 = NC, - P_31 = NC, - P_32 = SIO_21, - P_33 = SIO_22, - P_34 = SIO_23, - P_35 = SIO_24, - P_36 = SIO_25, - P_37 = NC, - P_38 = SIO_26, - P_39 = SIO_27, - P_40 = SIO_28, - P_41 = SIO_29, - P_42 = SIO_30, - P_43 = NC, - P_44 = SIO_0, - - //MTB aliases - GP0 = SIO_30, - GP1 = SIO_0, - AIN0 = SIO_1, - AIN1 = SIO_2, - AIN2 = SIO_3, - GP2 = SIO_7, - GP3 = SIO_13, - UART1_TX = SIO_17, - UART1_RX = SIO_18, - UART2_TX = SIO_25, - UART2_RX = SIO_26, - GP4 = SIO_14, - GP5 = SIO_15, //A0 for LCD on MTB - GP6 = SIO_16, //RESET for LCD on MTB - GP7 = SIO_19, - GP8 = SIO_20, - - //LEDs - LED1 = SIO_4, - LED2 = SIO_5, - LED3 = SIO_6, - - //Standardized button name - BUTTON1 = SIO_30, - - //Nordic SDK pin names - RX_PIN_NUMBER = p22, - TX_PIN_NUMBER = p21, - CTS_PIN_NUMBER = p24, - RTS_PIN_NUMBER = p23, - - // mBed interface Pins - USBTX = MBED_CONF_TARGET_USB_TX, - USBRX = MBED_CONF_TARGET_USB_RX, - - SPI_MOSI0 = SIO_10, - SPI_MISO0 = SIO_11, - SPI_SS0 = SIO_19, //CS for LCD on MTB - SPI_SCK0 = SIO_12, - - SPI_MOSI1 = SIO_27, - SPI_MISO1 = SIO_28, - SPI_SS1 = SIO_7, //CS for SD card on MTB - SPI_SCK1 = SIO_29, - - //Default SPI - SPIS_PSELMOSI = SPI_MOSI0, - SPIS_PSELMISO = SPI_MISO0, - SPIS_PSELSS = SPI_SS0, - SPIS_PSELSCK = SPI_SCK0, - - SPI_MOSI = SPI_MOSI0, - SPI_MISO = SPI_MISO0, - SPI_SS = SPI_SS0, - SPI_SCK = SPI_SCK0, - - I2C_SDA0 = SIO_8, - I2C_SCL0 = SIO_9, - -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_MTB_LAIRD_BL600/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_MTB_LAIRD_BL600/device.h deleted file mode 100644 index 69fb27de5ca..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_MTB_LAIRD_BL600/device.h +++ /dev/null @@ -1,23 +0,0 @@ -// The 'provides' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'provides' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_OSHCHIP/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_OSHCHIP/PinNames.h deleted file mode 100644 index 7d67c76c52f..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_OSHCHIP/PinNames.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -typedef enum { - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, - - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_4 = p4, - P0_5 = p5, - P0_6 = p6, - P0_7 = p7, - - P0_8 = p8, - P0_9 = p9, - P0_10 = p10, - P0_11 = p11, - P0_12 = p12, - P0_13 = p13, - P0_14 = p14, - P0_15 = p15, - - P0_16 = p16, - P0_17 = p17, - P0_18 = p18, - P0_19 = p19, - P0_20 = p20, - P0_21 = p21, - P0_22 = p22, - P0_23 = p23, - - P0_24 = p24, - P0_25 = p25, - P0_26 = p26, - P0_27 = p27, - P0_28 = p28, - P0_29 = p29, - P0_30 = p30, - /* - ┏━━━━━━━━━━┓ -UART┬── TX D0 ╶┨ 1 ╒╕ 16 ┠╴ VCC - └── RX D1 ╶┨ 2 ╘╛ 15 ┠╴ D8 SCL ─┬I²C - D2 ╶┨ 3 14 ┠╴ D7 SDA ─┘ - SPI┬ MOSI D3 ╶┨ 4 13 ┠╴ A0 - │ MISO D4 ╶┨ 5 ┌──┐12 ┠╴ A1 - │ SEL D5 ╶┨ 6 └──┘11 ┠╴ D9 AREF - └─ CLK D4 ╶┨ 7 10 ┠╴ A2 - GND ╶┨ 8 :: 9 ┠╴ A3 - ┗━━━━━━━━━━┛ - */ - - OSHCHIP_PIN_1 = p20, - OSHCHIP_PIN_2 = p18, - OSHCHIP_PIN_3 = p16, - OSHCHIP_PIN_4 = p15, - OSHCHIP_PIN_5 = p12, - OSHCHIP_PIN_6 = p11, - OSHCHIP_PIN_7 = p9, - OSHCHIP_PIN_9 = p1, - OSHCHIP_PIN_10 = p2, - OSHCHIP_PIN_11 = p0, - OSHCHIP_PIN_12 = p27, - OSHCHIP_PIN_13 = p26, - OSHCHIP_PIN_14 = p24, - OSHCHIP_PIN_15 = p21, - - LED1 = p8, - LED2 = p5, - LED3 = p3, - - LED_RED = LED1, - LED_GREEN = LED2, - LED_BLUE = LED3, - - RX_PIN_NUMBER = OSHCHIP_PIN_2, - TX_PIN_NUMBER = OSHCHIP_PIN_1, - CTS_PIN_NUMBER = (int)0xFFFFFFFF, //no connection - RTS_PIN_NUMBER = (int)0xFFFFFFFF, //no connection - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - - SPI_PSELMOSI0 = OSHCHIP_PIN_4, - SPI_PSELMISO0 = OSHCHIP_PIN_5, - SPI_PSELSS0 = OSHCHIP_PIN_6, - SPI_PSELSCK0 = OSHCHIP_PIN_7, - - SPI_PSELMOSI1 = OSHCHIP_PIN_4, - SPI_PSELMISO1 = OSHCHIP_PIN_5, - SPI_PSELSS1 = OSHCHIP_PIN_6, - SPI_PSELSCK1 = OSHCHIP_PIN_7, - - SPIS_PSELMOSI = OSHCHIP_PIN_4, - SPIS_PSELMISO = OSHCHIP_PIN_5, - SPIS_PSELSS = OSHCHIP_PIN_6, - SPIS_PSELSCK = OSHCHIP_PIN_7, - - I2C_SDA0 = OSHCHIP_PIN_14, - I2C_SCL0 = OSHCHIP_PIN_15, - - D0 = OSHCHIP_PIN_1, - D1 = OSHCHIP_PIN_2, - D2 = OSHCHIP_PIN_3, - D3 = OSHCHIP_PIN_4, - D4 = OSHCHIP_PIN_5, - D5 = OSHCHIP_PIN_6, - D6 = OSHCHIP_PIN_7, - D7 = OSHCHIP_PIN_15, - D8 = OSHCHIP_PIN_14, - D9 = OSHCHIP_PIN_11, - - A0 = OSHCHIP_PIN_13, - A1 = OSHCHIP_PIN_12, - A2 = OSHCHIP_PIN_10, - A3 = OSHCHIP_PIN_9, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_OSHCHIP/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_OSHCHIP/device.h deleted file mode 100644 index 493844b8012..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_OSHCHIP/device.h +++ /dev/null @@ -1,23 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_ACONNO_ACN52832/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_ACONNO_ACN52832/PinNames.h deleted file mode 100644 index 5078e98ceeb..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_ACONNO_ACN52832/PinNames.h +++ /dev/null @@ -1,150 +0,0 @@ -/******************************************************************************** - * \copyright - * \copyright - * Copyright 2018-2018, ARM Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 3 - -typedef enum { - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, - p31 = 31, - - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_4 = p4, - P0_5 = p5, - P0_6 = p6, - P0_7 = p7, - - P0_8 = p8, - P0_9 = p9, - P0_10 = p10, - P0_11 = p11, - P0_12 = p12, - P0_13 = p13, - P0_14 = p14, - P0_15 = p15, - - P0_16 = p16, - P0_17 = p17, - P0_18 = p18, - P0_19 = p19, - P0_20 = p20, - P0_21 = p21, - P0_22 = p22, - P0_23 = p23, - - P0_24 = p24, - P0_25 = p25, - P0_26 = p26, - P0_27 = p27, - P0_28 = p28, - P0_29 = p29, - P0_30 = p30, - P0_31 = p31, - - LED1 = p25, - LED2 = p26, - LED3 = p27, - - AIN0 = p2, - AIN1 = p3, - AIN2 = p4, - - GP0 = p19, - GP1 = p20, - GP2 = p28, - GP3 = p29, - GP4 = p30, - GP5 = p31, // LCD-A0 - GP6 = p5, // LCD-RESET - GP7 = p6, // LCD-CS - GP8 = p7, - - RX_PIN_NUMBER = p12, - TX_PIN_NUMBER = p11, - CTS_PIN_NUMBER = p9, - RTS_PIN_NUMBER = p8, - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - STDIO_UART_TX = TX_PIN_NUMBER, - STDIO_UART_RX = RX_PIN_NUMBER, - STDIO_UART_CTS = CTS_PIN_NUMBER, - STDIO_UART_RTS = RTS_PIN_NUMBER, - - SPI_MOSI = p16, - SPI_MISO = p17, - SPI_SCK = p18, - SPI_CS = p10, - - USER_BUTTON = GP0, - - I2C_SDA = p14, - I2C_SCL = p15, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_ACONNO_ACN52832/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_ACONNO_ACN52832/device.h deleted file mode 100644 index bffb79b9b5d..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_ACONNO_ACN52832/device.h +++ /dev/null @@ -1,13 +0,0 @@ -/******************************************************************************** - * \copyright - * \copyright - * Copyright 2018-2018, ARM Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ - -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/PinNames.h deleted file mode 100644 index 42495b6928e..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/PinNames.h +++ /dev/null @@ -1,245 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -typedef enum { - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, - p31 = 31, - - - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_4 = p4, - P0_5 = p5, - P0_6 = p6, - P0_7 = p7, - - P0_8 = p8, - P0_9 = p9, - P0_10 = p10, - P0_11 = p11, - P0_12 = p12, - P0_13 = p13, - P0_14 = p14, - P0_15 = p15, - - P0_16 = p16, - P0_17 = p17, - P0_18 = p18, - P0_19 = p19, - P0_20 = p20, - P0_21 = p21, - P0_22 = p22, - P0_23 = p23, - - P0_24 = p24, - P0_25 = p25, - P0_26 = p26, - P0_27 = p27, - P0_28 = p28, - P0_29 = p29, - P0_30 = p30, - P0_31 = p31, - - // Module pins. Refer datasheet for pin numbers. - SIO_1 = P0_1, - SIO_2 = P0_2, - SIO_3 = P0_3, - SIO_4 = P0_4, - SIO_5 = P0_5, - SIO_6 = P0_6, - SIO_7 = P0_7, - SIO_8 = P0_8, - SIO_9 = P0_9, //NFC1 - SIO_10 = P0_10, //NFC2 - SIO_11 = P0_11, - SIO_12 = P0_12, - SIO_13 = P0_13, - SIO_14 = P0_14, - SIO_15 = P0_15, - SIO_16 = P0_16, - SIO_17 = P0_17, - SIO_18 = P0_18, - SIO_19 = P0_19, - SIO_20 = P0_20, - - SIO_22 = P0_22, - SIO_23 = P0_23, - SIO_24 = P0_24, - SIO_25 = P0_25, - SIO_26 = P0_26, - SIO_27 = P0_27, - SIO_28 = P0_28, - SIO_29 = P0_29, - SIO_30 = P0_30, - SIO_31 = P0_31, - SIO_0 = P0_0, - - // Not connected - NC = (int)0xFFFFFFFF, - - //Mbed MTB pin defines. - P_1 = NC, - P_2 = SIO_24, //MISO - P_3 = SIO_23, //MOSI - P_4 = SIO_22, -// P_5 = SWDIO, -// P_6 = SWDCLK, -// P_7 = NRST, - P_8 = SIO_20, - P_9 = SIO_18, - P_10 = SIO_16, - P_11 = SIO_14, - P_12 = SIO_12, - P_13 = SIO_11, - P_14 = SIO_10, - P_15 = SIO_9, - P_16 = NC, - P_17 = SIO_8, - P_18 = SIO_7, - P_19 = SIO_6, - P_20 = SIO_5, - P_21 = SIO_4, - P_22 = SIO_3, - P_23 = SIO_2, - P_24 = SIO_1, - P_25 = SIO_0, - P_26 = NC, - P_27 = NC, - P_28 = SIO_13, - P_29 = SIO_15, - P_30 = SIO_17, - P_31 = SIO_19, - P_32 = SIO_31, - P_33 = SIO_30, - P_34 = SIO_29, - P_35 = SIO_28, - P_36 = SIO_27, - P_37 = SIO_26, - P_38 = SIO_25, - P_39 = NC, - - //LEDs - LED1 = SIO_28, - LED2 = SIO_29, - LED3 = SIO_30, - LED_RED = LED1, - LED_GREEN = LED2, - LED_BLUE = LED3, - - GP0 = SIO_11, - //Standardized button name - BUTTON1 = GP0, - - //Nordic SDK pin names - RX_PIN_NUMBER = SIO_8, - TX_PIN_NUMBER = SIO_6, - CTS_PIN_NUMBER = SIO_7, - RTS_PIN_NUMBER = SIO_5, - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - STDIO_UART_TX = TX_PIN_NUMBER, - STDIO_UART_RX = RX_PIN_NUMBER, - STDIO_UART_CTS = CTS_PIN_NUMBER, - STDIO_UART_RTS = RTS_PIN_NUMBER, - - SPI_MOSI = SIO_23, - SPI_MISO = SIO_24, - SPI_SS0 = SIO_17, //CS for LCD on MTB - SPI_SS1 = SIO_10, //CS for SD card on MTB - SPI_SCK1 = SIO_25, - SPI_SCK2 = SIO_31, - - //Default SPI - SPI_SCK = SPI_SCK1, - SPI_CS = SPI_SS1, - - I2C_SDA = SIO_26, - I2C_SCL = SIO_27, - - //MTB aliases - GP1 = SIO_13, - AIN0 = SIO_2, - AIN1 = SIO_3, - AIN2 = SIO_4, - GP2 = SIO_10, - GP3 = SIO_9, - GP4 = SIO_22, - GP5 = SIO_19, //A0 for LCD on MTB - GP6 = SIO_18, //RESET for LCD on MTB - GP7 = SIO_17, - GP8 = SIO_15, - -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/device.h deleted file mode 100644 index 493844b8012..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/device.h +++ /dev/null @@ -1,23 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_MURATA_WSM_BL241/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_MURATA_WSM_BL241/PinNames.h deleted file mode 100644 index 1b7d86506e6..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_MURATA_WSM_BL241/PinNames.h +++ /dev/null @@ -1,198 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2018, Arm Limited and affiliates. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 3 - -typedef enum { - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, - p31 = 31, - - // Module pins. Refer datasheet for pin numbers. - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_4 = p4, - P0_5 = p5, - P0_6 = p6, - P0_7 = p7, - - P0_8 = p8, - P0_9 = p9, - P0_10 = p10, - P0_11 = p11, - P0_12 = p12, - P0_13 = p13, - P0_14 = p14, - P0_15 = p15, - - P0_16 = p16, - P0_17 = p17, - P0_18 = p18, - P0_19 = p19, - P0_20 = p20, - P0_21 = p21, - P0_22 = p22, - P0_23 = p23, - - P0_24 = p24, - P0_25 = p25, - P0_26 = p26, - P0_27 = p27, - P0_28 = p28, - P0_29 = p29, - P0_30 = p30, - P0_31 = p31, - - // Not connected - NC = (int)0xFFFFFFFF, - - //Mbed MTB pin defines. - P_1 = P0_9, - P_2 = P0_6, - P_3 = P0_0, - P_4 = P0_1, - P_5 = NC, - P_6 = NC, - P_7 = NC, - P_8 = NC, - P_9 = P0_2, - P_10 = P0_5, - P_11 = P0_3, - P_12 = P0_4, - P_13 = P0_29, - P_14 = P0_7, - P_15 = P0_8, - - P_17 = P0_21, - - P_19 = NC, - P_20 = NC, - P_21 = NC, - P_22 = P0_18, - P_23 = P0_16, - P_24 = P0_15, - P_25 = P0_14, - P_26 = P0_10, - P_27 = P0_20, - P_28 = P0_17, - P_29 = P0_13, - P_30 = NC, - P_31 = NC, - P_32 = NC, - P_33 = NC, - P_34 = NC, - P_35 = NC, - P_36 = NC, - P_37 = NC, - - //LEDs - LED1 = P_22, - LED_RED = LED1, - - LED2 = NC, - LED3 = NC, - - GP0 = P_23, - //Standardized button name - BUTTON1 = GP0, - - //Nordic SDK pin names - RX_PIN_NUMBER = P_15, - TX_PIN_NUMBER = P_2, - - CTS_PIN_NUMBER = P_14, - RTS_PIN_NUMBER = P_10, - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - STDIO_UART_TX = TX_PIN_NUMBER, - STDIO_UART_RX = RX_PIN_NUMBER, - STDIO_UART_CTS = CTS_PIN_NUMBER, - STDIO_UART_RTS = RTS_PIN_NUMBER, - - SPI_MOSI = P_9, - SPI_MISO = P_11, - SPI_NCS = P_22, //CS for SPIFlash on MTB - SPI_SCK = P_12, - - I2C_SDA = P_25, - I2C_SCL = P_24, - - //MTB aliases - AIN0 = P_13, - -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 2, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_MURATA_WSM_BL241/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_MURATA_WSM_BL241/device.h deleted file mode 100644 index 099ae5ce7de..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_MURATA_WSM_BL241/device.h +++ /dev/null @@ -1,24 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2018, Arm Limited and affiliates. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_UBLOX_NINA_B1/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_UBLOX_NINA_B1/PinNames.h deleted file mode 100644 index ee77cb57c54..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_UBLOX_NINA_B1/PinNames.h +++ /dev/null @@ -1,157 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2016 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -typedef enum { - // nRF52 pin names - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, - p31 = 31, - NC = (int)0xFFFFFFFF, // Not connected - - //NINA-B112 module pin names - P_1 = p8, - P_2 = p11, - P_3 = p12, - P_4 = p13, - P_5 = p14, - P_6 = NC, - P_7 = p16, - P_8 = p18, - P_9 = NC, - P_10 = NC, - P_11 = NC, - P_12 = NC, - P_13 = NC, - P_14 = NC, - P_15 = NC, - P_16 = p28, - P_17 = p29, - P_18 = p30, - P_19 = p21, - P_20 = p31, - P_21 = p7, - P_22 = p6, - P_23 = p5, - P_24 = p2, - P_25 = p3, - P_26 = NC, - P_27 = p4, - P_28 = p9, - P_29 = p10, - P_30 = NC, - - // MTB aliases - GPIO18 = p30, - - LED1 = p4, // Red LED - LED2 = p10, // Green LED - GPIO27 = LED1, -// GPIO29 = LED2, - - GPIO7 = p16, //A0 for LCD - GPIO16 = p28, //RESET for LCD - - SW1 = p29, - GPIO17 = SW1, - //Standardized button names - BUTTON1 = SW1, - - // Nordic SDK pin names - RX_PIN_NUMBER = p5, - TX_PIN_NUMBER = p6, - CTS_PIN_NUMBER = p7, - RTS_PIN_NUMBER = p31, - STDIO_UART_TX = TX_PIN_NUMBER, - STDIO_UART_RX = RX_PIN_NUMBER, - STDIO_UART_CTS = CTS_PIN_NUMBER, - STDIO_UART_RTS = RTS_PIN_NUMBER, - - I2C_SDA = p2, - I2C_SCL = p3, - - SPI0_MOSI = p13, - SPI0_MISO = p12, - SPI0_SCK = p14, - SPI0_CS = p11, - SPI1_CS = p8, - - SPI_MOSI = SPI0_MOSI, - SPI_MISO = SPI0_MISO, - SPI_SCK = SPI0_SCK, - SPI_CS = SPI0_CS, - - // DAPLink - USBRX = RX_PIN_NUMBER, - USBTX = TX_PIN_NUMBER, - NTRST = p21, - SWO = p18, - -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_UBLOX_NINA_B1/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_UBLOX_NINA_B1/device.h deleted file mode 100644 index 99a6e40f2a0..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_UBLOX_NINA_B1/device.h +++ /dev/null @@ -1,21 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/ONBOARD_RM1000_AT.cpp b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/ONBOARD_RM1000_AT.cpp deleted file mode 100644 index 34f40c2daf9..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/ONBOARD_RM1000_AT.cpp +++ /dev/null @@ -1,154 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if MBED_CONF_NSAPI_PRESENT - -#include "ONBOARD_RM1000_AT.h" -#include "drivers/BufferedSerial.h" - -#include "mbed-trace/mbed_trace.h" -#ifndef TRACE_GROUP -#define TRACE_GROUP "RIOTMICRO" -#endif // TRACE_GROUP - -#include "gpio_api.h" -#include "PinNames.h" -#include "hal/serial_api.h" -#include "platform/mbed_thread.h" - -using namespace mbed; - -ONBOARD_RM1000_AT::ONBOARD_RM1000_AT(FileHandle *fh) : RM1000_AT(fh) -{ -} - -nsapi_error_t ONBOARD_RM1000_AT::hard_power_on() -{ - tr_debug("Calling ONBOARD_RM1000_AT::hard_power_on"); - - return NSAPI_ERROR_OK; -} - -nsapi_error_t ONBOARD_RM1000_AT::hard_power_off() -{ - tr_debug("Calling ONBOARD_RM1000_AT::hard_power_off"); - - return NSAPI_ERROR_OK; -} - -nsapi_error_t ONBOARD_RM1000_AT::soft_power_on() -{ - tr_debug("Calling ONBOARD_RM1000_AT::soft_power_on"); - - onboard_modem_init(); - return NSAPI_ERROR_OK; -} - -nsapi_error_t ONBOARD_RM1000_AT::soft_power_off() -{ - tr_debug("Calling ONBOARD_RM1000_AT::soft_power_off"); - - onboard_modem_deinit(); - return NSAPI_ERROR_OK; -} - -void ONBOARD_RM1000_AT::onboard_modem_init() -{ - char promptEnd; - - tr_debug("onboard_modem_init"); - - gpio_t gpio; - - gpio_init_out_ex(&gpio, MDMCHEN, 0); - gpio_init_out_ex(&gpio, MDMREMAP, 0); - // Take us out of reset - gpio_init_out_ex(&gpio, MDMRST, 0); - thread_sleep_for(100); - gpio_write(&gpio, 1); - - /* Initialize UART1 pins to allow collecting logs from a PC */ - gpio_init_in_ex(&gpio, MDM_UART1_TXD, PullNone); - gpio_init_in_ex(&gpio, MDM_UART1_RXD, PullNone); - - serial_t bootrom_uart; - serial_init(&bootrom_uart, MDM_UART0_TXD, MDM_UART0_RXD); - serial_baud(&bootrom_uart, 115200); - - tr_debug("%s: MODEM RESET", __func__); - - serial_getc(&bootrom_uart); - tr_debug("%s: MODEM first activity after reset", __func__); - /* Wait for some dots */ - for (int i = 0; i < 3; i++) { - do { - promptEnd = serial_getc(&bootrom_uart); - } while ('.' != promptEnd); - } - serial_putc(&bootrom_uart, ' '); - /* Wait for bootrom prompt */ - for (int i = 0; i < 2; i++) { - do { - promptEnd = serial_getc(&bootrom_uart); - } while ('>' != promptEnd); - } - serial_putc(&bootrom_uart, '6'); - serial_free(&bootrom_uart); - - /* Wait for stack prompt */ - tr_debug("%s: Wait for stack prompt", __func__); - thread_sleep_for(100); - serial_t cli_uart; - serial_init(&cli_uart, MDM_UART3_TXD, MDM_UART3_RXD); - serial_baud(&cli_uart, 230400); /* TODO make baud rate configurable */ - - do { - promptEnd = serial_getc(&cli_uart); - } while ('>' != promptEnd); - - serial_free(&cli_uart); - - tr_debug("%s: MODEM CLI prompt reached", __func__); - - tr_debug("Reset RM1000 completed"); -} - -void ONBOARD_RM1000_AT::onboard_modem_deinit() -{ - tr_debug("onboard_modem_deinit"); - - gpio_t gpio; - - // Back into reset - gpio_init_out_ex(&gpio, MDMRST, 0); -} - -CellularDevice *CellularDevice::get_target_default_instance() -{ - tr_debug("Calling CellularDevice::get_target_default_instance from ONBOARD_RM1000_AT"); - - static BufferedSerial serial(MDM_UART3_TXD, MDM_UART3_RXD, 230400); -#if DEVICE_SERIAL_FC - if (MDM_UART3_RTS != NC && MDM_UART3_CTS != NC) { - tr_debug("Modem flow control: RTS %d CTS %d", MDM_UART3_RTS, MDM_UART3_CTS); - serial.set_flow_control(SerialBase::RTSCTS, MDM_UART3_RTS, MDM_UART3_CTS); - } -#endif - static ONBOARD_RM1000_AT device(&serial); - return &device; -} - -#endif // MBED_CONF_NSAPI_PRESENT diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/ONBOARD_RM1000_AT.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/ONBOARD_RM1000_AT.h deleted file mode 100644 index 3fe90339d1a..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/ONBOARD_RM1000_AT.h +++ /dev/null @@ -1,43 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ONBOARD_RM1000_AT_ -#define ONBOARD_RM1000_AT_ - -#include "RM1000_AT.h" - -namespace mbed -{ - -class ONBOARD_RM1000_AT : public RM1000_AT -{ -public: - ONBOARD_RM1000_AT(FileHandle *fh); - - virtual nsapi_error_t hard_power_on(); - virtual nsapi_error_t hard_power_off(); - virtual nsapi_error_t soft_power_on(); - virtual nsapi_error_t soft_power_off(); - -private: - void onboard_modem_init(); - - void onboard_modem_deinit(); -}; - -} // namespace mbed - -#endif // ONBOARD_RM1000_AT_ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/TARGET_RM6100/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/TARGET_RM6100/PinNames.h deleted file mode 100644 index d0d1c67e4ce..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/TARGET_RM6100/PinNames.h +++ /dev/null @@ -1,138 +0,0 @@ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 3 - -typedef enum { - // nRF52 pin names - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, - p31 = 31, - NC = (int)0xFFFFFFFF, // Not connected - - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_4 = p4, - P0_5 = p5, - P0_6 = p6, - P0_7 = p7, - - P0_8 = p8, - P0_9 = p9, - P0_10 = p10, - P0_11 = p11, - P0_12 = p12, - P0_13 = p13, - P0_14 = p14, - P0_15 = p15, - - P0_16 = p16, - P0_17 = p17, - P0_18 = p18, - P0_19 = p19, - P0_20 = p20, - P0_21 = p21, - P0_22 = p22, - P0_23 = p23, - - P0_24 = p24, - P0_25 = p25, - P0_26 = p26, - P0_27 = p27, - P0_28 = p28, - P0_29 = p29, - P0_30 = p30, - P0_31 = p31, - - MDMCHEN = p13, - MDMREMAP = p14, - MDMRST = p25, - - MDM_UART0_TXD = p15, - MDM_UART0_RXD = p16, - MDM_UART1_TXD = p17, - MDM_UART1_RXD = p18, - - MDM_UART3_TXD = p19, - MDM_UART3_RXD = p20, - MDM_UART3_RTS = NC, - MDM_UART3_CTS = NC, - - LED1 = P0_10, - LED2 = P0_22, - - RX_PIN_NUMBER = NC, - TX_PIN_NUMBER = NC, - CTS_PIN_NUMBER = NC, - RTS_PIN_NUMBER = NC, - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - STDIO_UART_TX = TX_PIN_NUMBER, - STDIO_UART_RX = RX_PIN_NUMBER, - STDIO_UART_CTS = CTS_PIN_NUMBER, - STDIO_UART_RTS = RTS_PIN_NUMBER, - - A0 = NC, - A1 = p4, - A2 = p28, - A3 = p29, - A4 = p30, - A5 = p31, -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/TARGET_RM7100/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/TARGET_RM7100/PinNames.h deleted file mode 100644 index df814ce80a2..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/TARGET_RM7100/PinNames.h +++ /dev/null @@ -1,141 +0,0 @@ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 3 - -typedef enum { - // nRF52 pin names - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, - p31 = 31, - NC = (int)0xFFFFFFFF, // Not connected - - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_4 = p4, - P0_5 = p5, - P0_6 = p6, - P0_7 = p7, - - P0_8 = p8, - P0_9 = p9, - P0_10 = p10, - P0_11 = p11, - P0_12 = p12, - P0_13 = p13, - P0_14 = p14, - P0_15 = p15, - - P0_16 = p16, - P0_17 = p17, - P0_18 = p18, - P0_19 = p19, - P0_20 = p20, - P0_21 = p21, - P0_22 = p22, - P0_23 = p23, - - P0_24 = p24, - P0_25 = p25, - P0_26 = p26, - P0_27 = p27, - P0_28 = p28, - P0_29 = p29, - P0_30 = p30, - P0_31 = p31, - - MDMCHEN = p13, - MDMREMAP = p14, - MDMRST = p25, - - MDM_UART0_TXD = p15, - MDM_UART0_RXD = p16, - MDM_UART1_TXD = p17, - MDM_UART1_RXD = p18, - - MDM_UART3_TXD = p19, - MDM_UART3_RXD = p20, - MDM_UART3_RTS = NC, - MDM_UART3_CTS = NC, - - LED1 = P0_10, - LED2 = P0_22, - - RX_PIN_NUMBER = NC, - TX_PIN_NUMBER = NC, - CTS_PIN_NUMBER = NC, - RTS_PIN_NUMBER = NC, - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - STDIO_UART_TX = TX_PIN_NUMBER, - STDIO_UART_RX = RX_PIN_NUMBER, - STDIO_UART_CTS = CTS_PIN_NUMBER, - STDIO_UART_RTS = RTS_PIN_NUMBER, - - I2C_SDA0 = p12, - I2C_SCL0 = p11, - - A0 = p2, - A1 = p28, - A2 = p4, - A3 = p29, - A4 = p30, - A5 = p31, -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} - -#endif -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/device.h deleted file mode 100644 index 493844b8012..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/device.h +++ /dev/null @@ -1,23 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_MAKERDIARY_NRF52840_MDK/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_MAKERDIARY_NRF52840_MDK/PinNames.h deleted file mode 100644 index ec67b4c50b4..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_MAKERDIARY_NRF52840_MDK/PinNames.h +++ /dev/null @@ -1,252 +0,0 @@ -/* - * Copyright (c) 2016 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "nrf_gpio.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -///> define macro producing for example Px_y = NRF_GPIO_PIN_MAP(x, y) -#define PinDef(port_num, pin_num) P##port_num##_##pin_num = NRF_GPIO_PIN_MAP(port_num, pin_num) - - -typedef enum { - PinDef(0 , 0), // P0_0 = 0... - PinDef(0 , 1), - PinDef(0 , 2), - PinDef(0 , 3), - PinDef(0 , 4), - PinDef(0 , 5), - PinDef(0 , 6), - PinDef(0 , 7), - PinDef(0 , 8), - PinDef(0 , 9), - PinDef(0 , 10), - PinDef(0 , 11), - PinDef(0 , 12), - PinDef(0 , 13), - PinDef(0 , 14), - PinDef(0 , 15), - PinDef(0 , 16), - PinDef(0 , 17), - PinDef(0 , 18), - PinDef(0 , 19), - PinDef(0 , 20), - PinDef(0 , 21), - PinDef(0 , 22), - PinDef(0 , 23), - PinDef(0 , 24), - PinDef(0 , 25), - PinDef(0 , 26), - PinDef(0 , 27), - PinDef(0 , 28), - PinDef(0 , 29), - PinDef(0 , 30), - PinDef(0 , 31), - - PinDef(1 , 0), //P1_1 = 32... - PinDef(1 , 1), - PinDef(1 , 2), - PinDef(1 , 3), - PinDef(1 , 4), - PinDef(1 , 5), - PinDef(1 , 6), - PinDef(1 , 7), - PinDef(1 , 8), - PinDef(1 , 9), - PinDef(1 , 10), - PinDef(1 , 11), - PinDef(1 , 12), - PinDef(1 , 13), - PinDef(1 , 14), - PinDef(1 , 15), - - // Port0 - p0 = P0_0, - p1 = P0_1, - p2 = P0_2, - p3 = P0_3, - p4 = P0_4, - p5 = P0_5, - p6 = P0_6, - p7 = P0_7, - p8 = P0_8, - p9 = P0_9, - p10 = P0_10, - p11 = P0_11, - p12 = P0_12, - p13 = P0_13, - p14 = P0_14, - p15 = P0_15, - p16 = P0_16, - p17 = P0_17, - p18 = P0_18, - p19 = P0_19, - p20 = P0_20, - p21 = P0_21, - p22 = P0_22, - p23 = P0_23, - p24 = P0_24, - p25 = P0_25, - p26 = P0_26, - p27 = P0_27, - p28 = P0_28, - p29 = P0_29, - p30 = P0_30, - p31 = P0_31, - - // Port1 - p32 = P1_0, - p33 = P1_1, - p34 = P1_2, - p35 = P1_3, - p36 = P1_4, - p37 = P1_5, - p38 = P1_6, - p39 = P1_7, - p40 = P1_8, - p41 = P1_9, - p42 = P1_10, - p43 = P1_11, - p44 = P1_12, - p45 = P1_13, - p46 = P1_14, - p47 = P1_15, - - - LED_RED = p23, - LED_GREEN = p22, - LED_BLUE = p24, - - LED1 = LED_RED, - LED2 = LED_GREEN, - LED3 = LED_BLUE, - - BUTTON_USER = p32, - BUTTON_GROVE1 = p27, // on Base Dock Grove#1 - BUTTON_GROVE2 = p29, // on Base Dock Grove#2 - BUTTON_GROVE3 = p31, // on Base Dock Grove#3 - BUTTON_GROVE4 = p3, // on Base Dock Grove#4 - - BUTTON1 = BUTTON_GROVE1, // on Base Dock Grove#1 - BUTTON2 = BUTTON_GROVE2, // on Base Dock Grove#2 - BUTTON3 = BUTTON_GROVE3, // on Base Dock Grove#3 - BUTTON4 = BUTTON_GROVE4, // on Base Dock Grove#4 - USR_BTN = BUTTON_USER, // on Board - - RX_PIN_NUMBER = p19, - TX_PIN_NUMBER = p20, - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - STDIO_UART_TX = TX_PIN_NUMBER, - STDIO_UART_RX = RX_PIN_NUMBER, - - SPI_PSELMOSI0 = p15, - SPI_PSELMISO0 = p16, - SPI_PSELSS0 = p17, - SPI_PSELSCK0 = p21, - - SPI_PSELMOSI1 = p12, - SPI_PSELMISO1 = p13, - SPI_PSELSS1 = p11, - SPI_PSELSCK1 = p14, - - SPIS_PSELMOSI = p12, - SPIS_PSELMISO = p13, - SPIS_PSELSS = p11, - SPIS_PSELSCK = p14, - - I2C_SDA0 = p26, - I2C_SCL0 = p27, - - A0 = p2, - A1 = p3, - A4 = p28, - A5 = p29, - A6 = p30, - A7 = p31, - - /**** QSPI pins ****/ - QSPI1_IO0 = P1_5, - QSPI1_IO1 = P1_4, - QSPI1_IO2 = P1_2, - QSPI1_IO3 = P1_1, - QSPI1_SCK = P1_3, - QSPI1_CSN = P1_6, - - /**** QSPI FLASH pins ****/ - QSPI_FLASH1_IO0 = QSPI1_IO0, - QSPI_FLASH1_IO1 = QSPI1_IO1, - QSPI_FLASH1_IO2 = QSPI1_IO2, - QSPI_FLASH1_IO3 = QSPI1_IO3, - QSPI_FLASH1_SCK = QSPI1_SCK, - QSPI_FLASH1_CSN = QSPI1_CSN, - - // Not connected - NC = (int)0xFFFFFFFF, - CTS_PIN_NUMBER = NC, - RTS_PIN_NUMBER = NC, - STDIO_UART_CTS = CTS_PIN_NUMBER, - STDIO_UART_RTS = RTS_PIN_NUMBER - -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_MAKERDIARY_NRF52840_MDK/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_MAKERDIARY_NRF52840_MDK/device.h deleted file mode 100644 index 2427e752ea9..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_MAKERDIARY_NRF52840_MDK/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_MTB_LAIRD_BL654/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_MTB_LAIRD_BL654/PinNames.h deleted file mode 100644 index 360660ac8fd..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_MTB_LAIRD_BL654/PinNames.h +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright (c) 2016 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "nrf_gpio.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 3 - -///> define macro producing for example Px_y = NRF_GPIO_PIN_MAP(x, y) -#define PinDef(port_num, pin_num) P##port_num##_##pin_num = NRF_GPIO_PIN_MAP(port_num, pin_num) - - -typedef enum { - PinDef(0 , 0), // P0_0 = 0... - PinDef(0 , 1), - PinDef(0 , 2), - PinDef(0 , 3), - PinDef(0 , 4), - PinDef(0 , 5), - PinDef(0 , 6), - PinDef(0 , 7), - PinDef(0 , 8), - PinDef(0 , 9), - PinDef(0 , 10), - PinDef(0 , 11), - PinDef(0 , 12), - PinDef(0 , 13), - PinDef(0 , 14), - PinDef(0 , 15), - PinDef(0 , 16), - PinDef(0 , 17), - PinDef(0 , 18), - PinDef(0 , 19), - PinDef(0 , 20), - PinDef(0 , 21), - PinDef(0 , 22), - PinDef(0 , 23), - PinDef(0 , 24), - PinDef(0 , 25), - PinDef(0 , 26), - PinDef(0 , 27), - PinDef(0 , 28), - PinDef(0 , 29), - PinDef(0 , 30), - PinDef(0 , 31), - - PinDef(1 , 0), //P1_1 = 32... - PinDef(1 , 1), - PinDef(1 , 2), - PinDef(1 , 3), - PinDef(1 , 4), - PinDef(1 , 5), - PinDef(1 , 6), - PinDef(1 , 7), - PinDef(1 , 8), - PinDef(1 , 9), - PinDef(1 , 10), - PinDef(1 , 11), - PinDef(1 , 12), - PinDef(1 , 13), - PinDef(1 , 14), - PinDef(1 , 15), - - // Port0 - p0 = P0_0, - p1 = P0_1, - p2 = P0_2, - p3 = P0_3, - p4 = P0_4, - p5 = P0_5, - p6 = P0_6, - p7 = P0_7, - - p8 = P0_8, - p9 = P0_9, - p10 = P0_10, - p11 = P0_11, - p12 = P0_12, - p13 = P0_13, - p14 = P0_14, - p15 = P0_15, - - p16 = P0_16, - p17 = P0_17, - p18 = P0_18, - p19 = P0_19, - p20 = P0_20, - p21 = P0_21, - p22 = P0_22, - p23 = P0_23, - - p24 = P0_24, - p25 = P0_25, - p26 = P0_26, - p27 = P0_27, - p28 = P0_28, - p29 = P0_29, - p30 = P0_30, - p31 = P0_31, - - // Port1 - p32 = P1_0, - p33 = P1_1, - p34 = P1_2, - p35 = P1_3, - p36 = P1_4, - p37 = P1_5, - p38 = P1_6, - p39 = P1_7, - - p40 = P1_8, - p41 = P1_9, - p42 = P1_10, - p43 = P1_11, - p44 = P1_12, - p45 = P1_13, - p46 = P1_14, - p47 = P1_15, - - // Not connected - NC = (int)0xFFFFFFFF, - - SIO_0 = P0_0, - SIO_1 = P0_1, - SIO_2 = P0_2, - SIO_3 = P0_3, - SIO_4 = P0_4, - SIO_5 = P0_5, - SIO_6 = P0_6, - SIO_7 = P0_7, - SIO_8 = P0_8, - SIO_9 = P0_9, //NFC1 - SIO_10 = P0_10, //NFC2 - SIO_11 = P0_11, - SIO_12 = P0_12, - SIO_13 = P0_13, - SIO_14 = P0_14, - SIO_15 = P0_15, - - SIO_16 = P0_16, - SIO_17 = P0_17, - SIO_18 = NC, - SIO_19 = P0_19, - SIO_20 = P0_20, - SIO_21 = P0_21, - SIO_22 = P0_22, - SIO_23 = P0_23, - SIO_24 = P0_24, - SIO_25 = P0_25, - SIO_26 = P0_26, - SIO_27 = P0_27, - SIO_28 = P0_28, - SIO_29 = P0_29, - SIO_30 = P0_30, - SIO_31 = P0_31, - - SIO_32 = P1_0, - SIO_33 = P1_1, - SIO_34 = P1_2, - SIO_35 = P1_3, - SIO_36 = P1_4, - SIO_37 = P1_5, - SIO_38 = P1_6, - SIO_39 = P1_7, - SIO_40 = P1_8, - SIO_41 = P1_9, - SIO_42 = P1_10, - SIO_43 = P1_11, - SIO_44 = P1_12, - SIO_45 = P1_13, - SIO_46 = P1_14, - SIO_47 = P1_15, - - LED1 = SIO_38, - LED2 = SIO_39, - LED3 = SIO_37, - LED_RED = LED1, - LED_GREEN = LED3, - LED_BLUE = LED2, - - BUTTON1 = SIO_33, - USER_BUTTON = BUTTON1, - - //Nordic SDK pin names - RX_PIN_NUMBER = SIO_8, - TX_PIN_NUMBER = SIO_6, - CTS_PIN_NUMBER = SIO_7, - RTS_PIN_NUMBER = SIO_5, - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - STDIO_UART_TX = TX_PIN_NUMBER, - STDIO_UART_RX = RX_PIN_NUMBER, - STDIO_UART_CTS = CTS_PIN_NUMBER, - STDIO_UART_RTS = RTS_PIN_NUMBER, - - SPI_PSELMOSI0 = SIO_45, - SPI_PSELMISO0 = SIO_46, - SPI_PSELSS0 = SIO_42, //CS for SD card on MTB - SPI_PSELSCK0 = SIO_47, - - SPI_PSELMOSI1 = SIO_30, - SPI_PSELMISO1 = SIO_29, - SPI_PSELSS1 = SIO_41, //CS for LCD on MTB - SPI_PSELSCK1 = SIO_44, - - //Default SPI - SPI_MOSI = SPI_PSELMOSI0, - SPI_MISO = SPI_PSELMISO0, - SPI_SCK = SPI_PSELSCK0, - SPI_CS = SPI_PSELSS0, - -/* - SPIS_PSELMOSI = P1_2, - SPIS_PSELMISO = P1_3, - SPIS_PSELSS = P1_1, - SPIS_PSELSCK = P1_4, -*/ - - I2C_SDA0 = SIO_26, - I2C_SCL0 = SIO_27, - - I2C_SDA1 = SIO_25, - I2C_SCL1 = SIO_28, - - //Default I2C - I2C_SCL = I2C_SCL0, - I2C_SDA = I2C_SDA0, - - UART_TX1 = SIO_16, - UART_RX1 = SIO_15, - - UART_TX2 = SIO_21, - UART_RX2 = SIO_24, - - //Default UART - UART_TX = UART_TX1, - UART_RX = UART_RX1, - - /* QSPI */ - QSPI1_IO0 = P0_20, - QSPI1_IO1 = P0_21, - QSPI1_IO2 = P0_22, - QSPI1_IO3 = P0_23, - QSPI1_SCK = P0_19, - QSPI1_CSN = P0_17, - - /* QSPI FLASH */ - QSPI_FLASH1_IO0 = QSPI1_IO0, - QSPI_FLASH1_IO1 = QSPI1_IO1, - QSPI_FLASH1_IO2 = QSPI1_IO2, - QSPI_FLASH1_IO3 = QSPI1_IO3, - QSPI_FLASH1_SCK = QSPI1_SCK, - QSPI_FLASH1_CSN = QSPI1_CSN, - - //MTB aliases - GP0 = SIO_33, - GP1 = SIO_34, - AIN0 = SIO_2, - AIN1 = SIO_3, - AIN2 = SIO_4, - GP2 = SIO_42, - GP3 = SIO_43, - GP4 = SIO_19, - GP5 = SIO_17, //A0 for LCD on MTB - GP6 = SIO_40, //RESET for LCD on MTB - GP7 = SIO_41, - GP8 = SIO_12, - -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_MTB_LAIRD_BL654/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_MTB_LAIRD_BL654/device.h deleted file mode 100644 index 96a726c469b..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_MTB_LAIRD_BL654/device.h +++ /dev/null @@ -1,24 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/PeripheralPins.h b/targets/TARGET_NXP/TARGET_LPC11UXX/PeripheralPins.h deleted file mode 100644 index 28d12e031cc..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/PeripheralPins.h +++ /dev/null @@ -1,43 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -/************ADC***************/ -extern const PinMap PinMap_ADC[]; - -/************I2C***************/ -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -/************UART***************/ -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; - -/************SPI***************/ -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SSEL[]; - -/************PWM***************/ -extern const PinMap PinMap_PWM[]; - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/PortNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/PortNames.h deleted file mode 100644 index 3f272730a1a..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/PortNames.h +++ /dev/null @@ -1,31 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - Port0 = 0, - Port1 = 1 -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralNames.h deleted file mode 100644 index ffb2e121f86..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralNames.h +++ /dev/null @@ -1,71 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)LPC_USART_BASE -} UARTName; - -typedef enum { - I2C_0 = (int)LPC_I2C_BASE -} I2CName; - -typedef enum { - ADC0_0 = 0, - ADC0_1, - ADC0_2, - ADC0_3, - ADC0_4, - ADC0_5, - ADC0_6, - ADC0_7 -} ADCName; - -typedef enum { - SPI_0 = (int)LPC_SSP0_BASE, - SPI_1 = (int)LPC_SSP1_BASE -} SPIName; - -typedef enum { - PWM_1 = 0, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - PWM_7, - PWM_8, - PWM_9, - PWM_10, - PWM_11 -} PWMName; - -#define STDIO_UART_TX UART_TX -#define STDIO_UART_RX UART_RX -#define STDIO_UART UART_0 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralPins.c b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralPins.c deleted file mode 100644 index aba07325212..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralPins.c +++ /dev/null @@ -1,117 +0,0 @@ - -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {P0_11, ADC0_0, 0x02}, - {P0_12, ADC0_1, 0x02}, - {P0_13, ADC0_2, 0x02}, - {P0_14, ADC0_3, 0x02}, - {P0_15, ADC0_4, 0x02}, - {P0_16, ADC0_5, 0x01}, - {P0_22, ADC0_6, 0x01}, - {P0_23, ADC0_7, 0x01}, - {NC , NC , 0 } -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {P0_5, I2C_0, 1}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {P0_4, I2C_0, 1}, - {NC , NC, 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {P0_19, UART_0, 1}, - {P1_13, UART_0, 3}, - {P1_27, UART_0, 2}, - { NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {P0_18, UART_0, 1}, - {P1_14, UART_0, 3}, - {P1_26, UART_0, 2}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {P0_6 , SPI_0, 0x02}, - {P0_10, SPI_0, 0x02}, - {P1_29, SPI_0, 0x01}, - {P1_15, SPI_1, 0x03}, - {P1_20, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {P0_9 , SPI_0, 0x01}, - {P0_21, SPI_1, 0x02}, - {P1_22, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {P0_8 , SPI_0, 0x01}, - {P0_22, SPI_1, 0x03}, - {P1_21, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {P0_2 , SPI_0, 0x01}, - {P1_19, SPI_1, 0x02}, - {P1_23, SPI_1, 0x02}, - {NC , NC , 0} -}; - -/************PWM***************/ -/* To have a PWM where we can change both the period and the duty cycle, - * we need an entire timer. With the following conventions: - * * MR3 is used for the PWM period - * * MR0, MR1, MR2 are used for the duty cycle - */ -const PinMap PinMap_PWM[] = { - /* CT16B0 */ - {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */ - {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */ - {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */ - - /* CT16B1 */ - {P0_21, PWM_4, 1}, /* MR0 */ - {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */ - - /* CT32B0 */ - {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */ - {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */ - {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */ - - /* CT32B1 */ - {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */ - {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */ - {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */ - - {NC, NC, 0} -}; diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PinNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PinNames.h deleted file mode 100644 index de9cf536d1d..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PinNames.h +++ /dev/null @@ -1,178 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 5 - -typedef enum { - // LPC11U Pin Names - P0_0 = 0, - P0_1 = 1, - P0_2 = 2, - P0_3 = 3, - P0_4 = 4, - P0_5 = 5, - P0_6 = 6, - P0_7 = 7, - P0_8 = 8, - P0_9 = 9, - P0_10 = 10, - P0_11 = 11, - P0_12 = 12, - P0_13 = 13, - P0_14 = 14, - P0_15 = 15, - P0_16 = 16, - P0_17 = 17, - P0_18 = 18, - P0_19 = 19, - P0_20 = 20, - P0_21 = 21, - P0_22 = 22, - P0_23 = 23, - P0_24 = 24, - P0_25 = 25, - P0_26 = 26, - P0_27 = 27, - - P1_0 = 32, - P1_1 = 33, - P1_2 = 34, - P1_3 = 35, - P1_4 = 36, - P1_5 = 37, - P1_6 = 38, - P1_7 = 39, - P1_8 = 40, - P1_9 = 41, - P1_10 = 42, - P1_11 = 43, - P1_12 = 44, - P1_13 = 45, - P1_14 = 46, - P1_15 = 47, - P1_16 = 48, - P1_17 = 49, - P1_18 = 50, - P1_19 = 51, - P1_20 = 52, - P1_21 = 53, - P1_22 = 54, - P1_23 = 55, - P1_24 = 56, - P1_25 = 57, - P1_26 = 58, - P1_27 = 59, - P1_28 = 60, - P1_29 = 61, - - P1_31 = 63, - - // MicroNFCBoard pin names - M_RST = P0_0, - M_BOOT = P0_1, - M_RXD = P0_18, - M_TXD = P0_19, - M_SCL = P0_4, - M_SDA = P0_5, - M_D0 = P0_20, - - M_A0 = P0_16, - M_A1 = P0_15, - M_A2 = P0_14, - M_A3 = P0_13, - M_SCK = P0_10, - M_MOSI = P0_9, - M_MISO = P0_8, - M_NCS = P0_2, - M_IRQ = P0_7, - - // MicroNFCBoard pin numbers - p4 = M_RST, - p5 = M_BOOT, - p6 = M_RXD, - p7 = M_TXD, - p8 = M_SCL, - p9 = M_SDA, - p10 = M_D0, - - p11 = M_IRQ, - p12 = M_NCS, - p13 = M_MISO, - p14 = M_MOSI, - p15 = M_SCK, - p16 = M_A3, - p17 = M_A2, - p18 = M_A1, - p19 = M_A0, - - // Other Pin Names - LED1 = P0_11, - LED2 = P0_12, - - // Alias to have correct blue lights of death pattern - LED3 = LED2, - LED4 = LED1, - - UART_TX = M_TXD, - UART_RX = M_RXD, - - // Not connected - NC = (int)0xFFFFFFFF, - - // Standard but not supported pins - USBTX = NC, - USBRX = NC, - -} PinName; - -typedef enum { - CHANNEL0 = FLEX_INT0_IRQn, - CHANNEL1 = FLEX_INT1_IRQn, - CHANNEL2 = FLEX_INT2_IRQn, - CHANNEL3 = FLEX_INT3_IRQn, - CHANNEL4 = FLEX_INT4_IRQn, - CHANNEL5 = FLEX_INT5_IRQn, - CHANNEL6 = FLEX_INT6_IRQn, - CHANNEL7 = FLEX_INT7_IRQn -} Channel; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/device.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/device.h deleted file mode 100644 index 71deacc1116..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/device.h +++ /dev/null @@ -1,40 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/PeripheralNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/PeripheralNames.h deleted file mode 100644 index 705034a2fb6..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/PeripheralNames.h +++ /dev/null @@ -1,87 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)LPC_USART_BASE -} UARTName; - -typedef enum { - I2C_0 = (int)LPC_I2C_BASE -} I2CName; - -typedef enum { - ADC0_0 = 0, - ADC0_1, - ADC0_2, - ADC0_3, - ADC0_4, - ADC0_5, - ADC0_6, - ADC0_7 -} ADCName; - -typedef enum { - SPI_0 = (int)LPC_SSP0_BASE, - SPI_1 = (int)LPC_SSP1_BASE -} SPIName; - -typedef enum { - PWM_1 = 0, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - PWM_7, - PWM_8, - PWM_9, - PWM_10, - PWM_11 -} PWMName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_0 - -// Default peripherals -#define MBED_SPI0 p5, p6, p7, p8 -#define MBED_SPI1 p11, p12, p13, p14 - -#define MBED_UART0 p9, p10 -#define MBED_UARTUSB USBTX, USBRX - -#define MBED_I2C0 p28, p27 - -#define MBED_ANALOGIN0 p15 -#define MBED_ANALOGIN1 p16 -#define MBED_ANALOGIN2 p17 -#define MBED_ANALOGIN3 p18 -#define MBED_ANALOGIN4 p19 -#define MBED_ANALOGIN5 p20 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/PeripheralPins.c b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/PeripheralPins.c deleted file mode 100644 index b583d12c1bd..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/PeripheralPins.c +++ /dev/null @@ -1,117 +0,0 @@ - -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {P0_11, ADC0_0, 0x02}, - {P0_12, ADC0_1, 0x02}, - {P0_13, ADC0_2, 0x02}, - {P0_14, ADC0_3, 0x02}, - {P0_15, ADC0_4, 0x02}, - {P0_16, ADC0_5, 0x01}, - {P0_22, ADC0_6, 0x01}, - {P0_23, ADC0_7, 0x01}, - {NC , NC , 0 } -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {P0_5, I2C_0, 1}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {P0_4, I2C_0, 1}, - {NC , NC, 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {P0_19, UART_0, 1}, - {P1_13, UART_0, 3}, - {P1_27, UART_0, 2}, - { NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {P0_18, UART_0, 1}, - {P1_14, UART_0, 3}, - {P1_26, UART_0, 2}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {P0_6 , SPI_0, 0x02}, - {P0_10, SPI_0, 0x02}, - {P1_29, SPI_0, 0x01}, - {P1_15, SPI_1, 0x03}, - {P1_20, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {P0_9 , SPI_0, 0x01}, - {P0_21, SPI_1, 0x02}, - {P1_22, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {P0_8 , SPI_0, 0x01}, - {P0_22, SPI_1, 0x03}, - {P1_21, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {P0_2 , SPI_0, 0x01}, - {P1_19, SPI_1, 0x02}, - {P1_23, SPI_1, 0x02}, - {NC , NC , 0} -}; - -/************PWM***************/ -/* To have a PWM where we can change both the period and the duty cycle, - * we need an entire timer. With the following conventions: - * * MR3 is used for the PWM period - * * MR0, MR1, MR2 are used for the duty cycle - */ -const PinMap PinMap_PWM[] = { - /* CT16B0 */ - {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */ - {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */ - {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */ - - /* CT16B1 */ - {P0_21, PWM_4, 1}, /* MR0 */ - {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */ - - /* CT32B0 */ - {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */ - {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */ - {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */ - - /* CT32B1 */ - {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */ - {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */ - {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */ - - {NC, NC, 0} -}; diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/PinNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/PinNames.h deleted file mode 100644 index 6688e3caff1..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/PinNames.h +++ /dev/null @@ -1,166 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 5 - -typedef enum { - // LPC11U Pin Names - P0_0 = 0, - P0_1 = 1, - P0_2 = 2, - P0_3 = 3, - P0_4 = 4, - P0_5 = 5, - P0_6 = 6, - P0_7 = 7, - P0_8 = 8, - P0_9 = 9, - P0_10 = 10, - P0_11 = 11, - P0_12 = 12, - P0_13 = 13, - P0_14 = 14, - P0_15 = 15, - P0_16 = 16, - P0_17 = 17, - P0_18 = 18, - P0_19 = 19, - P0_20 = 20, - P0_21 = 21, - P0_22 = 22, - P0_23 = 23, - P0_24 = 24, - P0_25 = 25, - P0_26 = 26, - P0_27 = 27, - - P1_0 = 32, - P1_1 = 33, - P1_2 = 34, - P1_3 = 35, - P1_4 = 36, - P1_5 = 37, - P1_6 = 38, - P1_7 = 39, - P1_8 = 40, - P1_9 = 41, - P1_10 = 42, - P1_11 = 43, - P1_12 = 44, - P1_13 = 45, - P1_14 = 46, - P1_15 = 47, - P1_16 = 48, - P1_17 = 49, - P1_18 = 50, - P1_19 = 51, - P1_20 = 52, - P1_21 = 53, - P1_22 = 54, - P1_23 = 55, - P1_24 = 56, - P1_25 = 57, - P1_26 = 58, - P1_27 = 59, - P1_28 = 60, - P1_29 = 61, - - P1_31 = 63, - - // mbed DIP Pin Names - p5 = P0_9, - p6 = P0_8, - p7 = P1_29, - p8 = P0_2, - p9 = P1_27, - p10 = P1_26, - p11 = P1_22, - p12 = P1_21, - p13 = P1_20, - p14 = P1_23, - p15 = P0_11, - p16 = P0_12, - p17 = P0_13, - p18 = P0_14, - p19 = P0_16, - p20 = P0_22, - p21 = P0_7, - p22 = P0_17, - p23 = P1_17, - p24 = P1_18, - p25 = P1_24, - p26 = P1_25, - p27 = P0_4, - p28 = P0_5, - p29 = P1_5, - p30 = P1_2, - - p33 = P0_3, - p34 = P1_15, - p35 = P0_20, - p36 = P0_21, - - // Other mbed Pin Names - LED1 = P1_8, - LED2 = P1_9, - LED3 = P1_10, - LED4 = P1_11, - - USBTX = P0_19, - USBRX = P0_18, - - // Not connected - NC = (int)0xFFFFFFFF, -} PinName; - -typedef enum { - CHANNEL0 = FLEX_INT0_IRQn, - CHANNEL1 = FLEX_INT1_IRQn, - CHANNEL2 = FLEX_INT2_IRQn, - CHANNEL3 = FLEX_INT3_IRQn, - CHANNEL4 = FLEX_INT4_IRQn, - CHANNEL5 = FLEX_INT5_IRQn, - CHANNEL6 = FLEX_INT6_IRQn, - CHANNEL7 = FLEX_INT7_IRQn -} Channel; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/device.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/device.h deleted file mode 100644 index 5d57c9de571..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/device.h +++ /dev/null @@ -1,40 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_401/PeripheralNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_401/PeripheralNames.h deleted file mode 100644 index 705034a2fb6..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_401/PeripheralNames.h +++ /dev/null @@ -1,87 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)LPC_USART_BASE -} UARTName; - -typedef enum { - I2C_0 = (int)LPC_I2C_BASE -} I2CName; - -typedef enum { - ADC0_0 = 0, - ADC0_1, - ADC0_2, - ADC0_3, - ADC0_4, - ADC0_5, - ADC0_6, - ADC0_7 -} ADCName; - -typedef enum { - SPI_0 = (int)LPC_SSP0_BASE, - SPI_1 = (int)LPC_SSP1_BASE -} SPIName; - -typedef enum { - PWM_1 = 0, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - PWM_7, - PWM_8, - PWM_9, - PWM_10, - PWM_11 -} PWMName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_0 - -// Default peripherals -#define MBED_SPI0 p5, p6, p7, p8 -#define MBED_SPI1 p11, p12, p13, p14 - -#define MBED_UART0 p9, p10 -#define MBED_UARTUSB USBTX, USBRX - -#define MBED_I2C0 p28, p27 - -#define MBED_ANALOGIN0 p15 -#define MBED_ANALOGIN1 p16 -#define MBED_ANALOGIN2 p17 -#define MBED_ANALOGIN3 p18 -#define MBED_ANALOGIN4 p19 -#define MBED_ANALOGIN5 p20 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_401/PeripheralPins.c b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_401/PeripheralPins.c deleted file mode 100644 index b583d12c1bd..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_401/PeripheralPins.c +++ /dev/null @@ -1,117 +0,0 @@ - -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {P0_11, ADC0_0, 0x02}, - {P0_12, ADC0_1, 0x02}, - {P0_13, ADC0_2, 0x02}, - {P0_14, ADC0_3, 0x02}, - {P0_15, ADC0_4, 0x02}, - {P0_16, ADC0_5, 0x01}, - {P0_22, ADC0_6, 0x01}, - {P0_23, ADC0_7, 0x01}, - {NC , NC , 0 } -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {P0_5, I2C_0, 1}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {P0_4, I2C_0, 1}, - {NC , NC, 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {P0_19, UART_0, 1}, - {P1_13, UART_0, 3}, - {P1_27, UART_0, 2}, - { NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {P0_18, UART_0, 1}, - {P1_14, UART_0, 3}, - {P1_26, UART_0, 2}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {P0_6 , SPI_0, 0x02}, - {P0_10, SPI_0, 0x02}, - {P1_29, SPI_0, 0x01}, - {P1_15, SPI_1, 0x03}, - {P1_20, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {P0_9 , SPI_0, 0x01}, - {P0_21, SPI_1, 0x02}, - {P1_22, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {P0_8 , SPI_0, 0x01}, - {P0_22, SPI_1, 0x03}, - {P1_21, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {P0_2 , SPI_0, 0x01}, - {P1_19, SPI_1, 0x02}, - {P1_23, SPI_1, 0x02}, - {NC , NC , 0} -}; - -/************PWM***************/ -/* To have a PWM where we can change both the period and the duty cycle, - * we need an entire timer. With the following conventions: - * * MR3 is used for the PWM period - * * MR0, MR1, MR2 are used for the duty cycle - */ -const PinMap PinMap_PWM[] = { - /* CT16B0 */ - {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */ - {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */ - {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */ - - /* CT16B1 */ - {P0_21, PWM_4, 1}, /* MR0 */ - {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */ - - /* CT32B0 */ - {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */ - {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */ - {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */ - - /* CT32B1 */ - {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */ - {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */ - {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */ - - {NC, NC, 0} -}; diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_401/PinNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_401/PinNames.h deleted file mode 100644 index 3a74aab472e..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_401/PinNames.h +++ /dev/null @@ -1,195 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 5 - -typedef enum { - // LPC11U Pin Names - P0_0 = 0, - P0_1 = 1, - P0_2 = 2, - P0_3 = 3, - P0_4 = 4, - P0_5 = 5, - P0_6 = 6, - P0_7 = 7, - P0_8 = 8, - P0_9 = 9, - P0_10 = 10, - P0_11 = 11, - P0_12 = 12, - P0_13 = 13, - P0_14 = 14, - P0_15 = 15, - P0_16 = 16, - P0_17 = 17, - P0_18 = 18, - P0_19 = 19, - P0_20 = 20, - P0_21 = 21, - P0_22 = 22, - P0_23 = 23, - P0_24 = 24, - P0_25 = 25, - P0_26 = 26, - P0_27 = 27, - - P1_0 = 32, - P1_1 = 33, - P1_2 = 34, - P1_3 = 35, - P1_4 = 36, - P1_5 = 37, - P1_6 = 38, - P1_7 = 39, - P1_8 = 40, - P1_9 = 41, - P1_10 = 42, - P1_11 = 43, - P1_12 = 44, - P1_13 = 45, - P1_14 = 46, - P1_15 = 47, - P1_16 = 48, - P1_17 = 49, - P1_18 = 50, - P1_19 = 51, - P1_20 = 52, - P1_21 = 53, - P1_22 = 54, - P1_23 = 55, - P1_24 = 56, - P1_25 = 57, - P1_26 = 58, - P1_27 = 59, - P1_28 = 60, - P1_29 = 61, - - P1_31 = 63, - - // mbed DIP Pin Names - p5 = P0_9, - p6 = P0_8, - p7 = P1_29, - p8 = P0_2, - p9 = P1_27, - p10 = P1_26, - p11 = P1_22, - p12 = P1_21, - p13 = P1_20, - p14 = P1_23, - p15 = P0_11, - p16 = P0_12, - p17 = P0_13, - p18 = P0_14, - p19 = P0_16, - p20 = P0_22, - p21 = P0_7, - p22 = P0_17, - p23 = P1_17, - p24 = P1_18, - p25 = P1_24, - p26 = P1_25, - p27 = P0_4, - p28 = P0_5, - p29 = P1_5, - p30 = P1_2, - - p33 = P0_3, - p34 = P1_15, - p35 = P0_20, - p36 = P0_21, - - // Other mbed Pin Names - LED1 = P1_8, - LED2 = P1_9, - LED3 = P1_10, - LED4 = P1_11, - - USBTX = P0_19, - USBRX = P0_18, - - // for Arch V1.1 - D0 = P0_18, - D1 = P0_19, - D2 = P0_17, - D3 = P1_17, - D4 = P1_18, - D5 = P1_24, - D6 = P1_25, - D7 = P1_5, - D8 = P1_26, - D9 = P1_27, - D10 = P0_2, - D11 = P0_9, // P1_29 for Arch V1.0 - D12 = P0_8, - D13 = P1_29, // P0_9 for Arch V1.0 - - D14 = P0_5, - D15 = P0_4, - - A0 = P0_11, - A1 = P0_12, - A2 = P0_13, - A3 = P0_14, - A4 = P0_16, - A5 = P0_22, - - I2C_SCL = D15, - I2C_SDA = D14, - - // Not connected - NC = (int)0xFFFFFFFF, -} PinName; - -typedef enum { - CHANNEL0 = FLEX_INT0_IRQn, - CHANNEL1 = FLEX_INT1_IRQn, - CHANNEL2 = FLEX_INT2_IRQn, - CHANNEL3 = FLEX_INT3_IRQn, - CHANNEL4 = FLEX_INT4_IRQn, - CHANNEL5 = FLEX_INT5_IRQn, - CHANNEL6 = FLEX_INT6_IRQn, - CHANNEL7 = FLEX_INT7_IRQn -} Channel; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_401/device.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_401/device.h deleted file mode 100644 index 5d57c9de571..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_401/device.h +++ /dev/null @@ -1,40 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralNames.h deleted file mode 100644 index ffb2e121f86..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralNames.h +++ /dev/null @@ -1,71 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)LPC_USART_BASE -} UARTName; - -typedef enum { - I2C_0 = (int)LPC_I2C_BASE -} I2CName; - -typedef enum { - ADC0_0 = 0, - ADC0_1, - ADC0_2, - ADC0_3, - ADC0_4, - ADC0_5, - ADC0_6, - ADC0_7 -} ADCName; - -typedef enum { - SPI_0 = (int)LPC_SSP0_BASE, - SPI_1 = (int)LPC_SSP1_BASE -} SPIName; - -typedef enum { - PWM_1 = 0, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - PWM_7, - PWM_8, - PWM_9, - PWM_10, - PWM_11 -} PWMName; - -#define STDIO_UART_TX UART_TX -#define STDIO_UART_RX UART_RX -#define STDIO_UART UART_0 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralPins.c b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralPins.c deleted file mode 100644 index aba07325212..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralPins.c +++ /dev/null @@ -1,117 +0,0 @@ - -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {P0_11, ADC0_0, 0x02}, - {P0_12, ADC0_1, 0x02}, - {P0_13, ADC0_2, 0x02}, - {P0_14, ADC0_3, 0x02}, - {P0_15, ADC0_4, 0x02}, - {P0_16, ADC0_5, 0x01}, - {P0_22, ADC0_6, 0x01}, - {P0_23, ADC0_7, 0x01}, - {NC , NC , 0 } -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {P0_5, I2C_0, 1}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {P0_4, I2C_0, 1}, - {NC , NC, 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {P0_19, UART_0, 1}, - {P1_13, UART_0, 3}, - {P1_27, UART_0, 2}, - { NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {P0_18, UART_0, 1}, - {P1_14, UART_0, 3}, - {P1_26, UART_0, 2}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {P0_6 , SPI_0, 0x02}, - {P0_10, SPI_0, 0x02}, - {P1_29, SPI_0, 0x01}, - {P1_15, SPI_1, 0x03}, - {P1_20, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {P0_9 , SPI_0, 0x01}, - {P0_21, SPI_1, 0x02}, - {P1_22, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {P0_8 , SPI_0, 0x01}, - {P0_22, SPI_1, 0x03}, - {P1_21, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {P0_2 , SPI_0, 0x01}, - {P1_19, SPI_1, 0x02}, - {P1_23, SPI_1, 0x02}, - {NC , NC , 0} -}; - -/************PWM***************/ -/* To have a PWM where we can change both the period and the duty cycle, - * we need an entire timer. With the following conventions: - * * MR3 is used for the PWM period - * * MR0, MR1, MR2 are used for the duty cycle - */ -const PinMap PinMap_PWM[] = { - /* CT16B0 */ - {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */ - {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */ - {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */ - - /* CT16B1 */ - {P0_21, PWM_4, 1}, /* MR0 */ - {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */ - - /* CT32B0 */ - {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */ - {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */ - {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */ - - /* CT32B1 */ - {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */ - {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */ - {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */ - - {NC, NC, 0} -}; diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PinNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PinNames.h deleted file mode 100644 index d9b8eb4b00b..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PinNames.h +++ /dev/null @@ -1,138 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 5 - -typedef enum { - // LPC11U Pin Names - P0_0 = 0, - P0_1 = 1, - P0_2 = 2, - P0_3 = 3, - P0_4 = 4, - P0_5 = 5, - P0_6 = 6, - P0_7 = 7, - P0_8 = 8, - P0_9 = 9, - P0_10 = 10, - P0_11 = 11, - P0_12 = 12, - P0_13 = 13, - P0_14 = 14, - P0_15 = 15, - P0_16 = 16, - P0_17 = 17, - P0_18 = 18, - P0_19 = 19, - P0_20 = 20, - P0_21 = 21, - P0_22 = 22, - P0_23 = 23, - P0_24 = 24, - P0_25 = 25, - P0_26 = 26, - P0_27 = 27, - - P1_0 = 32, - P1_1 = 33, - P1_2 = 34, - P1_3 = 35, - P1_4 = 36, - P1_5 = 37, - P1_6 = 38, - P1_7 = 39, - P1_8 = 40, - P1_9 = 41, - P1_10 = 42, - P1_11 = 43, - P1_12 = 44, - P1_13 = 45, - P1_14 = 46, - P1_15 = 47, - P1_16 = 48, - P1_17 = 49, - P1_18 = 50, - P1_19 = 51, - P1_20 = 52, - P1_21 = 53, - P1_22 = 54, - P1_23 = 55, - P1_24 = 56, - P1_25 = 57, - P1_26 = 58, - P1_27 = 59, - P1_28 = 60, - P1_29 = 61, - - P1_31 = 63, - - // Other mbed Pin Names - LED1 = P0_7, - LED2 = P0_7, - LED3 = P0_7, - LED4 = P0_7, - - UART_TX = P0_19, - UART_RX = P0_18, - - // Not connected - NC = (int)0xFFFFFFFF, - - // Standard but not supported pins - USBTX = NC, - USBRX = NC, - -} PinName; - -typedef enum { - CHANNEL0 = FLEX_INT0_IRQn, - CHANNEL1 = FLEX_INT1_IRQn, - CHANNEL2 = FLEX_INT2_IRQn, - CHANNEL3 = FLEX_INT3_IRQn, - CHANNEL4 = FLEX_INT4_IRQn, - CHANNEL5 = FLEX_INT5_IRQn, - CHANNEL6 = FLEX_INT6_IRQn, - CHANNEL7 = FLEX_INT7_IRQn -} Channel; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/device.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/device.h deleted file mode 100644 index 71deacc1116..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/device.h +++ /dev/null @@ -1,40 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/PeripheralNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/PeripheralNames.h deleted file mode 100644 index 969f15f2f60..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/PeripheralNames.h +++ /dev/null @@ -1,71 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)LPC_USART_BASE -} UARTName; - -typedef enum { - I2C_0 = (int)LPC_I2C_BASE -} I2CName; - -typedef enum { - ADC0_0 = 0, - ADC0_1, - ADC0_2, - ADC0_3, - ADC0_4, - ADC0_5, - ADC0_6, - ADC0_7 -} ADCName; - -typedef enum { - SPI_0 = (int)LPC_SSP0_BASE, - SPI_1 = (int)LPC_SSP1_BASE -} SPIName; - -typedef enum { - PWM_1 = 0, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - PWM_7, - PWM_8, - PWM_9, - PWM_10, - PWM_11 -} PWMName; - -#define STDIO_UART_TX UART_TX -#define STDIO_UART_RX UART_RX -#define STDIO_UART UART_0 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/PeripheralPins.c b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/PeripheralPins.c deleted file mode 100644 index b583d12c1bd..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/PeripheralPins.c +++ /dev/null @@ -1,117 +0,0 @@ - -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {P0_11, ADC0_0, 0x02}, - {P0_12, ADC0_1, 0x02}, - {P0_13, ADC0_2, 0x02}, - {P0_14, ADC0_3, 0x02}, - {P0_15, ADC0_4, 0x02}, - {P0_16, ADC0_5, 0x01}, - {P0_22, ADC0_6, 0x01}, - {P0_23, ADC0_7, 0x01}, - {NC , NC , 0 } -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {P0_5, I2C_0, 1}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {P0_4, I2C_0, 1}, - {NC , NC, 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {P0_19, UART_0, 1}, - {P1_13, UART_0, 3}, - {P1_27, UART_0, 2}, - { NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {P0_18, UART_0, 1}, - {P1_14, UART_0, 3}, - {P1_26, UART_0, 2}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {P0_6 , SPI_0, 0x02}, - {P0_10, SPI_0, 0x02}, - {P1_29, SPI_0, 0x01}, - {P1_15, SPI_1, 0x03}, - {P1_20, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {P0_9 , SPI_0, 0x01}, - {P0_21, SPI_1, 0x02}, - {P1_22, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {P0_8 , SPI_0, 0x01}, - {P0_22, SPI_1, 0x03}, - {P1_21, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {P0_2 , SPI_0, 0x01}, - {P1_19, SPI_1, 0x02}, - {P1_23, SPI_1, 0x02}, - {NC , NC , 0} -}; - -/************PWM***************/ -/* To have a PWM where we can change both the period and the duty cycle, - * we need an entire timer. With the following conventions: - * * MR3 is used for the PWM period - * * MR0, MR1, MR2 are used for the duty cycle - */ -const PinMap PinMap_PWM[] = { - /* CT16B0 */ - {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */ - {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */ - {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */ - - /* CT16B1 */ - {P0_21, PWM_4, 1}, /* MR0 */ - {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */ - - /* CT32B0 */ - {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */ - {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */ - {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */ - - /* CT32B1 */ - {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */ - {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */ - {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */ - - {NC, NC, 0} -}; diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/PinNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/PinNames.h deleted file mode 100644 index 0d46ea96caf..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/PinNames.h +++ /dev/null @@ -1,166 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2014 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 5 - -typedef enum { - // LPC11U Pin Names - P0_0 = 0, - P0_1 = 1, - P0_2 = 2, - P0_3 = 3, - P0_4 = 4, - P0_5 = 5, - P0_6 = 6, - P0_7 = 7, - P0_8 = 8, - P0_9 = 9, - P0_10 = 10, - P0_11 = 11, - P0_12 = 12, - P0_13 = 13, - P0_14 = 14, - P0_15 = 15, - P0_16 = 16, - P0_17 = 17, - P0_18 = 18, - P0_19 = 19, - P0_20 = 20, - P0_21 = 21, - P0_22 = 22, - P0_23 = 23, - P0_24 = 24, - P0_25 = 25, - P0_26 = 26, - P0_27 = 27, - - P1_0 = 32, - P1_1 = 33, - P1_2 = 34, - P1_3 = 35, - P1_4 = 36, - P1_5 = 37, - P1_6 = 38, - P1_7 = 39, - P1_8 = 40, - P1_9 = 41, - P1_10 = 42, - P1_11 = 43, - P1_12 = 44, - P1_13 = 45, - P1_14 = 46, - P1_15 = 47, - P1_16 = 48, - P1_17 = 49, - P1_18 = 50, - P1_19 = 51, - P1_20 = 52, - P1_21 = 53, - P1_22 = 54, - P1_23 = 55, - P1_24 = 56, - P1_25 = 57, - P1_26 = 58, - P1_27 = 59, - P1_28 = 60, - P1_29 = 61, - - P1_31 = 63, - - // mbed DIP Pin Names - p3 = P0_7, - p4 = P0_8, - p5 = P0_9, - p6 = P0_10, - p7 = P0_22, - p8 = P0_11, - p9 = P0_12, - p10 = P0_13, - p11 = P0_14, - p12 = P0_15, - p13 = P0_16, - p14 = P0_23, - p15 = P1_15, - p16 = P0_17, - p17 = P0_18, - p18 = P0_19, - p19 = P0_1, - p20 = P1_19, - p21 = P0_0, - p22 = P0_20, - p23 = P0_2, - p24 = P0_3, - p25 = P0_4, - p26 = P0_5, - p27 = P0_21, - p28 = P0_6, - - // Other mbed Pin Names - LED1 = P0_7, - LED2 = P0_7, - LED3 = P0_7, - LED4 = P0_7, - - UART_TX = P0_19, - UART_RX = P0_18, - - // Not connected - NC = (int)0xFFFFFFFF, - - // Standard but not supported pins - USBTX = NC, - USBRX = NC, - -} PinName; - -typedef enum { - CHANNEL0 = FLEX_INT0_IRQn, - CHANNEL1 = FLEX_INT1_IRQn, - CHANNEL2 = FLEX_INT2_IRQn, - CHANNEL3 = FLEX_INT3_IRQn, - CHANNEL4 = FLEX_INT4_IRQn, - CHANNEL5 = FLEX_INT5_IRQn, - CHANNEL6 = FLEX_INT6_IRQn, - CHANNEL7 = FLEX_INT7_IRQn -} Channel; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/device.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/device.h deleted file mode 100644 index 5d57c9de571..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/device.h +++ /dev/null @@ -1,40 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralNames.h deleted file mode 100644 index 969f15f2f60..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralNames.h +++ /dev/null @@ -1,71 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)LPC_USART_BASE -} UARTName; - -typedef enum { - I2C_0 = (int)LPC_I2C_BASE -} I2CName; - -typedef enum { - ADC0_0 = 0, - ADC0_1, - ADC0_2, - ADC0_3, - ADC0_4, - ADC0_5, - ADC0_6, - ADC0_7 -} ADCName; - -typedef enum { - SPI_0 = (int)LPC_SSP0_BASE, - SPI_1 = (int)LPC_SSP1_BASE -} SPIName; - -typedef enum { - PWM_1 = 0, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - PWM_7, - PWM_8, - PWM_9, - PWM_10, - PWM_11 -} PWMName; - -#define STDIO_UART_TX UART_TX -#define STDIO_UART_RX UART_RX -#define STDIO_UART UART_0 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralPins.c b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralPins.c deleted file mode 100644 index b583d12c1bd..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralPins.c +++ /dev/null @@ -1,117 +0,0 @@ - -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {P0_11, ADC0_0, 0x02}, - {P0_12, ADC0_1, 0x02}, - {P0_13, ADC0_2, 0x02}, - {P0_14, ADC0_3, 0x02}, - {P0_15, ADC0_4, 0x02}, - {P0_16, ADC0_5, 0x01}, - {P0_22, ADC0_6, 0x01}, - {P0_23, ADC0_7, 0x01}, - {NC , NC , 0 } -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {P0_5, I2C_0, 1}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {P0_4, I2C_0, 1}, - {NC , NC, 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {P0_19, UART_0, 1}, - {P1_13, UART_0, 3}, - {P1_27, UART_0, 2}, - { NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {P0_18, UART_0, 1}, - {P1_14, UART_0, 3}, - {P1_26, UART_0, 2}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {P0_6 , SPI_0, 0x02}, - {P0_10, SPI_0, 0x02}, - {P1_29, SPI_0, 0x01}, - {P1_15, SPI_1, 0x03}, - {P1_20, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {P0_9 , SPI_0, 0x01}, - {P0_21, SPI_1, 0x02}, - {P1_22, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {P0_8 , SPI_0, 0x01}, - {P0_22, SPI_1, 0x03}, - {P1_21, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {P0_2 , SPI_0, 0x01}, - {P1_19, SPI_1, 0x02}, - {P1_23, SPI_1, 0x02}, - {NC , NC , 0} -}; - -/************PWM***************/ -/* To have a PWM where we can change both the period and the duty cycle, - * we need an entire timer. With the following conventions: - * * MR3 is used for the PWM period - * * MR0, MR1, MR2 are used for the duty cycle - */ -const PinMap PinMap_PWM[] = { - /* CT16B0 */ - {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */ - {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */ - {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */ - - /* CT16B1 */ - {P0_21, PWM_4, 1}, /* MR0 */ - {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */ - - /* CT32B0 */ - {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */ - {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */ - {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */ - - /* CT32B1 */ - {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */ - {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */ - {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */ - - {NC, NC, 0} -}; diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PinNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PinNames.h deleted file mode 100644 index f1b833936cc..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PinNames.h +++ /dev/null @@ -1,183 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 5 - -typedef enum { - // LPC11U Pin Names - P0_0 = 0, - P0_1 = 1, - P0_2 = 2, - P0_3 = 3, - P0_4 = 4, - P0_5 = 5, - P0_6 = 6, - P0_7 = 7, - P0_8 = 8, - P0_9 = 9, - P0_10 = 10, - P0_11 = 11, - P0_12 = 12, - P0_13 = 13, - P0_14 = 14, - P0_15 = 15, - P0_16 = 16, - P0_17 = 17, - P0_18 = 18, - P0_19 = 19, - P0_20 = 20, - P0_21 = 21, - P0_22 = 22, - P0_23 = 23, - P0_24 = 24, - P0_25 = 25, - P0_26 = 26, - P0_27 = 27, - - P1_0 = 32, - P1_1 = 33, - P1_2 = 34, - P1_3 = 35, - P1_4 = 36, - P1_5 = 37, - P1_6 = 38, - P1_7 = 39, - P1_8 = 40, - P1_9 = 41, - P1_10 = 42, - P1_11 = 43, - P1_12 = 44, - P1_13 = 45, - P1_14 = 46, - P1_15 = 47, - P1_16 = 48, - P1_17 = 49, - P1_18 = 50, - P1_19 = 51, - P1_20 = 52, - P1_21 = 53, - P1_22 = 54, - P1_23 = 55, - P1_24 = 56, - P1_25 = 57, - P1_26 = 58, - P1_27 = 59, - P1_28 = 60, - P1_29 = 61, - - P1_31 = 63, - - // LED Names - LED1 = P1_24, - LED2 = P1_25, - LED3 = P1_26, - LED4 = P0_0, - LED5 = P1_3, - LED6 = P1_2, - LED7 = P1_1, - LED8 = P1_0, - - // BTN Names - BTN1 = P0_16, - BTN2 = P0_1, - // Standardized button names - BUTTON1 = BTN1, - BUTTON2 = BTN2, - - // UART - UART_TX = P0_19, - UART_RX = P0_18, - - // Arduino Shield Receptacles Names - D0 = P0_18, - D1 = P0_19, - D2 = P1_17, - D3 = P1_24, - D4 = P1_5, - D5 = P0_1, - D6 = P1_27, - D7 = P0_7, - D8 = P0_2, - D9 = P1_25, - D10= P1_23, - D11= P0_21, - D12= P0_22, - D13= P1_15, - D14= P0_5, - D15= P0_4, - - A0 = P0_11, - A1 = P0_12, - A2 = P0_13, - A3 = P0_16, - A4 = P0_5, // same port as SDA - A5 = P0_4, // same port as SCL - - SDA= P0_5, // same port as A4 - SCL= P0_4, // same port as A5 - - //SD Card pins - SDMOSI = P0_9, - SDMISO = P0_8, - SDSCLK = P1_29, - SDSSEL = P1_12, - - // Not connected - NC = (int)0xFFFFFFFF, - - // Standard but not supported pins - USBTX = NC, - USBRX = NC, -} PinName; - -typedef enum { - CHANNEL0 = FLEX_INT0_IRQn, - CHANNEL1 = FLEX_INT1_IRQn, - CHANNEL2 = FLEX_INT2_IRQn, - CHANNEL3 = FLEX_INT3_IRQn, - CHANNEL4 = FLEX_INT4_IRQn, - CHANNEL5 = FLEX_INT5_IRQn, - CHANNEL6 = FLEX_INT6_IRQn, - CHANNEL7 = FLEX_INT7_IRQn -} Channel; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/device.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/device.h deleted file mode 100644 index 5d57c9de571..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/device.h +++ /dev/null @@ -1,40 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/PeripheralNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/PeripheralNames.h deleted file mode 100644 index 969f15f2f60..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/PeripheralNames.h +++ /dev/null @@ -1,71 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)LPC_USART_BASE -} UARTName; - -typedef enum { - I2C_0 = (int)LPC_I2C_BASE -} I2CName; - -typedef enum { - ADC0_0 = 0, - ADC0_1, - ADC0_2, - ADC0_3, - ADC0_4, - ADC0_5, - ADC0_6, - ADC0_7 -} ADCName; - -typedef enum { - SPI_0 = (int)LPC_SSP0_BASE, - SPI_1 = (int)LPC_SSP1_BASE -} SPIName; - -typedef enum { - PWM_1 = 0, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - PWM_7, - PWM_8, - PWM_9, - PWM_10, - PWM_11 -} PWMName; - -#define STDIO_UART_TX UART_TX -#define STDIO_UART_RX UART_RX -#define STDIO_UART UART_0 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/PeripheralPins.c b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/PeripheralPins.c deleted file mode 100644 index b583d12c1bd..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/PeripheralPins.c +++ /dev/null @@ -1,117 +0,0 @@ - -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {P0_11, ADC0_0, 0x02}, - {P0_12, ADC0_1, 0x02}, - {P0_13, ADC0_2, 0x02}, - {P0_14, ADC0_3, 0x02}, - {P0_15, ADC0_4, 0x02}, - {P0_16, ADC0_5, 0x01}, - {P0_22, ADC0_6, 0x01}, - {P0_23, ADC0_7, 0x01}, - {NC , NC , 0 } -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {P0_5, I2C_0, 1}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {P0_4, I2C_0, 1}, - {NC , NC, 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {P0_19, UART_0, 1}, - {P1_13, UART_0, 3}, - {P1_27, UART_0, 2}, - { NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {P0_18, UART_0, 1}, - {P1_14, UART_0, 3}, - {P1_26, UART_0, 2}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {P0_6 , SPI_0, 0x02}, - {P0_10, SPI_0, 0x02}, - {P1_29, SPI_0, 0x01}, - {P1_15, SPI_1, 0x03}, - {P1_20, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {P0_9 , SPI_0, 0x01}, - {P0_21, SPI_1, 0x02}, - {P1_22, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {P0_8 , SPI_0, 0x01}, - {P0_22, SPI_1, 0x03}, - {P1_21, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {P0_2 , SPI_0, 0x01}, - {P1_19, SPI_1, 0x02}, - {P1_23, SPI_1, 0x02}, - {NC , NC , 0} -}; - -/************PWM***************/ -/* To have a PWM where we can change both the period and the duty cycle, - * we need an entire timer. With the following conventions: - * * MR3 is used for the PWM period - * * MR0, MR1, MR2 are used for the duty cycle - */ -const PinMap PinMap_PWM[] = { - /* CT16B0 */ - {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */ - {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */ - {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */ - - /* CT16B1 */ - {P0_21, PWM_4, 1}, /* MR0 */ - {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */ - - /* CT32B0 */ - {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */ - {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */ - {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */ - - /* CT32B1 */ - {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */ - {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */ - {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */ - - {NC, NC, 0} -}; diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/PinNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/PinNames.h deleted file mode 100644 index 00995403676..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/PinNames.h +++ /dev/null @@ -1,139 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2014 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 5 - -typedef enum { - // LPC11U Pin Names - P0_0 = 0, - P0_1 = 1, - P0_2 = 2, - P0_3 = 3, - P0_4 = 4, - P0_5 = 5, - P0_6 = 6, - P0_7 = 7, - P0_8 = 8, - P0_9 = 9, - P0_10 = 10, - P0_11 = 11, - P0_12 = 12, - P0_13 = 13, - P0_14 = 14, - P0_15 = 15, - P0_16 = 16, - P0_17 = 17, - P0_18 = 18, - P0_19 = 19, - P0_20 = 20, - P0_21 = 21, - P0_22 = 22, - P0_23 = 23, - P0_24 = 24, - P0_25 = 25, - P0_26 = 26, - P0_27 = 27, - - P1_0 = 32, - P1_1 = 33, - P1_2 = 34, - P1_3 = 35, - P1_4 = 36, - P1_5 = 37, - P1_6 = 38, - P1_7 = 39, - P1_8 = 40, - P1_9 = 41, - P1_10 = 42, - P1_11 = 43, - P1_12 = 44, - P1_13 = 45, - P1_14 = 46, - P1_15 = 47, - P1_16 = 48, - P1_17 = 49, - P1_18 = 50, - P1_19 = 51, - P1_20 = 52, - P1_21 = 53, - P1_22 = 54, - P1_23 = 55, - P1_24 = 56, - P1_25 = 57, - P1_26 = 58, - P1_27 = 59, - P1_28 = 60, - P1_29 = 61, - - P1_31 = 63, - - - // Other mbed Pin Names - LED1 = P1_19, - LED2 = P1_19, // Negative On - LED3 = P1_19, - LED4 = P1_19, - - UART_TX = P0_19, - UART_RX = P0_18, - - // Not connected - NC = (int)0xFFFFFFFF, - - // Standard but not supported pins - USBTX = NC, - USBRX = NC, - -} PinName; - -typedef enum { - CHANNEL0 = FLEX_INT0_IRQn, - CHANNEL1 = FLEX_INT1_IRQn, - CHANNEL2 = FLEX_INT2_IRQn, - CHANNEL3 = FLEX_INT3_IRQn, - CHANNEL4 = FLEX_INT4_IRQn, - CHANNEL5 = FLEX_INT5_IRQn, - CHANNEL6 = FLEX_INT6_IRQn, - CHANNEL7 = FLEX_INT7_IRQn -} Channel; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/device.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/device.h deleted file mode 100644 index 5d57c9de571..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/device.h +++ /dev/null @@ -1,40 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/PeripheralNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/PeripheralNames.h deleted file mode 100644 index 969f15f2f60..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/PeripheralNames.h +++ /dev/null @@ -1,71 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)LPC_USART_BASE -} UARTName; - -typedef enum { - I2C_0 = (int)LPC_I2C_BASE -} I2CName; - -typedef enum { - ADC0_0 = 0, - ADC0_1, - ADC0_2, - ADC0_3, - ADC0_4, - ADC0_5, - ADC0_6, - ADC0_7 -} ADCName; - -typedef enum { - SPI_0 = (int)LPC_SSP0_BASE, - SPI_1 = (int)LPC_SSP1_BASE -} SPIName; - -typedef enum { - PWM_1 = 0, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - PWM_7, - PWM_8, - PWM_9, - PWM_10, - PWM_11 -} PWMName; - -#define STDIO_UART_TX UART_TX -#define STDIO_UART_RX UART_RX -#define STDIO_UART UART_0 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/PeripheralPins.c b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/PeripheralPins.c deleted file mode 100644 index b583d12c1bd..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/PeripheralPins.c +++ /dev/null @@ -1,117 +0,0 @@ - -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {P0_11, ADC0_0, 0x02}, - {P0_12, ADC0_1, 0x02}, - {P0_13, ADC0_2, 0x02}, - {P0_14, ADC0_3, 0x02}, - {P0_15, ADC0_4, 0x02}, - {P0_16, ADC0_5, 0x01}, - {P0_22, ADC0_6, 0x01}, - {P0_23, ADC0_7, 0x01}, - {NC , NC , 0 } -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {P0_5, I2C_0, 1}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {P0_4, I2C_0, 1}, - {NC , NC, 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {P0_19, UART_0, 1}, - {P1_13, UART_0, 3}, - {P1_27, UART_0, 2}, - { NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {P0_18, UART_0, 1}, - {P1_14, UART_0, 3}, - {P1_26, UART_0, 2}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {P0_6 , SPI_0, 0x02}, - {P0_10, SPI_0, 0x02}, - {P1_29, SPI_0, 0x01}, - {P1_15, SPI_1, 0x03}, - {P1_20, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {P0_9 , SPI_0, 0x01}, - {P0_21, SPI_1, 0x02}, - {P1_22, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {P0_8 , SPI_0, 0x01}, - {P0_22, SPI_1, 0x03}, - {P1_21, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {P0_2 , SPI_0, 0x01}, - {P1_19, SPI_1, 0x02}, - {P1_23, SPI_1, 0x02}, - {NC , NC , 0} -}; - -/************PWM***************/ -/* To have a PWM where we can change both the period and the duty cycle, - * we need an entire timer. With the following conventions: - * * MR3 is used for the PWM period - * * MR0, MR1, MR2 are used for the duty cycle - */ -const PinMap PinMap_PWM[] = { - /* CT16B0 */ - {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */ - {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */ - {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */ - - /* CT16B1 */ - {P0_21, PWM_4, 1}, /* MR0 */ - {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */ - - /* CT32B0 */ - {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */ - {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */ - {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */ - - /* CT32B1 */ - {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */ - {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */ - {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */ - - {NC, NC, 0} -}; diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501/PinNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501/PinNames.h deleted file mode 100644 index 89056391a4b..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501/PinNames.h +++ /dev/null @@ -1,181 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2014 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 5 - -typedef enum { - // LPC11U Pin Names - P0_0 = 0, - P0_1 = 1, - P0_2 = 2, - P0_3 = 3, - P0_4 = 4, - P0_5 = 5, - P0_6 = 6, - P0_7 = 7, - P0_8 = 8, - P0_9 = 9, - P0_10 = 10, - P0_11 = 11, - P0_12 = 12, - P0_13 = 13, - P0_14 = 14, - P0_15 = 15, - P0_16 = 16, - P0_17 = 17, - P0_18 = 18, - P0_19 = 19, - P0_20 = 20, - P0_21 = 21, - P0_22 = 22, - P0_23 = 23, - P0_24 = 24, - P0_25 = 25, - P0_26 = 26, - P0_27 = 27, - - P1_0 = 32, - P1_1 = 33, - P1_2 = 34, - P1_3 = 35, - P1_4 = 36, - P1_5 = 37, - P1_6 = 38, - P1_7 = 39, - P1_8 = 40, - P1_9 = 41, - P1_10 = 42, - P1_11 = 43, - P1_12 = 44, - P1_13 = 45, - P1_14 = 46, - P1_15 = 47, - P1_16 = 48, - P1_17 = 49, - P1_18 = 50, - P1_19 = 51, - P1_20 = 52, - P1_21 = 53, - P1_22 = 54, - P1_23 = 55, - P1_24 = 56, - P1_25 = 57, - P1_26 = 58, - P1_27 = 59, - P1_28 = 60, - P1_29 = 61, - - P1_31 = 63, - - // mbed DIP Pin Names - // CN1-1 (GND) - // CN1-2 (EXTPOWER) - // CN1-3 (NC) - p4 = P0_0, // CN1-4 - p5 = P0_9, // CN1-5 - p6 = P0_8, // CN1-6 - p7 = P0_10, // CN1-7 - p8 = P0_7, // CN1-8 - p9 = P0_19, // CN1-9 - p10 = P0_18, // CN1-10 - p11 = P0_21, // CN1-11 - p12 = P0_22, // CN1-12 - p13 = P1_15, // CN1-13 - p14 = P0_6, // CN1-14 - p15 = P0_11, // CN1-15 - p16 = P0_12, // CN1-16 - p17 = P0_13, // CN1-17 - p18 = P0_14, // CN1-18 - p19 = P0_15, // CN1-19 - p20 = P0_16, // CN1-20 - - p21 = P0_14, // CN2-20 - p22 = P0_2, // CN2-19 - p23 = P0_23, // CN2-18 - p24 = P0_17, // CN2-17 - p25 = P0_20, // CN2-16 - p26 = P1_15, // CN2-15 - p27 = P0_4, // CN2-14 - p28 = P0_5, // CN2-13 - p29 = P1_19, // CN2-12 - p30 = P0_1, // CN2-11 - // CN2-10 (D+USB) - // CN2-9 (D-USB) - p33 = P0_3, // CN2-8 (USB-VBUS) - // CN2-7 (NC) - // CN2-6 (NC) - // CN2-5 (NC) - // CN2-4 (NC) - // CN2-3 (NC) - // CN2-2 (VDD) - // CN2-1 (VDD) - - // Other mbed Pin Names - LED1 = P0_20, - LED2 = P0_21, - LED3 = P0_20, - LED4 = P0_21, - - UART_TX = P0_19, - UART_RX = P0_18, - - // Not connected - NC = (int)0xFFFFFFFF, - - // Standard but not supported pins - USBTX = NC, - USBRX = NC, - -} PinName; - -typedef enum { - CHANNEL0 = FLEX_INT0_IRQn, - CHANNEL1 = FLEX_INT1_IRQn, - CHANNEL2 = FLEX_INT2_IRQn, - CHANNEL3 = FLEX_INT3_IRQn, - CHANNEL4 = FLEX_INT4_IRQn, - CHANNEL5 = FLEX_INT5_IRQn, - CHANNEL6 = FLEX_INT6_IRQn, - CHANNEL7 = FLEX_INT7_IRQn -} Channel; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501/device.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501/device.h deleted file mode 100644 index 5d57c9de571..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501/device.h +++ /dev/null @@ -1,40 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501_IBDAP/PinNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501_IBDAP/PinNames.h deleted file mode 100644 index 1110f7e57c1..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501_IBDAP/PinNames.h +++ /dev/null @@ -1,184 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2014 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 5 - -typedef enum { - // LPC11U Pin Names - P0_0 = 0, - P0_1 = 1, - P0_2 = 2, - P0_3 = 3, - P0_4 = 4, - P0_5 = 5, - P0_6 = 6, - P0_7 = 7, - P0_8 = 8, - P0_9 = 9, - P0_10 = 10, - P0_11 = 11, - P0_12 = 12, - P0_13 = 13, - P0_14 = 14, - P0_15 = 15, - P0_16 = 16, - P0_17 = 17, - P0_18 = 18, - P0_19 = 19, - P0_20 = 20, - P0_21 = 21, - P0_22 = 22, - P0_23 = 23, - P0_24 = 24, - P0_25 = 25, - P0_26 = 26, - P0_27 = 27, - - P1_0 = 32, - P1_1 = 33, - P1_2 = 34, - P1_3 = 35, - P1_4 = 36, - P1_5 = 37, - P1_6 = 38, - P1_7 = 39, - P1_8 = 40, - P1_9 = 41, - P1_10 = 42, - P1_11 = 43, - P1_12 = 44, - P1_13 = 45, - P1_14 = 46, - P1_15 = 47, - P1_16 = 48, - P1_17 = 49, - P1_18 = 50, - P1_19 = 51, - P1_20 = 52, - P1_21 = 53, - P1_22 = 54, - P1_23 = 55, - P1_24 = 56, - P1_25 = 57, - P1_26 = 58, - P1_27 = 59, - P1_28 = 60, - P1_29 = 61, - - P1_31 = 63, - - // mbed DIP Pin Names - // CN1-1 (GND) - // CN1-2 (EXTPOWER) - // CN1-3 (NC) - p4 = P0_0, // CN1-4 - p5 = P0_9, // CN1-5 - p6 = P0_8, // CN1-6 - p7 = P0_10, // CN1-7 - p8 = P0_7, // CN1-8 - p9 = P0_19, // CN1-9 - p10 = P0_18, // CN1-10 - p11 = P0_21, // CN1-11 - p12 = P0_22, // CN1-12 - p13 = P1_15, // CN1-13 - p14 = P0_6, // CN1-14 - p15 = P0_11, // CN1-15 - p16 = P0_12, // CN1-16 - p17 = P0_13, // CN1-17 - p18 = P0_14, // CN1-18 - p19 = P0_15, // CN1-19 - p20 = P0_16, // CN1-20 - - p21 = P0_14, // CN2-20 - p22 = P0_2, // CN2-19 - p23 = P0_23, // CN2-18 - p24 = P0_17, // CN2-17 - p25 = P0_20, // CN2-16 - p26 = P1_15, // CN2-15 - p27 = P0_4, // CN2-14 - p28 = P0_5, // CN2-13 - p29 = P1_19, // CN2-12 - p30 = P0_1, // CN2-11 - // CN2-10 (D+USB) - // CN2-9 (D-USB) - p33 = P0_3, // CN2-8 (USB-VBUS) - // CN2-7 (NC) - // CN2-6 (NC) - // CN2-5 (NC) - // CN2-4 (NC) - // CN2-3 (NC) - // CN2-2 (VDD) - // CN2-1 (VDD) - - // Other mbed Pin Names - LED1 = P0_20, // GREEN LED - LED2 = P0_11, // RED LED - LED3 = P0_21, // BLUE LED - LED4 = P0_20, // repeat LED1 - - UART_TX = P0_19, - UART_RX = P0_18, - - I2C_SCL = P0_4, - I2C_SDA = P0_5, - - // Not connected - NC = (int)0xFFFFFFFF, - - // Standard but not supported pins - USBTX = NC, - USBRX = NC, - -} PinName; - -typedef enum { - CHANNEL0 = FLEX_INT0_IRQn, - CHANNEL1 = FLEX_INT1_IRQn, - CHANNEL2 = FLEX_INT2_IRQn, - CHANNEL3 = FLEX_INT3_IRQn, - CHANNEL4 = FLEX_INT4_IRQn, - CHANNEL5 = FLEX_INT5_IRQn, - CHANNEL6 = FLEX_INT6_IRQn, - CHANNEL7 = FLEX_INT7_IRQn -} Channel; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501_IBDAP/device.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501_IBDAP/device.h deleted file mode 100644 index 5d57c9de571..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501_IBDAP/device.h +++ /dev/null @@ -1,40 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_Y5_MBUG/PinNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_Y5_MBUG/PinNames.h deleted file mode 100644 index 5ba01455890..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_Y5_MBUG/PinNames.h +++ /dev/null @@ -1,140 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2014 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 5 - -typedef enum { - // LPC11U Pin Names - P0_0 = 0, - P0_1 = 1, - P0_2 = 2, - P0_3 = 3, - P0_4 = 4, - P0_5 = 5, - P0_6 = 6, - P0_7 = 7, - P0_8 = 8, - P0_9 = 9, - P0_10 = 10, - P0_11 = 11, - P0_12 = 12, - P0_13 = 13, - P0_14 = 14, - P0_15 = 15, - P0_16 = 16, - P0_17 = 17, - P0_18 = 18, - P0_19 = 19, - P0_20 = 20, - P0_21 = 21, - P0_22 = 22, - P0_23 = 23, - P0_24 = 24, - P0_25 = 25, - P0_26 = 26, - P0_27 = 27, - - P1_0 = 32, - P1_1 = 33, - P1_2 = 34, - P1_3 = 35, - P1_4 = 36, - P1_5 = 37, - P1_6 = 38, - P1_7 = 39, - P1_8 = 40, - P1_9 = 41, - P1_10 = 42, - P1_11 = 43, - P1_12 = 44, - P1_13 = 45, - P1_14 = 46, - P1_15 = 47, - P1_16 = 48, - P1_17 = 49, - P1_18 = 50, - P1_19 = 51, - P1_20 = 52, - P1_21 = 53, - P1_22 = 54, - P1_23 = 55, - P1_24 = 56, - P1_25 = 57, - P1_26 = 58, - P1_27 = 59, - P1_28 = 60, - P1_29 = 61, - - P1_31 = 63, - - // Not connected - NC = (int)0xFFFFFFFF, - - // Other mbed Pin Names - LED1 = P0_20, //Approved - LED2 = P0_9, //Approved - LED3 = P0_11, //Approved - LED4 = NC, - - UART_TX = P0_19, - UART_RX = P0_18, - - - - // Standard but not supported pins - USBTX = NC, - USBRX = NC - -} PinName; - -typedef enum { - CHANNEL0 = FLEX_INT0_IRQn, - CHANNEL1 = FLEX_INT1_IRQn, - CHANNEL2 = FLEX_INT2_IRQn, - CHANNEL3 = FLEX_INT3_IRQn, - CHANNEL4 = FLEX_INT4_IRQn, - CHANNEL5 = FLEX_INT5_IRQn, - CHANNEL6 = FLEX_INT6_IRQn, - CHANNEL7 = FLEX_INT7_IRQn -} Channel; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_Y5_MBUG/device.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_Y5_MBUG/device.h deleted file mode 100644 index 5d57c9de571..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_Y5_MBUG/device.h +++ /dev/null @@ -1,40 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/PeripheralNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/PeripheralNames.h deleted file mode 100644 index a6130fd4ee3..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/PeripheralNames.h +++ /dev/null @@ -1,91 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)LPC_USART_BASE -} UARTName; - -typedef enum { - I2C_0 = (int)LPC_I2C_BASE -} I2CName; - -typedef enum { - ADC0_0 = 0, - ADC0_1, - ADC0_2, - ADC0_3, - ADC0_4, - ADC0_5, - ADC0_6, - ADC0_7 -} ADCName; - -typedef enum { - SPI_0 = (int)LPC_SSP0_BASE, - SPI_1 = (int)LPC_SSP1_BASE -} SPIName; - -typedef enum { - PWM_1 = 0, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - PWM_7, - PWM_8, - PWM_9, - PWM_10, - PWM_11, - PWM_12, - PWM_13 -} PWMName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_0 - -// Default peripherals -#define MBED_SPI0 P0_9, P0_8, P0_6, P0_2 // MOSI, MISO, CLK, SEL -#define MBED_SPI1 P0_21, P0_22, P1_15, P01_19 // MOSI, MISO, CLK, SEL - -#define MBED_UART0 USBTX, USBRX -#define MBED_UARTUSB USBTX, USBRX - -#define MBED_I2C0 P0_5, P0_4 - -#define MBED_ANALOGIN0 P0_11 -#define MBED_ANALOGIN1 P0_12 -#define MBED_ANALOGIN2 P0_13 -#define MBED_ANALOGIN3 P0_14 -#define MBED_ANALOGIN4 P0_15 -#define MBED_ANALOGIN5 P0_16 -#define MBED_ANALOGIN6 P0_22 -#define MBED_ANALOGIN7 P0_23 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/PeripheralPins.c b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/PeripheralPins.c deleted file mode 100644 index 8819609c3ea..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/PeripheralPins.c +++ /dev/null @@ -1,106 +0,0 @@ - -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {P0_11, ADC0_0, 0x02}, - {P0_12, ADC0_1, 0x02}, - {P0_13, ADC0_2, 0x02}, - {P0_14, ADC0_3, 0x02}, - {P0_15, ADC0_4, 0x02}, - {P0_16, ADC0_5, 0x01}, - {P0_22, ADC0_6, 0x01}, - {P0_23, ADC0_7, 0x01}, - {NC , NC , 0 } -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {P0_5, I2C_0, 1}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {P0_4, I2C_0, 1}, - {NC , NC, 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {P0_19, UART_0, 1}, - { NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {P0_18, UART_0, 1}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {P0_6 , SPI_0, 0x02}, - {P0_10, SPI_0, 0x02}, - {P1_15, SPI_1, 0x03}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {P0_9 , SPI_0, 0x01}, - {P0_21, SPI_1, 0x02}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {P0_8 , SPI_0, 0x01}, - {P0_22, SPI_1, 0x03}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {P0_2 , SPI_0, 0x01}, - {P1_19, SPI_1, 0x02}, - {NC , NC , 0} -}; - -/************PWM***************/ -const PinMap PinMap_PWM[] = { - /* CT16B0 */ - {P0_8 , PWM_1, 2}, /* MR0 */ - {P0_9 , PWM_2, 2}, /* MR1 */ - {P0_10, PWM_3, 3}, /* MR2 */ - {P1_15, PWM_3, 2}, /* MR2 */ // Same channel as P0_10 - - /* CT16B1 */ - {P0_21, PWM_4, 1}, /* MR0 */ - {P0_22, PWM_5, 2}, /* MR1 */ - - /* CT32B0 */ - {P0_18, PWM_6, 2}, /* MR0 */ - {P0_19, PWM_7, 2}, /* MR1 */ - {P0_1 , PWM_8, 2}, /* MR2 */ - {P0_11, PWM_9, 3}, /* MR3 */ - - /* CT32B1 */ - {P0_13, PWM_10, 3}, /* MR0 */ - {P0_14, PWM_11, 3}, /* MR1 */ - {P0_15, PWM_12, 3}, /* MR2 */ - {P0_16, PWM_13, 2}, /* MR3 */ - - {NC, NC, 0} -}; diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/PinNames.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/PinNames.h deleted file mode 100644 index 272ebe11964..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/PinNames.h +++ /dev/null @@ -1,105 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 5 - -typedef enum { - // LPC11U24 HVQFN33 Pin Names - P0_0 = 0, - P0_1 = 1, - P0_2 = 2, - P0_3 = 3, - P0_4 = 4, - P0_5 = 5, - P0_6 = 6, - P0_7 = 7, - P0_8 = 8, - P0_9 = 9, - P0_10 = 10, - P0_11 = 11, - P0_12 = 12, - P0_13 = 13, - P0_14 = 14, - P0_15 = 15, - P0_16 = 16, - P0_17 = 17, - P0_18 = 18, - P0_19 = 19, - P0_20 = 20, - P0_21 = 21, - P0_22 = 22, - P0_23 = 23, - - P1_15 = 47, - P1_19 = 51, - - // Other mbed Pin Names - LED1 = P0_7, - LED2 = P0_8, - LED3 = P0_2, - LED4 = P0_20, - LED5 = P1_19, - LED6 = P0_17, - LED7 = P0_23, - - USBTX = P0_19, - USBRX = P0_18, - - I2C_SCL = P0_4, - I2C_SDA = P0_5, - - // Not connected - NC = (int)0xFFFFFFFF, -} PinName; - -typedef enum { - CHANNEL0 = FLEX_INT0_IRQn, - CHANNEL1 = FLEX_INT1_IRQn, - CHANNEL2 = FLEX_INT2_IRQn, - CHANNEL3 = FLEX_INT3_IRQn, - CHANNEL4 = FLEX_INT4_IRQn, - CHANNEL5 = FLEX_INT5_IRQn, - CHANNEL6 = FLEX_INT6_IRQn, - CHANNEL7 = FLEX_INT7_IRQn -} Channel; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/device.h b/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/device.h deleted file mode 100644 index 5d57c9de571..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/device.h +++ /dev/null @@ -1,40 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/analogin_api.c b/targets/TARGET_NXP/TARGET_LPC11UXX/analogin_api.c deleted file mode 100644 index 87dad12feb0..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/analogin_api.c +++ /dev/null @@ -1,119 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogin_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" // For the Peripheral to Pin Definitions found in the individual Target's Platform - -#define ANALOGIN_MEDIAN_FILTER 1 - -#define ADC_10BIT_RANGE 0x3FF -#define ADC_12BIT_RANGE 0xFFF - -static inline int div_round_up(int x, int y) { - return (x + (y - 1)) / y; -} - -#define LPC_IOCON0_BASE (LPC_IOCON_BASE) -#define LPC_IOCON1_BASE (LPC_IOCON_BASE + 0x60) - -#define ADC_RANGE ADC_10BIT_RANGE - -void analogin_init(analogin_t *obj, PinName pin) { - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - // Power up ADC - LPC_SYSCON->PDRUNCFG &= ~ (1 << 4); - LPC_SYSCON->SYSAHBCLKCTRL |= ((uint32_t)1 << 13); - - uint32_t pin_number = (uint32_t)pin; - __IO uint32_t *reg = (pin_number < 32) ? (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) : (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32)); - - // set pin to ADC mode - *reg &= ~(1 << 7); // set ADMODE = 0 (analog mode) - - uint32_t PCLK = SystemCoreClock; - uint32_t MAX_ADC_CLK = 4500000; - uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1; - - LPC_ADC->CR = (0 << 0) // no channels selected - | (clkdiv << 8) // max of 4.5MHz - | (0 << 16) // BURST = 0, software controlled - | ( 0 << 17 ); // CLKS = 0, not applicable - - pinmap_pinout(pin, PinMap_ADC); -} - -static inline uint32_t adc_read(analogin_t *obj) { - // Select the appropriate channel and start conversion - LPC_ADC->CR &= ~0xFF; - LPC_ADC->CR |= 1 << (int)obj->adc; - LPC_ADC->CR |= 1 << 24; - - // Repeatedly get the sample data until DONE bit - unsigned int data; - do { - data = LPC_ADC->GDR; - } while ((data & ((unsigned int)1 << 31)) == 0); - - // Stop conversion - LPC_ADC->CR &= ~(1 << 24); - - return (data >> 6) & ADC_RANGE; // 10 bit -} - -static inline void order(uint32_t *a, uint32_t *b) { - if (*a > *b) { - uint32_t t = *a; - *a = *b; - *b = t; - } -} - -static inline uint32_t adc_read_u32(analogin_t *obj) { - uint32_t value; -#if ANALOGIN_MEDIAN_FILTER - uint32_t v1 = adc_read(obj); - uint32_t v2 = adc_read(obj); - uint32_t v3 = adc_read(obj); - order(&v1, &v2); - order(&v2, &v3); - order(&v1, &v2); - value = v2; -#else - value = adc_read(obj); -#endif - return value; -} - -uint16_t analogin_read_u16(analogin_t *obj) { - uint32_t value = adc_read_u32(obj); - - return (value << 6) | ((value >> 4) & 0x003F); // 10 bit -} - -float analogin_read(analogin_t *obj) { - uint32_t value = adc_read_u32(obj); - return (float)value * (1.0f / (float)ADC_RANGE); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/LPC11Uxx.h b/targets/TARGET_NXP/TARGET_LPC11UXX/device/LPC11Uxx.h deleted file mode 100644 index bc3f737aa61..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/LPC11Uxx.h +++ /dev/null @@ -1,670 +0,0 @@ - -/****************************************************************************************************//** - * @file LPC11Uxx.h - * - * - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for - * default LPC11Uxx Device Series - * - * @version V0.1 - * @date 21. March 2011 - * - * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45 - * - * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1, - * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40 - * - *******************************************************************************************************/ - -// ################################################################################ -// Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000 -// ################################################################################ - -/** @addtogroup NXP - * @{ - */ - -/** @addtogroup LPC11Uxx - * @{ - */ - -#ifndef __LPC11UXX_H__ -#define __LPC11UXX_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -#if defined ( __CC_ARM ) - #pragma anon_unions -#endif - - /* Interrupt Number Definition */ - -typedef enum { -// ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------ -FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */ - FLEX_INT1_IRQn = 1, - FLEX_INT2_IRQn = 2, - FLEX_INT3_IRQn = 3, - FLEX_INT4_IRQn = 4, - FLEX_INT5_IRQn = 5, - FLEX_INT6_IRQn = 6, - FLEX_INT7_IRQn = 7, - GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */ - GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */ - Reserved0_IRQn = 10, /*!< Reserved Interrupt */ - Reserved1_IRQn = 11, - Reserved2_IRQn = 12, - Reserved3_IRQn = 13, - SSP1_IRQn = 14, /*!< SSP1 Interrupt */ - I2C_IRQn = 15, /*!< I2C Interrupt */ - TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */ - TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */ - TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */ - TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */ - SSP0_IRQn = 20, /*!< SSP0 Interrupt */ - UART_IRQn = 21, /*!< UART Interrupt */ - USB_IRQn = 22, /*!< USB IRQ Interrupt */ - USB_FIQn = 23, /*!< USB FIQ Interrupt */ - ADC_IRQn = 24, /*!< A/D Converter Interrupt */ - WDT_IRQn = 25, /*!< Watchdog timer Interrupt */ - BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */ - FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */ - Reserved4_IRQn = 28, /*!< Reserved Interrupt */ - Reserved5_IRQn = 29, /*!< Reserved Interrupt */ - USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */ - Reserved6_IRQn = 31, /*!< Reserved Interrupt */ -} IRQn_Type; - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */ - -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ -#include "system_LPC11Uxx.h" /*!< LPC11Uxx System */ - -/** @addtogroup Device_Peripheral_Registers - * @{ - */ - - -// ------------------------------------------------------------------------------------------------ -// ----- I2C ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C) - */ - -typedef struct { /*!< (@ 0x40000000) I2C Structure */ - __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */ - __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */ - __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */ - __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */ - __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */ - __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */ - __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/ - __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/ - __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/ - __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/ - __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/ - __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */ -union{ - __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */ - struct{ - __IO uint32_t MASK0; - __IO uint32_t MASK1; - __IO uint32_t MASK2; - __IO uint32_t MASK3; - }; - }; -} LPC_I2C_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- WWDT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT) - */ - -typedef struct { /*!< (@ 0x40004000) WWDT Structure */ - __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/ - __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */ - __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */ - __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */ - __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */ - __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */ - __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */ -} LPC_WWDT_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- USART ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART) - */ - -typedef struct { /*!< (@ 0x40008000) USART Structure */ - - union { - __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ - __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */ - __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */ - }; - - union { - __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */ - __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ - }; - - union { - __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */ - __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */ - }; - __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */ - __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */ - __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */ - __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */ - __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */ - __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */ - __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */ - __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */ - __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */ - __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */ - __I uint32_t RESERVED0[3]; - __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */ - __I uint32_t RESERVED1; - __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */ - __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ - __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ - __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */ - __IO uint32_t SYNCCTRL; -} LPC_USART_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- Timer ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3 - */ - -typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */ - __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */ - __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */ - __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */ - __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */ - __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */ - __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */ - union { - __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */ - struct{ - __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */ - __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */ - __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */ - __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */ - }; - }; - __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */ - union{ - __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */ - struct{ - __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */ - __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */ - __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */ - __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */ - }; - }; -__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */ - __I uint32_t RESERVED0[12]; - __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */ - __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */ -} LPC_CTxxBx_Type; - - - -// ------------------------------------------------------------------------------------------------ -// ----- ADC ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC) - */ - -typedef struct { /*!< (@ 0x4001C000) ADC Structure */ - __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */ - __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */ - __I uint32_t RESERVED0[1]; - __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */ - union{ - __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/ - struct{ - __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/ - __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/ - __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/ - __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/ - __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/ - __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/ - __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/ - __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/ - }; - }; - __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */ -} LPC_ADC_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- PMU ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU) - */ - -typedef struct { /*!< (@ 0x40038000) PMU Structure */ - __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */ - union{ - __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */ - struct{ - __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */ - __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */ - __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */ - __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */ - }; - }; -} LPC_PMU_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- FLASHCTRL ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL) - */ - -typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */ - __I uint32_t RESERVED0[4]; - __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */ - __I uint32_t RESERVED1[3]; - __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */ - __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */ - __I uint32_t RESERVED2[1]; - __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */ - __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */ - __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */ - __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */ - __I uint32_t RESERVED3[1001]; - __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */ - __I uint32_t RESERVED4[1]; - __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */ -} LPC_FLASHCTRL_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- SSP0/1 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0) - */ - -typedef struct { /*!< (@ 0x40040000) SSP0 Structure */ - __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */ - __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */ - __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */ - __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */ - __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */ - __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */ - __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */ - __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */ - __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */ -} LPC_SSPx_Type; - - - -// ------------------------------------------------------------------------------------------------ -// ----- IOCONFIG ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG) - */ - -typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */ - __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */ - __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */ - __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */ - __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */ - __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */ - __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */ - __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */ - __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */ - __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */ - __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */ - __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */ - __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */ - __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */ - __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */ - __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */ - __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */ - __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */ - __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */ - __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */ - __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */ - __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */ - __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */ - __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */ - __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */ - __IO uint32_t PIO1_0; /*!< Offset: 0x060 */ - __IO uint32_t PIO1_1; - __IO uint32_t PIO1_2; - __IO uint32_t PIO1_3; - __IO uint32_t PIO1_4; /*!< Offset: 0x070 */ - __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */ - __IO uint32_t PIO1_6; - __IO uint32_t PIO1_7; - __IO uint32_t PIO1_8; /*!< Offset: 0x080 */ - __IO uint32_t PIO1_9; - __IO uint32_t PIO1_10; - __IO uint32_t PIO1_11; - __IO uint32_t PIO1_12; /*!< Offset: 0x090 */ - __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */ - __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */ - __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */ - __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */ - __IO uint32_t PIO1_17; - __IO uint32_t PIO1_18; - __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */ - __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */ - __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */ - __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */ - __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */ - __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */ - __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */ - __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */ - __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */ - __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */ - __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */ - __IO uint32_t PIO1_30; - __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */ -} LPC_IOCON_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- SYSCON ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON) - */ - -typedef struct { /*!< (@ 0x40048000) SYSCON Structure */ - __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */ - __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */ - __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */ - __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */ - __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */ - __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */ - __I uint32_t RESERVED0[2]; - __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */ - __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */ - __I uint32_t RESERVED1[2]; - __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */ - __I uint32_t RESERVED2[3]; - __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */ - __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */ - __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */ - __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */ - __I uint32_t RESERVED3[8]; - __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */ - __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */ - __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */ - __I uint32_t RESERVED4[1]; - __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */ - __I uint32_t RESERVED5[4]; - __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */ - __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */ - __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */ - __I uint32_t RESERVED6[8]; - __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */ - __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */ - __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */ - __I uint32_t RESERVED7[5]; - __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */ - __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */ - __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */ - __I uint32_t RESERVED8[5]; - __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */ - __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */ - __I uint32_t RESERVED9[18]; - __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */ - __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */ - __I uint32_t RESERVED10[6]; - __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */ - __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */ - __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */ - __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */ - __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */ - __I uint32_t RESERVED11[25]; - __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */ - __I uint32_t RESERVED12[3]; - __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */ - __I uint32_t RESERVED13[6]; - __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */ - __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */ - __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */ - __I uint32_t RESERVED14[110]; - __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */ -} LPC_SYSCON_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PIN_INT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT) - */ - -typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */ - __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */ - __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */ - __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */ - __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */ - __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ - __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */ - __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */ - __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */ -} LPC_GPIO_PIN_INT_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_GROUP_INT0/1 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0) - */ - -typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */ - __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */ - __I uint32_t RESERVED0[7]; - __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */ - __I uint32_t RESERVED1[6]; - __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */ -} LPC_GPIO_GROUP_INTx_Type; - - - -// ------------------------------------------------------------------------------------------------ -// ----- USB ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB) - */ - -typedef struct { /*!< (@ 0x40080000) USB Structure */ - __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */ - __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */ - __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */ - __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */ - __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */ - __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */ - __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */ - __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */ - __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */ - __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */ - __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */ - __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */ - __I uint32_t RESERVED0[1]; - __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */ -} LPC_USB_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PORT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT) - */ - -typedef struct { - union { - struct { - __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */ - __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */ - }; - __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */ - }; - __I uint32_t RESERVED0[1008]; - union { - struct { - __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */ - __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */ - }; - __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */ - }; - uint32_t RESERVED1[960]; - __IO uint32_t DIR[2]; /* 0x2000 */ - uint32_t RESERVED2[30]; - __IO uint32_t MASK[2]; /* 0x2080 */ - uint32_t RESERVED3[30]; - __IO uint32_t PIN[2]; /* 0x2100 */ - uint32_t RESERVED4[30]; - __IO uint32_t MPIN[2]; /* 0x2180 */ - uint32_t RESERVED5[30]; - __IO uint32_t SET[2]; /* 0x2200 */ - uint32_t RESERVED6[30]; - __O uint32_t CLR[2]; /* 0x2280 */ - uint32_t RESERVED7[30]; - __O uint32_t NOT[2]; /* 0x2300 */ -} LPC_GPIO_Type; - - -#if defined ( __CC_ARM ) - #pragma no_anon_unions -#endif - - -// ------------------------------------------------------------------------------------------------ -// ----- Peripheral memory map ----- -// ------------------------------------------------------------------------------------------------ - -#define LPC_I2C_BASE (0x40000000) -#define LPC_WWDT_BASE (0x40004000) -#define LPC_USART_BASE (0x40008000) -#define LPC_CT16B0_BASE (0x4000C000) -#define LPC_CT16B1_BASE (0x40010000) -#define LPC_CT32B0_BASE (0x40014000) -#define LPC_CT32B1_BASE (0x40018000) -#define LPC_ADC_BASE (0x4001C000) -#define LPC_PMU_BASE (0x40038000) -#define LPC_FLASHCTRL_BASE (0x4003C000) -#define LPC_SSP0_BASE (0x40040000) -#define LPC_SSP1_BASE (0x40058000) -#define LPC_IOCON_BASE (0x40044000) -#define LPC_SYSCON_BASE (0x40048000) -#define LPC_GPIO_PIN_INT_BASE (0x4004C000) -#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000) -#define LPC_GPIO_GROUP_INT1_BASE (0x40060000) -#define LPC_USB_BASE (0x40080000) -#define LPC_GPIO_BASE (0x50000000) - - -// ------------------------------------------------------------------------------------------------ -// ----- Peripheral declaration ----- -// ------------------------------------------------------------------------------------------------ - -#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE) -#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE) -#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE) -#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE) -#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE) -#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE) -#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE) -#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE) -#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE) -#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE) -#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE) -#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE) -#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE) -#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE) -#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE) -#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE) -#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE) -#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE) -#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE) - - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group (null) */ -/** @} */ /* End of group LPC11Uxx */ - -#ifdef __cplusplus -} -#endif - - -#endif // __LPC11UXX_H__ diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_301/LPC11U24.sct b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_301/LPC11U24.sct deleted file mode 100644 index 92160daf1d2..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_301/LPC11U24.sct +++ /dev/null @@ -1,52 +0,0 @@ -#! armcc -E - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -; 32K flash -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x8000 -#endif - -; 6KB -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x10000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00001800 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 -#define VECTOR_SIZE 0xC0 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM - .ANY (USBRAM) - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_301/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_301/startup_LPC11xx.S deleted file mode 100644 index 6d5aa187654..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_301/startup_LPC11xx.S +++ /dev/null @@ -1,308 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_401/LPC11U24.sct b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_401/LPC11U24.sct deleted file mode 100644 index d57cef75e16..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_401/LPC11U24.sct +++ /dev/null @@ -1,52 +0,0 @@ -#! armcc -E - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -; 32K flash -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x8000 -#endif - -; 8KB -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x10000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00002000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 -#define VECTOR_SIZE 0xC0 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM - .ANY (USBRAM) - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_401/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_401/startup_LPC11xx.S deleted file mode 100644 index 6d5aa187654..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_401/startup_LPC11xx.S +++ /dev/null @@ -1,308 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/LPC11U34.sct b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/LPC11U34.sct deleted file mode 100644 index 478f7a63503..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/LPC11U34.sct +++ /dev/null @@ -1,52 +0,0 @@ -#! armcc -E - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -; 48K flash -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0xC000 -#endif - -; 8KB -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x10000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00002000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 -#define VECTOR_SIZE 0xC0 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM - .ANY (USBRAM) - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/startup_LPC11xx.S deleted file mode 100644 index 6d5aa187654..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/startup_LPC11xx.S +++ /dev/null @@ -1,308 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_401/LPC11U35.sct b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_401/LPC11U35.sct deleted file mode 100644 index 9c5c0c3b2d9..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_401/LPC11U35.sct +++ /dev/null @@ -1,52 +0,0 @@ -#! armcc -E - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -; 64K flash -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x10000 -#endif - -; 8KB -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x10000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00002000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 -#define VECTOR_SIZE 0xC0 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM - .ANY (USBRAM) - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_401/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_401/startup_LPC11xx.S deleted file mode 100644 index 6d5aa187654..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_401/startup_LPC11xx.S +++ /dev/null @@ -1,308 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/LPC11U37.sct b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/LPC11U37.sct deleted file mode 100644 index 27da59da172..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/LPC11U37.sct +++ /dev/null @@ -1,56 +0,0 @@ -#! armcc -E - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -; 128K flash -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x20000 -#endif - -; 8KB -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x10000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00002000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 -#define VECTOR_SIZE 0xC0 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM - .ANY (IOHANDLER_RAM) - } - - RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM - .ANY (USBRAM) - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/startup_LPC11xx.S deleted file mode 100644 index 1211625163a..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/startup_LPC11xx.S +++ /dev/null @@ -1,308 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37_501/LPC11U37.sct b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37_501/LPC11U37.sct deleted file mode 100644 index 27da59da172..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37_501/LPC11U37.sct +++ /dev/null @@ -1,56 +0,0 @@ -#! armcc -E - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -; 128K flash -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x20000 -#endif - -; 8KB -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x10000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00002000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 -#define VECTOR_SIZE 0xC0 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM - .ANY (IOHANDLER_RAM) - } - - RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM - .ANY (USBRAM) - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37_501/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37_501/startup_LPC11xx.S deleted file mode 100644 index 1211625163a..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37_501/startup_LPC11xx.S +++ /dev/null @@ -1,308 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/LPC11U35.sct b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/LPC11U35.sct deleted file mode 100644 index bfd38306be9..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/LPC11U35.sct +++ /dev/null @@ -1,56 +0,0 @@ -#! armcc -E - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -; 128K flash -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x10000 -#endif - -; 8KB -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x10000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00002000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 -#define VECTOR_SIZE 0xC0 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM - .ANY (IOHANDLER_RAM) - } - - RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM - .ANY (USBRAM) - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/startup_LPC11xx.S deleted file mode 100644 index 6d5aa187654..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/startup_LPC11xx.S +++ /dev/null @@ -1,308 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_OC_MBUINO/LPC11U24.sct b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_OC_MBUINO/LPC11U24.sct deleted file mode 100644 index db5dfc9dd32..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_OC_MBUINO/LPC11U24.sct +++ /dev/null @@ -1,52 +0,0 @@ -#! armcc -E - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -; 128K flash -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x8000 -#endif - -; 8KB (0x2000) -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x10000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00001800 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 -#define VECTOR_SIZE 0xC0 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM - .ANY (USBRAM) - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_OC_MBUINO/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_OC_MBUINO/startup_LPC11xx.S deleted file mode 100644 index 6d5aa187654..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_OC_MBUINO/startup_LPC11xx.S +++ /dev/null @@ -1,308 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_301/LPC11U24.sct b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_301/LPC11U24.sct deleted file mode 100644 index bcd213ebb52..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_301/LPC11U24.sct +++ /dev/null @@ -1,26 +0,0 @@ -#! armcc -E - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k) - ER_IROM1 0x00000000 0x8000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 - ; 6KB - 0xC0 = 0x1740 - RW_IRAM1 0x100000C0 0x1740-Stack_Size { - .ANY (+RW +ZI) - } - ARM_LIB_STACK (0x100000C0+0x1740) EMPTY -Stack_Size { ; stack - } - RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM - .ANY (USBRAM) - } -} - diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_301/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_301/startup_LPC11xx.S deleted file mode 100644 index 69346881f38..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_301/startup_LPC11xx.S +++ /dev/null @@ -1,307 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_401/LPC11U24.sct b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_401/LPC11U24.sct deleted file mode 100644 index 36e3a42330a..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_401/LPC11U24.sct +++ /dev/null @@ -1,26 +0,0 @@ -#! armcc -E - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k) - ER_IROM1 0x00000000 0x8000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 - ; 8KB - 0xC0 = 0x1F40 - RW_IRAM1 0x100000C0 0x1F40-Stack_Size { - .ANY (+RW +ZI) - } - ARM_LIB_STACK (0x100000C0+0x1F40) EMPTY -Stack_Size { ; stack - } - RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM - .ANY (USBRAM) - } -} - diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_401/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_401/startup_LPC11xx.S deleted file mode 100644 index 69346881f38..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_401/startup_LPC11xx.S +++ /dev/null @@ -1,307 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/LPC11U34.sct b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/LPC11U34.sct deleted file mode 100644 index 23f4dac75c2..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/LPC11U34.sct +++ /dev/null @@ -1,26 +0,0 @@ -#! armcc -E - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k) - ER_IROM1 0x00000000 0xC000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 - ; 8KB - 0xC0 = 0x1F40 - RW_IRAM1 0x100000C0 0x1F40-Stack_Size { - .ANY (+RW +ZI) - } - ARM_LIB_STACK (0x100000C0+0x1F40) EMPTY -Stack_Size { ; stack - } - RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM - .ANY (USBRAM) - } -} - diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/startup_LPC11xx.S deleted file mode 100644 index 69346881f38..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/startup_LPC11xx.S +++ /dev/null @@ -1,307 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_401/LPC11U35.sct b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_401/LPC11U35.sct deleted file mode 100644 index edf8fb023f4..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_401/LPC11U35.sct +++ /dev/null @@ -1,26 +0,0 @@ -#! armcc -E - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x00000000 0x10000 { ; load region size_region (64k) - ER_IROM1 0x00000000 0x10000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 - ; 8KB - 0xC0 = 0x1F40 - RW_IRAM1 0x100000C0 0x1F40-Stack_Size { - .ANY (+RW +ZI) - } - ARM_LIB_STACK (0x100000C0+0x1F40) EMPTY -Stack_Size { ; stack - } - RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM - .ANY (USBRAM) - } -} - diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_401/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_401/startup_LPC11xx.S deleted file mode 100644 index 69346881f38..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_401/startup_LPC11xx.S +++ /dev/null @@ -1,307 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_501/LPC11U35.sct b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_501/LPC11U35.sct deleted file mode 100644 index 4ea27ceb6c9..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_501/LPC11U35.sct +++ /dev/null @@ -1,29 +0,0 @@ -#! armcc -E - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x00000000 0x10000 { ; load region size_region (64k) - ER_IROM1 0x00000000 0x10000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 - ; 8KB - 0xC0 = 0x1F40 - RW_IRAM1 0x100000C0 0x1F40-Stack_Size { - .ANY (+RW +ZI) - } - ARM_LIB_STACK (0x100000C0+0x1F40) EMPTY -Stack_Size { ; stack - } - RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM - .ANY (IOHANDLER_RAM) - } - RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM - .ANY (USBRAM) - } -} - diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_501/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_501/startup_LPC11xx.S deleted file mode 100644 index 69346881f38..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_501/startup_LPC11xx.S +++ /dev/null @@ -1,307 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/LPC11U37.sct b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/LPC11U37.sct deleted file mode 100644 index 7d37c2b52e3..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/LPC11U37.sct +++ /dev/null @@ -1,29 +0,0 @@ -#! armcc -E - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x00000000 0x20000 { ; load region size_region (128K) - ER_IROM1 0x00000000 0x10000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 - ; 8KB - 0xC0 = 0x1F40 - RW_IRAM1 0x100000C0 0x1F40-Stack_Size { - .ANY (+RW +ZI) - } - ARM_LIB_STACK (0x100000C0+0x1F40) EMPTY -Stack_Size { ; stack - } - RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM - .ANY (IOHANDLER_RAM) - } - RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM - .ANY (USBRAM) - } -} - diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/startup_LPC11xx.S deleted file mode 100644 index 6576878acdb..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/startup_LPC11xx.S +++ /dev/null @@ -1,307 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U37_501/LPC11U37.sct b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U37_501/LPC11U37.sct deleted file mode 100644 index 7d37c2b52e3..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U37_501/LPC11U37.sct +++ /dev/null @@ -1,29 +0,0 @@ -#! armcc -E - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x00000000 0x20000 { ; load region size_region (128K) - ER_IROM1 0x00000000 0x10000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 - ; 8KB - 0xC0 = 0x1F40 - RW_IRAM1 0x100000C0 0x1F40-Stack_Size { - .ANY (+RW +ZI) - } - ARM_LIB_STACK (0x100000C0+0x1F40) EMPTY -Stack_Size { ; stack - } - RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM - .ANY (IOHANDLER_RAM) - } - RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM - .ANY (USBRAM) - } -} - diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U37_501/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U37_501/startup_LPC11xx.S deleted file mode 100644 index 6576878acdb..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U37_501/startup_LPC11xx.S +++ /dev/null @@ -1,307 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_OC_MBUINO/LPC11U24.sct b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_OC_MBUINO/LPC11U24.sct deleted file mode 100644 index bcd213ebb52..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_OC_MBUINO/LPC11U24.sct +++ /dev/null @@ -1,26 +0,0 @@ -#! armcc -E - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k) - ER_IROM1 0x00000000 0x8000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 - ; 6KB - 0xC0 = 0x1740 - RW_IRAM1 0x100000C0 0x1740-Stack_Size { - .ANY (+RW +ZI) - } - ARM_LIB_STACK (0x100000C0+0x1740) EMPTY -Stack_Size { ; stack - } - RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM - .ANY (USBRAM) - } -} - diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_OC_MBUINO/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_OC_MBUINO/startup_LPC11xx.S deleted file mode 100644 index 69346881f38..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_OC_MBUINO/startup_LPC11xx.S +++ /dev/null @@ -1,307 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC11xx.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * for the NXP LPC11xx Device Series -; * @version: V1.0 -; * @date: 25. Nov. 2008 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2008 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - ; for LPC11Uxx (With USB) - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Reserved_IRQHandler PROC - EXPORT Reserved_IRQHandler [WEAK] - B . - ENDP - -Default_Handler PROC -; for LPC11Uxx (With USB) - EXPORT NMI_Handler [WEAK] - EXPORT FLEX_INT0_IRQHandler [WEAK] - EXPORT FLEX_INT1_IRQHandler [WEAK] - EXPORT FLEX_INT2_IRQHandler [WEAK] - EXPORT FLEX_INT3_IRQHandler [WEAK] - EXPORT FLEX_INT4_IRQHandler [WEAK] - EXPORT FLEX_INT5_IRQHandler [WEAK] - EXPORT FLEX_INT6_IRQHandler [WEAK] - EXPORT FLEX_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT TIMER16_0_IRQHandler [WEAK] - EXPORT TIMER16_1_IRQHandler [WEAK] - EXPORT TIMER32_0_IRQHandler [WEAK] - EXPORT TIMER32_1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT UART_IRQHandler [WEAK] - - EXPORT USB_IRQHandler [WEAK] - EXPORT USB_FIQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT USBWakeup_IRQHandler [WEAK] - -NMI_Handler -FLEX_INT0_IRQHandler -FLEX_INT1_IRQHandler -FLEX_INT2_IRQHandler -FLEX_INT3_IRQHandler -FLEX_INT4_IRQHandler -FLEX_INT5_IRQHandler -FLEX_INT6_IRQHandler -FLEX_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -SSP1_IRQHandler -I2C_IRQHandler -TIMER16_0_IRQHandler -TIMER16_1_IRQHandler -TIMER32_0_IRQHandler -TIMER32_1_IRQHandler -SSP0_IRQHandler -UART_IRQHandler -USB_IRQHandler -USB_FIQHandler -ADC_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -FMC_IRQHandler -USBWakeup_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_301/LPC11U24.ld b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_301/LPC11U24.ld deleted file mode 100644 index 6bed1c00ef6..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_301/LPC11U24.ld +++ /dev/null @@ -1,161 +0,0 @@ -/* Linker script for mbed LPC1768 */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Linker script to configure memory regions. */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K - RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1740 - USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - *(.text.SystemInit) - - /* Only vectors and code running at reset are safe to be in first 512 - bytes since RAM can be mapped into this area for RAM based interrupt - vectors. */ - . = 0x00000200; - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_401/LPC11U24.ld b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_401/LPC11U24.ld deleted file mode 100644 index 122fa8cc772..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_401/LPC11U24.ld +++ /dev/null @@ -1,161 +0,0 @@ -/* Linker script for mbed LPC1768 */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Linker script to configure memory regions. */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K - RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 - USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - *(.text.SystemInit) - - /* Only vectors and code running at reset are safe to be in first 512 - bytes since RAM can be mapped into this area for RAM based interrupt - vectors. */ - . = 0x00000200; - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U34_421/LPC11U34.ld b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U34_421/LPC11U34.ld deleted file mode 100644 index 7d15795046b..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U34_421/LPC11U34.ld +++ /dev/null @@ -1,159 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 48K - RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 - USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - - /* Only vectors and code running at reset are safe to be in first 512 - bytes since RAM can be mapped into this area for RAM based interrupt - vectors. */ - . = 0x00000200; - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_401/LPC11U35.ld b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_401/LPC11U35.ld deleted file mode 100644 index 876f1f932a6..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_401/LPC11U35.ld +++ /dev/null @@ -1,159 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K - RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 - USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - - /* Only vectors and code running at reset are safe to be in first 512 - bytes since RAM can be mapped into this area for RAM based interrupt - vectors. */ - . = 0x00000200; - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_501/LPC11U35.ld b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_501/LPC11U35.ld deleted file mode 100644 index 876f1f932a6..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_501/LPC11U35.ld +++ /dev/null @@ -1,159 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K - RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 - USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - - /* Only vectors and code running at reset are safe to be in first 512 - bytes since RAM can be mapped into this area for RAM based interrupt - vectors. */ - . = 0x00000200; - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_Y5_MBUG/LPC11U35.ld b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_Y5_MBUG/LPC11U35.ld deleted file mode 100644 index 876f1f932a6..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_Y5_MBUG/LPC11U35.ld +++ /dev/null @@ -1,159 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K - RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 - USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - - /* Only vectors and code running at reset are safe to be in first 512 - bytes since RAM can be mapped into this area for RAM based interrupt - vectors. */ - . = 0x00000200; - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37H_401/LPC11U37.ld b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37H_401/LPC11U37.ld deleted file mode 100644 index 56800d54312..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37H_401/LPC11U37.ld +++ /dev/null @@ -1,160 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K - RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 - RAMIO (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 - USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - - /* Only vectors and code running at reset are safe to be in first 512 - bytes since RAM can be mapped into this area for RAM based interrupt - vectors. */ - . = 0x00000200; - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37_501/LPC11U37.ld b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37_501/LPC11U37.ld deleted file mode 100644 index 15d44a9adef..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37_501/LPC11U37.ld +++ /dev/null @@ -1,159 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K - RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 - USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - - /* Only vectors and code running at reset are safe to be in first 512 - bytes since RAM can be mapped into this area for RAM based interrupt - vectors. */ - . = 0x00000200; - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPCCAPPUCCINO/LPC11U37.ld b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPCCAPPUCCINO/LPC11U37.ld deleted file mode 100644 index 15d44a9adef..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPCCAPPUCCINO/LPC11U37.ld +++ /dev/null @@ -1,159 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K - RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 - USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - - /* Only vectors and code running at reset are safe to be in first 512 - bytes since RAM can be mapped into this area for RAM based interrupt - vectors. */ - . = 0x00000200; - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_OC_MBUINO/LPC11U24.ld b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_OC_MBUINO/LPC11U24.ld deleted file mode 100644 index 6bed1c00ef6..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_OC_MBUINO/LPC11U24.ld +++ /dev/null @@ -1,161 +0,0 @@ -/* Linker script for mbed LPC1768 */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Linker script to configure memory regions. */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K - RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1740 - USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - *(.text.SystemInit) - - /* Only vectors and code running at reset are safe to be in first 512 - bytes since RAM can be mapped into this area for RAM based interrupt - vectors. */ - . = 0x00000200; - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/startup_LPC11xx.S deleted file mode 100644 index 2b695fd9207..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/startup_LPC11xx.S +++ /dev/null @@ -1,218 +0,0 @@ -/* File: startup_ARMCM0.S - * Purpose: startup file for Cortex-M0 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.2 - * Date: 15 Nov 2011 - * - * Copyright (c) 2011, ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the ARM Limited nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - .syntax unified - .arch armv6-m - -/* Memory Model - The HEAP starts at the end of the DATA section and grows upward. - - The STACK starts at the end of the RAM and grows downward. - - The HEAP and stack STACK are only checked at compile time: - (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE - - This is just a check for the bare minimum for the Heap+Stack area before - aborting compilation, it is not the run time limit: - Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 - */ - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x80 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x80 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .space Heap_Size - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - -/* LPC11xx interrupts */ - .long WAKEUP_IRQHandler /* 16 0 Wake-up on pin PIO0_0 */ - .long WAKEUP_IRQHandler /* 17 1 Wake-up on pin PIO0_1 */ - .long WAKEUP_IRQHandler /* 18 2 Wake-up on pin PIO0_2 */ - .long WAKEUP_IRQHandler /* 19 3 Wake-up on pin PIO0_3 */ - .long WAKEUP_IRQHandler /* 20 4 Wake-up on pin PIO0_4 */ - .long WAKEUP_IRQHandler /* 21 5 Wake-up on pin PIO0_5 */ - .long WAKEUP_IRQHandler /* 22 6 Wake-up on pin PIO0_6 */ - .long WAKEUP_IRQHandler /* 23 7 Wake-up on pin PIO0_7 */ - .long WAKEUP_IRQHandler /* 24 8 Wake-up on pin PIO0_8 */ - .long WAKEUP_IRQHandler /* 25 9 Wake-up on pin PIO0_9 */ - .long WAKEUP_IRQHandler /* 26 10 Wake-up on pin PIO0_10 */ - .long WAKEUP_IRQHandler /* 27 11 Wake-up on pin PIO0_11 */ - .long WAKEUP_IRQHandler /* 28 12 Wake-up on pin PIO1_0 */ - .long Default_Handler /* 29 13 */ - .long SSP1_IRQHandler /* 30 14 SSP1 */ - .long I2C_IRQHandler /* 31 15 I2C0 SI (state change) */ - .long TIMER16_0_IRQHandler /* 32 16 CT16B0 16 bit timer 0 */ - .long TIMER16_1_IRQHandler /* 33 17 CT16B1 16 bit timer 1 */ - .long TIMER32_0_IRQHandler /* 34 18 CT32B0 32 bit timer 0 */ - .long TIMER32_1_IRQHandler /* 35 19 CT32B1 32 bit timer 1 */ - .long SSP0_IRQHandler /* 36 20 SSP */ - .long UART_IRQHandler /* 37 21 UART */ - .long USB_IRQHandler /* 38 22 USB IRQ */ - .long USB_FIQHandler /* 39 23 USB FIQ */ - .long ADC_IRQHandler /* 40 24 ADC end of conversion */ - .long WDT_IRQHandler /* 41 25 Watchdog interrupt (WDINT) */ - .long BOD_IRQHandler /* 42 26 BOD Brown-out detect */ - .long Default_Handler /* 43 27 */ - .long PIOINT3_IRQHandler /* 44 28 PIO_3 GPIO interrupt status of port 3 */ - .long PIOINT2_IRQHandler /* 45 29 PIO_2 GPIO interrupt status of port 2 */ - .long PIOINT1_IRQHandler /* 46 30 PIO_1 GPIO interrupt status of port 1 */ - .long PIOINT0_IRQHandler /* 47 31 PIO_0 GPIO interrupt status of port 0 */ - - .size __isr_vector, . - __isr_vector - - .section .text.Reset_Handler - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .Lflash_to_ram_loop_end - - movs r4, 0 -.Lflash_to_ram_loop: - ldr r0, [r1,r4] - str r0, [r2,r4] - adds r4, 4 - cmp r4, r3 - blt .Lflash_to_ram_loop -.Lflash_to_ram_loop_end: - - ldr r0, =SystemInit - blx r0 - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler SVC_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_default_handler WAKEUP_IRQHandler - def_irq_default_handler SSP1_IRQHandler - def_irq_default_handler I2C_IRQHandler - def_irq_default_handler TIMER16_0_IRQHandler - def_irq_default_handler TIMER16_1_IRQHandler - def_irq_default_handler TIMER32_0_IRQHandler - def_irq_default_handler TIMER32_1_IRQHandler - def_irq_default_handler SSP0_IRQHandler - def_irq_default_handler UART_IRQHandler - def_irq_default_handler USB_IRQHandler - def_irq_default_handler USB_FIQHandler - def_irq_default_handler ADC_IRQHandler - def_irq_default_handler WDT_IRQHandler - def_irq_default_handler BOD_IRQHandler - def_irq_default_handler PIOINT3_IRQHandler - def_irq_default_handler PIOINT2_IRQHandler - def_irq_default_handler PIOINT1_IRQHandler - def_irq_default_handler PIOINT0_IRQHandler - def_irq_default_handler DEF_IRQHandler - - .end - diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U24_301/LPC11U24.icf b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U24_301/LPC11U24.icf deleted file mode 100644 index d3c91e89259..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U24_301/LPC11U24.icf +++ /dev/null @@ -1,45 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; -define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000; -define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF; -define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0; -define symbol __ICFEDIT_region_RAM_end__ = 0x100017DF; -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} - -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x800; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __CRP_start__ = 0x000002FC; -define symbol __CRP_end__ = 0x000002FF; - -define symbol __URAM_start__ = 0x20004000; -define symbol __URAM_end__ = 0x200047FF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region URAM_region = mem:[from __URAM_start__ to __URAM_end__]; -define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block HEAP, block CSTACK }; -place in CRP_region { section .crp }; -place in URAM_region { section USB_PACKET_MEMORY }; diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U24_301/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U24_301/startup_LPC11xx.S deleted file mode 100644 index 0d9b2ef0072..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U24_301/startup_LPC11xx.S +++ /dev/null @@ -1,333 +0,0 @@ -/************************************************** - * - * Part one of the system initialization code, contains low-level - * initialization, plain thumb variant. - * - * Copyright 2012 IAR Systems. All rights reserved. - * - * $Revision: 28 $ - * - **************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - DATA - - -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - PUBWEAK FLEX_INT0_IRQHandler - PUBWEAK FLEX_INT1_IRQHandler - PUBWEAK FLEX_INT2_IRQHandler - PUBWEAK FLEX_INT3_IRQHandler - PUBWEAK FLEX_INT4_IRQHandler - PUBWEAK FLEX_INT5_IRQHandler - PUBWEAK FLEX_INT6_IRQHandler - PUBWEAK FLEX_INT7_IRQHandler - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT1_IRQHandler - PUBWEAK SSP1_IRQHandler - PUBWEAK I2C_IRQHandler - PUBWEAK TIMER16_0_IRQHandler - PUBWEAK TIMER16_1_IRQHandler - PUBWEAK TIMER32_0_IRQHandler - PUBWEAK TIMER32_1_IRQHandler - PUBWEAK SSP0_IRQHandler - PUBWEAK UART_IRQHandler - PUBWEAK USB_IRQHandler - PUBWEAK USB_FIQHandler - PUBWEAK ADC_IRQHandler - PUBWEAK WDT_IRQHandler - PUBWEAK BOD_IRQHandler - PUBWEAK FMC_IRQHandler - PUBWEAK USBWakeup_IRQHandler - PUBWEAK Reserved_IRQHandler - - SECTION .text:CODE:REORDER:NOROOT(1) - THUMB -NMI_Handler: - B . -HardFault_Handler: - B . -MemManage_Handler: - B . -BusFault_Handler: - B . -UsageFault_Handler: - B . -SVC_Handler: - B . -DebugMon_Handler: - B . -PendSV_Handler: - B . -SysTick_Handler: - B . -FLEX_INT0_IRQHandler: - B . -FLEX_INT1_IRQHandler: - B . -FLEX_INT2_IRQHandler: - B . -FLEX_INT3_IRQHandler: - B . -FLEX_INT4_IRQHandler: - B . -FLEX_INT5_IRQHandler: - B . -FLEX_INT6_IRQHandler: - B . -FLEX_INT7_IRQHandler: - B . -GINT0_IRQHandler: - B . -GINT1_IRQHandler: - B . -SSP1_IRQHandler: - B . -I2C_IRQHandler: - B . -TIMER16_0_IRQHandler: - B . -TIMER16_1_IRQHandler: - B . -TIMER32_0_IRQHandler: - B . -TIMER32_1_IRQHandler: - B . -SSP0_IRQHandler: - B . -UART_IRQHandler: - B . -USB_IRQHandler: - B . -USB_FIQHandler: - B . -ADC_IRQHandler: - B . -WDT_IRQHandler: - B . -BOD_IRQHandler: - B . -FMC_IRQHandler: - B . -USBWakeup_IRQHandler: - B . -Reserved_IRQHandler: - B . -Default_Handler: - B . - - SECTION .crp:CODE:ROOT(2) - DATA -/* Code Read Protection -NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode -CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. - - Copy RAM to flash command can not write to Sector 0. - - Erase command can erase Sector 0 only when all sectors - are selected for erase. - - Compare command is disabled. - - Read Memory command is disabled. -CRP2 0x87654321 - Read Memory is disabled. - - Write to RAM is disabled. - - "Go" command is disabled. - - Copy RAM to flash is disabled. - - Compare is disabled. -CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry - by pulling PIO0_1 LOW is disabled if a valid user code is - present in flash sector 0. -Caution: If CRP3 is selected, no future factory testing can be -performed on the device. -*/ - DCD 0xFFFFFFFF - - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U24_401/LPC11U24.icf b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U24_401/LPC11U24.icf deleted file mode 100644 index ef4ec28459a..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U24_401/LPC11U24.icf +++ /dev/null @@ -1,45 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; -define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000; -define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF; -define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0; -define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF; -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} - -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0xA00; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __CRP_start__ = 0x000002FC; -define symbol __CRP_end__ = 0x000002FF; - -define symbol __URAM_start__ = 0x20004000; -define symbol __URAM_end__ = 0x200047FF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region URAM_region = mem:[from __URAM_start__ to __URAM_end__]; -define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block HEAP, block CSTACK }; -place in CRP_region { section .crp }; -place in URAM_region { section USB_PACKET_MEMORY }; diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U24_401/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U24_401/startup_LPC11xx.S deleted file mode 100644 index 0d9b2ef0072..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U24_401/startup_LPC11xx.S +++ /dev/null @@ -1,333 +0,0 @@ -/************************************************** - * - * Part one of the system initialization code, contains low-level - * initialization, plain thumb variant. - * - * Copyright 2012 IAR Systems. All rights reserved. - * - * $Revision: 28 $ - * - **************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - DATA - - -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - PUBWEAK FLEX_INT0_IRQHandler - PUBWEAK FLEX_INT1_IRQHandler - PUBWEAK FLEX_INT2_IRQHandler - PUBWEAK FLEX_INT3_IRQHandler - PUBWEAK FLEX_INT4_IRQHandler - PUBWEAK FLEX_INT5_IRQHandler - PUBWEAK FLEX_INT6_IRQHandler - PUBWEAK FLEX_INT7_IRQHandler - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT1_IRQHandler - PUBWEAK SSP1_IRQHandler - PUBWEAK I2C_IRQHandler - PUBWEAK TIMER16_0_IRQHandler - PUBWEAK TIMER16_1_IRQHandler - PUBWEAK TIMER32_0_IRQHandler - PUBWEAK TIMER32_1_IRQHandler - PUBWEAK SSP0_IRQHandler - PUBWEAK UART_IRQHandler - PUBWEAK USB_IRQHandler - PUBWEAK USB_FIQHandler - PUBWEAK ADC_IRQHandler - PUBWEAK WDT_IRQHandler - PUBWEAK BOD_IRQHandler - PUBWEAK FMC_IRQHandler - PUBWEAK USBWakeup_IRQHandler - PUBWEAK Reserved_IRQHandler - - SECTION .text:CODE:REORDER:NOROOT(1) - THUMB -NMI_Handler: - B . -HardFault_Handler: - B . -MemManage_Handler: - B . -BusFault_Handler: - B . -UsageFault_Handler: - B . -SVC_Handler: - B . -DebugMon_Handler: - B . -PendSV_Handler: - B . -SysTick_Handler: - B . -FLEX_INT0_IRQHandler: - B . -FLEX_INT1_IRQHandler: - B . -FLEX_INT2_IRQHandler: - B . -FLEX_INT3_IRQHandler: - B . -FLEX_INT4_IRQHandler: - B . -FLEX_INT5_IRQHandler: - B . -FLEX_INT6_IRQHandler: - B . -FLEX_INT7_IRQHandler: - B . -GINT0_IRQHandler: - B . -GINT1_IRQHandler: - B . -SSP1_IRQHandler: - B . -I2C_IRQHandler: - B . -TIMER16_0_IRQHandler: - B . -TIMER16_1_IRQHandler: - B . -TIMER32_0_IRQHandler: - B . -TIMER32_1_IRQHandler: - B . -SSP0_IRQHandler: - B . -UART_IRQHandler: - B . -USB_IRQHandler: - B . -USB_FIQHandler: - B . -ADC_IRQHandler: - B . -WDT_IRQHandler: - B . -BOD_IRQHandler: - B . -FMC_IRQHandler: - B . -USBWakeup_IRQHandler: - B . -Reserved_IRQHandler: - B . -Default_Handler: - B . - - SECTION .crp:CODE:ROOT(2) - DATA -/* Code Read Protection -NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode -CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. - - Copy RAM to flash command can not write to Sector 0. - - Erase command can erase Sector 0 only when all sectors - are selected for erase. - - Compare command is disabled. - - Read Memory command is disabled. -CRP2 0x87654321 - Read Memory is disabled. - - Write to RAM is disabled. - - "Go" command is disabled. - - Copy RAM to flash is disabled. - - Compare is disabled. -CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry - by pulling PIO0_1 LOW is disabled if a valid user code is - present in flash sector 0. -Caution: If CRP3 is selected, no future factory testing can be -performed on the device. -*/ - DCD 0xFFFFFFFF - - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U35_401/LPC11U35.icf b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U35_401/LPC11U35.icf deleted file mode 100644 index 52f6519ece1..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U35_401/LPC11U35.icf +++ /dev/null @@ -1,45 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x000000C0; -define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; -define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000; -define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF; -define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0; -define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF; -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} - -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x800; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __CRP_start__ = 0x000002FC; -define symbol __CRP_end__ = 0x000002FF; - -define symbol __URAM_start__ = 0x20004000; -define symbol __URAM_end__ = 0x200047FF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region URAM_region = mem:[from __URAM_start__ to __URAM_end__]; -define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block HEAP, block CSTACK }; -place in CRP_region { section .crp }; -place in URAM_region { section USB_PACKET_MEMORY }; diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U35_401/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U35_401/startup_LPC11xx.S deleted file mode 100644 index 0d9b2ef0072..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U35_401/startup_LPC11xx.S +++ /dev/null @@ -1,333 +0,0 @@ -/************************************************** - * - * Part one of the system initialization code, contains low-level - * initialization, plain thumb variant. - * - * Copyright 2012 IAR Systems. All rights reserved. - * - * $Revision: 28 $ - * - **************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - DATA - - -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - PUBWEAK FLEX_INT0_IRQHandler - PUBWEAK FLEX_INT1_IRQHandler - PUBWEAK FLEX_INT2_IRQHandler - PUBWEAK FLEX_INT3_IRQHandler - PUBWEAK FLEX_INT4_IRQHandler - PUBWEAK FLEX_INT5_IRQHandler - PUBWEAK FLEX_INT6_IRQHandler - PUBWEAK FLEX_INT7_IRQHandler - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT1_IRQHandler - PUBWEAK SSP1_IRQHandler - PUBWEAK I2C_IRQHandler - PUBWEAK TIMER16_0_IRQHandler - PUBWEAK TIMER16_1_IRQHandler - PUBWEAK TIMER32_0_IRQHandler - PUBWEAK TIMER32_1_IRQHandler - PUBWEAK SSP0_IRQHandler - PUBWEAK UART_IRQHandler - PUBWEAK USB_IRQHandler - PUBWEAK USB_FIQHandler - PUBWEAK ADC_IRQHandler - PUBWEAK WDT_IRQHandler - PUBWEAK BOD_IRQHandler - PUBWEAK FMC_IRQHandler - PUBWEAK USBWakeup_IRQHandler - PUBWEAK Reserved_IRQHandler - - SECTION .text:CODE:REORDER:NOROOT(1) - THUMB -NMI_Handler: - B . -HardFault_Handler: - B . -MemManage_Handler: - B . -BusFault_Handler: - B . -UsageFault_Handler: - B . -SVC_Handler: - B . -DebugMon_Handler: - B . -PendSV_Handler: - B . -SysTick_Handler: - B . -FLEX_INT0_IRQHandler: - B . -FLEX_INT1_IRQHandler: - B . -FLEX_INT2_IRQHandler: - B . -FLEX_INT3_IRQHandler: - B . -FLEX_INT4_IRQHandler: - B . -FLEX_INT5_IRQHandler: - B . -FLEX_INT6_IRQHandler: - B . -FLEX_INT7_IRQHandler: - B . -GINT0_IRQHandler: - B . -GINT1_IRQHandler: - B . -SSP1_IRQHandler: - B . -I2C_IRQHandler: - B . -TIMER16_0_IRQHandler: - B . -TIMER16_1_IRQHandler: - B . -TIMER32_0_IRQHandler: - B . -TIMER32_1_IRQHandler: - B . -SSP0_IRQHandler: - B . -UART_IRQHandler: - B . -USB_IRQHandler: - B . -USB_FIQHandler: - B . -ADC_IRQHandler: - B . -WDT_IRQHandler: - B . -BOD_IRQHandler: - B . -FMC_IRQHandler: - B . -USBWakeup_IRQHandler: - B . -Reserved_IRQHandler: - B . -Default_Handler: - B . - - SECTION .crp:CODE:ROOT(2) - DATA -/* Code Read Protection -NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode -CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. - - Copy RAM to flash command can not write to Sector 0. - - Erase command can erase Sector 0 only when all sectors - are selected for erase. - - Compare command is disabled. - - Read Memory command is disabled. -CRP2 0x87654321 - Read Memory is disabled. - - Write to RAM is disabled. - - "Go" command is disabled. - - Copy RAM to flash is disabled. - - Compare is disabled. -CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry - by pulling PIO0_1 LOW is disabled if a valid user code is - present in flash sector 0. -Caution: If CRP3 is selected, no future factory testing can be -performed on the device. -*/ - DCD 0xFFFFFFFF - - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U35_501/LPC11U35.icf b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U35_501/LPC11U35.icf deleted file mode 100644 index 001ec345195..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U35_501/LPC11U35.icf +++ /dev/null @@ -1,50 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x000000C0; -define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; -define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000; -define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF; -define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0; -define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF; -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} - -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x800; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __CRP_start__ = 0x000002FC; -define symbol __CRP_end__ = 0x000002FF; - -define symbol __URAM_start__ = 0x20004000; -define symbol __URAM_end__ = 0x200047FF; - -define symbol __SRAM1_start__ = 0x20000000; -define symbol __SRAM1_end__ = 0x200007FF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region URAM_region = mem:[from __URAM_start__ to __URAM_end__]; -define region SRAM1_region = mem:[from __SRAM1_start__ to __SRAM1_end__]; -define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block HEAP, block CSTACK }; -place in CRP_region { section .crp }; -place in URAM_region { section USB_PACKET_MEMORY }; -place in SRAM1_region { section .SRAM1 }; diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U35_501/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U35_501/startup_LPC11xx.S deleted file mode 100644 index 0d9b2ef0072..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U35_501/startup_LPC11xx.S +++ /dev/null @@ -1,333 +0,0 @@ -/************************************************** - * - * Part one of the system initialization code, contains low-level - * initialization, plain thumb variant. - * - * Copyright 2012 IAR Systems. All rights reserved. - * - * $Revision: 28 $ - * - **************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - DATA - - -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - PUBWEAK FLEX_INT0_IRQHandler - PUBWEAK FLEX_INT1_IRQHandler - PUBWEAK FLEX_INT2_IRQHandler - PUBWEAK FLEX_INT3_IRQHandler - PUBWEAK FLEX_INT4_IRQHandler - PUBWEAK FLEX_INT5_IRQHandler - PUBWEAK FLEX_INT6_IRQHandler - PUBWEAK FLEX_INT7_IRQHandler - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT1_IRQHandler - PUBWEAK SSP1_IRQHandler - PUBWEAK I2C_IRQHandler - PUBWEAK TIMER16_0_IRQHandler - PUBWEAK TIMER16_1_IRQHandler - PUBWEAK TIMER32_0_IRQHandler - PUBWEAK TIMER32_1_IRQHandler - PUBWEAK SSP0_IRQHandler - PUBWEAK UART_IRQHandler - PUBWEAK USB_IRQHandler - PUBWEAK USB_FIQHandler - PUBWEAK ADC_IRQHandler - PUBWEAK WDT_IRQHandler - PUBWEAK BOD_IRQHandler - PUBWEAK FMC_IRQHandler - PUBWEAK USBWakeup_IRQHandler - PUBWEAK Reserved_IRQHandler - - SECTION .text:CODE:REORDER:NOROOT(1) - THUMB -NMI_Handler: - B . -HardFault_Handler: - B . -MemManage_Handler: - B . -BusFault_Handler: - B . -UsageFault_Handler: - B . -SVC_Handler: - B . -DebugMon_Handler: - B . -PendSV_Handler: - B . -SysTick_Handler: - B . -FLEX_INT0_IRQHandler: - B . -FLEX_INT1_IRQHandler: - B . -FLEX_INT2_IRQHandler: - B . -FLEX_INT3_IRQHandler: - B . -FLEX_INT4_IRQHandler: - B . -FLEX_INT5_IRQHandler: - B . -FLEX_INT6_IRQHandler: - B . -FLEX_INT7_IRQHandler: - B . -GINT0_IRQHandler: - B . -GINT1_IRQHandler: - B . -SSP1_IRQHandler: - B . -I2C_IRQHandler: - B . -TIMER16_0_IRQHandler: - B . -TIMER16_1_IRQHandler: - B . -TIMER32_0_IRQHandler: - B . -TIMER32_1_IRQHandler: - B . -SSP0_IRQHandler: - B . -UART_IRQHandler: - B . -USB_IRQHandler: - B . -USB_FIQHandler: - B . -ADC_IRQHandler: - B . -WDT_IRQHandler: - B . -BOD_IRQHandler: - B . -FMC_IRQHandler: - B . -USBWakeup_IRQHandler: - B . -Reserved_IRQHandler: - B . -Default_Handler: - B . - - SECTION .crp:CODE:ROOT(2) - DATA -/* Code Read Protection -NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode -CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. - - Copy RAM to flash command can not write to Sector 0. - - Erase command can erase Sector 0 only when all sectors - are selected for erase. - - Compare command is disabled. - - Read Memory command is disabled. -CRP2 0x87654321 - Read Memory is disabled. - - Write to RAM is disabled. - - "Go" command is disabled. - - Copy RAM to flash is disabled. - - Compare is disabled. -CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry - by pulling PIO0_1 LOW is disabled if a valid user code is - present in flash sector 0. -Caution: If CRP3 is selected, no future factory testing can be -performed on the device. -*/ - DCD 0xFFFFFFFF - - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U37_501/LPC11U37.icf b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U37_501/LPC11U37.icf deleted file mode 100644 index 82c6546a02a..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U37_501/LPC11U37.icf +++ /dev/null @@ -1,50 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x000000C0; -define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; -define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000; -define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF; -define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0; -define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF; -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} - -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x800; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __CRP_start__ = 0x000002FC; -define symbol __CRP_end__ = 0x000002FF; - -define symbol __URAM_start__ = 0x20004000; -define symbol __URAM_end__ = 0x200047FF; - -define symbol __SRAM1_start__ = 0x20000000; -define symbol __SRAM1_end__ = 0x200007FF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region URAM_region = mem:[from __URAM_start__ to __URAM_end__]; -define region SRAM1_region = mem:[from __SRAM1_start__ to __SRAM1_end__]; -define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block HEAP, block CSTACK }; -place in CRP_region { section .crp }; -place in URAM_region { section USB_PACKET_MEMORY }; -place in SRAM1_region { section .SRAM1 }; diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U37_501/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U37_501/startup_LPC11xx.S deleted file mode 100644 index 0d9b2ef0072..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_LPC11U37_501/startup_LPC11xx.S +++ /dev/null @@ -1,333 +0,0 @@ -/************************************************** - * - * Part one of the system initialization code, contains low-level - * initialization, plain thumb variant. - * - * Copyright 2012 IAR Systems. All rights reserved. - * - * $Revision: 28 $ - * - **************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - DATA - - -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - PUBWEAK FLEX_INT0_IRQHandler - PUBWEAK FLEX_INT1_IRQHandler - PUBWEAK FLEX_INT2_IRQHandler - PUBWEAK FLEX_INT3_IRQHandler - PUBWEAK FLEX_INT4_IRQHandler - PUBWEAK FLEX_INT5_IRQHandler - PUBWEAK FLEX_INT6_IRQHandler - PUBWEAK FLEX_INT7_IRQHandler - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT1_IRQHandler - PUBWEAK SSP1_IRQHandler - PUBWEAK I2C_IRQHandler - PUBWEAK TIMER16_0_IRQHandler - PUBWEAK TIMER16_1_IRQHandler - PUBWEAK TIMER32_0_IRQHandler - PUBWEAK TIMER32_1_IRQHandler - PUBWEAK SSP0_IRQHandler - PUBWEAK UART_IRQHandler - PUBWEAK USB_IRQHandler - PUBWEAK USB_FIQHandler - PUBWEAK ADC_IRQHandler - PUBWEAK WDT_IRQHandler - PUBWEAK BOD_IRQHandler - PUBWEAK FMC_IRQHandler - PUBWEAK USBWakeup_IRQHandler - PUBWEAK Reserved_IRQHandler - - SECTION .text:CODE:REORDER:NOROOT(1) - THUMB -NMI_Handler: - B . -HardFault_Handler: - B . -MemManage_Handler: - B . -BusFault_Handler: - B . -UsageFault_Handler: - B . -SVC_Handler: - B . -DebugMon_Handler: - B . -PendSV_Handler: - B . -SysTick_Handler: - B . -FLEX_INT0_IRQHandler: - B . -FLEX_INT1_IRQHandler: - B . -FLEX_INT2_IRQHandler: - B . -FLEX_INT3_IRQHandler: - B . -FLEX_INT4_IRQHandler: - B . -FLEX_INT5_IRQHandler: - B . -FLEX_INT6_IRQHandler: - B . -FLEX_INT7_IRQHandler: - B . -GINT0_IRQHandler: - B . -GINT1_IRQHandler: - B . -SSP1_IRQHandler: - B . -I2C_IRQHandler: - B . -TIMER16_0_IRQHandler: - B . -TIMER16_1_IRQHandler: - B . -TIMER32_0_IRQHandler: - B . -TIMER32_1_IRQHandler: - B . -SSP0_IRQHandler: - B . -UART_IRQHandler: - B . -USB_IRQHandler: - B . -USB_FIQHandler: - B . -ADC_IRQHandler: - B . -WDT_IRQHandler: - B . -BOD_IRQHandler: - B . -FMC_IRQHandler: - B . -USBWakeup_IRQHandler: - B . -Reserved_IRQHandler: - B . -Default_Handler: - B . - - SECTION .crp:CODE:ROOT(2) - DATA -/* Code Read Protection -NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode -CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. - - Copy RAM to flash command can not write to Sector 0. - - Erase command can erase Sector 0 only when all sectors - are selected for erase. - - Compare command is disabled. - - Read Memory command is disabled. -CRP2 0x87654321 - Read Memory is disabled. - - Write to RAM is disabled. - - "Go" command is disabled. - - Copy RAM to flash is disabled. - - Compare is disabled. -CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry - by pulling PIO0_1 LOW is disabled if a valid user code is - present in flash sector 0. -Caution: If CRP3 is selected, no future factory testing can be -performed on the device. -*/ - DCD 0xFFFFFFFF - - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_OC_MBUINO/LPC11U24.icf b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_OC_MBUINO/LPC11U24.icf deleted file mode 100644 index dc029b0dff3..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_OC_MBUINO/LPC11U24.icf +++ /dev/null @@ -1,45 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; -define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000; -define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF; -define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0; -define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF; -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} - -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x800; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __CRP_start__ = 0x000002FC; -define symbol __CRP_end__ = 0x000002FF; - -define symbol __URAM_start__ = 0x20004000; -define symbol __URAM_end__ = 0x200047FF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region URAM_region = mem:[from __URAM_start__ to __URAM_end__]; -define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block HEAP, block CSTACK }; -place in CRP_region { section .crp }; -place in URAM_region { section USB_PACKET_MEMORY }; diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_OC_MBUINO/startup_LPC11xx.S b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_OC_MBUINO/startup_LPC11xx.S deleted file mode 100644 index 0d9b2ef0072..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_IAR/TARGET_OC_MBUINO/startup_LPC11xx.S +++ /dev/null @@ -1,333 +0,0 @@ -/************************************************** - * - * Part one of the system initialization code, contains low-level - * initialization, plain thumb variant. - * - * Copyright 2012 IAR Systems. All rights reserved. - * - * $Revision: 28 $ - * - **************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - DATA - - -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx - DCD FLEX_INT1_IRQHandler - DCD FLEX_INT2_IRQHandler - DCD FLEX_INT3_IRQHandler - DCD FLEX_INT4_IRQHandler - DCD FLEX_INT5_IRQHandler - DCD FLEX_INT6_IRQHandler - DCD FLEX_INT7_IRQHandler - DCD GINT0_IRQHandler - DCD GINT1_IRQHandler ; PIO0 (0:7) - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD Reserved_IRQHandler - DCD SSP1_IRQHandler ; SSP1 - DCD I2C_IRQHandler ; I2C - DCD TIMER16_0_IRQHandler ; 16-bit Timer0 - DCD TIMER16_1_IRQHandler ; 16-bit Timer1 - DCD TIMER32_0_IRQHandler ; 32-bit Timer0 - DCD TIMER32_1_IRQHandler ; 32-bit Timer1 - DCD SSP0_IRQHandler ; SSP0 - DCD UART_IRQHandler ; UART - DCD USB_IRQHandler ; USB IRQ - DCD USB_FIQHandler ; USB FIQ - DCD ADC_IRQHandler ; A/D Converter - DCD WDT_IRQHandler ; Watchdog timer - DCD BOD_IRQHandler ; Brown Out Detect - DCD FMC_IRQHandler ; IP2111 Flash Memory Controller - DCD Reserved_IRQHandler ; Reserved - DCD Reserved_IRQHandler ; Reserved - DCD USBWakeup_IRQHandler ; USB wake up - DCD Reserved_IRQHandler ; Reserved - - ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space - - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill - DCD 0xFFFFFFFF ; Datafill -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - PUBWEAK FLEX_INT0_IRQHandler - PUBWEAK FLEX_INT1_IRQHandler - PUBWEAK FLEX_INT2_IRQHandler - PUBWEAK FLEX_INT3_IRQHandler - PUBWEAK FLEX_INT4_IRQHandler - PUBWEAK FLEX_INT5_IRQHandler - PUBWEAK FLEX_INT6_IRQHandler - PUBWEAK FLEX_INT7_IRQHandler - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT1_IRQHandler - PUBWEAK SSP1_IRQHandler - PUBWEAK I2C_IRQHandler - PUBWEAK TIMER16_0_IRQHandler - PUBWEAK TIMER16_1_IRQHandler - PUBWEAK TIMER32_0_IRQHandler - PUBWEAK TIMER32_1_IRQHandler - PUBWEAK SSP0_IRQHandler - PUBWEAK UART_IRQHandler - PUBWEAK USB_IRQHandler - PUBWEAK USB_FIQHandler - PUBWEAK ADC_IRQHandler - PUBWEAK WDT_IRQHandler - PUBWEAK BOD_IRQHandler - PUBWEAK FMC_IRQHandler - PUBWEAK USBWakeup_IRQHandler - PUBWEAK Reserved_IRQHandler - - SECTION .text:CODE:REORDER:NOROOT(1) - THUMB -NMI_Handler: - B . -HardFault_Handler: - B . -MemManage_Handler: - B . -BusFault_Handler: - B . -UsageFault_Handler: - B . -SVC_Handler: - B . -DebugMon_Handler: - B . -PendSV_Handler: - B . -SysTick_Handler: - B . -FLEX_INT0_IRQHandler: - B . -FLEX_INT1_IRQHandler: - B . -FLEX_INT2_IRQHandler: - B . -FLEX_INT3_IRQHandler: - B . -FLEX_INT4_IRQHandler: - B . -FLEX_INT5_IRQHandler: - B . -FLEX_INT6_IRQHandler: - B . -FLEX_INT7_IRQHandler: - B . -GINT0_IRQHandler: - B . -GINT1_IRQHandler: - B . -SSP1_IRQHandler: - B . -I2C_IRQHandler: - B . -TIMER16_0_IRQHandler: - B . -TIMER16_1_IRQHandler: - B . -TIMER32_0_IRQHandler: - B . -TIMER32_1_IRQHandler: - B . -SSP0_IRQHandler: - B . -UART_IRQHandler: - B . -USB_IRQHandler: - B . -USB_FIQHandler: - B . -ADC_IRQHandler: - B . -WDT_IRQHandler: - B . -BOD_IRQHandler: - B . -FMC_IRQHandler: - B . -USBWakeup_IRQHandler: - B . -Reserved_IRQHandler: - B . -Default_Handler: - B . - - SECTION .crp:CODE:ROOT(2) - DATA -/* Code Read Protection -NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode -CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. - - Copy RAM to flash command can not write to Sector 0. - - Erase command can erase Sector 0 only when all sectors - are selected for erase. - - Compare command is disabled. - - Read Memory command is disabled. -CRP2 0x87654321 - Read Memory is disabled. - - Write to RAM is disabled. - - "Go" command is disabled. - - Copy RAM to flash is disabled. - - Compare is disabled. -CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry - by pulling PIO0_1 LOW is disabled if a valid user code is - present in flash sector 0. -Caution: If CRP3 is selected, no future factory testing can be -performed on the device. -*/ - DCD 0xFFFFFFFF - - END diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/cmsis.h b/targets/TARGET_NXP/TARGET_LPC11UXX/device/cmsis.h deleted file mode 100644 index 4e385791313..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC11U24 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC11Uxx.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/cmsis_nvic.c b/targets/TARGET_NXP/TARGET_LPC11UXX/device/cmsis_nvic.c deleted file mode 100644 index 5f6802e6d27..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/cmsis_nvic.c +++ /dev/null @@ -1,82 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "cmsis_nvic.h" - -/* In the M0, there is no VTOR. In the LPC range such as the LPC11U, - * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0), - * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF - * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0 - * - * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH - * above the vector table before 0x200 will actually go to RAM. So we need to provide - * a solution where the compiler gets the right results based on the memory map - * - * Option 1 - We allocate and copy 0x200 of RAM rather than just the table - * - const data and instructions before 0x200 will be copied to and fetched/exec from RAM - * - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0 - * - * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there - * - No flash accesses will go to ram, as there will be nothing there - * - RAM only needs to be allocated for the vectors, as all other ram addresses are normal - * - RAM overhead: 0, FLASH overhead: 320 bytes - * - * Option 2 is the one to go for, as RAM is the most valuable resource - */ - -#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - int i; - // Space for dynamic vectors, initialised to allocate in R/W - static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; - - // Copy and switch to dynamic vectors if first time called - if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) { - // Add volatile qualifier to avoid armclang aggressive optimization - volatile uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0 - for(i = 0; i < NVIC_NUM_VECTORS; i++) { - vectors[i] = old_vectors[i]; - } - LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block - } - - // Set the vector - vectors[IRQn + 16] = vector; -} - -uint32_t NVIC_GetVector(IRQn_Type IRQn) { - // We can always read vectors at 0x0, as the addresses are remapped - uint32_t *vectors = (uint32_t*)0; - - // Return the vector - return vectors[IRQn + 16]; -} - diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/cmsis_nvic.h b/targets/TARGET_NXP/TARGET_LPC11UXX/device/cmsis_nvic.h deleted file mode 100644 index 324e797047f..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/cmsis_nvic.h +++ /dev/null @@ -1,51 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#include "cmsis.h" - -#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals -#define NVIC_USER_IRQ_OFFSET 16 - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/power_api.h b/targets/TARGET_NXP/TARGET_LPC11UXX/device/power_api.h deleted file mode 100644 index 23296c5ffa8..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/power_api.h +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $ - * Project: NXP LPC11Uxx software example - * - * Description: - * Power API Header File for NXP LPC11Uxx Device Series - * - **************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * NXP Semiconductors assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. NXP Semiconductors - * reserves the right to make changes in the software without - * notification. NXP Semiconductors also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. -****************************************************************************/ -#ifndef __LPC11UXX_POWER_API_H__ -#define __LPC11UXX_POWER_API_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#define PWRROMD_PRESENT - -typedef struct _PWRD { - void (*set_pll)(unsigned int cmd[], unsigned int resp[]); - void (*set_power)(unsigned int cmd[], unsigned int resp[]); -} PWRD; - -typedef struct _ROM { -#ifdef USBROMD_PRESENT - const USB * pUSBD; -#else - const unsigned p_usbd; -#endif /* USBROMD_PRESENT */ - const unsigned p_clib; - const unsigned p_cand; -#ifdef PWRROMD_PRESENT - const PWRD * pPWRD; -#else - const unsigned p_pwrd; -#endif /* PWRROMD_PRESENT */ - const unsigned p_dev1; - const unsigned p_dev2; - const unsigned p_dev3; - const unsigned p_dev4; -} ROM; - -//PLL setup related definitions -#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified -#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified -#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified -#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified - -#define PLL_CMD_SUCCESS 0 //PLL setup successfully found -#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output) -#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified -#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions -#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup - -//power setup elated definitions -#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface) -#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation) -#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance) -#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance - -#define PARAM_CMD_SUCCESS 0 //power setting successfully found -#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz) -#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid) - -#define MAX_CLOCK_KHZ_PARAM 50000 - -#ifdef __cplusplus -} -#endif - -#endif /* __LPC11UXX_POWER_API_H__ */ - diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/system_LPC11Uxx.c b/targets/TARGET_NXP/TARGET_LPC11UXX/device/system_LPC11Uxx.c deleted file mode 100644 index 7c4d7e73cf4..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/system_LPC11Uxx.c +++ /dev/null @@ -1,450 +0,0 @@ -/****************************************************************************** - * @file system_LPC11Uxx.c - * @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File - * for the NXP LPC13xx Device Series - * @version V1.10 - * @date 24. November 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#include -#include "LPC11Uxx.h" - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration ---------------------------------- -// -// Clock Configuration -// System Oscillator Control Register (SYSOSCCTRL) -// BYPASS: System Oscillator Bypass Enable -// If enabled then PLL input (sys_osc_clk) is fed -// directly from XTALIN and XTALOUT pins. -// FREQRANGE: System Oscillator Frequency Range -// Determines frequency range for Low-power oscillator. -// <0=> 1 - 20 MHz -// <1=> 15 - 25 MHz -// -// -// Watchdog Oscillator Control Register (WDTOSCCTRL) -// DIVSEL: Select Divider for Fclkana -// wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL)) -// <0-31> -// FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana) -// <0=> Undefined -// <1=> 0.5 MHz -// <2=> 0.8 MHz -// <3=> 1.1 MHz -// <4=> 1.4 MHz -// <5=> 1.6 MHz -// <6=> 1.8 MHz -// <7=> 2.0 MHz -// <8=> 2.2 MHz -// <9=> 2.4 MHz -// <10=> 2.6 MHz -// <11=> 2.7 MHz -// <12=> 2.9 MHz -// <13=> 3.1 MHz -// <14=> 3.2 MHz -// <15=> 3.4 MHz -// -// -// System PLL Control Register (SYSPLLCTRL) -// F_clkout = M * F_clkin = F_CCO / (2 * P) -// F_clkin must be in the range of 10 MHz to 25 MHz -// F_CCO must be in the range of 156 MHz to 320 MHz -// MSEL: Feedback Divider Selection -// M = MSEL + 1 -// <0-31> -// PSEL: Post Divider Selection -// <0=> P = 1 -// <1=> P = 2 -// <2=> P = 4 -// <3=> P = 8 -// -// -// System PLL Clock Source Select Register (SYSPLLCLKSEL) -// SEL: System PLL Clock Source -// <0=> IRC Oscillator -// <1=> System Oscillator -// <2=> Reserved -// <3=> Reserved -// -// -// Main Clock Source Select Register (MAINCLKSEL) -// SEL: Clock Source for Main Clock -// <0=> IRC Oscillator -// <1=> Input Clock to System PLL -// <2=> WDT Oscillator -// <3=> System PLL Clock Out -// -// -// System AHB Clock Divider Register (SYSAHBCLKDIV) -// DIV: System AHB Clock Divider -// Divides main clock to provide system clock to core, memories, and peripherals. -// 0 = is disabled -// <0-255> -// -// -// USB PLL Control Register (USBPLLCTRL) -// F_clkout = M * F_clkin = F_CCO / (2 * P) -// F_clkin must be in the range of 10 MHz to 25 MHz -// F_CCO must be in the range of 156 MHz to 320 MHz -// MSEL: Feedback Divider Selection -// M = MSEL + 1 -// <0-31> -// PSEL: Post Divider Selection -// <0=> P = 1 -// <1=> P = 2 -// <2=> P = 4 -// <3=> P = 8 -// -// -// USB PLL Clock Source Select Register (USBPLLCLKSEL) -// SEL: USB PLL Clock Source -// USB PLL clock source must be switched to System Oscillator for correct USB operation -// <0=> IRC Oscillator -// <1=> System Oscillator -// <2=> Reserved -// <3=> Reserved -// -// -// USB Clock Source Select Register (USBCLKSEL) -// SEL: System PLL Clock Source -// <0=> USB PLL out -// <1=> Main clock -// <2=> Reserved -// <3=> Reserved -// -// -// USB Clock Divider Register (USBCLKDIV) -// DIV: USB Clock Divider -// Divides USB clock to 48 MHz. -// 0 = is disabled -// <0-255> -// -// -*/ -#define CLOCK_SETUP 1 -#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 -#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 -#define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000 -#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 -#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 -#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 -#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000 -#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000 -#define USBCLKSEL_Val 0x00000000 // Reset: 0x000 -#define USBCLKDIV_Val 0x00000001 // Reset: 0x001 - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) - #error "SYSOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) - #error "WDTOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2)) - #error "SYSPLLCLKSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) - #error "SYSPLLCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) - #error "MAINCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) - #error "SYSAHBCLKDIV: Value out of range!" -#endif - -#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1)) - #error "USBPLLCLKSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF)) - #error "USBPLLCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1)) - #error "USBCLKSEL: Value out of range!" -#endif - -#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255)) - #error "USBCLKDIV: Value out of range!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define __XTAL (12000000UL) /* Oscillator frequency */ -#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ -#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ - - -#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) -#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) - -#if (CLOCK_SETUP) /* Clock Setup */ - #if (__FREQSEL == 0) - #define __WDT_OSC_CLK ( 0) /* undefined */ - #elif (__FREQSEL == 1) - #define __WDT_OSC_CLK ( 500000 / __DIVSEL) - #elif (__FREQSEL == 2) - #define __WDT_OSC_CLK ( 800000 / __DIVSEL) - #elif (__FREQSEL == 3) - #define __WDT_OSC_CLK (1100000 / __DIVSEL) - #elif (__FREQSEL == 4) - #define __WDT_OSC_CLK (1400000 / __DIVSEL) - #elif (__FREQSEL == 5) - #define __WDT_OSC_CLK (1600000 / __DIVSEL) - #elif (__FREQSEL == 6) - #define __WDT_OSC_CLK (1800000 / __DIVSEL) - #elif (__FREQSEL == 7) - #define __WDT_OSC_CLK (2000000 / __DIVSEL) - #elif (__FREQSEL == 8) - #define __WDT_OSC_CLK (2200000 / __DIVSEL) - #elif (__FREQSEL == 9) - #define __WDT_OSC_CLK (2400000 / __DIVSEL) - #elif (__FREQSEL == 10) - #define __WDT_OSC_CLK (2600000 / __DIVSEL) - #elif (__FREQSEL == 11) - #define __WDT_OSC_CLK (2700000 / __DIVSEL) - #elif (__FREQSEL == 12) - #define __WDT_OSC_CLK (2900000 / __DIVSEL) - #elif (__FREQSEL == 13) - #define __WDT_OSC_CLK (3100000 / __DIVSEL) - #elif (__FREQSEL == 14) - #define __WDT_OSC_CLK (3200000 / __DIVSEL) - #else - #define __WDT_OSC_CLK (3400000 / __DIVSEL) - #endif - - /* sys_pllclkin calculation */ - #if ((SYSPLLCLKSEL_Val & 0x03) == 0) - #define __SYS_PLLCLKIN (__IRC_OSC_CLK) - #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) - #define __SYS_PLLCLKIN (__SYS_OSC_CLK) - #else - #define __SYS_PLLCLKIN (0) - #endif - - #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) - - /* main clock calculation */ - #if ((MAINCLKSEL_Val & 0x03) == 0) - #define __MAIN_CLOCK (__IRC_OSC_CLK) - #elif ((MAINCLKSEL_Val & 0x03) == 1) - #define __MAIN_CLOCK (__SYS_PLLCLKIN) - #elif ((MAINCLKSEL_Val & 0x03) == 2) - #if (__FREQSEL == 0) - #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!" - #else - #define __MAIN_CLOCK (__WDT_OSC_CLK) - #endif - #elif ((MAINCLKSEL_Val & 0x03) == 3) - #define __MAIN_CLOCK (__SYS_PLLCLKOUT) - #else - #define __MAIN_CLOCK (0) - #endif - - #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) - -#else - #define __SYSTEM_CLOCK (__IRC_OSC_CLK) -#endif // CLOCK_SETUP - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - uint32_t wdt_osc = 0; - - /* Determine clock frequency according to clock register values */ - switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { - case 0: wdt_osc = 0; break; - case 1: wdt_osc = 500000; break; - case 2: wdt_osc = 800000; break; - case 3: wdt_osc = 1100000; break; - case 4: wdt_osc = 1400000; break; - case 5: wdt_osc = 1600000; break; - case 6: wdt_osc = 1800000; break; - case 7: wdt_osc = 2000000; break; - case 8: wdt_osc = 2200000; break; - case 9: wdt_osc = 2400000; break; - case 10: wdt_osc = 2600000; break; - case 11: wdt_osc = 2700000; break; - case 12: wdt_osc = 2900000; break; - case 13: wdt_osc = 3100000; break; - case 14: wdt_osc = 3200000; break; - case 15: wdt_osc = 3400000; break; - } - wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; - - switch (LPC_SYSCON->MAINCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; - break; - case 1: /* Input Clock to System PLL */ - switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; - break; - case 1: /* System oscillator */ - SystemCoreClock = __SYS_OSC_CLK; - break; - case 2: /* Reserved */ - case 3: /* Reserved */ - SystemCoreClock = 0; - break; - } - break; - case 2: /* WDT Oscillator */ - SystemCoreClock = wdt_osc; - break; - case 3: /* System PLL Clock Out */ - switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - if (LPC_SYSCON->SYSPLLCTRL & 0x180) { - SystemCoreClock = __IRC_OSC_CLK; - } else { - SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - } - break; - case 1: /* System oscillator */ - if (LPC_SYSCON->SYSPLLCTRL & 0x180) { - SystemCoreClock = __SYS_OSC_CLK; - } else { - SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - } - break; - case 2: /* Reserved */ - case 3: /* Reserved */ - SystemCoreClock = 0; - break; - } - break; - } - - SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; - -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) { - volatile uint32_t i; - -#if (CLOCK_SETUP) /* Clock Setup */ - -#if ((SYSPLLCLKSEL_Val & 0x03) == 1) - LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */ - LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; - for (i = 0; i < 200; i++) __NOP(); -#endif - - LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ - LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */ - LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */ - LPC_SYSCON->SYSPLLCLKUEN = 0x01; - while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ -#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */ - LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */ - while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ -#endif - -#if (((MAINCLKSEL_Val & 0x03) == 2) ) - LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */ - for (i = 0; i < 200; i++) __NOP(); -#endif - - LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */ - LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */ - LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */ - LPC_SYSCON->MAINCLKUEN = 0x01; - while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ - - LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; - -#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */ - LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */ - -#if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */ - LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */ - LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */ - LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */ - LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */ - LPC_SYSCON->USBPLLCLKUEN = 0x01; - while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */ - LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val; - while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */ - LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */ -#endif - - LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */ - LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */ - -#else /* USB clock is not used */ - LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */ - LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */ -#endif - -#endif - - /* System clock to the IOCON needs to be enabled or - most of the I/O related peripherals won't work. */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16); -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/device/system_LPC11Uxx.h b/targets/TARGET_NXP/TARGET_LPC11UXX/device/system_LPC11Uxx.h deleted file mode 100644 index aaf73f70524..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/system_LPC11Uxx.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_LPC11Uxx.h - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File - * for the NXP LPC11Uxx Device Series - * @version V1.10 - * @date 24. November 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC11Uxx_H -#define __SYSTEM_LPC11Uxx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC11Uxx_H */ diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/gpio_api.c b/targets/TARGET_NXP/TARGET_LPC11UXX/gpio_api.c deleted file mode 100644 index 8a5a55a5e0d..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/gpio_api.c +++ /dev/null @@ -1,64 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" - -uint32_t gpio_set(PinName pin) { - MBED_ASSERT(pin != (PinName)NC); - int f = ((pin == P0_0) || - (pin == P0_10) || - (pin == P0_11) || - (pin == P0_12) || - (pin == P0_13) || - (pin == P0_14) || - (pin == P0_15)) ? (1) : (0); - - pin_function(pin, f); - - return (1 << ((int)pin & 0x1F)); -} - -void gpio_init(gpio_t *obj, PinName pin) { - obj->pin = pin; - if (pin == (PinName)NC) - return; - - obj->mask = gpio_set(pin); - - unsigned int port = (unsigned int)pin >> PORT_SHIFT; - - obj->reg_set = &LPC_GPIO->SET[port]; - obj->reg_clr = &LPC_GPIO->CLR[port]; - obj->reg_in = &LPC_GPIO->PIN[port]; - obj->reg_dir = &LPC_GPIO->DIR[port]; -} - -void gpio_mode(gpio_t *obj, PinMode mode) { - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) { - MBED_ASSERT(obj->pin != (PinName)NC); - switch (direction) { - case PIN_INPUT : - *obj->reg_dir &= ~obj->mask; - break; - case PIN_OUTPUT: - *obj->reg_dir |= obj->mask; - break; - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/gpio_irq_api.c b/targets/TARGET_NXP/TARGET_LPC11UXX/gpio_irq_api.c deleted file mode 100644 index ef4e16c7101..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/gpio_irq_api.c +++ /dev/null @@ -1,141 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "cmsis.h" -#include "gpio_irq_api.h" -#include "mbed_error.h" - -#define CHANNEL_NUM 8 -#define LPC_GPIO_X LPC_GPIO_PIN_INT -#define PININT_IRQ 0 - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler irq_handler; - -static inline void handle_interrupt_in(uint32_t channel) { - uint32_t ch_bit = (1 << channel); - // Return immediately if: - // * The interrupt was already served - // * There is no user handler - // * It is a level interrupt, not an edge interrupt - if ( ((LPC_GPIO_X->IST & ch_bit) == 0) || - (channel_ids[channel] == 0 ) || - (LPC_GPIO_X->ISEL & ch_bit ) ) return; - - if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_RISE); - LPC_GPIO_X->RISE = ch_bit; - } - if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_FALL); - } - LPC_GPIO_X->IST = ch_bit; -} - -void gpio_irq0(void) {handle_interrupt_in(0);} -void gpio_irq1(void) {handle_interrupt_in(1);} -void gpio_irq2(void) {handle_interrupt_in(2);} -void gpio_irq3(void) {handle_interrupt_in(3);} -void gpio_irq4(void) {handle_interrupt_in(4);} -void gpio_irq5(void) {handle_interrupt_in(5);} -void gpio_irq6(void) {handle_interrupt_in(6);} -void gpio_irq7(void) {handle_interrupt_in(7);} - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { - if (pin == NC) return -1; - - irq_handler = handler; - - int found_free_channel = 0; - int i = 0; - for (i=0; ich = i; - found_free_channel = 1; - break; - } - } - if (!found_free_channel) return -1; - - /* Enable AHB clock to the GPIO domain. */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); - - /* Enable AHB clock to the FlexInt, GroupedInt domain. */ - LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24)); - - /* To select a pin for any of the eight pin interrupts, write the pin number - * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55. - * @see: mbed_capi/PinNames.h - */ - LPC_SYSCON->PINTSEL[obj->ch] = (pin >> 5) ? (pin - 8) : (pin); - - // Interrupt Wake-Up Enable - LPC_SYSCON->STARTERP0 |= 1 << obj->ch; - - void (*channels_irq)(void) = NULL; - switch (obj->ch) { - case 0: channels_irq = &gpio_irq0; break; - case 1: channels_irq = &gpio_irq1; break; - case 2: channels_irq = &gpio_irq2; break; - case 3: channels_irq = &gpio_irq3; break; - case 4: channels_irq = &gpio_irq4; break; - case 5: channels_irq = &gpio_irq5; break; - case 6: channels_irq = &gpio_irq6; break; - case 7: channels_irq = &gpio_irq7; break; - } - NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq); - NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->ch] = 0; - LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch); -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { - unsigned int ch_bit = (1 << obj->ch); - - // Clear interrupt - if (!(LPC_GPIO_X->ISEL & ch_bit)) - LPC_GPIO_X->IST = ch_bit; - - // Edge trigger - LPC_GPIO_X->ISEL &= ~ch_bit; - if (event == IRQ_RISE) { - if (enable) { - LPC_GPIO_X->IENR |= ch_bit; - } else { - LPC_GPIO_X->IENR &= ~ch_bit; - } - } else { - if (enable) { - LPC_GPIO_X->IENF |= ch_bit; - } else { - LPC_GPIO_X->IENF &= ~ch_bit; - } - } -} - -void gpio_irq_enable(gpio_irq_t *obj) { - NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); -} - -void gpio_irq_disable(gpio_irq_t *obj) { - NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h b/targets/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h deleted file mode 100644 index fe6d6c1e05c..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h +++ /dev/null @@ -1,56 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - - __IO uint32_t *reg_dir; - __IO uint32_t *reg_set; - __IO uint32_t *reg_clr; - __I uint32_t *reg_in; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) { - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) - *obj->reg_set = obj->mask; - else - *obj->reg_clr = obj->mask; -} - -static inline int gpio_read(gpio_t *obj) { - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -static inline int gpio_is_connected(const gpio_t *obj) { - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c deleted file mode 100644 index eed896272dd..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c +++ /dev/null @@ -1,406 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" // For the Peripheral to Pin Definitions found in the individual Target's Platform - -#define I2C_CONSET(x) (x->i2c->CONSET) -#define I2C_CONCLR(x) (x->i2c->CONCLR) -#define I2C_STAT(x) (x->i2c->STAT) -#define I2C_DAT(x) (x->i2c->DAT) -#define I2C_SCLL(x, val) (x->i2c->SCLL = val) -#define I2C_SCLH(x, val) (x->i2c->SCLH = val) - -static const uint32_t I2C_addr_offset[2][4] = { - {0x0C, 0x20, 0x24, 0x28}, - {0x30, 0x34, 0x38, 0x3C} -}; - -static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) { - I2C_CONCLR(obj) = (start << 5) - | (stop << 4) - | (interrupt << 3) - | (acknowledge << 2); -} - -static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) { - I2C_CONSET(obj) = (start << 5) - | (stop << 4) - | (interrupt << 3) - | (acknowledge << 2); -} - -// Clear the Serial Interrupt (SI) -static inline void i2c_clear_SI(i2c_t *obj) { - i2c_conclr(obj, 0, 0, 1, 0); -} - -static inline int i2c_status(i2c_t *obj) { - return I2C_STAT(obj); -} - -// Wait until the Serial Interrupt (SI) is set -static int i2c_wait_SI(i2c_t *obj) { - int timeout = 0; - while (!(I2C_CONSET(obj) & (1 << 3))) { - timeout++; - if (timeout > 100000) return -1; - } - return 0; -} - -static inline void i2c_interface_enable(i2c_t *obj) { - I2C_CONSET(obj) = 0x40; -} - -static inline void i2c_power_enable(i2c_t *obj) { - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 5); - LPC_SYSCON->PRESETCTRL |= 1 << 1; -} - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) { - // determine the SPI to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - obj->i2c = (LPC_I2C_Type *)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT((int)obj->i2c != NC); - - // enable power - i2c_power_enable(obj); - - // set default frequency at 100k - i2c_frequency(obj, 100000); - i2c_conclr(obj, 1, 1, 1, 1); - i2c_interface_enable(obj); - - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); -} - -inline int i2c_start(i2c_t *obj) { - int status = 0; - int isInterrupted = I2C_CONSET(obj) & (1 << 3); - - // 8.1 Before master mode can be entered, I2CON must be initialised to: - // - I2EN STA STO SI AA - - - // - 1 0 0 x x - - - // if AA = 0, it can't enter slave mode - i2c_conclr(obj, 1, 1, 0, 1); - - // The master mode may now be entered by setting the STA bit - // this will generate a start condition when the bus becomes free - i2c_conset(obj, 1, 0, 0, 1); - // Clearing SI bit when it wasn't set on entry can jump past state - // 0x10 or 0x08 and erroneously send uninitialized slave address. - if (isInterrupted) - i2c_clear_SI(obj); - - i2c_wait_SI(obj); - status = i2c_status(obj); - - // Clear start bit now that it's transmitted - i2c_conclr(obj, 1, 0, 0, 0); - return status; -} - -inline int i2c_stop(i2c_t *obj) { - int timeout = 0; - - // write the stop bit - i2c_conset(obj, 0, 1, 0, 0); - i2c_clear_SI(obj); - - // wait for STO bit to reset - while(I2C_CONSET(obj) & (1 << 4)) { - timeout ++; - if (timeout > 100000) return 1; - } - - return 0; -} - - -static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) { - // write the data - I2C_DAT(obj) = value; - - // clear SI to init a send - i2c_clear_SI(obj); - - // wait and return status - i2c_wait_SI(obj); - return i2c_status(obj); -} - -static inline int i2c_do_read(i2c_t *obj, int last) { - // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack) - if (last) { - i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK - } else { - i2c_conset(obj, 0, 0, 0, 1); // send a ACK - } - - // accept byte - i2c_clear_SI(obj); - - // wait for it to arrive - i2c_wait_SI(obj); - - // return the data - return (I2C_DAT(obj) & 0xFF); -} - -void i2c_frequency(i2c_t *obj, int hz) { - // No peripheral clock divider on the M0 - uint32_t PCLK = SystemCoreClock; - - uint32_t pulse = PCLK / (hz * 2); - - // I2C Rate - I2C_SCLL(obj, pulse); - I2C_SCLH(obj, pulse); -} - -// The I2C does a read or a write as a whole operation -// There are two types of error conditions it can encounter -// 1) it can not obtain the bus -// 2) it gets error responses at part of the transmission -// -// We tackle them as follows: -// 1) we retry until we get the bus. we could have a "timeout" if we can not get it -// which basically turns it in to a 2) -// 2) on error, we use the standard error mechanisms to report/debug -// -// Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programatically -// check for that - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { - int count, status; - - status = i2c_start(obj); - - if ((status != 0x10) && (status != 0x08)) { - i2c_stop(obj); - return I2C_ERROR_BUS_BUSY; - } - - status = i2c_do_write(obj, (address | 0x01), 1); - if (status != 0x40) { - i2c_stop(obj); - return I2C_ERROR_NO_SLAVE; - } - - // Read in all except last byte - for (count = 0; count < (length - 1); count++) { - int value = i2c_do_read(obj, 0); - status = i2c_status(obj); - if (status != 0x50) { - i2c_stop(obj); - return count; - } - data[count] = (char) value; - } - - // read in last byte - int value = i2c_do_read(obj, 1); - status = i2c_status(obj); - if (status != 0x58) { - i2c_stop(obj); - return length - 1; - } - - data[count] = (char) value; - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - } - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { - int i, status; - - status = i2c_start(obj); - - if ((status != 0x10) && (status != 0x08)) { - i2c_stop(obj); - return I2C_ERROR_BUS_BUSY; - } - - status = i2c_do_write(obj, (address & 0xFE), 1); - if (status != 0x18) { - i2c_stop(obj); - return I2C_ERROR_NO_SLAVE; - } - - for (i=0; i= 0) && (idx <= 3)) { - addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx]; - *((uint32_t *) addr) = address & 0xFF; - } -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -#endif // #if DEVICE_I2C diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/objects.h b/targets/TARGET_NXP/TARGET_LPC11UXX/objects.h deleted file mode 100644 index 755e77311a6..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/objects.h +++ /dev/null @@ -1,66 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - uint32_t ch; -}; - -struct port_s { - __IO uint32_t *reg_dir; - __IO uint32_t *reg_mpin; - PortName port; - uint32_t mask; -}; - -struct pwmout_s { - PWMName pwm; -}; - -struct serial_s { - LPC_USART_Type *uart; - int index; -}; - -struct analogin_s { - ADCName adc; -}; - -struct i2c_s { - LPC_I2C_Type *i2c; -}; - -struct spi_s { - LPC_SSPx_Type *spi; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/pinmap.c b/targets/TARGET_NXP/TARGET_LPC11UXX/pinmap.c deleted file mode 100644 index 9ca018c86ad..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/pinmap.c +++ /dev/null @@ -1,56 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define LPC_IOCON0_BASE (LPC_IOCON_BASE) -#define LPC_IOCON1_BASE (LPC_IOCON_BASE + 0x60) - -void pin_function(PinName pin, int function) { - MBED_ASSERT(pin != (PinName)NC); - if (pin == (PinName)NC) return; - - uint32_t pin_number = (uint32_t)pin; - - __IO uint32_t *reg = (pin_number < 32) ? - (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) : - (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32)); - - // pin function bits: [2:0] -> 111 = (0x7) - *reg = (*reg & ~0x7) | (function & 0x7); -} - -void pin_mode(PinName pin, PinMode mode) { - MBED_ASSERT(pin != (PinName)NC); - uint32_t pin_number = (uint32_t)pin; - uint32_t drain = ((uint32_t) mode & (uint32_t) OpenDrain) >> 2; - - __IO uint32_t *reg = (pin_number < 32) ? - (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) : - (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32)); - uint32_t tmp = *reg; - - // pin mode bits: [4:3] -> 11000 = (0x3 << 3) - tmp &= ~(0x3 << 3); - tmp |= (mode & 0x3) << 3; - - // drain - tmp &= ~(0x1 << 10); - tmp |= drain << 10; - - *reg = tmp; -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/port_api.c b/targets/TARGET_NXP/TARGET_LPC11UXX/port_api.c deleted file mode 100644 index 334c3473918..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/port_api.c +++ /dev/null @@ -1,67 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" - -PinName port_pin(PortName port, int pin_n) { - return (PinName)((port << PORT_SHIFT) | pin_n); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { - obj->port = port; - obj->mask = mask; - - LPC_GPIO->MASK[port] = ~mask; - - obj->reg_mpin = &LPC_GPIO->MPIN[port]; - obj->reg_dir = &LPC_GPIO->DIR[port]; - - uint32_t i; - // The function is set per pin: reuse gpio logic - for (i=0; i<32; i++) { - if (obj->mask & (1<port, i)); - } - } - - port_dir(obj, dir); -} - -void port_mode(port_t *obj, PinMode mode) { - uint32_t i; - // The mode is set per pin: reuse pinmap logic - for (i=0; i<32; i++) { - if (obj->mask & (1<port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) { - switch (dir) { - case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; - case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; - } -} - -void port_write(port_t *obj, int value) { - *obj->reg_mpin = value; -} - -int port_read(port_t *obj) { - return (*obj->reg_mpin); -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/pwmout_api.c b/targets/TARGET_NXP/TARGET_LPC11UXX/pwmout_api.c deleted file mode 100644 index 394b597fb51..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/pwmout_api.c +++ /dev/null @@ -1,162 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pwmout_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" // For the Peripheral to Pin Definitions found in the individual Target's Platform - -#define TCR_CNT_EN 0x00000001 -#define TCR_RESET 0x00000002 - -typedef struct { - uint8_t timer; - uint8_t mr; -} timer_mr; - -static timer_mr pwm_timer_map[11] = { - {0, 0}, {0, 1}, {0, 2}, - {1, 0}, {1, 1}, - {2, 0}, {2, 1}, {2, 2}, - {3, 0}, {3, 1}, {3, 2}, -}; - -static LPC_CTxxBx_Type *Timers[4] = { - LPC_CT16B0, LPC_CT16B1, - LPC_CT32B0, LPC_CT32B1 -}; - -void pwmout_init(pwmout_t* obj, PinName pin) { - // determine the channel - PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - MBED_ASSERT(pwm != (PWMName)NC); - - obj->pwm = pwm; - - // Timer registers - timer_mr tid = pwm_timer_map[pwm]; - LPC_CTxxBx_Type *timer = Timers[tid.timer]; - - // Disable timer - timer->TCR = 0; - - // Power the correspondent timer - LPC_SYSCON->SYSAHBCLKCTRL |= 1 << (tid.timer + 7); - - /* Enable PWM function */ - timer->PWMC = (1 << 3)|(1 << 2)|(1 << 1)|(1 << 0); - - /* Reset Functionality on MR3 controlling the PWM period */ - timer->MCR = 1 << 10; - - // default to 20ms: standard for servos, and fine for e.g. brightness control - pwmout_period_ms(obj, 20); - pwmout_write (obj, 0); - - // Wire pinout - pinmap_pinout(pin, PinMap_PWM); -} - -void pwmout_free(pwmout_t* obj) { - // [TODO] -} - -void pwmout_write(pwmout_t* obj, float value) { - if (value < 0.0f) { - value = 0.0; - } else if (value > 1.0f) { - value = 1.0; - } - - timer_mr tid = pwm_timer_map[obj->pwm]; - LPC_CTxxBx_Type *timer = Timers[tid.timer]; - uint32_t t_off = timer->MR3 - (uint32_t)((float)(timer->MR3) * value); - - timer->MR[tid.mr] = t_off; -} - -float pwmout_read(pwmout_t* obj) { - timer_mr tid = pwm_timer_map[obj->pwm]; - LPC_CTxxBx_Type *timer = Timers[tid.timer]; - - float v = (float)(timer->MR3 - timer->MR[tid.mr]) / (float)(timer->MR3); - return (v > 1.0f) ? (1.0f) : (v); -} - -void pwmout_period(pwmout_t* obj, float seconds) { - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) { - pwmout_period_us(obj, ms * 1000); -} - -// Set the PWM period, keeping the duty cycle the same. -void pwmout_period_us(pwmout_t* obj, int us) { - int i = 0; - uint32_t period_ticks = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000); - - timer_mr tid = pwm_timer_map[obj->pwm]; - LPC_CTxxBx_Type *timer = Timers[tid.timer]; - uint32_t old_period_ticks = timer->MR3; - - // for 16bit timer, set prescaler to avoid overflow - if (timer == LPC_CT16B0 || timer == LPC_CT16B1) { - uint16_t high_period_ticks = period_ticks >> 16; - timer->PR = high_period_ticks; - period_ticks /= (high_period_ticks + 1); - } - - timer->TCR = TCR_RESET; - timer->MR3 = period_ticks; - - // Scale the pulse width to preserve the duty ratio - if (old_period_ticks > 0) { - for (i=0; i<3; i++) { - uint32_t t_off = period_ticks - (uint32_t)(((uint64_t)timer->MR[i] * (uint64_t)period_ticks) / (uint64_t)old_period_ticks); - timer->MR[i] = t_off; - } - } - timer->TCR = TCR_CNT_EN; -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) { - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) { - timer_mr tid = pwm_timer_map[obj->pwm]; - LPC_CTxxBx_Type *timer = Timers[tid.timer]; - uint32_t t_on = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000 / (timer->PR + 1)); - - timer->TCR = TCR_RESET; - if (t_on > timer->MR3) { - pwmout_period_us(obj, us); - t_on = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000 / (timer->PR + 1)); - } - uint32_t t_off = timer->MR3 - t_on; - timer->MR[tid.mr] = t_off; - timer->TCR = TCR_CNT_EN; -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/serial_api.c b/targets/TARGET_NXP/TARGET_LPC11UXX/serial_api.c deleted file mode 100644 index 2545c8d1a07..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/serial_api.c +++ /dev/null @@ -1,320 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -// math.h required for floating point operations for baud rate calculation -#include -#include -#include - -#include "serial_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" // For the Peripheral to Pin Definitions found in the individual Target's Platform - -/****************************************************************************** - * INITIALIZATION - ******************************************************************************/ -#define UART_NUM 1 - -static uint32_t serial_irq_ids[UART_NUM] = {0}; -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) { - int is_stdio_uart = 0; - - // determine the UART to use - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)uart != NC); - - obj->uart = (LPC_USART_Type *)uart; - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12); - - // [TODO] Consider more elegant approach - // disconnect USBTX/RX mapping mux, for case when switching ports -#ifdef USBTX - pin_function(USBTX, 0); - pin_function(USBRX, 0); -#endif - - // enable fifos and default rx trigger level - obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled - | 0 << 1 // Rx Fifo Reset - | 0 << 2 // Tx Fifo Reset - | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars - - // disable irqs - obj->uart->IER = 0 << 0 // Rx Data available irq enable - | 0 << 1 // Tx Fifo empty irq enable - | 0 << 2; // Rx Line Status irq enable - - // set default baud rate and format - serial_baud (obj, 9600); - serial_format(obj, 8, ParityNone, 1); - - // pinout the chosen uart - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - // set rx/tx pins in PullUp mode - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - switch (uart) { - case UART_0: obj->index = 0; break; - } - - is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); - - if (is_stdio_uart) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) { - serial_irq_ids[obj->index] = 0; -} - -// serial_baud -// set the baud rate, taking in to account the current SystemFrequency -void serial_baud(serial_t *obj, int baudrate) { - LPC_SYSCON->UARTCLKDIV = 0x1; - uint32_t PCLK = SystemCoreClock; - // First we check to see if the basic divide with no DivAddVal/MulVal - // ratio gives us an integer result. If it does, we set DivAddVal = 0, - // MulVal = 1. Otherwise, we search the valid ratio value range to find - // the closest match. This could be more elegant, using search methods - // and/or lookup tables, but the brute force method is not that much - // slower, and is more maintainable. - uint16_t DL = PCLK / (16 * baudrate); - - uint8_t DivAddVal = 0; - uint8_t MulVal = 1; - int hit = 0; - uint16_t dlv; - uint8_t mv, dav; - if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder - int err_best = baudrate, b; - for (mv = 1; mv < 16 && !hit; mv++) - { - for (dav = 0; dav < mv; dav++) - { - // baudrate = PCLK / (16 * dlv * (1 + (DivAdd / Mul)) - // solving for dlv, we get dlv = mul * PCLK / (16 * baudrate * (divadd + mul)) - // mul has 4 bits, PCLK has 27 so we have 1 bit headroom which can be used for rounding - // for many values of mul and PCLK we have 2 or more bits of headroom which can be used to improve precision - // note: X / 32 doesn't round correctly. Instead, we use ((X / 16) + 1) / 2 for correct rounding - - if ((mv * PCLK * 2) & 0x80000000) // 1 bit headroom - dlv = ((((2 * mv * PCLK) / (baudrate * (dav + mv))) / 16) + 1) / 2; - else // 2 bits headroom, use more precision - dlv = ((((4 * mv * PCLK) / (baudrate * (dav + mv))) / 32) + 1) / 2; - - // datasheet says if DLL==DLM==0, then 1 is used instead since divide by zero is ungood - if (dlv == 0) - dlv = 1; - - // datasheet says if dav > 0 then DL must be >= 2 - if ((dav > 0) && (dlv < 2)) - dlv = 2; - - // integer rearrangement of the baudrate equation (with rounding) - b = ((PCLK * mv / (dlv * (dav + mv) * 8)) + 1) / 2; - - // check to see how we went - b = abs(b - baudrate); - if (b < err_best) - { - err_best = b; - - DL = dlv; - MulVal = mv; - DivAddVal = dav; - - if (b == baudrate) - { - hit = 1; - break; - } - } - } - } - } - - // set LCR[DLAB] to enable writing to divider registers - obj->uart->LCR |= (1 << 7); - - // set divider values - obj->uart->DLM = (DL >> 8) & 0xFF; - obj->uart->DLL = (DL >> 0) & 0xFF; - obj->uart->FDR = (uint32_t) DivAddVal << 0 - | (uint32_t) MulVal << 4; - - // clear LCR[DLAB] - obj->uart->LCR &= ~(1 << 7); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits - MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || - (parity == ParityForced1) || (parity == ParityForced0)); - - stop_bits -= 1; - data_bits -= 5; - - int parity_enable = 0, parity_select = 0; - switch (parity) { - case ParityNone: parity_enable = 0; parity_select = 0; break; - case ParityOdd : parity_enable = 1; parity_select = 0; break; - case ParityEven: parity_enable = 1; parity_select = 1; break; - case ParityForced1: parity_enable = 1; parity_select = 2; break; - case ParityForced0: parity_enable = 1; parity_select = 3; break; - default: - break; - } - - obj->uart->LCR = data_bits << 0 - | stop_bits << 2 - | parity_enable << 3 - | parity_select << 4; -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ -static inline void uart_irq(uint32_t iir, uint32_t index) { - // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling - SerialIrq irq_type; - switch (iir) { - case 1: irq_type = TxIrq; break; - case 2: irq_type = RxIrq; break; - default: return; - } - - if (serial_irq_ids[index] != 0) - irq_handler(serial_irq_ids[index], irq_type); -} - -void uart0_irq() {uart_irq((LPC_USART->IIR >> 1) & 0x7, 0);} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - switch ((int)obj->uart) { - case UART_0: irq_n=UART_IRQn ; vector = (uint32_t)&uart0_irq; break; - } - - if (enable) { - obj->uart->IER |= 1 << irq; - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - } else { // disable - int all_disabled = 0; - SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); - - obj->uart->IER &= ~(1 << irq); - all_disabled = (obj->uart->IER & (1 << other_irq)) == 0; - - if (all_disabled) - NVIC_DisableIRQ(irq_n); - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ -int serial_getc(serial_t *obj) { - while (!serial_readable(obj)); - return obj->uart->RBR; -} - -void serial_putc(serial_t *obj, int c) { - while (!serial_writable(obj)); - obj->uart->THR = c; -} - -int serial_readable(serial_t *obj) { - return obj->uart->LSR & 0x01; -} - -int serial_writable(serial_t *obj) { - return obj->uart->LSR & 0x20; -} - -void serial_clear(serial_t *obj) { - obj->uart->FCR = 1 << 1 // rx FIFO reset - | 1 << 2 // tx FIFO reset - | 0 << 6; // interrupt depth -} - -void serial_pinout_tx(PinName tx) { - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) { - obj->uart->LCR |= (1 << 6); -} - -void serial_break_clear(serial_t *obj) { - obj->uart->LCR &= ~(1 << 6); -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_CTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_RTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_RTS; -} - diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/sleep.c b/targets/TARGET_NXP/TARGET_LPC11UXX/sleep.c deleted file mode 100644 index 261e1408713..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/sleep.c +++ /dev/null @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" -#include "cmsis.h" -#include "mbed_interface.h" - -void hal_sleep(void) { - // ensure debug is disconnected - #if DEVICE_SEMIHOST - mbed_interface_disconnect(); - #endif - - // PCON[PD] set to sleep - LPC_PMU->PCON = 0x0; - - // SRC[SLEEPDEEP] set to 0 = sleep - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - - // wait for interrupt - __WFI(); -} - -/* -* The mbed lpc1768 does not support the deepsleep mode -* as a debugger is connected to it (the mbed interface). -* -* As mentionned in an application note from NXP: -* -* http://www.po-star.com/public/uploads/20120319123122_141.pdf -* -* {{{ -* The user should be aware of certain limitations during debugging. -* The most important is that, due to limitations of the Cortex-M3 -* integration, the LPC17xx cannot wake up in the usual manner from -* Deep Sleep and Power-down modes. It is recommended not to use these -* modes during debug. Once an application is downloaded via JTAG/SWD -* interface, the USB to SWD/JTAG debug adapter (Keil ULINK2 for example) -* should be removed from the target board, and thereafter, power cycle -* the LPC17xx to allow wake-up from deep sleep and power-down modes -* }}} -* -* As the interface firmware does not reset the target when a -* mbed_interface_disconnect() semihosting call is made, the -* core cannot wake-up from deepsleep. -* -* We treat a deepsleep() as a normal sleep(). -*/ - -void hal_deepsleep(void) { - // ensure debug is disconnected - #if DEVICE_SEMIHOST - mbed_interface_disconnect(); - #endif - - // PCON[PD] set to deepsleep - LPC_PMU->PCON = 0x1; - - // SRC[SLEEPDEEP] set to 1 = deep sleep - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - // Power up everything after powerdown - LPC_SYSCON->PDAWAKECFG &= 0xFFFFF800; - - // wait for interrupt - __WFI(); -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/spi_api.c b/targets/TARGET_NXP/TARGET_LPC11UXX/spi_api.c deleted file mode 100644 index 69230d7c68e..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/spi_api.c +++ /dev/null @@ -1,229 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include -#include "spi_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" // For the Peripheral to Pin Definitions found in the individual Target's Platform - -static inline int ssp_disable(spi_t *obj); -static inline int ssp_enable(spi_t *obj); - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { - // determine the SPI to use - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->spi = (LPC_SSPx_Type*)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT((int)obj->spi != NC); - - // enable power and clocking - switch ((int)obj->spi) { - case SPI_0: - LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11; - LPC_SYSCON->SSP0CLKDIV = 0x01; - LPC_SYSCON->PRESETCTRL |= 1 << 0; - break; - case SPI_1: - LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18; - LPC_SYSCON->SSP1CLKDIV = 0x01; - LPC_SYSCON->PRESETCTRL |= 1 << 2; - break; - } - - // pin out the spi pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - if (ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } -} - -void spi_free(spi_t *obj) {} - -void spi_format(spi_t *obj, int bits, int mode, int slave) { - MBED_ASSERT((bits >= 4 && bits <= 16) || (mode >= 0 && mode <= 3)); - - ssp_disable(obj); - - int polarity = (mode & 0x2) ? 1 : 0; - int phase = (mode & 0x1) ? 1 : 0; - - // set it up - int DSS = bits - 1; // DSS (data select size) - int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity - int SPH = (phase) ? 1 : 0; // SPH - clock out phase - - int FRF = 0; // FRF (frame format) = SPI - uint32_t tmp = obj->spi->CR0; - tmp &= ~(0x00FF); // Clear DSS, FRF, CPOL and CPHA [7:0] - tmp |= DSS << 0 - | FRF << 4 - | SPO << 6 - | SPH << 7; - obj->spi->CR0 = tmp; - - tmp = obj->spi->CR1; - tmp &= ~(0xD); - tmp |= 0 << 0 // LBM - loop back mode - off - | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave - | 0 << 3; // SOD - slave output disable - na - obj->spi->CR1 = tmp; - - ssp_enable(obj); -} - -void spi_frequency(spi_t *obj, int hz) { - ssp_disable(obj); - - uint32_t PCLK = SystemCoreClock; - - int prescaler; - - for (prescaler = 2; prescaler <= 254; prescaler += 2) { - int prescale_hz = PCLK / prescaler; - - // calculate the divider - int divider = floor(((float)prescale_hz / (float)hz) + 0.5f); - - // check we can support the divider - if (divider < 256) { - // prescaler - obj->spi->CPSR = prescaler; - - // divider - obj->spi->CR0 &= ~(0xFF00); // Clear SCR: Serial clock rate [15:8] - obj->spi->CR0 |= (divider - 1) << 8; - ssp_enable(obj); - return; - } - } - error("Couldn't setup requested SPI frequency"); -} - -static inline int ssp_disable(spi_t *obj) { - return obj->spi->CR1 &= ~(1 << 1); -} - -static inline int ssp_enable(spi_t *obj) { - return obj->spi->CR1 |= (1 << 1); -} - -static inline int ssp_readable(spi_t *obj) { - return obj->spi->SR & (1 << 2); -} - -static inline int ssp_writeable(spi_t *obj) { - return obj->spi->SR & (1 << 1); -} - -static inline void ssp_write(spi_t *obj, int value) { - while (!ssp_writeable(obj)); - obj->spi->DR = value; -} - -static inline int ssp_read(spi_t *obj) { - while (!ssp_readable(obj)); - return obj->spi->DR; -} - -static inline int ssp_busy(spi_t *obj) { - return (obj->spi->SR & (1 << 4)) ? (1) : (0); -} - -int spi_master_write(spi_t *obj, int value) { - ssp_write(obj, value); - return ssp_read(obj); -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) { - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_slave_receive(spi_t *obj) { - return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); -} - -int spi_slave_read(spi_t *obj) { - return obj->spi->DR; -} - -void spi_slave_write(spi_t *obj, int value) { - while (ssp_writeable(obj) == 0) ; - obj->spi->DR = value; -} - -int spi_busy(spi_t *obj) { - return ssp_busy(obj); -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/us_ticker.c b/targets/TARGET_NXP/TARGET_LPC11UXX/us_ticker.c deleted file mode 100644 index 0ae71396742..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/us_ticker.c +++ /dev/null @@ -1,76 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -#if DEVICE_USTICKER - -#define US_TICKER_TIMER ((LPC_CTxxBx_Type *)LPC_CT32B1_BASE) -#define US_TICKER_TIMER_IRQn TIMER_32_1_IRQn - -int us_ticker_inited = 0; - -void us_ticker_init(void) { - if (us_ticker_inited) return; - us_ticker_inited = 1; - - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10); // Clock TIMER_1 - uint32_t PCLK = SystemCoreClock; - - US_TICKER_TIMER->TCR = 0x2; // reset - - uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks) - US_TICKER_TIMER->PR = prescale - 1; - US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0 - - NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); - NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); -} - -uint32_t us_ticker_read() { - if (!us_ticker_inited) - us_ticker_init(); - - return US_TICKER_TIMER->TC; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) { - // set match value - US_TICKER_TIMER->MR0 = (uint32_t)timestamp; - // enable match interrupt - US_TICKER_TIMER->MCR |= 1; -} - -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn); -} - -void us_ticker_disable_interrupt(void) { - US_TICKER_TIMER->MCR &= ~1; -} - -void us_ticker_clear_interrupt(void) { - US_TICKER_TIMER->IR = 1; -} - -void us_ticker_free(void) -{ - -} - -#endif // DEVICE_USTICKER diff --git a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/PeripheralNames.h b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/PeripheralNames.h deleted file mode 100644 index 55ca9e3d2df..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/PeripheralNames.h +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// Default peripherals -#define MBED_SPI0 P0_14, P0_15, P0_12, P0_13 - -#define MBED_UART0 P0_4, P0_0 -#define MBED_UARTUSB USBTX, USBRX - -#define MBED_I2C0 P0_10, P0_11 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/PinNames.h b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/PinNames.h deleted file mode 100644 index a5551fcfea6..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/PinNames.h +++ /dev/null @@ -1,108 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -typedef enum { - P0_0 = 0, - P0_1 = 1, - P0_2 = 2, - P0_3 = 3, - P0_4 = 4, - P0_5 = 5, - P0_6 = 6, - P0_7 = 7, - P0_8 = 8, - P0_9 = 9, - P0_10 = 10, - P0_11 = 11, - P0_12 = 12, - P0_13 = 13, - P0_14 = 14, - P0_15 = 15, - P0_16 = 16, - P0_17 = 17, - - D0 = P0_0, - D1 = P0_4, - D2 = P0_6, - D3 = P0_8, - D4 = P0_9, - - D7 = P0_7, - D8 = P0_17, - D9 = P0_16, - D10 = P0_13, - D11 = P0_14, - D12 = P0_15, - D13 = P0_12, - D14 = P0_10, - D15 = P0_11, - - A4 = P0_10, - A5 = P0_11, - - // Elektor CoCO-ri-Co board - LED_RED = P0_11, - LED_GREEN = P0_10, - - // mbed original LED naming - LED1 = LED_RED, - LED2 = LED_GREEN, - LED3 = LED_RED, - LED4 = LED_GREEN, - - // Serial to USB pins - USBTX = P0_6, - USBRX = P0_1, - - // Not connected - NC = (int)0xFFFFFFFF, -} PinName; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX - -typedef struct { - unsigned char n; - unsigned char offset; -} SWM_Map; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_ARM_MICRO/LPC812.sct b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_ARM_MICRO/LPC812.sct deleted file mode 100644 index b5cf68bbd5c..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_ARM_MICRO/LPC812.sct +++ /dev/null @@ -1,48 +0,0 @@ -#! armcc -E - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -; 16K flash -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x4000 -#endif - -; 4KB -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x10000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00001000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 -#define VECTOR_SIZE 0xC0 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S deleted file mode 100644 index 85beb968cbd..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S +++ /dev/null @@ -1,185 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC8xx.s -; * @purpose: CMSIS Cortex-M0+ Core Device Startup File -; * for the NXP LPC8xx Device Series -; * @version: V1.0 -; * @date: 16. Aug. 2012 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD SPI0_IRQHandler ; SPI0 controller - DCD SPI1_IRQHandler ; SPI1 controller - DCD 0 ; Reserved - DCD UART0_IRQHandler ; UART0 - DCD UART1_IRQHandler ; UART1 - DCD UART2_IRQHandler ; UART2 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C_IRQHandler ; I2C controller - DCD SCT_IRQHandler ; Smart Counter Timer - DCD MRT_IRQHandler ; Multi-Rate Timer - DCD CMP_IRQHandler ; Comparator - DCD WDT_IRQHandler ; PIO1 (0:11) - DCD BOD_IRQHandler ; Brown Out Detect - DCD 0 ; Reserved - DCD WKT_IRQHandler ; Wakeup timer - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PININT0_IRQHandler ; PIO INT0 - DCD PININT1_IRQHandler ; PIO INT1 - DCD PININT2_IRQHandler ; PIO INT2 - DCD PININT3_IRQHandler ; PIO INT3 - DCD PININT4_IRQHandler ; PIO INT4 - DCD PININT5_IRQHandler ; PIO INT5 - DCD PININT6_IRQHandler ; PIO INT6 - DCD PININT7_IRQHandler ; PIO INT7 - - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) -; now, under COMMON lpc8xx_nmi.c and lpc8xx_nmi.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT NMI_Handler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT SCT_IRQHandler [WEAK] - EXPORT MRT_IRQHandler [WEAK] - EXPORT CMP_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - - EXPORT WKT_IRQHandler [WEAK] - - EXPORT PININT0_IRQHandler [WEAK] - EXPORT PININT1_IRQHandler [WEAK] - EXPORT PININT2_IRQHandler [WEAK] - EXPORT PININT3_IRQHandler [WEAK] - EXPORT PININT4_IRQHandler [WEAK] - EXPORT PININT5_IRQHandler [WEAK] - EXPORT PININT6_IRQHandler [WEAK] - EXPORT PININT7_IRQHandler [WEAK] - -NMI_Handler -SPI0_IRQHandler -SPI1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -I2C_IRQHandler -SCT_IRQHandler -MRT_IRQHandler -CMP_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -WKT_IRQHandler -PININT0_IRQHandler -PININT1_IRQHandler -PININT2_IRQHandler -PININT3_IRQHandler -PININT4_IRQHandler -PININT5_IRQHandler -PININT6_IRQHandler -PININT7_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_GCC_ARM/LPC812.ld b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_GCC_ARM/LPC812.ld deleted file mode 100644 index f51f0d6dfe7..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_GCC_ARM/LPC812.ld +++ /dev/null @@ -1,156 +0,0 @@ -/* Linker script for mbed LPC812-GCC-ARM based on LPC824.ld */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Linker script to configure memory regions. */ -MEMORY -{ - /* Define each memory region */ - FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x4000 /* 16K bytes */ - RAM (rwx) : ORIGIN = 0x10000000+0xC0, LENGTH = 0x1000-0xC0 /* 4K bytes */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - *(.text.SystemInit) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_IAR/LPC812.icf b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_IAR/LPC812.icf deleted file mode 100644 index 51713a8e07e..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_IAR/LPC812.icf +++ /dev/null @@ -1,39 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00003FFF; -define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000; -define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF; -define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0; -define symbol __ICFEDIT_region_RAM_end__ = 0x10000FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x800; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __CRP_start__ = 0x000002FC; -define symbol __CRP_end__ = 0x000002FF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block HEAP, block CSTACK }; -place in CRP_region { section .crp }; diff --git a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_IAR/startup_LPC8xx.S b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_IAR/startup_LPC8xx.S deleted file mode 100644 index 48ead87f409..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_IAR/startup_LPC8xx.S +++ /dev/null @@ -1,198 +0,0 @@ -/************************************************** - * - * Part one of the system initialization code, contains low-level - * initialization, plain thumb variant. - * - * Copyright 2011 IAR Systems. All rights reserved. - * - * $Revision: 47876 $ - * - **************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD SPI0_IRQHandler ; SPI0 controller - DCD SPI1_IRQHandler ; SPI1 controller - DCD 0 ; Reserved - DCD UART0_IRQHandler ; UART0 - DCD UART1_IRQHandler ; UART1 - DCD UART2_IRQHandler ; UART2 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C_IRQHandler ; I2C controller - DCD SCT_IRQHandler ; Smart Counter Timer - DCD MRT_IRQHandler ; Multi-Rate Timer - DCD CMP_IRQHandler ; Comparator - DCD WDT_IRQHandler ; PIO1 (0:11) - DCD BOD_IRQHandler ; Brown Out Detect - DCD 0 ; Reserved - DCD WKT_IRQHandler ; Wakeup timer - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PININT0_IRQHandler ; PIO INT0 - DCD PININT1_IRQHandler ; PIO INT1 - DCD PININT2_IRQHandler ; PIO INT2 - DCD PININT3_IRQHandler ; PIO INT3 - DCD PININT4_IRQHandler ; PIO INT4 - DCD PININT5_IRQHandler ; PIO INT5 - DCD PININT6_IRQHandler ; PIO INT6 - DCD PININT7_IRQHandler ; PIO INT7 -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK SVC_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI1_IRQHandler - PUBWEAK UART0_IRQHandler - PUBWEAK UART1_IRQHandler - PUBWEAK UART2_IRQHandler - PUBWEAK I2C_IRQHandler - PUBWEAK SCT_IRQHandler - PUBWEAK MRT_IRQHandler - PUBWEAK CMP_IRQHandler - PUBWEAK WDT_IRQHandler - PUBWEAK BOD_IRQHandler - PUBWEAK WKT_IRQHandler - PUBWEAK PININT0_IRQHandler - PUBWEAK PININT1_IRQHandler - PUBWEAK PININT2_IRQHandler - PUBWEAK PININT3_IRQHandler - PUBWEAK PININT4_IRQHandler - PUBWEAK PININT5_IRQHandler - PUBWEAK PININT6_IRQHandler - PUBWEAK PININT7_IRQHandler - - SECTION .text:CODE:REORDER:NOROOT(1) - THUMB - -NMI_Handler -HardFault_Handler -SVC_Handler -PendSV_Handler -SysTick_Handler -SPI0_IRQHandler -SPI1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -I2C_IRQHandler -SCT_IRQHandler -MRT_IRQHandler -CMP_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -WKT_IRQHandler -PININT0_IRQHandler -PININT1_IRQHandler -PININT2_IRQHandler -PININT3_IRQHandler -PININT4_IRQHandler -PININT5_IRQHandler -PININT6_IRQHandler -PININT7_IRQHandler -Default_IRQHandler - B Default_IRQHandler - - SECTION .crp:CODE:ROOT(2) - DATA -/* Code Read Protection -NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode -CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. - - Copy RAM to flash command can not write to Sector 0. - - Erase command can erase Sector 0 only when all sectors - are selected for erase. - - Compare command is disabled. - - Read Memory command is disabled. -CRP2 0x87654321 - Read Memory is disabled. - - Write to RAM is disabled. - - "Go" command is disabled. - - Copy RAM to flash is disabled. - - Compare is disabled. -CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry - by pulling PIO0_1 LOW is disabled if a valid user code is - present in flash sector 0. -Caution: If CRP3 is selected, no future factory testing can be -performed on the device. -*/ - DCD 0xFFFFFFFF - - END diff --git a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/system_LPC8xx.c b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/system_LPC8xx.c deleted file mode 100644 index c96d6c446b1..00000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/system_LPC8xx.c +++ /dev/null @@ -1,381 +0,0 @@ -/****************************************************************************** - * @file: system_LPC8xx.c - * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File - * for the NXP LPC8xx Device Series - * @version: V1.0 - * @date: 16. Aug. 2012 - *---------------------------------------------------------------------------- - * - * Copyright (C) 2012 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#include -#include "LPC8xx.h" - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration ---------------------------------- -// -// Clock Configuration -// System Oscillator Control Register (SYSOSCCTRL) -// BYPASS: System Oscillator Bypass Enable -// If enabled then PLL input (sys_osc_clk) is fed -// directly from XTALIN and XTALOUT pins. -// FREQRANGE: System Oscillator Frequency Range -// Determines frequency range for Low-power oscillator. -// <0=> 1 - 20 MHz -// <1=> 15 - 25 MHz -// -// -// Watchdog Oscillator Control Register (WDTOSCCTRL) -// DIVSEL: Select Divider for Fclkana -// wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL)) -// <0-31> -// FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana) -// <0=> Undefined -// <1=> 0.5 MHz -// <2=> 0.8 MHz -// <3=> 1.1 MHz -// <4=> 1.4 MHz -// <5=> 1.6 MHz -// <6=> 1.8 MHz -// <7=> 2.0 MHz -// <8=> 2.2 MHz -// <9=> 2.4 MHz -// <10=> 2.6 MHz -// <11=> 2.7 MHz -// <12=> 2.9 MHz -// <13=> 3.1 MHz -// <14=> 3.2 MHz -// <15=> 3.4 MHz -// -// -// System PLL Control Register (SYSPLLCTRL) -// F_clkout = M * F_clkin = F_CCO / (2 * P) -// F_clkin must be in the range of 10 MHz to 25 MHz -// F_CCO must be in the range of 156 MHz to 320 MHz -// MSEL: Feedback Divider Selection -// M = MSEL + 1 -// <0-31> -// PSEL: Post Divider Selection -// <0=> P = 1 -// <1=> P = 2 -// <2=> P = 4 -// <3=> P = 8 -// -// -// System PLL Clock Source Select Register (SYSPLLCLKSEL) -// SEL: System PLL Clock Source -// <0=> IRC Oscillator -// <1=> System Oscillator -// <2=> Reserved -// <3=> CLKIN pin -// -// -// Main Clock Source Select Register (MAINCLKSEL) -// SEL: Clock Source for Main Clock -// <0=> IRC Oscillator -// <1=> Input Clock to System PLL -// <2=> WDT Oscillator -// <3=> System PLL Clock Out -// -// -// System AHB Clock Divider Register (SYSAHBCLKDIV) -// DIV: System AHB Clock Divider -// Divides main clock to provide system clock to core, memories, and peripherals. -// 0 = is disabled -// <0-255> -// -// -*/ -#define CLOCK_SETUP 1 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal: - -//Fixed to use PLL -#if (CLOCK_SETUP == 1) -//use PLL for IRC - #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz - #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 Select IRC - #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT - #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz - -#elif (CLOCK_SETUP == 2) -//use PLL for XTAL - #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz - #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 Select XTAL - #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT - #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz -#endif - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) - #error "SYSOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) - #error "WDTOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3)) - #error "SYSPLLCLKSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) - #error "SYSPLLCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) - #error "MAINCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) - #error "SYSAHBCLKDIV: Value out of range!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define __XTAL (12000000UL) /* Oscillator frequency */ -#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ -#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ -#define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */ - - -#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) -#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) - -#if (CLOCK_SETUP) /* Clock Setup */ - #if (__FREQSEL == 0) - #define __WDT_OSC_CLK ( 0) /* undefined */ - #elif (__FREQSEL == 1) - #define __WDT_OSC_CLK ( 500000 / __DIVSEL) - #elif (__FREQSEL == 2) - #define __WDT_OSC_CLK ( 800000 / __DIVSEL) - #elif (__FREQSEL == 3) - #define __WDT_OSC_CLK (1100000 / __DIVSEL) - #elif (__FREQSEL == 4) - #define __WDT_OSC_CLK (1400000 / __DIVSEL) - #elif (__FREQSEL == 5) - #define __WDT_OSC_CLK (1600000 / __DIVSEL) - #elif (__FREQSEL == 6) - #define __WDT_OSC_CLK (1800000 / __DIVSEL) - #elif (__FREQSEL == 7) - #define __WDT_OSC_CLK (2000000 / __DIVSEL) - #elif (__FREQSEL == 8) - #define __WDT_OSC_CLK (2200000 / __DIVSEL) - #elif (__FREQSEL == 9) - #define __WDT_OSC_CLK (2400000 / __DIVSEL) - #elif (__FREQSEL == 10) - #define __WDT_OSC_CLK (2600000 / __DIVSEL) - #elif (__FREQSEL == 11) - #define __WDT_OSC_CLK (2700000 / __DIVSEL) - #elif (__FREQSEL == 12) - #define __WDT_OSC_CLK (2900000 / __DIVSEL) - #elif (__FREQSEL == 13) - #define __WDT_OSC_CLK (3100000 / __DIVSEL) - #elif (__FREQSEL == 14) - #define __WDT_OSC_CLK (3200000 / __DIVSEL) - #else - #define __WDT_OSC_CLK (3400000 / __DIVSEL) - #endif - - /* sys_pllclkin calculation */ - #if ((SYSPLLCLKSEL_Val & 0x03) == 0) - #define __SYS_PLLCLKIN (__IRC_OSC_CLK) - #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) - #define __SYS_PLLCLKIN (__SYS_OSC_CLK) - #elif ((SYSPLLCLKSEL_Val & 0x03) == 3) - #define __SYS_PLLCLKIN (__CLKIN_CLK) - #else - #define __SYS_PLLCLKIN (0) - #endif - - #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) - - /* main clock calculation */ - #if ((MAINCLKSEL_Val & 0x03) == 0) - #define __MAIN_CLOCK (__IRC_OSC_CLK) - #elif ((MAINCLKSEL_Val & 0x03) == 1) - #define __MAIN_CLOCK (__SYS_PLLCLKIN) - #elif ((MAINCLKSEL_Val & 0x03) == 2) - #if (__FREQSEL == 0) - #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!" - #else - #define __MAIN_CLOCK (__WDT_OSC_CLK) - #endif - #elif ((MAINCLKSEL_Val & 0x03) == 3) - #define __MAIN_CLOCK (__SYS_PLLCLKOUT) - #else - #define __MAIN_CLOCK (0) - #endif - - #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) - -#else - #define __SYSTEM_CLOCK (__IRC_OSC_CLK) -#endif // CLOCK_SETUP - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */ -uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ - -//Replaced SystemCoreClock with MainClock -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - uint32_t wdt_osc = 0; - - /* Determine clock frequency according to clock register values */ - switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { - case 0: wdt_osc = 0; break; - case 1: wdt_osc = 500000; break; - case 2: wdt_osc = 800000; break; - case 3: wdt_osc = 1100000; break; - case 4: wdt_osc = 1400000; break; - case 5: wdt_osc = 1600000; break; - case 6: wdt_osc = 1800000; break; - case 7: wdt_osc = 2000000; break; - case 8: wdt_osc = 2200000; break; - case 9: wdt_osc = 2400000; break; - case 10: wdt_osc = 2600000; break; - case 11: wdt_osc = 2700000; break; - case 12: wdt_osc = 2900000; break; - case 13: wdt_osc = 3100000; break; - case 14: wdt_osc = 3200000; break; - case 15: wdt_osc = 3400000; break; - } - wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; - - switch (LPC_SYSCON->MAINCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - MainClock = __IRC_OSC_CLK; - break; - case 1: /* Input Clock to System PLL */ - switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - MainClock = __IRC_OSC_CLK; - break; - case 1: /* System oscillator */ - MainClock = __SYS_OSC_CLK; - break; - case 2: /* Reserved */ - MainClock = 0; - break; - case 3: /* CLKIN pin */ - MainClock = __CLKIN_CLK; - break; - } - break; - case 2: /* WDT Oscillator */ - MainClock = wdt_osc; - break; - case 3: /* System PLL Clock Out */ - switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - break; - case 1: /* System oscillator */ - MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - break; - case 2: /* Reserved */ - MainClock = 0; - break; - case 3: /* CLKIN pin */ - MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - break; - } - break; - } - - SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV; -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) { - volatile uint32_t i; - - /* System clock to the IOCON & the SWM need to be enabled or - most of the I/O related peripherals won't work. */ - LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) ); - -#if (CLOCK_SETUP) /* Clock Setup */ - -#if ((SYSPLLCLKSEL_Val & 0x03) == 1) - LPC_IOCON->PIO0_8 &= ~(0x3 << 3); - LPC_IOCON->PIO0_9 &= ~(0x3 << 3); - LPC_SWM->PINENABLE0 &= ~(0x3 << 4); - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */ - LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; - for (i = 0; i < 200; i++) __NOP(); -#endif -#if ((SYSPLLCLKSEL_Val & 0x03) == 3) - LPC_IOCON->PIO0_1 &= ~(0x3 << 3); - LPC_SWM->PINENABLE0 &= ~(0x1 << 7); - for (i = 0; i < 200; i++) __NOP(); -#endif - - LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ - LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */ - while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ -#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */ - LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */ - while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ -#endif - -#if (((MAINCLKSEL_Val & 0x03) == 2) ) - LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */ - for (i = 0; i < 200; i++) __NOP(); -#endif - - LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */ - LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */ - while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ - - LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; -#endif -} diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralNames.h deleted file mode 100644 index 6bfba03fcbd..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralNames.h +++ /dev/null @@ -1,75 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE -} ADCName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE -} UARTName; - -#define DEVICE_SPI_COUNT 2 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE -} PWMName; - -typedef enum { - CAN_1 = (int)CAN1_BASE -} CANName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralPins.c deleted file mode 100644 index 28b470a7449..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralPins.c +++ /dev/null @@ -1,216 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - * - * Automatically generated from STM32F103C(8-B)Tx.xml - */ - -#include "PeripheralPins.h" -#include "mbed_toolchain.h" - -//============================================================================== -// Notes -// -// - The pins mentioned Px_y_ALTz are alternative possibilities which use other -// HW peripheral instances. You can use them the same way as any other "normal" -// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board -// pinout image on mbed.org. -// -// - The pins which are connected to other components present on the board have -// the comment "Connected to xxx". The pin function may not work properly in this -// case. These pins may not be displayed on the board pinout image on mbed.org. -// Please read the board reference manual and schematic for more information. -// -// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented -// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. -// -//============================================================================== - - -//*** ADC *** - -MBED_WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1 - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3 - {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4 - {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5 - {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6 - {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7 - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8 - {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC_IN9 - {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC_IN10 - {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC_IN11 - {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC_IN12 - {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC_IN13 - {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC_IN14 - {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC_IN15 - {NC, NC, 0} -}; - -const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC_IN16 - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC_IN17 - {NC, NC, 0} -}; - -//*** I2C *** - -MBED_WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)}, - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 2)}, - {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_I2C_SCL[] = { - {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 2)}, - {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)}, - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM4 cannot be used because already used by the us_ticker -// You have to comment all PWM_4 -MBED_WEAK const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM2_CH1 - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM2_CH2 - {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM2_CH3 - {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM2_CH4 - {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM3_CH1 - {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM3_CH2 - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM1_CH1 - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 6, 1, 0)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM1_CH2 - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 6, 2, 0)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM1_CH3 - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 6, 3, 0)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM1_CH4 - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 6, 4, 0)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 6, 2, 1)}, // TIM1_CH2N - {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM3_CH3 - {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 3, 0)}, // TIM3_CH3 - {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 6, 3, 1)}, // TIM1_CH3N - {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM3_CH4 - {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 4, 0)}, // TIM3_CH4 - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 2, 0)}, // TIM2_CH2 - {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 1, 0)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 2, 0)}, // TIM3_CH2 -// {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM4_CH1 -// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM4_CH2 -// {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM4_CH3 -// {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM4_CH4 - {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 3, 0)}, // TIM2_CH3 - {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 4, 0)}, // TIM2_CH4 - {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 1)}, // TIM1_CH1N - {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 1)}, // TIM1_CH2N - {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 1)}, // TIM1_CH3N - {NC, NC, 0} -}; - -//*** SERIAL *** - -MBED_WEAK const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 3)}, // GPIO_Remap_USART1 - {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, - {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 5)}, // GPIO_PartialRemap_USART3 - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_RX[] = { - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)}, - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)}, - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 3)}, // GPIO_Remap_USART1 - {PB_11, UART_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)}, - {PC_11, UART_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 5)}, // GPIO_PartialRemap_USART3 - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, - {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, - {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, - {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, - {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, - {NC, NC, 0} -}; - -//*** SPI *** - -MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, - {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, - {NC, NC, 0} -}; - -//*** CAN *** - -MBED_WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)}, - {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 10)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_CAN_TD[] = { - {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, - {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 10)}, - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PinNames.h deleted file mode 100644 index 6756cb7bb7a..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PinNames.h +++ /dev/null @@ -1,186 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ALT0 = 0x100, - ALT1 = 0x200, - ALT2 = 0x300, - ALT3 = 0x400 -} ALTx; - -typedef enum { - PA_0 = 0x00, - PA_1 = 0x01, - PA_2 = 0x02, - PA_3 = 0x03, - PA_4 = 0x04, - PA_5 = 0x05, - PA_6 = 0x06, - PA_7 = 0x07, - PA_7_ALT0 = 0x07 | ALT0, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - - PB_0 = 0x10, - PB_0_ALT0 = 0x10 | ALT0, - PB_1 = 0x11, - PB_1_ALT0 = 0x11 | ALT0, - PB_2 = 0x12, - PB_3 = 0x13, - PB_4 = 0x14, - PB_5 = 0x15, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_9 = 0x19, - PB_10 = 0x1A, - PB_11 = 0x1B, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_14 = 0x1E, - PB_15 = 0x1F, - - PC_0 = 0x20, - PC_1 = 0x21, - PC_2 = 0x22, - PC_3 = 0x23, - PC_4 = 0x24, - PC_5 = 0x25, - PC_6 = 0x26, - PC_7 = 0x27, - PC_8 = 0x28, - PC_9 = 0x29, - PC_10 = 0x2A, - PC_11 = 0x2B, - PC_12 = 0x2C, - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, - - PD_2 = 0x32, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - - // PCB printout - A0 = PA_0, - A1 = PA_1, - A2 = PA_2, - A3 = PA_3, - A4 = PA_4, - A5 = PA_5, - A6 = PA_6, - A7 = PA_7, - A8 = PA_8, - A9 = PA_9, - A10 = PA_10, - A11 = PA_11, - A12 = PA_12, - A15 = PA_15, - - B0 = PB_0, - B1 = PB_1, - B2 = PB_2, - B3 = PB_3, - B4 = PB_4, - B5 = PB_5, - B6 = PB_6, - B7 = PB_7, - B8 = PB_8, - B9 = PB_9, - B10 = PB_10, - B11 = PB_11, - B12 = PB_12, - B13 = PB_13, - B14 = PB_14, - B15 = PB_15, - - C13 = PC_13, - C14 = PC_14, - C15 = PC_15, - - // STDIO for console print -#ifdef MBED_CONF_TARGET_STDIO_UART_TX - STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, -#else - STDIO_UART_TX = PA_2, -#endif -#ifdef MBED_CONF_TARGET_STDIO_UART_RX - STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, -#else - STDIO_UART_RX = PA_3, -#endif - - // Generic signals namings - LED1 = PC_13, - LED2 = PC_13, - LED3 = PC_13, - LED4 = PC_13, - SERIAL_TX = STDIO_UART_TX, - SERIAL_RX = STDIO_UART_RX, - USBTX = STDIO_UART_TX, - USBRX = STDIO_UART_RX, - I2C_SCL = PB_6, - I2C_SDA = PB_7, - SPI_MOSI = PA_7, - SPI_MISO = PA_6, - SPI_SCK = PA_5, - SPI_CS = PA_4, - PWM_OUT = PB_5, - - //USB pins - USB_DM = PA_11, - USB_DP = PA_12, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/TOOLCHAIN_GCC_ARM/STM32F103XB.ld b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/TOOLCHAIN_GCC_ARM/STM32F103XB.ld deleted file mode 100644 index 52b01a214a5..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/TOOLCHAIN_GCC_ARM/STM32F103XB.ld +++ /dev/null @@ -1,163 +0,0 @@ -/* Linker script to configure memory regions. */ -/* 0xEC reserved for vectors - 8byte aligned = 0xF0 */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64K - RAM (rwx) : ORIGIN = 0x200000F0, LENGTH = 20K - (0xEC+0x4) -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * _estack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - _sidata = .; - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/TOOLCHAIN_GCC_ARM/startup_stm32f103xb.S b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/TOOLCHAIN_GCC_ARM/startup_stm32f103xb.S deleted file mode 100644 index 9f79c00cd41..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/TOOLCHAIN_GCC_ARM/startup_stm32f103xb.S +++ /dev/null @@ -1,371 +0,0 @@ -/** - *************** (C) COPYRIGHT 2016 STMicroelectronics ************************ - * @file startup_stm32f103xb.s - * @author MCD Application Team - * @version V4.1.0 - * @date 29-April-2016 - * @brief STM32F103xB Devices vector table for Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main - bl _start - -LoopForever: - b LoopForever - - -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_CAN1_TX_IRQHandler - .word USB_LP_CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_IRQHandler - .word TIM1_UP_IRQHandler - .word TIM1_TRG_COM_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word USBWakeUp_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x108. This is for boot in RAM mode for - STM32F10x Medium Density devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak USB_HP_CAN1_TX_IRQHandler - .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler - - .weak USB_LP_CAN1_RX0_IRQHandler - .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_IRQHandler - .thumb_set TIM1_BRK_IRQHandler,Default_Handler - - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_IRQHandler - .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak USBWakeUp_IRQHandler - .thumb_set USBWakeUp_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/cmsis_nvic.h deleted file mode 100644 index f1334d99ecb..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/cmsis_nvic.h +++ /dev/null @@ -1,40 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -// CORE: 16 vectors (= 64 bytes from 0x00 to 0x3F) -// MCU Peripherals: 43 vectors (= 172 bytes from 0x40 to 0xEB) -// Total: 236 bytes to be reserved in RAM (see scatter file) -#define NVIC_NUM_VECTORS (16 + 43) -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/stm32f103xb.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/stm32f103xb.h deleted file mode 100644 index 9ff8ad63859..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/stm32f103xb.h +++ /dev/null @@ -1,10642 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f103xb.h - * @author MCD Application Team - * @version V4.2.0 - * @date 31-March-2017 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F1xx devices. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f103xb - * @{ - */ - -#ifndef __STM32F103xB_H -#define __STM32F103xB_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ - #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ -#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32F10x Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - - /*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 2, /*!< Tamper Interrupt */ - RTC_IRQn = 3, /*!< RTC global Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32f1xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SMPR1; - __IO uint32_t SMPR2; - __IO uint32_t JOFR1; - __IO uint32_t JOFR2; - __IO uint32_t JOFR3; - __IO uint32_t JOFR4; - __IO uint32_t HTR; - __IO uint32_t LTR; - __IO uint32_t SQR1; - __IO uint32_t SQR2; - __IO uint32_t SQR3; - __IO uint32_t JSQR; - __IO uint32_t JDR1; - __IO uint32_t JDR2; - __IO uint32_t JDR3; - __IO uint32_t JDR4; - __IO uint32_t DR; -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ - __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ - uint32_t RESERVED[16]; - __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ -} ADC_Common_TypeDef; - -/** - * @brief Backup Registers - */ - -typedef struct -{ - uint32_t RESERVED0; - __IO uint32_t DR1; - __IO uint32_t DR2; - __IO uint32_t DR3; - __IO uint32_t DR4; - __IO uint32_t DR5; - __IO uint32_t DR6; - __IO uint32_t DR7; - __IO uint32_t DR8; - __IO uint32_t DR9; - __IO uint32_t DR10; - __IO uint32_t RTCCR; - __IO uint32_t CR; - __IO uint32_t CSR; -} BKP_TypeDef; - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; - __IO uint32_t TDTR; - __IO uint32_t TDLR; - __IO uint32_t TDHR; -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; - __IO uint32_t RDTR; - __IO uint32_t RDLR; - __IO uint32_t RDHR; -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; - __IO uint32_t FR2; -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; - __IO uint32_t MSR; - __IO uint32_t TSR; - __IO uint32_t RF0R; - __IO uint32_t RF1R; - __IO uint32_t IER; - __IO uint32_t ESR; - __IO uint32_t BTR; - uint32_t RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - uint32_t RESERVED1[12]; - __IO uint32_t FMR; - __IO uint32_t FM1R; - uint32_t RESERVED2; - __IO uint32_t FS1R; - uint32_t RESERVED3; - __IO uint32_t FFA1R; - uint32_t RESERVED4; - __IO uint32_t FA1R; - uint32_t RESERVED5[8]; - CAN_FilterRegister_TypeDef sFilterRegister[14]; -} CAN_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ - uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; - __IO uint32_t CR; -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; - __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; - __IO uint32_t IFCR; -} DMA_TypeDef; - - - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; - __IO uint32_t EMR; - __IO uint32_t RTSR; - __IO uint32_t FTSR; - __IO uint32_t SWIER; - __IO uint32_t PR; -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; - __IO uint32_t KEYR; - __IO uint32_t OPTKEYR; - __IO uint32_t SR; - __IO uint32_t CR; - __IO uint32_t AR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WRPR; -} FLASH_TypeDef; - -/** - * @brief Option Bytes Registers - */ - -typedef struct -{ - __IO uint16_t RDP; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRP0; - __IO uint16_t WRP1; - __IO uint16_t WRP2; - __IO uint16_t WRP3; -} OB_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t CRL; - __IO uint32_t CRH; - __IO uint32_t IDR; - __IO uint32_t ODR; - __IO uint32_t BSRR; - __IO uint32_t BRR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/** - * @brief Alternate Function I/O - */ - -typedef struct -{ - __IO uint32_t EVCR; - __IO uint32_t MAPR; - __IO uint32_t EXTICR[4]; - uint32_t RESERVED0; - __IO uint32_t MAPR2; -} AFIO_TypeDef; -/** - * @brief Inter Integrated Circuit Interface - */ - -typedef struct -{ - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t OAR1; - __IO uint32_t OAR2; - __IO uint32_t DR; - __IO uint32_t SR1; - __IO uint32_t SR2; - __IO uint32_t CCR; - __IO uint32_t TRISE; -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFGR; - __IO uint32_t CIR; - __IO uint32_t APB2RSTR; - __IO uint32_t APB1RSTR; - __IO uint32_t AHBENR; - __IO uint32_t APB2ENR; - __IO uint32_t APB1ENR; - __IO uint32_t BDCR; - __IO uint32_t CSR; - - -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t CRH; - __IO uint32_t CRL; - __IO uint32_t PRLH; - __IO uint32_t PRLL; - __IO uint32_t DIVH; - __IO uint32_t DIVL; - __IO uint32_t CNTH; - __IO uint32_t CNTL; - __IO uint32_t ALRH; - __IO uint32_t ALRL; -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLKCR; - __IO uint32_t ARG; - __IO uint32_t CMD; - __I uint32_t RESPCMD; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __I uint32_t RESP4; - __IO uint32_t DTIMER; - __IO uint32_t DLEN; - __IO uint32_t DCTRL; - __I uint32_t DCOUNT; - __I uint32_t STA; - __IO uint32_t ICR; - __IO uint32_t MASK; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO; -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SR; - __IO uint32_t DR; - __IO uint32_t CRCPR; - __IO uint32_t RXCRCR; - __IO uint32_t TXCRCR; - __IO uint32_t I2SCFGR; -} SPI_TypeDef; - -/** - * @brief TIM Timers - */ -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ - __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ -}TIM_TypeDef; - - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ -} USART_TypeDef; - -/** - * @brief Universal Serial Bus Full Speed Device - */ - -typedef struct -{ - __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ - __IO uint16_t RESERVED0; /*!< Reserved */ - __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ - __IO uint16_t RESERVED1; /*!< Reserved */ - __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ - __IO uint16_t RESERVED2; /*!< Reserved */ - __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ - __IO uint16_t RESERVED3; /*!< Reserved */ - __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ - __IO uint16_t RESERVED4; /*!< Reserved */ - __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ - __IO uint16_t RESERVED5; /*!< Reserved */ - __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ - __IO uint16_t RESERVED6; /*!< Reserved */ - __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ - __IO uint16_t RESERVED7[17]; /*!< Reserved */ - __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ - __IO uint16_t RESERVED8; /*!< Reserved */ - __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ - __IO uint16_t RESERVED9; /*!< Reserved */ - __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ - __IO uint16_t RESERVEDA; /*!< Reserved */ - __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ - __IO uint16_t RESERVEDB; /*!< Reserved */ - __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ - __IO uint16_t RESERVEDC; /*!< Reserved */ -} USB_TypeDef; - - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - - -#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */ -#define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */ -#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */ -#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ - - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U) -#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U) -#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U) -#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U) -#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) -#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) -#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) -#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) -#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) -#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U) -#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U) -#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U) -#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U) -#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U) -#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) -#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U) -#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U) -#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) -#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) - -#define SDIO_BASE (PERIPH_BASE + 0x00018000U) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U) -#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) -#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */ -#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ -#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ -#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */ - - - -#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */ - -/* USB device FS */ -#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */ -#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */ - - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define TIM2 ((TIM_TypeDef *)TIM2_BASE) -#define TIM3 ((TIM_TypeDef *)TIM3_BASE) -#define TIM4 ((TIM_TypeDef *)TIM4_BASE) -#define RTC ((RTC_TypeDef *)RTC_BASE) -#define WWDG ((WWDG_TypeDef *)WWDG_BASE) -#define IWDG ((IWDG_TypeDef *)IWDG_BASE) -#define SPI2 ((SPI_TypeDef *)SPI2_BASE) -#define USART2 ((USART_TypeDef *)USART2_BASE) -#define USART3 ((USART_TypeDef *)USART3_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#define I2C2 ((I2C_TypeDef *)I2C2_BASE) -#define USB ((USB_TypeDef *)USB_BASE) -#define CAN1 ((CAN_TypeDef *)CAN1_BASE) -#define BKP ((BKP_TypeDef *)BKP_BASE) -#define PWR ((PWR_TypeDef *)PWR_BASE) -#define AFIO ((AFIO_TypeDef *)AFIO_BASE) -#define EXTI ((EXTI_TypeDef *)EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) -#define ADC2 ((ADC_TypeDef *)ADC2_BASE) -#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) -#define TIM1 ((TIM_TypeDef *)TIM1_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define USART1 ((USART_TypeDef *)USART1_BASE) -#define SDIO ((SDIO_TypeDef *)SDIO_BASE) -#define DMA1 ((DMA_TypeDef *)DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) -#define RCC ((RCC_TypeDef *)RCC_BASE) -#define CRC ((CRC_TypeDef *)CRC_BASE) -#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) -#define OB ((OB_TypeDef *)OB_BASE) -#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) - - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* CRC calculation unit (CRC) */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR_Pos (0U) -#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ -#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR_Pos (0U) -#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ -#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET_Pos (0U) -#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ -#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ - -/******************************************************************************/ -/* */ -/* Power Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPDS_Pos (0U) -#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ -#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ -#define PWR_CR_PDDS_Pos (1U) -#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ -#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF_Pos (2U) -#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ -#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF_Pos (3U) -#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ -#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ -#define PWR_CR_PVDE_Pos (4U) -#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ -#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ - -#define PWR_CR_PLS_Pos (5U) -#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ -#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ -#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ -#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ - -/*!< PVD level configuration */ -#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ -#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ -#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ -#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ -#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ -#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ -#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ -#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ - -/* Legacy defines */ -#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 -#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 -#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 -#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 -#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 -#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 -#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 -#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 - -#define PWR_CR_DBP_Pos (8U) -#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ -#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ - - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF_Pos (0U) -#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ -#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ -#define PWR_CSR_SBF_Pos (1U) -#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ -#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ -#define PWR_CSR_PVDO_Pos (2U) -#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ -#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ -#define PWR_CSR_EWUP_Pos (8U) -#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ -#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ - -/******************************************************************************/ -/* */ -/* Backup registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DR1 register ********************/ -#define BKP_DR1_D_Pos (0U) -#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR2 register ********************/ -#define BKP_DR2_D_Pos (0U) -#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR3 register ********************/ -#define BKP_DR3_D_Pos (0U) -#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR4 register ********************/ -#define BKP_DR4_D_Pos (0U) -#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR5 register ********************/ -#define BKP_DR5_D_Pos (0U) -#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR6 register ********************/ -#define BKP_DR6_D_Pos (0U) -#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR7 register ********************/ -#define BKP_DR7_D_Pos (0U) -#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR8 register ********************/ -#define BKP_DR8_D_Pos (0U) -#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR9 register ********************/ -#define BKP_DR9_D_Pos (0U) -#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR10 register *******************/ -#define BKP_DR10_D_Pos (0U) -#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ - -#define RTC_BKP_NUMBER 10 - -/****************** Bit definition for BKP_RTCCR register *******************/ -#define BKP_RTCCR_CAL_Pos (0U) -#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ -#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ -#define BKP_RTCCR_CCO_Pos (7U) -#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ -#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ -#define BKP_RTCCR_ASOE_Pos (8U) -#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ -#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS_Pos (9U) -#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ -#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ - -/******************** Bit definition for BKP_CR register ********************/ -#define BKP_CR_TPE_Pos (0U) -#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */ -#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ -#define BKP_CR_TPAL_Pos (1U) -#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ -#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ - -/******************* Bit definition for BKP_CSR register ********************/ -#define BKP_CSR_CTE_Pos (0U) -#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ -#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ -#define BKP_CSR_CTI_Pos (1U) -#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ -#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ -#define BKP_CSR_TPIE_Pos (2U) -#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ -#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF_Pos (8U) -#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ -#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ -#define BKP_CSR_TIF_Pos (9U) -#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ -#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ - -/******************************************************************************/ -/* */ -/* Reset and Clock Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION_Pos (0U) -#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIRDY_Pos (1U) -#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSITRIM_Pos (3U) -#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ -#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ -#define RCC_CR_HSICAL_Pos (8U) -#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ -#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ -#define RCC_CR_HSEON_Pos (16U) -#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ -#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY_Pos (17U) -#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ -#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP_Pos (18U) -#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ -#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSON_Pos (19U) -#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ -#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ -#define RCC_CR_PLLON_Pos (24U) -#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ -#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ -#define RCC_CR_PLLRDY_Pos (25U) -#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ -#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ - - -/******************* Bit definition for RCC_CFGR register *******************/ -/*!< SW configuration */ -#define RCC_CFGR_SW_Pos (0U) -#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ -#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ -#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ - -#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ - -/*!< SWS configuration */ -#define RCC_CFGR_SWS_Pos (2U) -#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ -#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ -#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ - -#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ - -/*!< HPRE configuration */ -#define RCC_CFGR_HPRE_Pos (4U) -#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ -#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ -#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ -#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ -#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ - -#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ - -/*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1_Pos (8U) -#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ -#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ -#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ -#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ - -#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ - -/*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2_Pos (11U) -#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ -#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ -#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ -#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ - -#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ - -/*!< ADCPPRE configuration */ -#define RCC_CFGR_ADCPRE_Pos (14U) -#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ -#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ -#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ - -#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ -#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ -#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ -#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ - -#define RCC_CFGR_PLLSRC_Pos (16U) -#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ -#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ - -#define RCC_CFGR_PLLXTPRE_Pos (17U) -#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ -#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ - -/*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMULL_Pos (18U) -#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ -#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ -#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ -#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ -#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ - -#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */ -#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */ - -#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */ -#define RCC_CFGR_PLLMULL3_Pos (18U) -#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ -#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ -#define RCC_CFGR_PLLMULL4_Pos (19U) -#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ -#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */ -#define RCC_CFGR_PLLMULL5_Pos (18U) -#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ -#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */ -#define RCC_CFGR_PLLMULL6_Pos (20U) -#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ -#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */ -#define RCC_CFGR_PLLMULL7_Pos (18U) -#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ -#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */ -#define RCC_CFGR_PLLMULL8_Pos (19U) -#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ -#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */ -#define RCC_CFGR_PLLMULL9_Pos (18U) -#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ -#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */ -#define RCC_CFGR_PLLMULL10_Pos (21U) -#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */ -#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */ -#define RCC_CFGR_PLLMULL11_Pos (18U) -#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */ -#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */ -#define RCC_CFGR_PLLMULL12_Pos (19U) -#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */ -#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */ -#define RCC_CFGR_PLLMULL13_Pos (18U) -#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */ -#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */ -#define RCC_CFGR_PLLMULL14_Pos (20U) -#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */ -#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */ -#define RCC_CFGR_PLLMULL15_Pos (18U) -#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */ -#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */ -#define RCC_CFGR_PLLMULL16_Pos (19U) -#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */ -#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */ -#define RCC_CFGR_USBPRE_Pos (22U) -#define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */ -#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */ - -/*!< MCO configuration */ -#define RCC_CFGR_MCO_Pos (24U) -#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ -#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ -#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ -#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ -#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ - -#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ -#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ -#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ -#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ -#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ - - /* Reference defines */ - #define RCC_CFGR_MCOSEL RCC_CFGR_MCO - #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 - #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 - #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 - #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK - #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK - #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI - #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE - #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 - -/*!<****************** Bit definition for RCC_CIR register ********************/ -#define RCC_CIR_LSIRDYF_Pos (0U) -#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ -#define RCC_CIR_LSERDYF_Pos (1U) -#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ -#define RCC_CIR_HSIRDYF_Pos (2U) -#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ -#define RCC_CIR_HSERDYF_Pos (3U) -#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ -#define RCC_CIR_PLLRDYF_Pos (4U) -#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ -#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ -#define RCC_CIR_CSSF_Pos (7U) -#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ -#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ -#define RCC_CIR_LSIRDYIE_Pos (8U) -#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ -#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ -#define RCC_CIR_LSERDYIE_Pos (9U) -#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ -#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ -#define RCC_CIR_HSIRDYIE_Pos (10U) -#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ -#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ -#define RCC_CIR_HSERDYIE_Pos (11U) -#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ -#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ -#define RCC_CIR_PLLRDYIE_Pos (12U) -#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ -#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ -#define RCC_CIR_LSIRDYC_Pos (16U) -#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ -#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ -#define RCC_CIR_LSERDYC_Pos (17U) -#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ -#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ -#define RCC_CIR_HSIRDYC_Pos (18U) -#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ -#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ -#define RCC_CIR_HSERDYC_Pos (19U) -#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ -#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ -#define RCC_CIR_PLLRDYC_Pos (20U) -#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ -#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ -#define RCC_CIR_CSSC_Pos (23U) -#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ -#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ - - -/***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_AFIORST_Pos (0U) -#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ -#define RCC_APB2RSTR_IOPARST_Pos (2U) -#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ -#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ -#define RCC_APB2RSTR_IOPBRST_Pos (3U) -#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ -#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ -#define RCC_APB2RSTR_IOPCRST_Pos (4U) -#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ -#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ -#define RCC_APB2RSTR_IOPDRST_Pos (5U) -#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ -#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ -#define RCC_APB2RSTR_ADC1RST_Pos (9U) -#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ - -#define RCC_APB2RSTR_ADC2RST_Pos (10U) -#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */ -#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */ - -#define RCC_APB2RSTR_TIM1RST_Pos (11U) -#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ -#define RCC_APB2RSTR_SPI1RST_Pos (12U) -#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ -#define RCC_APB2RSTR_USART1RST_Pos (14U) -#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ - - -#define RCC_APB2RSTR_IOPERST_Pos (6U) -#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ -#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ - - - - -/***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST_Pos (0U) -#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ -#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ -#define RCC_APB1RSTR_TIM3RST_Pos (1U) -#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ -#define RCC_APB1RSTR_WWDGRST_Pos (11U) -#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ -#define RCC_APB1RSTR_USART2RST_Pos (17U) -#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ -#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ -#define RCC_APB1RSTR_I2C1RST_Pos (21U) -#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ - -#define RCC_APB1RSTR_CAN1RST_Pos (25U) -#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ -#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */ - -#define RCC_APB1RSTR_BKPRST_Pos (27U) -#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ -#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ -#define RCC_APB1RSTR_PWRRST_Pos (28U) -#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ - -#define RCC_APB1RSTR_TIM4RST_Pos (2U) -#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ -#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ -#define RCC_APB1RSTR_SPI2RST_Pos (14U) -#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ -#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ -#define RCC_APB1RSTR_USART3RST_Pos (18U) -#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ -#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ -#define RCC_APB1RSTR_I2C2RST_Pos (22U) -#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ -#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ - -#define RCC_APB1RSTR_USBRST_Pos (23U) -#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ -#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */ - - - - - - -/****************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMA1EN_Pos (0U) -#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ -#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ -#define RCC_AHBENR_SRAMEN_Pos (2U) -#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ -#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ -#define RCC_AHBENR_FLITFEN_Pos (4U) -#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ -#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ -#define RCC_AHBENR_CRCEN_Pos (6U) -#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ -#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ - - - - -/****************** Bit definition for RCC_APB2ENR register *****************/ -#define RCC_APB2ENR_AFIOEN_Pos (0U) -#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ -#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ -#define RCC_APB2ENR_IOPAEN_Pos (2U) -#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ -#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ -#define RCC_APB2ENR_IOPBEN_Pos (3U) -#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ -#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ -#define RCC_APB2ENR_IOPCEN_Pos (4U) -#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ -#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ -#define RCC_APB2ENR_IOPDEN_Pos (5U) -#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ -#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ -#define RCC_APB2ENR_ADC1EN_Pos (9U) -#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ -#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ - -#define RCC_APB2ENR_ADC2EN_Pos (10U) -#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */ -#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */ - -#define RCC_APB2ENR_TIM1EN_Pos (11U) -#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ -#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ -#define RCC_APB2ENR_SPI1EN_Pos (12U) -#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ -#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ -#define RCC_APB2ENR_USART1EN_Pos (14U) -#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ -#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ - - -#define RCC_APB2ENR_IOPEEN_Pos (6U) -#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ -#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ - - - - -/***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN_Pos (0U) -#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ -#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ -#define RCC_APB1ENR_TIM3EN_Pos (1U) -#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ -#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ -#define RCC_APB1ENR_WWDGEN_Pos (11U) -#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ -#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_USART2EN_Pos (17U) -#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ -#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ -#define RCC_APB1ENR_I2C1EN_Pos (21U) -#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ -#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ - -#define RCC_APB1ENR_CAN1EN_Pos (25U) -#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ -#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */ - -#define RCC_APB1ENR_BKPEN_Pos (27U) -#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ -#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ -#define RCC_APB1ENR_PWREN_Pos (28U) -#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ -#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ - -#define RCC_APB1ENR_TIM4EN_Pos (2U) -#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ -#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ -#define RCC_APB1ENR_SPI2EN_Pos (14U) -#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ -#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ -#define RCC_APB1ENR_USART3EN_Pos (18U) -#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ -#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ -#define RCC_APB1ENR_I2C2EN_Pos (22U) -#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ -#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ - -#define RCC_APB1ENR_USBEN_Pos (23U) -#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ -#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */ - - - - - - -/******************* Bit definition for RCC_BDCR register *******************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY_Pos (1U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP_Pos (2U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ - -#define RCC_BDCR_RTCSEL_Pos (8U) -#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ -#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ - -/*!< RTC congiguration */ -#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ -#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ - -#define RCC_BDCR_RTCEN_Pos (15U) -#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ -#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ -#define RCC_BDCR_BDRST_Pos (16U) -#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ - -/******************* Bit definition for RCC_CSR register ********************/ -#define RCC_CSR_LSION_Pos (0U) -#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY_Pos (1U) -#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_RMVF_Pos (24U) -#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ -#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ -#define RCC_CSR_PINRSTF_Pos (26U) -#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ -#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF_Pos (27U) -#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ -#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF_Pos (28U) -#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ -#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF_Pos (29U) -#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ -#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF_Pos (30U) -#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ -#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF_Pos (31U) -#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ -#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ - - - -/******************************************************************************/ -/* */ -/* General Purpose and Alternate Function I/O */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CRL register *******************/ -#define GPIO_CRL_MODE_Pos (0U) -#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ -#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ - -#define GPIO_CRL_MODE0_Pos (0U) -#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_CRL_MODE1_Pos (4U) -#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ -#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ -#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ - -#define GPIO_CRL_MODE2_Pos (8U) -#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ -#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ -#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ - -#define GPIO_CRL_MODE3_Pos (12U) -#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ -#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ -#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ - -#define GPIO_CRL_MODE4_Pos (16U) -#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ -#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ -#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ - -#define GPIO_CRL_MODE5_Pos (20U) -#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ -#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ -#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ - -#define GPIO_CRL_MODE6_Pos (24U) -#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ -#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ -#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ - -#define GPIO_CRL_MODE7_Pos (28U) -#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ -#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ -#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ - -#define GPIO_CRL_CNF_Pos (2U) -#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ -#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ - -#define GPIO_CRL_CNF0_Pos (2U) -#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ -#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ -#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ - -#define GPIO_CRL_CNF1_Pos (6U) -#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ -#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ -#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ - -#define GPIO_CRL_CNF2_Pos (10U) -#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ -#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ -#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ - -#define GPIO_CRL_CNF3_Pos (14U) -#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ -#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ -#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ - -#define GPIO_CRL_CNF4_Pos (18U) -#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ -#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ -#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ - -#define GPIO_CRL_CNF5_Pos (22U) -#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ -#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ -#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ - -#define GPIO_CRL_CNF6_Pos (26U) -#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ -#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ -#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ - -#define GPIO_CRL_CNF7_Pos (30U) -#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ -#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ -#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ - -/******************* Bit definition for GPIO_CRH register *******************/ -#define GPIO_CRH_MODE_Pos (0U) -#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ -#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ - -#define GPIO_CRH_MODE8_Pos (0U) -#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ -#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ -#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ - -#define GPIO_CRH_MODE9_Pos (4U) -#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ -#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ -#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ - -#define GPIO_CRH_MODE10_Pos (8U) -#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ -#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ -#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ - -#define GPIO_CRH_MODE11_Pos (12U) -#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ -#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ -#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ - -#define GPIO_CRH_MODE12_Pos (16U) -#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ -#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ -#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ - -#define GPIO_CRH_MODE13_Pos (20U) -#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ -#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ -#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ - -#define GPIO_CRH_MODE14_Pos (24U) -#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ -#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ -#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ - -#define GPIO_CRH_MODE15_Pos (28U) -#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ -#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ -#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ - -#define GPIO_CRH_CNF_Pos (2U) -#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ -#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ - -#define GPIO_CRH_CNF8_Pos (2U) -#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ -#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ -#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ - -#define GPIO_CRH_CNF9_Pos (6U) -#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ -#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ -#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ - -#define GPIO_CRH_CNF10_Pos (10U) -#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ -#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ -#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ - -#define GPIO_CRH_CNF11_Pos (14U) -#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ -#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ -#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ - -#define GPIO_CRH_CNF12_Pos (18U) -#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ -#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ -#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ - -#define GPIO_CRH_CNF13_Pos (22U) -#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ -#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ -#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ - -#define GPIO_CRH_CNF14_Pos (26U) -#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ -#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ -#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ - -#define GPIO_CRH_CNF15_Pos (30U) -#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ -#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ -#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ - -/*!<****************** Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_IDR0_Pos (0U) -#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ -#define GPIO_IDR_IDR1_Pos (1U) -#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ -#define GPIO_IDR_IDR2_Pos (2U) -#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ -#define GPIO_IDR_IDR3_Pos (3U) -#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ -#define GPIO_IDR_IDR4_Pos (4U) -#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ -#define GPIO_IDR_IDR5_Pos (5U) -#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ -#define GPIO_IDR_IDR6_Pos (6U) -#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ -#define GPIO_IDR_IDR7_Pos (7U) -#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ -#define GPIO_IDR_IDR8_Pos (8U) -#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ -#define GPIO_IDR_IDR9_Pos (9U) -#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ -#define GPIO_IDR_IDR10_Pos (10U) -#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ -#define GPIO_IDR_IDR11_Pos (11U) -#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ -#define GPIO_IDR_IDR12_Pos (12U) -#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ -#define GPIO_IDR_IDR13_Pos (13U) -#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ -#define GPIO_IDR_IDR14_Pos (14U) -#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ -#define GPIO_IDR_IDR15_Pos (15U) -#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ - -/******************* Bit definition for GPIO_ODR register *******************/ -#define GPIO_ODR_ODR0_Pos (0U) -#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ -#define GPIO_ODR_ODR1_Pos (1U) -#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ -#define GPIO_ODR_ODR2_Pos (2U) -#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ -#define GPIO_ODR_ODR3_Pos (3U) -#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ -#define GPIO_ODR_ODR4_Pos (4U) -#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ -#define GPIO_ODR_ODR5_Pos (5U) -#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ -#define GPIO_ODR_ODR6_Pos (6U) -#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ -#define GPIO_ODR_ODR7_Pos (7U) -#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ -#define GPIO_ODR_ODR8_Pos (8U) -#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ -#define GPIO_ODR_ODR9_Pos (9U) -#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ -#define GPIO_ODR_ODR10_Pos (10U) -#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ -#define GPIO_ODR_ODR11_Pos (11U) -#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ -#define GPIO_ODR_ODR12_Pos (12U) -#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ -#define GPIO_ODR_ODR13_Pos (13U) -#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ -#define GPIO_ODR_ODR14_Pos (14U) -#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ -#define GPIO_ODR_ODR15_Pos (15U) -#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSRR register *******************/ -#define GPIO_BSRR_BS0_Pos (0U) -#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ -#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ -#define GPIO_BSRR_BS1_Pos (1U) -#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ -#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ -#define GPIO_BSRR_BS2_Pos (2U) -#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ -#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ -#define GPIO_BSRR_BS3_Pos (3U) -#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ -#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ -#define GPIO_BSRR_BS4_Pos (4U) -#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ -#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ -#define GPIO_BSRR_BS5_Pos (5U) -#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ -#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ -#define GPIO_BSRR_BS6_Pos (6U) -#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ -#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ -#define GPIO_BSRR_BS7_Pos (7U) -#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ -#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ -#define GPIO_BSRR_BS8_Pos (8U) -#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ -#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ -#define GPIO_BSRR_BS9_Pos (9U) -#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ -#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ -#define GPIO_BSRR_BS10_Pos (10U) -#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ -#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ -#define GPIO_BSRR_BS11_Pos (11U) -#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ -#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ -#define GPIO_BSRR_BS12_Pos (12U) -#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ -#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ -#define GPIO_BSRR_BS13_Pos (13U) -#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ -#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ -#define GPIO_BSRR_BS14_Pos (14U) -#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ -#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ -#define GPIO_BSRR_BS15_Pos (15U) -#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ -#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ - -#define GPIO_BSRR_BR0_Pos (16U) -#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ -#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ -#define GPIO_BSRR_BR1_Pos (17U) -#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ -#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ -#define GPIO_BSRR_BR2_Pos (18U) -#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ -#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ -#define GPIO_BSRR_BR3_Pos (19U) -#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ -#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ -#define GPIO_BSRR_BR4_Pos (20U) -#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ -#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ -#define GPIO_BSRR_BR5_Pos (21U) -#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ -#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ -#define GPIO_BSRR_BR6_Pos (22U) -#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ -#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ -#define GPIO_BSRR_BR7_Pos (23U) -#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ -#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ -#define GPIO_BSRR_BR8_Pos (24U) -#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ -#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ -#define GPIO_BSRR_BR9_Pos (25U) -#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ -#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ -#define GPIO_BSRR_BR10_Pos (26U) -#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ -#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ -#define GPIO_BSRR_BR11_Pos (27U) -#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ -#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ -#define GPIO_BSRR_BR12_Pos (28U) -#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ -#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ -#define GPIO_BSRR_BR13_Pos (29U) -#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ -#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ -#define GPIO_BSRR_BR14_Pos (30U) -#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ -#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ -#define GPIO_BSRR_BR15_Pos (31U) -#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ -#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BRR register *******************/ -#define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ -#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ -#define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ -#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ -#define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ -#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ -#define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ -#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ -#define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ -#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ -#define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ -#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ -#define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ -#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ -#define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ -#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ -#define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ -#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ -#define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ -#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ -#define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ -#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ -#define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ -#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ -#define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ -#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ -#define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ -#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ -#define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ -#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ -#define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ -#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCKR_LCK0_Pos (0U) -#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ -#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ -#define GPIO_LCKR_LCK1_Pos (1U) -#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ -#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ -#define GPIO_LCKR_LCK2_Pos (2U) -#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ -#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ -#define GPIO_LCKR_LCK3_Pos (3U) -#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ -#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ -#define GPIO_LCKR_LCK4_Pos (4U) -#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ -#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ -#define GPIO_LCKR_LCK5_Pos (5U) -#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ -#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ -#define GPIO_LCKR_LCK6_Pos (6U) -#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ -#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ -#define GPIO_LCKR_LCK7_Pos (7U) -#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ -#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ -#define GPIO_LCKR_LCK8_Pos (8U) -#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ -#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ -#define GPIO_LCKR_LCK9_Pos (9U) -#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ -#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ -#define GPIO_LCKR_LCK10_Pos (10U) -#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ -#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ -#define GPIO_LCKR_LCK11_Pos (11U) -#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ -#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ -#define GPIO_LCKR_LCK12_Pos (12U) -#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ -#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ -#define GPIO_LCKR_LCK13_Pos (13U) -#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ -#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ -#define GPIO_LCKR_LCK14_Pos (14U) -#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ -#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ -#define GPIO_LCKR_LCK15_Pos (15U) -#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ -#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ -#define GPIO_LCKR_LCKK_Pos (16U) -#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ -#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for AFIO_EVCR register *******************/ -#define AFIO_EVCR_PIN_Pos (0U) -#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ -#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ -#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ -#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ -#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ -#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ - -/*!< PIN configuration */ -#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ -#define AFIO_EVCR_PIN_PX1_Pos (0U) -#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ -#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ -#define AFIO_EVCR_PIN_PX2_Pos (1U) -#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ -#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ -#define AFIO_EVCR_PIN_PX3_Pos (0U) -#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ -#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ -#define AFIO_EVCR_PIN_PX4_Pos (2U) -#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ -#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ -#define AFIO_EVCR_PIN_PX5_Pos (0U) -#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ -#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ -#define AFIO_EVCR_PIN_PX6_Pos (1U) -#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ -#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ -#define AFIO_EVCR_PIN_PX7_Pos (0U) -#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ -#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ -#define AFIO_EVCR_PIN_PX8_Pos (3U) -#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ -#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ -#define AFIO_EVCR_PIN_PX9_Pos (0U) -#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ -#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ -#define AFIO_EVCR_PIN_PX10_Pos (1U) -#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ -#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ -#define AFIO_EVCR_PIN_PX11_Pos (0U) -#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ -#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ -#define AFIO_EVCR_PIN_PX12_Pos (2U) -#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ -#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ -#define AFIO_EVCR_PIN_PX13_Pos (0U) -#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ -#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ -#define AFIO_EVCR_PIN_PX14_Pos (1U) -#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ -#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ -#define AFIO_EVCR_PIN_PX15_Pos (0U) -#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ -#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ - -#define AFIO_EVCR_PORT_Pos (4U) -#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ -#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ -#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ -#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ -#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ - -/*!< PORT configuration */ -#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ -#define AFIO_EVCR_PORT_PB_Pos (4U) -#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ -#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ -#define AFIO_EVCR_PORT_PC_Pos (5U) -#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ -#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ -#define AFIO_EVCR_PORT_PD_Pos (4U) -#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ -#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ -#define AFIO_EVCR_PORT_PE_Pos (6U) -#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ -#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ - -#define AFIO_EVCR_EVOE_Pos (7U) -#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ -#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ - -/****************** Bit definition for AFIO_MAPR register *******************/ -#define AFIO_MAPR_SPI1_REMAP_Pos (0U) -#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ -#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ -#define AFIO_MAPR_I2C1_REMAP_Pos (1U) -#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ -#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ -#define AFIO_MAPR_USART1_REMAP_Pos (2U) -#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ -#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ -#define AFIO_MAPR_USART2_REMAP_Pos (3U) -#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ -#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ - -#define AFIO_MAPR_USART3_REMAP_Pos (4U) -#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ -#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ -#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ - -/* USART3_REMAP configuration */ -#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) -#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ -#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_MAPR_TIM1_REMAP_Pos (6U) -#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ -#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ -#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ - -/*!< TIM1_REMAP configuration */ -#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_MAPR_TIM2_REMAP_Pos (8U) -#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ -#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ -#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ - -/*!< TIM2_REMAP configuration */ -#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_MAPR_TIM3_REMAP_Pos (10U) -#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ -#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ -#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ - -/*!< TIM3_REMAP configuration */ -#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_MAPR_TIM4_REMAP_Pos (12U) -#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ -#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_MAPR_CAN_REMAP_Pos (13U) -#define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */ -#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */ -#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */ - -/*!< CAN_REMAP configuration */ -#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) -#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) -#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_MAPR_PD01_REMAP_Pos (15U) -#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ -#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ - -/*!< SWJ_CFG configuration */ -#define AFIO_MAPR_SWJ_CFG_Pos (24U) -#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ -#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ -#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ -#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ - -#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) -#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) -#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ -#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ - - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0_Pos (0U) -#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ -#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1_Pos (4U) -#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ -#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2_Pos (8U) -#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ -#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3_Pos (12U) -#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ -#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ - -/*!< EXTI0 configuration */ -#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB_Pos (0U) -#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ -#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC_Pos (1U) -#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ -#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD_Pos (0U) -#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ -#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE_Pos (2U) -#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ -#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF_Pos (0U) -#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ -#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG_Pos (1U) -#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ -#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ - -/*!< EXTI1 configuration */ -#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB_Pos (4U) -#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ -#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC_Pos (5U) -#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ -#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD_Pos (4U) -#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ -#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE_Pos (6U) -#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ -#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF_Pos (4U) -#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ -#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG_Pos (5U) -#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ -#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ - -/*!< EXTI2 configuration */ -#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB_Pos (8U) -#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ -#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC_Pos (9U) -#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ -#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD_Pos (8U) -#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ -#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE_Pos (10U) -#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ -#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF_Pos (8U) -#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ -#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG_Pos (9U) -#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ -#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ - -/*!< EXTI3 configuration */ -#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB_Pos (12U) -#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ -#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC_Pos (13U) -#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ -#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD_Pos (12U) -#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ -#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE_Pos (14U) -#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ -#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF_Pos (12U) -#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ -#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG_Pos (13U) -#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ -#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4_Pos (0U) -#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ -#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5_Pos (4U) -#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ -#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6_Pos (8U) -#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ -#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7_Pos (12U) -#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ -#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ - -/*!< EXTI4 configuration */ -#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB_Pos (0U) -#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ -#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC_Pos (1U) -#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ -#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD_Pos (0U) -#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ -#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE_Pos (2U) -#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ -#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF_Pos (0U) -#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ -#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG_Pos (1U) -#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ -#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ - -/* EXTI5 configuration */ -#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB_Pos (4U) -#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ -#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC_Pos (5U) -#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ -#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD_Pos (4U) -#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ -#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE_Pos (6U) -#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ -#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF_Pos (4U) -#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ -#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG_Pos (5U) -#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ -#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ - -/*!< EXTI6 configuration */ -#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB_Pos (8U) -#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ -#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC_Pos (9U) -#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ -#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD_Pos (8U) -#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ -#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE_Pos (10U) -#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ -#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF_Pos (8U) -#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ -#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG_Pos (9U) -#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ -#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ - -/*!< EXTI7 configuration */ -#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB_Pos (12U) -#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ -#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC_Pos (13U) -#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ -#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD_Pos (12U) -#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ -#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE_Pos (14U) -#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ -#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF_Pos (12U) -#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ -#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG_Pos (13U) -#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ -#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8_Pos (0U) -#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ -#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9_Pos (4U) -#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ -#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10_Pos (8U) -#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ -#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11_Pos (12U) -#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ -#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ - -/*!< EXTI8 configuration */ -#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB_Pos (0U) -#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ -#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC_Pos (1U) -#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ -#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD_Pos (0U) -#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ -#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE_Pos (2U) -#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ -#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF_Pos (0U) -#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ -#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG_Pos (1U) -#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ -#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ - -/*!< EXTI9 configuration */ -#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB_Pos (4U) -#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ -#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC_Pos (5U) -#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ -#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD_Pos (4U) -#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ -#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE_Pos (6U) -#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ -#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF_Pos (4U) -#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ -#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG_Pos (5U) -#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ -#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ - -/*!< EXTI10 configuration */ -#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB_Pos (8U) -#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ -#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC_Pos (9U) -#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ -#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD_Pos (8U) -#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ -#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE_Pos (10U) -#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ -#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF_Pos (8U) -#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ -#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG_Pos (9U) -#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ -#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ - -/*!< EXTI11 configuration */ -#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB_Pos (12U) -#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ -#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC_Pos (13U) -#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ -#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD_Pos (12U) -#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ -#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE_Pos (14U) -#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ -#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF_Pos (12U) -#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ -#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG_Pos (13U) -#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ -#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12_Pos (0U) -#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ -#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13_Pos (4U) -#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ -#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14_Pos (8U) -#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ -#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15_Pos (12U) -#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ -#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ - -/* EXTI12 configuration */ -#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB_Pos (0U) -#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ -#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC_Pos (1U) -#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ -#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD_Pos (0U) -#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ -#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE_Pos (2U) -#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ -#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF_Pos (0U) -#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ -#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG_Pos (1U) -#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ -#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ - -/* EXTI13 configuration */ -#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB_Pos (4U) -#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ -#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC_Pos (5U) -#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ -#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD_Pos (4U) -#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ -#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE_Pos (6U) -#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ -#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF_Pos (4U) -#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ -#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG_Pos (5U) -#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ -#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ - -/*!< EXTI14 configuration */ -#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB_Pos (8U) -#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ -#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC_Pos (9U) -#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ -#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD_Pos (8U) -#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ -#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE_Pos (10U) -#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ -#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF_Pos (8U) -#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ -#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG_Pos (9U) -#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ -#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ - -/*!< EXTI15 configuration */ -#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB_Pos (12U) -#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ -#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC_Pos (13U) -#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ -#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD_Pos (12U) -#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ -#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE_Pos (14U) -#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ -#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF_Pos (12U) -#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ -#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG_Pos (13U) -#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ -#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ - -/****************** Bit definition for AFIO_MAPR2 register ******************/ - - - -/******************************************************************************/ -/* */ -/* External Interrupt/Event Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0_Pos (0U) -#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ -#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1_Pos (1U) -#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ -#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2_Pos (2U) -#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ -#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3_Pos (3U) -#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ -#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4_Pos (4U) -#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ -#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5_Pos (5U) -#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ -#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6_Pos (6U) -#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ -#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7_Pos (7U) -#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ -#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8_Pos (8U) -#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ -#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9_Pos (9U) -#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ -#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10_Pos (10U) -#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ -#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11_Pos (11U) -#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ -#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12_Pos (12U) -#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ -#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13_Pos (13U) -#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ -#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14_Pos (14U) -#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ -#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15_Pos (15U) -#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ -#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16_Pos (16U) -#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ -#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17_Pos (17U) -#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ -#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18_Pos (18U) -#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ -#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ - -/* References Defines */ -#define EXTI_IMR_IM0 EXTI_IMR_MR0 -#define EXTI_IMR_IM1 EXTI_IMR_MR1 -#define EXTI_IMR_IM2 EXTI_IMR_MR2 -#define EXTI_IMR_IM3 EXTI_IMR_MR3 -#define EXTI_IMR_IM4 EXTI_IMR_MR4 -#define EXTI_IMR_IM5 EXTI_IMR_MR5 -#define EXTI_IMR_IM6 EXTI_IMR_MR6 -#define EXTI_IMR_IM7 EXTI_IMR_MR7 -#define EXTI_IMR_IM8 EXTI_IMR_MR8 -#define EXTI_IMR_IM9 EXTI_IMR_MR9 -#define EXTI_IMR_IM10 EXTI_IMR_MR10 -#define EXTI_IMR_IM11 EXTI_IMR_MR11 -#define EXTI_IMR_IM12 EXTI_IMR_MR12 -#define EXTI_IMR_IM13 EXTI_IMR_MR13 -#define EXTI_IMR_IM14 EXTI_IMR_MR14 -#define EXTI_IMR_IM15 EXTI_IMR_MR15 -#define EXTI_IMR_IM16 EXTI_IMR_MR16 -#define EXTI_IMR_IM17 EXTI_IMR_MR17 -#define EXTI_IMR_IM18 EXTI_IMR_MR18 -#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */ - -/******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0_Pos (0U) -#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ -#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1_Pos (1U) -#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ -#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2_Pos (2U) -#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ -#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3_Pos (3U) -#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ -#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4_Pos (4U) -#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ -#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5_Pos (5U) -#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ -#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6_Pos (6U) -#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ -#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7_Pos (7U) -#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ -#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8_Pos (8U) -#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ -#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9_Pos (9U) -#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ -#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10_Pos (10U) -#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ -#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11_Pos (11U) -#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ -#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12_Pos (12U) -#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ -#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13_Pos (13U) -#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ -#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14_Pos (14U) -#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ -#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15_Pos (15U) -#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ -#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16_Pos (16U) -#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ -#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17_Pos (17U) -#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ -#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18_Pos (18U) -#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ -#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ - -/* References Defines */ -#define EXTI_EMR_EM0 EXTI_EMR_MR0 -#define EXTI_EMR_EM1 EXTI_EMR_MR1 -#define EXTI_EMR_EM2 EXTI_EMR_MR2 -#define EXTI_EMR_EM3 EXTI_EMR_MR3 -#define EXTI_EMR_EM4 EXTI_EMR_MR4 -#define EXTI_EMR_EM5 EXTI_EMR_MR5 -#define EXTI_EMR_EM6 EXTI_EMR_MR6 -#define EXTI_EMR_EM7 EXTI_EMR_MR7 -#define EXTI_EMR_EM8 EXTI_EMR_MR8 -#define EXTI_EMR_EM9 EXTI_EMR_MR9 -#define EXTI_EMR_EM10 EXTI_EMR_MR10 -#define EXTI_EMR_EM11 EXTI_EMR_MR11 -#define EXTI_EMR_EM12 EXTI_EMR_MR12 -#define EXTI_EMR_EM13 EXTI_EMR_MR13 -#define EXTI_EMR_EM14 EXTI_EMR_MR14 -#define EXTI_EMR_EM15 EXTI_EMR_MR15 -#define EXTI_EMR_EM16 EXTI_EMR_MR16 -#define EXTI_EMR_EM17 EXTI_EMR_MR17 -#define EXTI_EMR_EM18 EXTI_EMR_MR18 - -/****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0_Pos (0U) -#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ -#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1_Pos (1U) -#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ -#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2_Pos (2U) -#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ -#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3_Pos (3U) -#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ -#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4_Pos (4U) -#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ -#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5_Pos (5U) -#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ -#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6_Pos (6U) -#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ -#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7_Pos (7U) -#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ -#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8_Pos (8U) -#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ -#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9_Pos (9U) -#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ -#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10_Pos (10U) -#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ -#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11_Pos (11U) -#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ -#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12_Pos (12U) -#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ -#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13_Pos (13U) -#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ -#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14_Pos (14U) -#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ -#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15_Pos (15U) -#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ -#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16_Pos (16U) -#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ -#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17_Pos (17U) -#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ -#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18_Pos (18U) -#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ -#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ - -/* References Defines */ -#define EXTI_RTSR_RT0 EXTI_RTSR_TR0 -#define EXTI_RTSR_RT1 EXTI_RTSR_TR1 -#define EXTI_RTSR_RT2 EXTI_RTSR_TR2 -#define EXTI_RTSR_RT3 EXTI_RTSR_TR3 -#define EXTI_RTSR_RT4 EXTI_RTSR_TR4 -#define EXTI_RTSR_RT5 EXTI_RTSR_TR5 -#define EXTI_RTSR_RT6 EXTI_RTSR_TR6 -#define EXTI_RTSR_RT7 EXTI_RTSR_TR7 -#define EXTI_RTSR_RT8 EXTI_RTSR_TR8 -#define EXTI_RTSR_RT9 EXTI_RTSR_TR9 -#define EXTI_RTSR_RT10 EXTI_RTSR_TR10 -#define EXTI_RTSR_RT11 EXTI_RTSR_TR11 -#define EXTI_RTSR_RT12 EXTI_RTSR_TR12 -#define EXTI_RTSR_RT13 EXTI_RTSR_TR13 -#define EXTI_RTSR_RT14 EXTI_RTSR_TR14 -#define EXTI_RTSR_RT15 EXTI_RTSR_TR15 -#define EXTI_RTSR_RT16 EXTI_RTSR_TR16 -#define EXTI_RTSR_RT17 EXTI_RTSR_TR17 -#define EXTI_RTSR_RT18 EXTI_RTSR_TR18 - -/****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0_Pos (0U) -#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ -#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1_Pos (1U) -#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ -#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2_Pos (2U) -#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ -#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3_Pos (3U) -#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ -#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4_Pos (4U) -#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ -#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5_Pos (5U) -#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ -#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6_Pos (6U) -#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ -#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7_Pos (7U) -#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ -#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8_Pos (8U) -#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ -#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9_Pos (9U) -#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ -#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10_Pos (10U) -#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ -#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11_Pos (11U) -#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ -#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12_Pos (12U) -#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ -#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13_Pos (13U) -#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ -#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14_Pos (14U) -#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ -#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15_Pos (15U) -#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ -#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16_Pos (16U) -#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ -#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17_Pos (17U) -#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ -#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18_Pos (18U) -#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ -#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ - -/* References Defines */ -#define EXTI_FTSR_FT0 EXTI_FTSR_TR0 -#define EXTI_FTSR_FT1 EXTI_FTSR_TR1 -#define EXTI_FTSR_FT2 EXTI_FTSR_TR2 -#define EXTI_FTSR_FT3 EXTI_FTSR_TR3 -#define EXTI_FTSR_FT4 EXTI_FTSR_TR4 -#define EXTI_FTSR_FT5 EXTI_FTSR_TR5 -#define EXTI_FTSR_FT6 EXTI_FTSR_TR6 -#define EXTI_FTSR_FT7 EXTI_FTSR_TR7 -#define EXTI_FTSR_FT8 EXTI_FTSR_TR8 -#define EXTI_FTSR_FT9 EXTI_FTSR_TR9 -#define EXTI_FTSR_FT10 EXTI_FTSR_TR10 -#define EXTI_FTSR_FT11 EXTI_FTSR_TR11 -#define EXTI_FTSR_FT12 EXTI_FTSR_TR12 -#define EXTI_FTSR_FT13 EXTI_FTSR_TR13 -#define EXTI_FTSR_FT14 EXTI_FTSR_TR14 -#define EXTI_FTSR_FT15 EXTI_FTSR_TR15 -#define EXTI_FTSR_FT16 EXTI_FTSR_TR16 -#define EXTI_FTSR_FT17 EXTI_FTSR_TR17 -#define EXTI_FTSR_FT18 EXTI_FTSR_TR18 - -/****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0_Pos (0U) -#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ -#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1_Pos (1U) -#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ -#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2_Pos (2U) -#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ -#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3_Pos (3U) -#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ -#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4_Pos (4U) -#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ -#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5_Pos (5U) -#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ -#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6_Pos (6U) -#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ -#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7_Pos (7U) -#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ -#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8_Pos (8U) -#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ -#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9_Pos (9U) -#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ -#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10_Pos (10U) -#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ -#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11_Pos (11U) -#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ -#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12_Pos (12U) -#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ -#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13_Pos (13U) -#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ -#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14_Pos (14U) -#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ -#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15_Pos (15U) -#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ -#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16_Pos (16U) -#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ -#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17_Pos (17U) -#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ -#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18_Pos (18U) -#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ -#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ - -/* References Defines */ -#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 -#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 -#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 -#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 -#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 -#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 -#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 -#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 -#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 -#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 -#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 -#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 -#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 -#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 -#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 -#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 -#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 -#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 -#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 - -/******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0_Pos (0U) -#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ -#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ -#define EXTI_PR_PR1_Pos (1U) -#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ -#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ -#define EXTI_PR_PR2_Pos (2U) -#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ -#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ -#define EXTI_PR_PR3_Pos (3U) -#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ -#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ -#define EXTI_PR_PR4_Pos (4U) -#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ -#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ -#define EXTI_PR_PR5_Pos (5U) -#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ -#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ -#define EXTI_PR_PR6_Pos (6U) -#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ -#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ -#define EXTI_PR_PR7_Pos (7U) -#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ -#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ -#define EXTI_PR_PR8_Pos (8U) -#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ -#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ -#define EXTI_PR_PR9_Pos (9U) -#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ -#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ -#define EXTI_PR_PR10_Pos (10U) -#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ -#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ -#define EXTI_PR_PR11_Pos (11U) -#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ -#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ -#define EXTI_PR_PR12_Pos (12U) -#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ -#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ -#define EXTI_PR_PR13_Pos (13U) -#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ -#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ -#define EXTI_PR_PR14_Pos (14U) -#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ -#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ -#define EXTI_PR_PR15_Pos (15U) -#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ -#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ -#define EXTI_PR_PR16_Pos (16U) -#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ -#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ -#define EXTI_PR_PR17_Pos (17U) -#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ -#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18_Pos (18U) -#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ -#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ - -/* References Defines */ -#define EXTI_PR_PIF0 EXTI_PR_PR0 -#define EXTI_PR_PIF1 EXTI_PR_PR1 -#define EXTI_PR_PIF2 EXTI_PR_PR2 -#define EXTI_PR_PIF3 EXTI_PR_PR3 -#define EXTI_PR_PIF4 EXTI_PR_PR4 -#define EXTI_PR_PIF5 EXTI_PR_PR5 -#define EXTI_PR_PIF6 EXTI_PR_PR6 -#define EXTI_PR_PIF7 EXTI_PR_PR7 -#define EXTI_PR_PIF8 EXTI_PR_PR8 -#define EXTI_PR_PIF9 EXTI_PR_PR9 -#define EXTI_PR_PIF10 EXTI_PR_PR10 -#define EXTI_PR_PIF11 EXTI_PR_PR11 -#define EXTI_PR_PIF12 EXTI_PR_PR12 -#define EXTI_PR_PIF13 EXTI_PR_PR13 -#define EXTI_PR_PIF14 EXTI_PR_PR14 -#define EXTI_PR_PIF15 EXTI_PR_PR15 -#define EXTI_PR_PIF16 EXTI_PR_PR16 -#define EXTI_PR_PIF17 EXTI_PR_PR17 -#define EXTI_PR_PIF18 EXTI_PR_PR18 - -/******************************************************************************/ -/* */ -/* DMA Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1_Pos (0U) -#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ -#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1_Pos (1U) -#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ -#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1_Pos (2U) -#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ -#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1_Pos (3U) -#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ -#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2_Pos (4U) -#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ -#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2_Pos (5U) -#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ -#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2_Pos (6U) -#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ -#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2_Pos (7U) -#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ -#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3_Pos (8U) -#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ -#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3_Pos (9U) -#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ -#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3_Pos (10U) -#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ -#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3_Pos (11U) -#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ -#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4_Pos (12U) -#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ -#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4_Pos (13U) -#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ -#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4_Pos (14U) -#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ -#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4_Pos (15U) -#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ -#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5_Pos (16U) -#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ -#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5_Pos (17U) -#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ -#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5_Pos (18U) -#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ -#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5_Pos (19U) -#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ -#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6_Pos (20U) -#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ -#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6_Pos (21U) -#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ -#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6_Pos (22U) -#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ -#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6_Pos (23U) -#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ -#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7_Pos (24U) -#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ -#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7_Pos (25U) -#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ -#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7_Pos (26U) -#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ -#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7_Pos (27U) -#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ -#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ - -/******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1_Pos (0U) -#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ -#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1_Pos (1U) -#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ -#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1_Pos (2U) -#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ -#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1_Pos (3U) -#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ -#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2_Pos (4U) -#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ -#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2_Pos (5U) -#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ -#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2_Pos (6U) -#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ -#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2_Pos (7U) -#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ -#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3_Pos (8U) -#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ -#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3_Pos (9U) -#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ -#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3_Pos (10U) -#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ -#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3_Pos (11U) -#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ -#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4_Pos (12U) -#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ -#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4_Pos (13U) -#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ -#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4_Pos (14U) -#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ -#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4_Pos (15U) -#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ -#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5_Pos (16U) -#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ -#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5_Pos (17U) -#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ -#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5_Pos (18U) -#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ -#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5_Pos (19U) -#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ -#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6_Pos (20U) -#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ -#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6_Pos (21U) -#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ -#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6_Pos (22U) -#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ -#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6_Pos (23U) -#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ -#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7_Pos (24U) -#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ -#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7_Pos (25U) -#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ -#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7_Pos (26U) -#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ -#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7_Pos (27U) -#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ -#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CCR register *******************/ -#define DMA_CCR_EN_Pos (0U) -#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ -#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ -#define DMA_CCR_TCIE_Pos (1U) -#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ -#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ -#define DMA_CCR_HTIE_Pos (2U) -#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ -#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ -#define DMA_CCR_TEIE_Pos (3U) -#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ -#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ -#define DMA_CCR_DIR_Pos (4U) -#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ -#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ -#define DMA_CCR_CIRC_Pos (5U) -#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ -#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ -#define DMA_CCR_PINC_Pos (6U) -#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ -#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ -#define DMA_CCR_MINC_Pos (7U) -#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ -#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ - -#define DMA_CCR_PSIZE_Pos (8U) -#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ -#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ -#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ - -#define DMA_CCR_MSIZE_Pos (10U) -#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ -#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ -#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ - -#define DMA_CCR_PL_Pos (12U) -#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ -#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ -#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ -#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ - -#define DMA_CCR_MEM2MEM_Pos (14U) -#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ -#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ - -/****************** Bit definition for DMA_CNDTR register ******************/ -#define DMA_CNDTR_NDT_Pos (0U) -#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ -#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CPAR register *******************/ -#define DMA_CPAR_PA_Pos (0U) -#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ -#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CMAR register *******************/ -#define DMA_CMAR_MA_Pos (0U) -#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ -#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter (ADC) */ -/* */ -/******************************************************************************/ - -/* - * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) - */ -#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ - -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD_Pos (0U) -#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ -#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_SR_EOS_Pos (1U) -#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */ -#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_SR_JEOS_Pos (2U) -#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ -#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_SR_JSTRT_Pos (3U) -#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ -#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ -#define ADC_SR_STRT_Pos (4U) -#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ -#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ - -/* Legacy defines */ -#define ADC_SR_EOC (ADC_SR_EOS) -#define ADC_SR_JEOC (ADC_SR_JEOS) - -/******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH_Pos (0U) -#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ -#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ -#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ -#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ -#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ -#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ - -#define ADC_CR1_EOSIE_Pos (5U) -#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ -#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_CR1_AWDIE_Pos (6U) -#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ -#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_CR1_JEOSIE_Pos (7U) -#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ -#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_CR1_SCAN_Pos (8U) -#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ -#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ -#define ADC_CR1_AWDSGL_Pos (9U) -#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ -#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CR1_JAUTO_Pos (10U) -#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ -#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ -#define ADC_CR1_DISCEN_Pos (11U) -#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ -#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ -#define ADC_CR1_JDISCEN_Pos (12U) -#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ -#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ - -#define ADC_CR1_DISCNUM_Pos (13U) -#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ -#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ -#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ -#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ - -#define ADC_CR1_DUALMOD_Pos (16U) -#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ -#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ -#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ -#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */ -#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ -#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ - -#define ADC_CR1_JAWDEN_Pos (22U) -#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ -#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CR1_AWDEN_Pos (23U) -#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ -#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ - -/* Legacy defines */ -#define ADC_CR1_EOCIE (ADC_CR1_EOSIE) -#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) - -/******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON_Pos (0U) -#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ -#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ -#define ADC_CR2_CONT_Pos (1U) -#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ -#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CR2_CAL_Pos (2U) -#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ -#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ -#define ADC_CR2_RSTCAL_Pos (3U) -#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ -#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ -#define ADC_CR2_DMA_Pos (8U) -#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ -#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ -#define ADC_CR2_ALIGN_Pos (11U) -#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ -#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ - -#define ADC_CR2_JEXTSEL_Pos (12U) -#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ -#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ -#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ -#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ - -#define ADC_CR2_JEXTTRIG_Pos (15U) -#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ -#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ - -#define ADC_CR2_EXTSEL_Pos (17U) -#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ -#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ -#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ -#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ - -#define ADC_CR2_EXTTRIG_Pos (20U) -#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ -#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ -#define ADC_CR2_JSWSTART_Pos (21U) -#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ -#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR2_SWSTART_Pos (22U) -#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ -#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR2_TSVREFE_Pos (23U) -#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ -#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ - -/****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP10_Pos (0U) -#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ -#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR1_SMP11_Pos (3U) -#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ -#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR1_SMP12_Pos (6U) -#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR1_SMP13_Pos (9U) -#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR1_SMP14_Pos (12U) -#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ -#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR1_SMP15_Pos (15U) -#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ -#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR1_SMP16_Pos (18U) -#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR1_SMP17_Pos (21U) -#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ - -/****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP0_Pos (0U) -#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ -#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR2_SMP1_Pos (3U) -#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ -#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR2_SMP2_Pos (6U) -#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR2_SMP3_Pos (9U) -#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR2_SMP4_Pos (12U) -#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ -#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR2_SMP5_Pos (15U) -#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ -#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR2_SMP6_Pos (18U) -#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR2_SMP7_Pos (21U) -#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ - -#define ADC_SMPR2_SMP8_Pos (24U) -#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ -#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ - -#define ADC_SMPR2_SMP9_Pos (27U) -#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ -#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ - -/****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1_Pos (0U) -#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ -#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ - -/****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2_Pos (0U) -#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ -#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ - -/****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3_Pos (0U) -#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ -#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ - -/****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4_Pos (0U) -#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ -#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ - -/******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT_Pos (0U) -#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ -#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ - -/******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT_Pos (0U) -#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ -#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ - -/******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_SQ13_Pos (0U) -#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ -#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ -#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ - -#define ADC_SQR1_SQ14_Pos (5U) -#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ -#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ -#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ - -#define ADC_SQR1_SQ15_Pos (10U) -#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ -#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ -#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ -#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ - -#define ADC_SQR1_SQ16_Pos (15U) -#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ -#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ -#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ -#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ - -#define ADC_SQR1_L_Pos (20U) -#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ -#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */ -#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ - -/******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ7_Pos (0U) -#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ -#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ - -#define ADC_SQR2_SQ8_Pos (5U) -#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ -#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ -#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ - -#define ADC_SQR2_SQ9_Pos (10U) -#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ -#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ -#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ -#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ - -#define ADC_SQR2_SQ10_Pos (15U) -#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ -#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ -#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ -#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ - -#define ADC_SQR2_SQ11_Pos (20U) -#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ -#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ -#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ -#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ - -#define ADC_SQR2_SQ12_Pos (25U) -#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ -#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ -#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ - -/******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ1_Pos (0U) -#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ -#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ - -#define ADC_SQR3_SQ2_Pos (5U) -#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ -#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ -#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ - -#define ADC_SQR3_SQ3_Pos (10U) -#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ -#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ -#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ -#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ - -#define ADC_SQR3_SQ4_Pos (15U) -#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ -#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ -#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ -#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ - -#define ADC_SQR3_SQ5_Pos (20U) -#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ -#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ -#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ -#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ - -#define ADC_SQR3_SQ6_Pos (25U) -#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ -#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ -#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ - -/******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1_Pos (0U) -#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ -#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ -#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ - -#define ADC_JSQR_JSQ2_Pos (5U) -#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ -#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ -#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ -#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ - -#define ADC_JSQR_JSQ3_Pos (10U) -#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ -#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ -#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ -#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ - -#define ADC_JSQR_JSQ4_Pos (15U) -#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ -#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ -#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ - -#define ADC_JSQR_JL_Pos (20U) -#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ -#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ - -/******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ - -/******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ - -/******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ - -/******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA_Pos (0U) -#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ -#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_ADC2DATA_Pos (16U) -#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ -#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ - - -/*****************************************************************************/ -/* */ -/* Timers (TIM) */ -/* */ -/*****************************************************************************/ -/******************* Bit definition for TIM_CR1 register *******************/ -#define TIM_CR1_CEN_Pos (0U) -#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ -#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f1xx - * @{ - */ - -#ifndef __STM32F1XX_H -#define __STM32F1XX_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32F1) -#define STM32F1 -#endif /* STM32F1 */ - -/* Uncomment the line below according to the target STM32L device used in your - application - */ - -#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \ - !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \ - !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC) - /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ - /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ - /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ - /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ - /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ - /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ - /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ - /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ - /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */ -#define STM32F103xB /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */ - /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ - /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ - /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ - /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ -#define USE_HAL_DRIVER -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number V4.2.0 - */ -#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ -#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ - |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32F1_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32F100xB) - #include "stm32f100xb.h" -#elif defined(STM32F100xE) - #include "stm32f100xe.h" -#elif defined(STM32F101x6) - #include "stm32f101x6.h" -#elif defined(STM32F101xB) - #include "stm32f101xb.h" -#elif defined(STM32F101xE) - #include "stm32f101xe.h" -#elif defined(STM32F101xG) - #include "stm32f101xg.h" -#elif defined(STM32F102x6) - #include "stm32f102x6.h" -#elif defined(STM32F102xB) - #include "stm32f102xb.h" -#elif defined(STM32F103x6) - #include "stm32f103x6.h" -#elif defined(STM32F103xB) - #include "stm32f103xb.h" -#elif defined(STM32F103xE) - #include "stm32f103xe.h" -#elif defined(STM32F103xG) - #include "stm32f103xg.h" -#elif defined(STM32F105xC) - #include "stm32f105xc.h" -#elif defined(STM32F107xC) - #include "stm32f107xc.h" -#else - #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32f1xx_hal.h" -#endif /* USE_HAL_DRIVER */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32F1xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_clock.c deleted file mode 100644 index 3aa2e4c37be..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_clock.c +++ /dev/null @@ -1,232 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI - * | (external 8 MHz clock) | (internal 8 MHz) - * | 2- PLL_HSE_XTAL | - * | (external 8 MHz xtal) | - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 72 | 64 - *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 72 | 64 - *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 36 | 32 - *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 72 | 64 - *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | NO | NO - *----------------------------------------------------------------------------- - ****************************************************************************** - */ - -#include "stm32f1xx.h" - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ -#define USE_PLL_HSE_EXTC (0) /* Use external clock */ -#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ - - -#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) -uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif - -uint8_t SetSysClock_PLL_HSI(void); - - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ - /* Set HSION bit */ - RCC->CR |= 0x00000001U; - - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ -#if !defined(STM32F105xC) && !defined(STM32F107xC) - RCC->CFGR &= 0xF8FF0000U; -#else - RCC->CFGR &= 0xF0FF0000U; -#endif /* STM32F105xC */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= 0xFEF6FFFFU; - - /* Reset HSEBYP bit */ - RCC->CR &= 0xFFFBFFFFU; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= 0xFF80FFFFU; - -#if defined(STM32F105xC) || defined(STM32F107xC) - /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= 0xEBFFFFFFU; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000U; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000U; -#elif defined(STM32F100xB) || defined(STM32F100xE) - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000U; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000U; -#else - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000U; -#endif /* STM32F105xC */ - -#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ -#endif - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif - -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -void SetSysClock(void) -{ - /* 1- Try to start with HSE and external clock */ -#if USE_PLL_HSE_EXTC != 0 - if (SetSysClock_PLL_HSE(1) == 0) -#endif - { - /* 2- If fail try to start with HSE and external xtal */ -#if USE_PLL_HSE_XTAL != 0 - if (SetSysClock_PLL_HSE(0) == 0) -#endif - { - /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) { - while(1) { - // [TODO] Put something here to tell the user that a problem occured... - } - } - } - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 72 MHz or 64 MHz -} - -#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable HSE oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ - } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ - } - RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9) - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz - - return 1; // OK -} -#endif - -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable HSI oscillator and activate PLL with HSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16) - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz - - return 1; // OK -} - diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_stm32f1xx.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_stm32f1xx.h deleted file mode 100644 index f2557fa9579..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_stm32f1xx.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f10x.h - * @author MCD Application Team - * @version V4.2.0 - * @date 31-March-2017 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F10X_H -#define __SYSTEM_STM32F10X_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F10x_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F10x_System_Exported_types - * @{ - */ - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F10X_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/us_ticker_data.h deleted file mode 100644 index 3bfb085eafe..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/us_ticker_data.h +++ /dev/null @@ -1,45 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __US_TICKER_DATA_H -#define __US_TICKER_DATA_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "stm32f1xx.h" -#include "stm32f1xx_ll_tim.h" -#include "cmsis_nvic.h" - -#define TIM_MST TIM4 -#define TIM_MST_IRQ TIM4_IRQn -#define TIM_MST_RCC __HAL_RCC_TIM4_CLK_ENABLE() -#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM4() - -#define TIM_MST_RESET_ON __HAL_RCC_TIM4_FORCE_RESET() -#define TIM_MST_RESET_OFF __HAL_RCC_TIM4_RELEASE_RESET() - -#define TIM_MST_BIT_WIDTH 16 // 16 or 32 - -#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) - - -#ifdef __cplusplus -} -#endif - -#endif // __US_TICKER_DATA_H - diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h deleted file mode 100644 index 5ddc595468a..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h +++ /dev/null @@ -1,63 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - IRQn_Type irq_n; - uint32_t irq_index; - uint32_t event; - PinName pin; -}; - -struct port_s { - PortName port; - uint32_t mask; - PinDirection direction; - __IO uint32_t *reg_in; - __IO uint32_t *reg_out; -}; - -#include "common_objects.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/ONBOARD_TELIT_HE910.cpp b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/ONBOARD_TELIT_HE910.cpp deleted file mode 100644 index 6a351744da6..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/ONBOARD_TELIT_HE910.cpp +++ /dev/null @@ -1,94 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if MBED_CONF_NSAPI_PRESENT - - -#include "gpio_api.h" -#include "platform/mbed_thread.h" -#include "PinNames.h" - -#include "drivers/BufferedSerial.h" -#include "ONBOARD_TELIT_HE910.h" -#include "ThisThread.h" -#include "CellularLog.h" - -using namespace mbed; - -ONBOARD_TELIT_HE910::ONBOARD_TELIT_HE910(FileHandle *fh) : TELIT_HE910(fh) -{ -} - -nsapi_error_t ONBOARD_TELIT_HE910::hard_power_on() -{ - //does nothing at the moment, TODO: MultiTech to add hardware initialization stuff if needed - return NSAPI_ERROR_OK; -} - -nsapi_error_t ONBOARD_TELIT_HE910::hard_power_off() -{ - //does nothing at the moment, TODO: MultiTech to add hardware de-initialization stuff if needed - return NSAPI_ERROR_OK; -} - -nsapi_error_t ONBOARD_TELIT_HE910::soft_power_on() -{ - /* keep the power line low for 200 milisecond */ - press_power_button(200); - /* give modem a little time to respond */ - thread_sleep_for(100); - // From Telit_xE910 Global form factor App note: It is mandatory to avoid sending data to the serial ports during the first 200ms of the module start-up. - rtos::ThisThread::sleep_for(200); - return NSAPI_ERROR_OK; -} - -nsapi_error_t ONBOARD_TELIT_HE910::soft_power_off() -{ - gpio_t gpio; - - gpio_init_out_ex(&gpio, MDMPWRON, 0); - /* keep the power line low for more than 10 seconds. - * If 3G_ON_OFF pin is kept low for more than a second, a controlled disconnect and shutdown takes - * place, Due to the network disconnect, shut-off can take up to 30 seconds. However, we wait for 10 - * seconds only */ - thread_sleep_for(10 * 1000); - return NSAPI_ERROR_OK; -} - -void ONBOARD_TELIT_HE910::press_power_button(int time_ms) -{ - gpio_t gpio; - - gpio_init_out_ex(&gpio, MDMPWRON, 1); - gpio_write(&gpio, 0); - thread_sleep_for(time_ms); - gpio_write(&gpio, 1); -} - -CellularDevice *CellularDevice::get_target_default_instance() -{ - static BufferedSerial serial(MDMTXD, MDMRXD, 115200); -#if DEVICE_SERIAL_FC - if (MDMRTS != NC && MDMCTS != NC) { - tr_debug("Modem flow control: RTS %d CTS %d", MDMRTS, MDMCTS); - serial.set_flow_control(SerialBase::RTSCTS, MDMRTS, MDMCTS); - } -#endif - static ONBOARD_TELIT_HE910 device(&serial); - return &device; -} - -#endif // MBED_CONF_NSAPI_PRESENT diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/ONBOARD_TELIT_HE910.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/ONBOARD_TELIT_HE910.h deleted file mode 100644 index cd38da6a8ff..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/ONBOARD_TELIT_HE910.h +++ /dev/null @@ -1,39 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ONBOARD_TELIT_HE910_ -#define ONBOARD_TELIT_HE910_ - -#include "TELIT_HE910.h" - -namespace mbed { - -class ONBOARD_TELIT_HE910 : public TELIT_HE910 { -public: - ONBOARD_TELIT_HE910(FileHandle *fh); - - virtual nsapi_error_t hard_power_on(); - virtual nsapi_error_t hard_power_off(); - virtual nsapi_error_t soft_power_on(); - virtual nsapi_error_t soft_power_off(); - -private: - void press_power_button(int time_ms); -}; - -} // namespace mbed - -#endif // ONBOARD_TELIT_HE910_ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralNames.h deleted file mode 100644 index c251b7a3114..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralNames.h +++ /dev/null @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE -} ADCName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_6 = (int)USART6_BASE -} UARTName; - -#define DEVICE_SPI_COUNT 5 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE, - SPI_4 = (int)SPI4_BASE, - SPI_5 = (int)SPI5_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE, - I2C_3 = (int)I2C3_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE, - PWM_5 = (int)TIM5_BASE, - PWM_9 = (int)TIM9_BASE, - PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE -} PWMName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralPins.c deleted file mode 100644 index 7c2b21786f6..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralPins.c +++ /dev/null @@ -1,212 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "PeripheralPins.h" - -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== - -//*** ADC *** - -const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 - {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 - {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 - {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 - {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 - {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 - {NC, NC, 0} -}; - -const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used - {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used - {NC, NC, 0} -}; - -//*** I2C *** - -const PinMap PinMap_I2C_SDA[] = { - {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, - {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, -// {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, // Warning: also on SCL - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO -// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, - {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO - {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM5 cannot be used because already used by the us_ticker -const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 -// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 -// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 - {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 -// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 -// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO -// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - - {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N -// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N -// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO - {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO - {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 -// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)}, // TIM10_CH1 - {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 -// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO - {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - - {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO - {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - - {NC, NC, 0} -}; - -//*** SERIAL *** - -const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -//*** SPI *** - -const PinMap PinMap_SPI_MOSI[] = { - {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO - {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO - {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, - {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, - {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO - {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, -// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, -// {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Warning: also on NSS - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, -// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, - {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, -// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, -// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, - {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Warning: also on SCLK -// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Warning: also on SCLK - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h deleted file mode 100644 index 42fa8e5fa16..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h +++ /dev/null @@ -1,247 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - // Not connected - NC = -1, - - PA_0 = 0x00, - PA_1 = 0x01, - PA_2 = 0x02, - PA_3 = 0x03, - PA_4 = 0x04, - PA_5 = 0x05, - PA_6 = 0x06, - PA_7 = 0x07, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - - PB_0 = 0x10, - PB_1 = 0x11, - PB_2 = 0x12, - PB_3 = 0x13, - PB_4 = 0x14, - PB_5 = 0x15, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_9 = 0x19, - PB_10 = 0x1A, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_14 = 0x1E, - PB_15 = 0x1F, - - PC_0 = 0x20, - PC_1 = 0x21, - PC_2 = 0x22, - PC_3 = 0x23, - PC_4 = 0x24, - PC_5 = 0x25, - PC_6 = 0x26, - PC_7 = 0x27, - PC_8 = 0x28, - PC_9 = 0x29, - PC_10 = 0x2A, - PC_11 = 0x2B, - PC_12 = 0x2C, - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, - - PD_2 = 0x32, - - PH_0 = 0x70, - PH_1 = 0x71, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, - - // Module pins - // Defined based on the external pin (40-pin connector) alternate function mapping (Page 15 of MTQ-H5-B01 device guide) - // Device guide used: S000628,Version1.4 - P_1 = PB_6, - P_2 = PA_14, - P_3 = PA_15, - P_4 = PB_4, - P_5 = NC, - P_6 = NC, - P_7 = NC, - P_8 = NC, - P_9 = PA_2, - P_10 = PA_7, - P_11 = PB_1, - P_12 = PA_1, - P_13 = NC, - P_14 = PB_5, - P_15 = PA_5, - P_16 = PB_8, - P_17 = PB_15, - P_18 = PC_2, - P_19 = PB_0, - P_20 = PC_0, - P_21 = PC_1, - P_22 = PC_4, - P_23 = PB_13, - P_24 = PC_9, - P_25 = PB_9, - P_26 = PA_6, - P_27 = PC_8, - P_28 = NC, - P_29 = PA_0, - P_30 = PA_9, - P_31 = PA_8, - P_32 = PA_3, - P_33 = NC, - P_34 = NC, - P_35 = NC, - P_36 = NC, - P_37 = NC, - P_38 = PB_3, - P_39 = PA_13, - P_40 = PB_7, - - // STDIO for console print -#ifdef MBED_CONF_TARGET_STDIO_UART_TX - STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, -#elif MBED_CONF_TARGET_USB_TX - STDIO_UART_TX = MBED_CONF_TARGET_USB_TX, -#else - STDIO_UART_TX = PB_6, -#endif - -#ifdef MBED_CONF_TARGET_STDIO_UART_RX - STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, -#elif MBED_CONF_TARGET_USB_RX - STDIO_UART_TX = MBED_CONF_TARGET_USB_RX, -#else - STDIO_UART_RX = PB_7, -#endif - - //DAPLink - USBTX = STDIO_UART_TX, - USBRX = STDIO_UART_RX, - SWDIO = PA_13, - SWCLK = PA_14, - - I2C1_SCL = PB_8, - I2C1_SDA = PB_9, - I2C3_SCL = PA_8, - I2C3_SDA = PC_9, - - I2C_SCL = I2C1_SCL, - I2C_SDA = I2C1_SDA, - - SPI1_MOSI = PB_5, - SPI1_MISO = PA_6, - SPI1_SCK = PA_5, - SPI2_MOSI = PB_15, - SPI2_MISO = PC_2, - SPI2_SCK = PB_13, - - SPI_MOSI = SPI1_MOSI, - SPI_MISO = SPI1_MISO, - SPI_SCK = SPI1_SCK, - SPI_CS1 = PA_3, //LCD CS - SPI_CS2 = PA_15, //SD Card CS - - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - SERIAL_RTS = PA_0, - SERIAL_CTS = PA_1, - SERIAL_DCD = PA_7, - SERIAL_DSR = PA_9, - SERIAL_DTR = PA_8, - SERIAL_RI = PB_1, - - WAKEUP = PA_0, - - // Generic signals namings - LED1 = PA_7, - LED2 = PC_4, - LED3 = PB_13, //MTB mapped to LINK_STATUS pin on module. - SW1 = PB_4, - GPIO1 = PC_8, - GPIO3 = PB_1, - AIN0 = PB_0, - AIN1 = PC_0, - AIN2 = PC_1, - - //Standardized button names - BUTTON1 = SW1, - - RADIO_TX = PC_7, - RADIO_RX = PC_6, - RADIO_RTS = PB_10, - RADIO_CTS = PB_12, - RADIO_DCD = NC, - RADIO_DSR = NC, - RADIO_DTR = NC, - RADIO_RI = NC, - MDMPWRON = PC_13, // 3G_ONOFF DragonFly Design Guide, Page No. 16 - MDMTXD = RADIO_TX, // Transmit Data - MDMRXD = RADIO_RX, // Receive Data - MDMRTS = RADIO_RTS, // Request to Send - MDMCTS = RADIO_CTS, // Clear to Send - MDMDCD = RADIO_DCD, // Data Carrier Detect - MDMDSR = RADIO_DSR, // Data Set Ready - MDMDTR = RADIO_DTR, // Data Terminal Ready - MDMRI = RADIO_RI, // Ring Indicator - -} PinName; - -#define ACTIVE_HIGH_POLARITY 1 -#define ACTIVE_LOW_POLARITY 0 - -#define MDM_PIN_POLARITY ACTIVE_HIGH_POLARITY - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S deleted file mode 100644 index 3610462185e..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S +++ /dev/null @@ -1,343 +0,0 @@ -;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** -;* File Name : startup_stm32f411xe.s -;* Author : MCD Application Team -;* Description : STM32F411xExx devices vector table for MDK-ARM_MICRO toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD 0 ; Reserved - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FPU_IRQHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -DMA1_Stream7_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -FPU_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_ARM_MICRO/stm32f411re.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_ARM_MICRO/stm32f411re.sct deleted file mode 100644 index 41289836449..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_ARM_MICRO/stm32f411re.sct +++ /dev/null @@ -1,77 +0,0 @@ -#! armcc -E -; Scatter-Loading Description File -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2014, STMicroelectronics -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; FIRST 64 KB FLASH FOR BOOTLOADER -; REST 448 KB FLASH FOR APPLICATION -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08010000 -#endif - -; STM32F411RE: 512 KB FLASH (0x80000) -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x70000 -#endif - -; 128 KB SRAM (0x20000) -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x20000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x20000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM -#define VECTOR_SIZE 0x198 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S deleted file mode 100644 index acee724ddff..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S +++ /dev/null @@ -1,343 +0,0 @@ -;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** -;* File Name : startup_stm32f411xe.s -;* Author : MCD Application Team -;* Description : STM32F411xExx devices vector table for MDK-ARM_STD toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD 0 ; Reserved - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FPU_IRQHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -DMA1_Stream7_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -FPU_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_ARM_STD/stm32f411re.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_ARM_STD/stm32f411re.sct deleted file mode 100644 index 6bfeeaeae2d..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_ARM_STD/stm32f411re.sct +++ /dev/null @@ -1,74 +0,0 @@ -#! armcc -E -; Scatter-Loading Description File -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2014, STMicroelectronics -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x80000 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -#define MBED_RAM_START 0x20000000 -#define MBED_RAM_SIZE 0x20000 -#define MBED_VECTTABLE_RAM_START (MBED_RAM_START) -#define MBED_VECTTABLE_RAM_SIZE 0x198 -#define MBED_CRASH_REPORT_RAM_START (MBED_VECTTABLE_RAM_START + MBED_VECTTABLE_RAM_SIZE) -#define MBED_CRASH_REPORT_RAM_SIZE 0x100 -#define MBED_RAM0_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE) -#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE) - -; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000) -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data - } - - ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM - RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE-Stack_Size) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack - } -} - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld deleted file mode 100644 index 2e34f3f3d4b..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld +++ /dev/null @@ -1,160 +0,0 @@ -/* Linker script for STM32F411 */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Linker script to configure memory regions. */ -MEMORY -{ - /* First 64kB of flash reserved for bootloader */ - /* Other 448kB for application */ - FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 448K -/* CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K */ - RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S deleted file mode 100644 index b7f10ce5fc5..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S +++ /dev/null @@ -1,297 +0,0 @@ -/* File: startup_STM32F40x.S - * Purpose: startup file for Cortex-M4 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.4 - * Date: 09 July 2012 - * - * Copyright (c) 2011, 2012, ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the ARM Limited nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - .syntax unified - .arch armv7-m - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0xc00 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x400 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts */ - .long WWDG_IRQHandler /* Window WatchDog */ - .long PVD_IRQHandler /* PVD through EXTI Line detection */ - .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .long FLASH_IRQHandler /* FLASH */ - .long RCC_IRQHandler /* RCC */ - .long EXTI0_IRQHandler /* EXTI Line0 */ - .long EXTI1_IRQHandler /* EXTI Line1 */ - .long EXTI2_IRQHandler /* EXTI Line2 */ - .long EXTI3_IRQHandler /* EXTI Line3 */ - .long EXTI4_IRQHandler /* EXTI Line4 */ - .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long EXTI9_5_IRQHandler /* External Line[9:5]s */ - .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .long TIM2_IRQHandler /* TIM2 */ - .long TIM3_IRQHandler /* TIM3 */ - .long TIM4_IRQHandler /* TIM4 */ - .long I2C1_EV_IRQHandler /* I2C1 Event */ - .long I2C1_ER_IRQHandler /* I2C1 Error */ - .long I2C2_EV_IRQHandler /* I2C2 Event */ - .long I2C2_ER_IRQHandler /* I2C2 Error */ - .long SPI1_IRQHandler /* SPI1 */ - .long SPI2_IRQHandler /* SPI2 */ - .long USART1_IRQHandler /* USART1 */ - .long USART2_IRQHandler /* USART2 */ - .long 0 /* Reserved */ - .long EXTI15_10_IRQHandler /* External Line[15:10]s */ - .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .long 0 /* Reserved */ - .long SDIO_IRQHandler /* SDIO */ - .long TIM5_IRQHandler /* TIM5 */ - .long SPI3_IRQHandler /* SPI3 */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long OTG_FS_IRQHandler /* USB OTG FS */ - .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .long USART6_IRQHandler /* USART6 */ - .long I2C3_EV_IRQHandler /* I2C3 event */ - .long I2C3_ER_IRQHandler /* I2C3 error */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long FPU_IRQHandler /* FPU */ - .long SPI4_IRQHandler /* SPI4 */ - .long SPI5_IRQHandler /* SPI5 */ - - .size __isr_vector, . - __isr_vector - - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 - - ldr r0, =SystemInit - blx r0 - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler MemManage_Handler - def_default_handler BusFault_Handler - def_default_handler UsageFault_Handler - def_default_handler SVC_Handler - def_default_handler DebugMon_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_default_handler WWDG_IRQHandler - def_irq_default_handler PVD_IRQHandler - def_irq_default_handler TAMP_STAMP_IRQHandler - def_irq_default_handler RTC_WKUP_IRQHandler - def_irq_default_handler FLASH_IRQHandler - def_irq_default_handler RCC_IRQHandler - def_irq_default_handler EXTI0_IRQHandler - def_irq_default_handler EXTI1_IRQHandler - def_irq_default_handler EXTI2_IRQHandler - def_irq_default_handler EXTI3_IRQHandler - def_irq_default_handler EXTI4_IRQHandler - def_irq_default_handler DMA1_Stream0_IRQHandler - def_irq_default_handler DMA1_Stream1_IRQHandler - def_irq_default_handler DMA1_Stream2_IRQHandler - def_irq_default_handler DMA1_Stream3_IRQHandler - def_irq_default_handler DMA1_Stream4_IRQHandler - def_irq_default_handler DMA1_Stream5_IRQHandler - def_irq_default_handler DMA1_Stream6_IRQHandler - def_irq_default_handler ADC_IRQHandler - def_irq_default_handler EXTI9_5_IRQHandler - def_irq_default_handler TIM1_BRK_TIM9_IRQHandler - def_irq_default_handler TIM1_UP_TIM10_IRQHandler - def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler - def_irq_default_handler TIM1_CC_IRQHandler - def_irq_default_handler TIM2_IRQHandler - def_irq_default_handler TIM3_IRQHandler - def_irq_default_handler TIM4_IRQHandler - def_irq_default_handler I2C1_EV_IRQHandler - def_irq_default_handler I2C1_ER_IRQHandler - def_irq_default_handler I2C2_EV_IRQHandler - def_irq_default_handler I2C2_ER_IRQHandler - def_irq_default_handler SPI1_IRQHandler - def_irq_default_handler SPI2_IRQHandler - def_irq_default_handler USART1_IRQHandler - def_irq_default_handler USART2_IRQHandler - def_irq_default_handler EXTI15_10_IRQHandler - def_irq_default_handler RTC_Alarm_IRQHandler - def_irq_default_handler OTG_FS_WKUP_IRQHandler - def_irq_default_handler DMA1_Stream7_IRQHandler - def_irq_default_handler SDIO_IRQHandler - def_irq_default_handler TIM5_IRQHandler - def_irq_default_handler SPI3_IRQHandler - def_irq_default_handler DMA2_Stream0_IRQHandler - def_irq_default_handler DMA2_Stream1_IRQHandler - def_irq_default_handler DMA2_Stream2_IRQHandler - def_irq_default_handler DMA2_Stream3_IRQHandler - def_irq_default_handler DMA2_Stream4_IRQHandler - def_irq_default_handler OTG_FS_IRQHandler - def_irq_default_handler DMA2_Stream5_IRQHandler - def_irq_default_handler DMA2_Stream6_IRQHandler - def_irq_default_handler DMA2_Stream7_IRQHandler - def_irq_default_handler USART6_IRQHandler - def_irq_default_handler I2C3_EV_IRQHandler - def_irq_default_handler I2C3_ER_IRQHandler - def_irq_default_handler FPU_IRQHandler - def_irq_default_handler SPI4_IRQHandler - def_irq_default_handler SPI5_IRQHandler - def_irq_default_handler DEF_IRQHandler - - .end diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_IAR/startup_stm32f411xe.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_IAR/startup_stm32f411xe.S deleted file mode 100644 index b56c8f521d1..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_IAR/startup_stm32f411xe.S +++ /dev/null @@ -1,521 +0,0 @@ -;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** -;* File Name : startup_stm32f411xe.s -;* Author : MCD Application Team -;* Description : STM32F411xExx devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD 0 ; Reserved - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FPU_IRQHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TAMP_STAMP_IRQHandler - B TAMP_STAMP_IRQHandler - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream0_IRQHandler - B DMA1_Stream0_IRQHandler - - PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream1_IRQHandler - B DMA1_Stream1_IRQHandler - - PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream2_IRQHandler - B DMA1_Stream2_IRQHandler - - PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream3_IRQHandler - B DMA1_Stream3_IRQHandler - - PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream4_IRQHandler - B DMA1_Stream4_IRQHandler - - PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream5_IRQHandler - B DMA1_Stream5_IRQHandler - - PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream6_IRQHandler - B DMA1_Stream6_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_BRK_TIM9_IRQHandler - B TIM1_BRK_TIM9_IRQHandler - - PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_UP_TIM10_IRQHandler - B TIM1_UP_TIM10_IRQHandler - - PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_TRG_COM_TIM11_IRQHandler - B TIM1_TRG_COM_TIM11_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_WKUP_IRQHandler - B OTG_FS_WKUP_IRQHandler - - PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream7_IRQHandler - B DMA1_Stream7_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK SPI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI3_IRQHandler - B SPI3_IRQHandler - - PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream0_IRQHandler - B DMA2_Stream0_IRQHandler - - PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream1_IRQHandler - B DMA2_Stream1_IRQHandler - - PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream2_IRQHandler - B DMA2_Stream2_IRQHandler - - PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream3_IRQHandler - B DMA2_Stream3_IRQHandler - - PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream4_IRQHandler - B DMA2_Stream4_IRQHandler - - PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler - - PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream5_IRQHandler - B DMA2_Stream5_IRQHandler - - PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream6_IRQHandler - B DMA2_Stream6_IRQHandler - - PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream7_IRQHandler - B DMA2_Stream7_IRQHandler - - PUBWEAK USART6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART6_IRQHandler - B USART6_IRQHandler - - PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_EV_IRQHandler - B I2C3_EV_IRQHandler - - PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_ER_IRQHandler - B I2C3_ER_IRQHandler - - PUBWEAK FPU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPU_IRQHandler - B FPU_IRQHandler - - PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI4_IRQHandler - B SPI4_IRQHandler - - PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI5_IRQHandler - B SPI5_IRQHandler - - END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_IAR/stm32f411xe.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_IAR/stm32f411xe.icf deleted file mode 100644 index bf12247ac10..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/TOOLCHAIN_IAR/stm32f411xe.icf +++ /dev/null @@ -1,33 +0,0 @@ -/* [ROM = 512kb = 0x80000] */ -define symbol __intvec_start__ = 0x08010000; -define symbol __region_ROM_start__ = 0x08010000; -define symbol __region_ROM_end__ = 0x0807FFFF; - -/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */ -define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x20000197; /* Aligned on 8 bytes */ -define symbol __region_RAM_start__ = 0x20000198; -define symbol __region_RAM_end__ = 0x2001FFFF; - -/* Memory regions */ -define memory mem with size = 4G; -define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; -define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; - -/* Stack and Heap */ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __size_heap__ = 0x10000; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block STACKHEAP with fixed order { block HEAP, block CSTACK }; - -initialize by copy with packing = zeros { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, block STACKHEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/cmsis_nvic.h deleted file mode 100644 index e44a1ce9f61..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/cmsis_nvic.h +++ /dev/null @@ -1,41 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -// STM32F411RE -// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F -// MCU Peripherals: 86 vectors = 344 bytes from 0x40 to 0x197 -// Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM -#define NVIC_NUM_VECTORS 102 -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/objects.h deleted file mode 100644 index 16467b7c876..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/objects.h +++ /dev/null @@ -1,63 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - IRQn_Type irq_n; - uint32_t irq_index; - uint32_t event; - PinName pin; -}; - -struct port_s { - PortName port; - uint32_t mask; - PinDirection direction; - __IO uint32_t *reg_in; - __IO uint32_t *reg_out; -}; - -#include "common_objects.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/system_clock.c deleted file mode 100644 index 6a43c3ff975..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/system_clock.c +++ /dev/null @@ -1,248 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI - * | (external 8 MHz clock) | (internal 16 MHz) - * | 2- PLL_HSE_XTAL | - * | (external 8 MHz xtal) | - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 100 | 100 - *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 100 | 100 - *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 50 | 50 - *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 100 | 100 - *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | NO | NO - *----------------------------------------------------------------------------- -**/ - -#include "stm32f4xx.h" -#include "mbed_debug.h" - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ -#define USE_PLL_HSE_EXTC (0) /* Use external clock */ -#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ - -#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) -uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif - -uint8_t SetSysClock_PLL_HSI(void); - -/** - * @brief Setup the microcontroller system - * Initialize the FPU setting, vector table location and External memory - * configuration. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - -#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ - -#if defined(__ICCARM__) -#pragma section=".intvec" -#define FLASH_VTOR_BASE ((uint32_t)__section_begin(".intvec")) -#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - extern uint32_t Load$$LR$$LR_IROM1$$Base[]; -#define FLASH_VTOR_BASE ((uint32_t)Load$$LR$$LR_IROM1$$Base) -#elif defined(__GNUC__) - extern uint32_t g_pfnVectors[]; -#define FLASH_VTOR_BASE ((uint32_t)g_pfnVectors) -#else -#error "Flash vector address not set for this toolchain" -#endif - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_VTOR_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif - -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -void SetSysClock(void) -{ - /* 1- Try to start with HSE and external clock */ -#if USE_PLL_HSE_EXTC != 0 - if (SetSysClock_PLL_HSE(1) == 0) -#endif - { - /* 2- If fail try to start with HSE and external xtal */ -#if USE_PLL_HSE_XTAL != 0 - if (SetSysClock_PLL_HSE(0) == 0) -#endif - { - /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) { - while (1) { - // [TODO] Put something here to tell the user that a problem occured... - } - } - } - } - - /* Output clock on MCO2 pin(PC9) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz -} - -#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); - - /* Enable HSE oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ - } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ - } - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) - //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) - RCC_OscInitStruct.PLL.PLLM = 13; // VCO input clock = 2 MHz (8 MHz / 4) - RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 400 MHz (2 MHz * 200) - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) - RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - - //if (bypass == 0) - // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal - //else - // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock - - return 1; // OK -} -#endif - -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); - - /* Enable HSI oscillator and activate PLL with HSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) - //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) - RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) - RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) - RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz - - return 1; // OK -} - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/us_ticker_data.h deleted file mode 100644 index 176c61cb481..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/us_ticker_data.h +++ /dev/null @@ -1,45 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __US_TICKER_DATA_H -#define __US_TICKER_DATA_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "stm32f4xx.h" -#include "stm32f4xx_ll_tim.h" -#include "cmsis_nvic.h" - -#define TIM_MST TIM5 -#define TIM_MST_IRQ TIM5_IRQn -#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() -#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() - -#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() -#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() - -#define TIM_MST_BIT_WIDTH 32 // 16 or 32 - -#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) - - -#ifdef __cplusplus -} -#endif - -#endif // __US_TICKER_DATA_H - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_OLIMEX_STM32E407_F407ZG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_OLIMEX_STM32E407_F407ZG/PeripheralNames.h deleted file mode 100644 index c6aba58973a..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_OLIMEX_STM32E407_F407ZG/PeripheralNames.h +++ /dev/null @@ -1,101 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE, - ADC_2 = (int)ADC2_BASE, - ADC_3 = (int)ADC3_BASE -} ADCName; - -typedef enum { - DAC_0 = 0, - DAC_1 -} DACName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE, - UART_4 = (int)UART4_BASE, - UART_5 = (int)UART5_BASE, - UART_6 = (int)USART6_BASE, -} UARTName; - -#define DEVICE_SPI_COUNT 3 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE, - I2C_3 = (int)I2C3_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE, - PWM_5 = (int)TIM5_BASE, - PWM_8 = (int)TIM8_BASE, - PWM_9 = (int)TIM9_BASE, - PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE, - PWM_12 = (int)TIM12_BASE, - PWM_13 = (int)TIM13_BASE, - PWM_14 = (int)TIM14_BASE -} PWMName; - -typedef enum { - CAN_1 = (int)CAN1_BASE, - CAN_2 = (int)CAN2_BASE -} CANName; - -typedef enum { - USB_FS = (int)USB_OTG_FS_PERIPH_BASE, - USB_HS = (int)USB_OTG_HS_PERIPH_BASE -} USBName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_OLIMEX_STM32E407_F407ZG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_OLIMEX_STM32E407_F407ZG/PeripheralPins.c deleted file mode 100644 index 3b0c461fd8e..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_OLIMEX_STM32E407_F407ZG/PeripheralPins.c +++ /dev/null @@ -1,379 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2019, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - * - * Automatically generated from STM32F407Z(E-G)Tx.xml - */ - -#include "PeripheralPins.h" -#include "mbed_toolchain.h" - -//============================================================================== -// Notes -// -// - The pins mentioned Px_y_ALTz are alternative possibilities which use other -// HW peripheral instances. You can use them the same way as any other "normal" -// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board -// pinout image on mbed.org. -// -// - The pins which are connected to other components present on the board have -// the comment "Connected to xxx". The pin function may not work properly in this -// case. These pins may not be displayed on the board pinout image on mbed.org. -// Please read the board reference manual and schematic for more information. -// -// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented -// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. -// -//============================================================================== - - -//*** ADC *** - -MBED_WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 - {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 - {PA_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 - {PA_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 - {PA_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 - {PA_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 - {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 - {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 - {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 - {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 - {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 - {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 - {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 - {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 - {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 - {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 - {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 - {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11 - {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 - {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 - {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 - {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 - {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13 - {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 - {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 - {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 - {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 - {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9 - {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14 - {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15 - {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 - {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 - {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 - {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 - {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - {NC, NC, 0} -}; - -// !!! SECTION TO BE CHECKED WITH DEVICE REFERENCE MANUAL -MBED_WEAK const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, - {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, - {NC, NC, 0} -}; - -//*** DAC *** - -MBED_WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 - {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 - {NC, NC, 0} -}; - -//*** I2C *** - -MBED_WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM cannot be used because already used by the us_ticker -// You have to comment all PWM using TIM_MST defined in hal_tick.h file -// or update python script (check TIM_MST_LIST) and re-run it -MBED_WEAK const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_0_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_1_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PA_2_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PA_2_ALT1, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 - {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PA_3_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PA_3_ALT1, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 - {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 - {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 - {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {NC, NC, 0} -}; - -//*** SERIAL *** - -MBED_WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -//*** SPI *** - -MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; - -//*** CAN *** - -MBED_WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_CAN_TD[] = { - {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {NC, NC, 0} -}; - -//*** USBDEVICE *** - -MBED_WEAK const PinMap PinMap_USB_FS[] = { -// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF - {PA_9, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS - {PA_10, USB_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_ID - {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DM - {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DP - {NC, NC, 0} -}; - -//*** USBDEVICE *** - -MBED_WEAK const PinMap PinMap_USB_HS[] = { -#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS) -// {PA_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_SOF - {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_ID - {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS - {PB_14, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DM - {PB_15, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DP -#else /* MBED_CONF_TARGET_USB_SPEED */ - {PA_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D0 - {PA_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_CK - {PB_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D1 - {PB_1, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D2 - {PB_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D7 - {PB_10, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D3 - {PB_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D4 - {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D5 - {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D6 - {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_STP - {PC_2, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR - {PC_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT -#endif /* MBED_CONF_TARGET_USB_SPEED */ - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_OLIMEX_STM32E407_F407ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_OLIMEX_STM32E407_F407ZG/PinNames.h deleted file mode 100644 index f6f36d714d4..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_OLIMEX_STM32E407_F407ZG/PinNames.h +++ /dev/null @@ -1,379 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2019, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - * - * Automatically generated from STM32F407Z(E-G)Tx.xml - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ALT0 = 0x100, - ALT1 = 0x200, - ALT2 = 0x300, - ALT3 = 0x400 -} ALTx; - -typedef enum { - // Not connected - NC = (int)0xFFFFFFFF, - - PA_0 = 0x00, - PA_0_ALT0 = PA_0 | ALT0, - PA_0_ALT1 = PA_0 | ALT1, - PA_1 = 0x01, - PA_1_ALT0 = PA_1 | ALT0, - PA_1_ALT1 = PA_1 | ALT1, - PA_2 = 0x02, - PA_2_ALT0 = PA_2 | ALT0, - PA_2_ALT1 = PA_2 | ALT1, - PA_3 = 0x03, - PA_3_ALT0 = PA_3 | ALT0, - PA_3_ALT1 = PA_3 | ALT1, - PA_4 = 0x04, - PA_4_ALT0 = PA_4 | ALT0, - PA_5 = 0x05, - PA_5_ALT0 = PA_5 | ALT0, - PA_6 = 0x06, - PA_6_ALT0 = PA_6 | ALT0, - PA_7 = 0x07, - PA_7_ALT0 = PA_7 | ALT0, - PA_7_ALT1 = PA_7 | ALT1, - PA_7_ALT2 = PA_7 | ALT2, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - PA_15_ALT0 = PA_15 | ALT0, - - PB_0 = 0x10, - PB_0_ALT0 = PB_0 | ALT0, - PB_0_ALT1 = PB_0 | ALT1, - PB_1 = 0x11, - PB_1_ALT0 = PB_1 | ALT0, - PB_1_ALT1 = PB_1 | ALT1, - PB_2 = 0x12, - PB_3 = 0x13, - PB_3_ALT0 = PB_3 | ALT0, - PB_4 = 0x14, - PB_4_ALT0 = PB_4 | ALT0, - PB_4_ALT1 = PB_4 | ALT1, - PB_5 = 0x15, - PB_5_ALT0 = PB_5 | ALT0, - PB_5_ALT1 = PB_5 | ALT1, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_8_ALT0 = PB_8 | ALT0, - PB_8_ALT1 = PB_8 | ALT1, - PB_9 = 0x19, - PB_9_ALT0 = PB_9 | ALT0, - PB_9_ALT1 = PB_9 | ALT1, - PB_10 = 0x1A, - PB_11 = 0x1B, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_14 = 0x1E, - PB_14_ALT0 = PB_14 | ALT0, - PB_14_ALT1 = PB_14 | ALT1, - PB_15 = 0x1F, - PB_15_ALT0 = PB_15 | ALT0, - PB_15_ALT1 = PB_15 | ALT1, - - PC_0 = 0x20, - PC_0_ALT0 = PC_0 | ALT0, - PC_0_ALT1 = PC_0 | ALT1, - PC_1 = 0x21, - PC_1_ALT0 = PC_1 | ALT0, - PC_1_ALT1 = PC_1 | ALT1, - PC_2 = 0x22, - PC_2_ALT0 = PC_2 | ALT0, - PC_2_ALT1 = PC_2 | ALT1, - PC_3 = 0x23, - PC_3_ALT0 = PC_3 | ALT0, - PC_3_ALT1 = PC_3 | ALT1, - PC_4 = 0x24, - PC_4_ALT0 = PC_4 | ALT0, - PC_5 = 0x25, - PC_5_ALT0 = PC_5 | ALT0, - PC_6 = 0x26, - PC_6_ALT0 = PC_6 | ALT0, - PC_7 = 0x27, - PC_7_ALT0 = PC_7 | ALT0, - PC_8 = 0x28, - PC_8_ALT0 = PC_8 | ALT0, - PC_9 = 0x29, - PC_9_ALT0 = PC_9 | ALT0, - PC_10 = 0x2A, - PC_10_ALT0 = PC_10 | ALT0, - PC_11 = 0x2B, - PC_11_ALT0 = PC_11 | ALT0, - PC_12 = 0x2C, - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, - - PD_0 = 0x30, - PD_1 = 0x31, - PD_2 = 0x32, - PD_3 = 0x33, - PD_4 = 0x34, - PD_5 = 0x35, - PD_6 = 0x36, - PD_7 = 0x37, - PD_8 = 0x38, - PD_9 = 0x39, - PD_10 = 0x3A, - PD_11 = 0x3B, - PD_12 = 0x3C, - PD_13 = 0x3D, - PD_14 = 0x3E, - PD_15 = 0x3F, - - PE_0 = 0x40, - PE_1 = 0x41, - PE_2 = 0x42, - PE_3 = 0x43, - PE_4 = 0x44, - PE_5 = 0x45, - PE_6 = 0x46, - PE_7 = 0x47, - PE_8 = 0x48, - PE_9 = 0x49, - PE_10 = 0x4A, - PE_11 = 0x4B, - PE_12 = 0x4C, - PE_13 = 0x4D, - PE_14 = 0x4E, - PE_15 = 0x4F, - - PF_0 = 0x50, - PF_1 = 0x51, - PF_2 = 0x52, - PF_3 = 0x53, - PF_4 = 0x54, - PF_5 = 0x55, - PF_6 = 0x56, - PF_7 = 0x57, - PF_8 = 0x58, - PF_9 = 0x59, - PF_10 = 0x5A, - PF_11 = 0x5B, - PF_12 = 0x5C, - PF_13 = 0x5D, - PF_14 = 0x5E, - PF_15 = 0x5F, - - PG_0 = 0x60, - PG_1 = 0x61, - PG_2 = 0x62, - PG_3 = 0x63, - PG_4 = 0x64, - PG_5 = 0x65, - PG_6 = 0x66, - PG_7 = 0x67, - PG_8 = 0x68, - PG_9 = 0x69, - PG_10 = 0x6A, - PG_11 = 0x6B, - PG_12 = 0x6C, - PG_13 = 0x6D, - PG_14 = 0x6E, - PG_15 = 0x6F, - - PH_0 = 0x70, - PH_1 = 0x71, - PH_2 = 0x72, - PH_3 = 0x73, - PH_4 = 0x74, - PH_5 = 0x75, - PH_6 = 0x76, - PH_7 = 0x77, - PH_8 = 0x78, - PH_9 = 0x79, - PH_10 = 0x7A, - PH_11 = 0x7B, - PH_12 = 0x7C, - PH_13 = 0x7D, - PH_14 = 0x7E, - PH_15 = 0x7F, - - PI_0 = 0x80, - PI_1 = 0x81, - PI_2 = 0x82, - PI_3 = 0x83, - PI_4 = 0x84, - PI_5 = 0x85, - PI_6 = 0x86, - PI_7 = 0x87, - PI_8 = 0x88, - PI_9 = 0x89, - PI_10 = 0x8A, - PI_11 = 0x8B, - PI_12 = 0x8C, - PI_13 = 0x8D, - PI_14 = 0x8E, - PI_15 = 0x8F, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, - - // STDIO for console print -#ifdef MBED_CONF_TARGET_STDIO_UART_TX - STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, -#else - STDIO_UART_TX = PB_10, -#endif -#ifdef MBED_CONF_TARGET_STDIO_UART_RX - STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, -#else - STDIO_UART_RX = PB_11, -#endif - - // Generic signals namings - USER_BUTTON = PA_0, - // Standardized button names - BUTTON1 = USER_BUTTON, - SERIAL_TX = STDIO_UART_TX, /* USART2 */ - SERIAL_RX = STDIO_UART_RX, - USBTX = STDIO_UART_TX, /* USART2 */ - USBRX = STDIO_UART_RX, - I2C_SCL = PB_8, /* I2C1 */ - I2C_SDA = PB_9, - SPI_MOSI = PA_7, - SPI_MISO = PA_6, - SPI_SCK = PA_5, - SPI_CS = PB_6, - PWM_OUT = PB_3, - - - LED1 = PC_13, - LED2 = NC, - LED3 = NC, - LED4 = NC, - LED5 = NC, - LED6 = NC, - WAKEUP_BUTTON = PA_0, - - USB_OTG_FS_VBUSON = PB_0, - USB_OTG_FS_FAULT = PB_1, - USB_OTG_HS_VBUSON = PA_8, - USB_OTG_HS_FAULT = PF_11, - - /**** USB FS pins ****/ - USB_OTG_FS_DM = PA_11, - USB_OTG_FS_DP = PA_12, - USB_OTG_FS_ID = PA_10, - USB_OTG_FS_SOF = PA_8, - USB_OTG_FS_VBUS = PA_9, - - /**** USB HS pins ****/ - USB_OTG_HS_DM = PB_14, - USB_OTG_HS_DP = PB_15, - USB_OTG_HS_ID = PB_12, - USB_OTG_HS_SOF = PA_4, - USB_OTG_HS_ULPI_CK = PA_5, - USB_OTG_HS_ULPI_D0 = PA_3, - USB_OTG_HS_ULPI_D1 = PB_0, - USB_OTG_HS_ULPI_D2 = PB_1, - USB_OTG_HS_ULPI_D3 = PB_10, - USB_OTG_HS_ULPI_D4 = PB_11, - USB_OTG_HS_ULPI_D5 = PB_12, - USB_OTG_HS_ULPI_D6 = PB_13, - USB_OTG_HS_ULPI_D7 = PB_5, - USB_OTG_HS_ULPI_DIR = PC_2, - USB_OTG_HS_ULPI_NXT = PC_3, - USB_OTG_HS_ULPI_STP = PC_0, - USB_OTG_HS_VBUS = PB_13, - - /**** ETHERNET pins ****/ - ETH_COL = PA_3, - ETH_CRS = PA_0, - ETH_CRS_DV = PA_7, - ETH_MDC = PC_1, - ETH_MDIO = PA_2, - ETH_PPS_OUT = PG_8, - ETH_PPS_OUT_ALT0 = PB_5, - ETH_REF_CLK = PA_1, - ETH_RXD0 = PC_4, - ETH_RXD1 = PC_5, - ETH_RXD2 = PB_0, - ETH_RXD3 = PB_1, - ETH_RX_CLK = PA_1, - ETH_RX_DV = PA_7, - ETH_RX_ER = PB_10, - ETH_TXD0 = PB_12, - ETH_TXD0_ALT0 = PG_13, - ETH_TXD1 = PB_13, - ETH_TXD1_ALT0 = PG_14, - ETH_TXD2 = PC_2, - ETH_TXD3 = PE_2, - ETH_TXD3_ALT0 = PB_8, - ETH_TX_CLK = PC_3, - ETH_TX_EN = PB_11, - ETH_TX_EN_ALT0 = PG_11, - - /**** OSCILLATOR pins ****/ - RCC_OSC32_IN = PC_14, - RCC_OSC32_OUT = PC_15, - RCC_OSC_IN = PH_0, - RCC_OSC_OUT = PH_1, - - /**** DEBUG pins ****/ - SYS_JTCK_SWCLK = PA_14, - SYS_JTDI = PA_15, - SYS_JTDO_SWO = PB_3, - SYS_JTMS_SWDIO = PA_13, - SYS_JTRST = PB_4, - SYS_TRACECLK = PE_2, - SYS_TRACED0 = PE_3, - SYS_TRACED1 = PE_4, - SYS_TRACED2 = PE_5, - SYS_TRACED3 = PE_6, - SYS_WKUP = PA_0 -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_OLIMEX_STM32E407_F407ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_OLIMEX_STM32E407_F407ZG/system_clock.c deleted file mode 100644 index 5870e2266e7..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_OLIMEX_STM32E407_F407ZG/system_clock.c +++ /dev/null @@ -1,187 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) - * | 3- USE_PLL_HSI (internal 16 MHz) - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 168 - * AHBCLK (MHz) | 168 - * APB1CLK (MHz) | 42 - * APB2CLK (MHz) | 84 - * USB capable | YES - *----------------------------------------------------------------------------- -**/ - -#include "stm32f4xx.h" -#include "mbed_error.h" - - -// clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) -#define USE_PLL_HSI 0x2 // Use HSI internal clock - - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -uint8_t SetSysClock_PLL_HSI(void); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ - - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -void SetSysClock(void) -{ -#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) - /* 1- Try to start with HSE and external clock */ - if (SetSysClock_PLL_HSE(1) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) - /* 2- If fail try to start with HSE and external xtal */ - if (SetSysClock_PLL_HSE(0) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSI) - /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) -#endif - { - { - error("SetSysClock failed\n"); - } - } - } - } - - /* Output clock on MCO2 pin(PC9) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz -} - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); - - /* Enable HSE oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ - } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ - } - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 12; // VCO input clock = 1 MHz (12 MHz / 12) - RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336) - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 168 MHz (336 MHz / 2) - RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 168 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz (SPI1 clock...) - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - /* - if (bypass == 0) - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - else - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz - */ - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); - - /* Enable HSI oscillator and activate PLL with HSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) - RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336) - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 168 MHz (336 MHz / 2) - RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 168 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PeripheralNames.h deleted file mode 100644 index 39e63b8b25d..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PeripheralNames.h +++ /dev/null @@ -1,83 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE -} ADCName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_6 = (int)USART6_BASE -} UARTName; - -#define STDIO_UART_TX PB_6 -#define STDIO_UART_RX PB_7 -#define STDIO_UART UART_1 - -#define DEVICE_SPI_COUNT 5 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE, - SPI_4 = (int)SPI4_BASE, - SPI_5 = (int)SPI5_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE, - I2C_3 = (int)I2C3_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE, - PWM_5 = (int)TIM5_BASE, - PWM_9 = (int)TIM9_BASE, - PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE -} PWMName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PeripheralPins.c deleted file mode 100644 index 15b94ee212c..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PeripheralPins.c +++ /dev/null @@ -1,224 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "PeripheralPins.h" - -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== - -//*** ADC *** - -const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 -// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // SERIAL_TX -// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // SERIAL_RX -// {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // SPI_CS -// {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // SPI_CLK -// {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // SPI_MISO -// {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // SPI_MOSI -// {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // SPI_CLK -// {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 // SPI_CS -// {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Push SW 3 -// {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Push SW 4 -// {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 // Slide SW 1 -// {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 // Slide SW 2 -// {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // LED-4 -// {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // Display LED - {NC, NC, 0} -}; - -const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used - {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used - {NC, NC, 0} -}; - -//*** I2C *** - -const PinMap PinMap_I2C_SDA[] = { - {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, -// {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, -// {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, -// {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, // Warning: also on SCL - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, -// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, - {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, -// {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM5 cannot be used because already used by the us_ticker -const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // SERIAL_TX -// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // SERIAL_TX -// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // SERIAL_TX - {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // SERIAL_RX -// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // SERIAL_RX -// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // SERIAL_RX - {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO -// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO -// {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 -// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 -// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 -// {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 -// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - -// {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N -// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 -// {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N -// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO -// {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO -// {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 -// {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO -// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 -// {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 -// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 1, 0)}, // TIM10_CH1 -// {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 -// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO -// {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N -// {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N -// {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - -// {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 -// {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO -// {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 -// {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - - {NC, NC, 0} -}; - -//*** SERIAL *** - -const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX -// {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // WAKE_OUT -// {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // GPS_EN -// {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // GPS module SPI - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX -// {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // MPU9250 SPI MOSI -// {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // MPU9250 SPI MISO -// {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // GROVE SDA - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RTS[] = { -// {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, -// {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_CTS[] = { -// {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, -// {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {NC, NC, 0} -}; - -//*** SPI *** - -const PinMap PinMap_SPI_MOSI[] = { -// {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO - {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, -// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, -// {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, -// {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO -// {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, - {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, -// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, -// {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO - {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, -// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, -// {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, -// {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Warning: also on NSS - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, -// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, -// {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { -// {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, -// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, -// {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Warning: also on SCLK -// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Warning: also on SCLK - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PinNames.h deleted file mode 100644 index 480bfa9152e..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PinNames.h +++ /dev/null @@ -1,208 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PA_0 = 0x00, - PA_1 = 0x01, - PA_2 = 0x02, - PA_3 = 0x03, - PA_4 = 0x04, - PA_5 = 0x05, - PA_6 = 0x06, - PA_7 = 0x07, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - - PB_0 = 0x10, - PB_1 = 0x11, - PB_2 = 0x12, - PB_3 = 0x13, - PB_4 = 0x14, - PB_5 = 0x15, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_9 = 0x19, - PB_10 = 0x1A, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_14 = 0x1E, - PB_15 = 0x1F, - - PC_0 = 0x20, - PC_1 = 0x21, - PC_2 = 0x22, - PC_3 = 0x23, - PC_4 = 0x24, - PC_5 = 0x25, - PC_6 = 0x26, - PC_7 = 0x27, - PC_8 = 0x28, - PC_9 = 0x29, - PC_10 = 0x2A, - PC_11 = 0x2B, - PC_12 = 0x2C, - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, - - PD_2 = 0x32, - - PH_0 = 0x70, - PH_1 = 0x71, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, - - // External IO connector namings - A0 = PA_0, - A1 = PA_1, - VBAT_AD_IN = A0, - VBAT_AD_EN = A1, - I2C_SCL = PB_10, - I2C_SDA = PB_3, - SPI_MOSI = PA_7, - SPI_MISO = PA_6, - SPI_SCK = PA_5, - SPI_CS = PA_4, - - EXT_PIN_3 = PA_7, - EXT_PIN_4 = PA_6, - EXT_PIN_5 = PA_5, - EXT_PIN_6 = PA_4, - EXT_PIN_7 = PA_3, - EXT_PIN_8 = PA_2, - EXT_PIN_9 = PB_10, - EXT_PIN_10 = PB_3, - EXT_PIN_13 = PA_0, - EXT_PIN_14 = PA_1, - - EXT_I2C_SCL = I2C_SCL, - EXT_I2C_SDA = I2C_SDA, - EXT_SPI_MOSI = SPI_MOSI, - EXT_SPI_MISO = SPI_MISO, - EXT_SPI_SCK = SPI_SCK, - EXT_SPI_CS = SPI_CS, - EXT_SERIAL_TX = PA_2, - EXT_SERIAL_RX = PA_3, - - SCM_I2C_SCL = PA_8, - SCM_I2C_SDA = PC_9, - SCM_SPI_MOSI = PB_15, - SCM_SPI_MISO = PB_14, - SCM_SPI_SCK = PB_13, - SCM_SPI_CS = PB_12, - SCM_WAKE_IN = PC_8, - SCM_WAKE_OUT = PA_9, - - GPS_INT = PB_5, - GPS_1PPS = PB_4, - GPS_WAKEUP = PD_2, - GPS_EN = PA_11, - GPS_SERIAL_TX = PC_6, - GPS_SERIAL_RX = PC_7, - GPS_SPI_MOSI = PC_12, - GPS_SPI_MISO = PC_11, - GPS_SPI_SCK = PC_10, - GPS_SPI_CS = PA_15, - - LCD_LED = PC_5, - LCD_I2C_SCL = PB_8, - LCD_I2C_SDA = PB_9, - BME280_I2C_SCL = PB_8, - BME280_I2C_SDA = PB_9, - - MPU9250_SPI_MOSI = PA_10, - MPU9250_SPI_MISO = PA_12, - MPU9250_SPI_SCK = PB_0, - MPU9250_SPI_CS = PB_1, - - // Generic signals namings - LED1 = PC_13, - LED2 = PC_15, - LED3 = PH_1, - LED4 = PC_4, - LED_RED = LED1, - - // Standardized button names - SW1 = PC_14, - SW2 = PH_0, - SW3 = PC_0, - SW4 = PC_1, - SW5 = PC_2, - SW6 = PC_3, - - USER_BUTTON = SW1, - BUTTON1 = SW1, - BUTTON2 = SW2, - BUTTON3 = SW3, - BUTTON4 = SW4, - SLIDE_SW1 = SW5, - SLIDE_SW2 = SW6, - - // Serial port pins - SERIAL_TX = PB_6, - SERIAL_RX = PB_7, - USBTX = PB_6, - USBRX = PB_7, - - // USB pins - // USB_OTG_FS_SOF = PA_8, - // USB_OTG_FS_VBUS = PA_9, - // USB_OTG_FS_ID = PA_10, - // USB_OTG_FS_DM = PA_11, - // USB_OTG_FS_DP = PA_12, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/system_clock.c deleted file mode 100644 index 12bc55d9625..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/system_clock.c +++ /dev/null @@ -1,193 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) | DEVICE_USBDEVICE=1 - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) | - * | 3- USE_PLL_HSI (internal 16 MHz) | - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 100 | 96 - * AHBCLK (MHz) | 100 | 96 - * APB1CLK (MHz) | 50 | 48 - * APB2CLK (MHz) | 100 | 96 - * USB capable | NO | YES - *----------------------------------------------------------------------------- -**/ - -#include "stm32f4xx.h" -#include "mbed_error.h" - - -// clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) -#define USE_PLL_HSI 0x2 // Use HSI internal clock - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -uint8_t SetSysClock_PLL_HSI(void); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ - - -/** -* @brief Configures the System clock source, PLL Multiplier and Divider factors, -* AHB/APBx prescalers and Flash settings -* @note This function should be called only once the RCC clock configuration -* is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ - -void SetSysClock(void) -{ -#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) - /* 1- Try to start with HSE and external clock */ - if (SetSysClock_PLL_HSE(1) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) - /* 2- If fail try to start with HSE and external xtal */ - if (SetSysClock_PLL_HSE(0) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSI) - /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) -#endif - { - { - error("SetSysClock failed\n"); - } - } - } - } - - /* Output clock on MCO2 pin(PC9) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); -} - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); - - // Enable HSE oscillator and activate PLL with HSE as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT - } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN - } - - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4) -#if (DEVICE_USBDEVICE) - RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192) -#else /* DEVICE_USBDEVICE */ - RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) -#endif /* DEVICE_USBDEVICE */ - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz or 96 MHz (depending on DEVICE_USBDEVICE) - RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (DEVICE_USBDEVICE=1) - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100/96 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100/96 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50/48 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100/96 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //if (bypass == 0) - // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal - //else - // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); - - // Enable HSI oscillator and activate PLL with HSI as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) -#if (DEVICE_USBDEVICE) - RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192) -#else /* DEVICE_USBDEVICE */ - RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) -#endif /* DEVICE_USBDEVICE */ - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz or 96 MHz (depending on DEVICE_USBDEVICE) - RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (DEVICE_USBDEVICE=1) - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/PeripheralNames.h deleted file mode 100644 index 0be5095f039..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/PeripheralNames.h +++ /dev/null @@ -1,76 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2016 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE -} ADCName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE, - UART_6 = (int)USART6_BASE -} UARTName; - -#define DEVICE_SPI_COUNT 5 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE, - SPI_4 = (int)SPI4_BASE, - SPI_5 = (int)SPI5_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE, - I2C_3 = (int)I2C3_BASE, - FMPI2C_1 = (int)FMPI2C1_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE, - PWM_5 = (int)TIM5_BASE, - PWM_8 = (int)TIM8_BASE, - PWM_9 = (int)TIM9_BASE, - PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE, - PWM_12 = (int)TIM12_BASE, - PWM_13 = (int)TIM13_BASE, - PWM_14 = (int)TIM14_BASE -} PWMName; - -typedef enum { - CAN_1 = (int)CAN1_BASE, - CAN_2 = (int)CAN2_BASE -} CANName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/PeripheralPins.c deleted file mode 100644 index ad824e64986..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/PeripheralPins.c +++ /dev/null @@ -1,326 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2016 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "PeripheralPins.h" - -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== - -//*** ADC *** - -const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - A0 - {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 - {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 - LED1 - {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 - {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - A1 - {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - A3 - {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 - {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - A2 - {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 - A4 - {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 - A5 - {NC, NC, 0} -}; - -const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used - {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used - {NC, NC, 0} -}; - -//*** I2C *** - -const PinMap PinMap_I2C_SDA[] = { -// {PB_3, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, - {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, - {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, -// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, - {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, -// {PB_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, -// {PC_7, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, - {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, -// {PD_13, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, -// {PD_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, - {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, -// {PF_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, -// {PB_10, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_FMPI2C1)}, - {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, -// {PB_15, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, -// {PC_6, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, -// {PD_12, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, -// {PD_14, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, - {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, -// {PF_14, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM5 cannot be used because already used by the us_ticker -const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 -// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 -// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 - {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 -// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 -// {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N -// {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 -// {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N -// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 -// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - - {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N -// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 -// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N -// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 -// {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 -// {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 -// {PB_9, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N -// {PB_14, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 - {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N -// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N -// {PB_15, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 - {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N -// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - - {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 -// {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 -// {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 -// {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 -// {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - - {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - - {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 - {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - -// {PF_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 -// {PF_4, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 -// {PF_5, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 -// {PF_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - - {NC, NC, 0} -}; - -//*** SERIAL *** - -const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RTS[] = { - {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_CTS[] = { - {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)}, - {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -//*** SPI *** - -const PinMap PinMap_SPI_MOSI[] = { - {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, -// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, - {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, -// {PE_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, -// {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_14, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, - {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, -// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, -// {PE_5, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, -// {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_13, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, -// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, -// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, - {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, -// {PE_2, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, -// {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, - {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, -// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, - {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, -// {PE_4, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, -// {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, - {PE_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, - {NC, NC, 0} -}; - -//*** CAN *** - -const PinMap PinMap_CAN_RD[] = { - {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)}, - {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PG_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PG_11, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_CAN_TD[] = { - {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)}, - {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PG_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PG_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/PinNames.h deleted file mode 100644 index 42969ea6bce..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/PinNames.h +++ /dev/null @@ -1,327 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2016 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PA_0 = 0x00, - PA_1 = 0x01, - PA_2 = 0x02, - PA_3 = 0x03, - PA_4 = 0x04, - PA_5 = 0x05, - PA_6 = 0x06, - PA_7 = 0x07, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - - PB_0 = 0x10, - PB_1 = 0x11, - PB_2 = 0x12, - PB_3 = 0x13, - PB_4 = 0x14, - PB_5 = 0x15, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_9 = 0x19, - PB_10 = 0x1A, - PB_11 = 0x1B, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_14 = 0x1E, - PB_15 = 0x1F, - - PC_0 = 0x20, - PC_1 = 0x21, - PC_2 = 0x22, - PC_3 = 0x23, - PC_4 = 0x24, - PC_5 = 0x25, - PC_6 = 0x26, - PC_7 = 0x27, - PC_8 = 0x28, - PC_9 = 0x29, - PC_10 = 0x2A, - PC_11 = 0x2B, - PC_12 = 0x2C, - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, - - PD_0 = 0x30, - PD_1 = 0x31, - PD_2 = 0x32, - PD_3 = 0x33, - PD_4 = 0x34, - PD_5 = 0x35, - PD_6 = 0x36, - PD_7 = 0x37, - PD_8 = 0x38, - PD_9 = 0x39, - PD_10 = 0x3A, - PD_11 = 0x3B, - PD_12 = 0x3C, - PD_13 = 0x3D, - PD_14 = 0x3E, - PD_15 = 0x3F, - - PE_0 = 0x40, - PE_1 = 0x41, - PE_2 = 0x42, - PE_3 = 0x43, - PE_4 = 0x44, - PE_5 = 0x45, - PE_6 = 0x46, - PE_7 = 0x47, - PE_8 = 0x48, - PE_9 = 0x49, - PE_10 = 0x4A, - PE_11 = 0x4B, - PE_12 = 0x4C, - PE_13 = 0x4D, - PE_14 = 0x4E, - PE_15 = 0x4F, - - PF_0 = 0x50, - PF_1 = 0x51, - PF_2 = 0x52, - PF_3 = 0x53, - PF_4 = 0x54, - PF_5 = 0x55, - PF_6 = 0x56, - PF_7 = 0x57, - PF_8 = 0x58, - PF_9 = 0x59, - PF_10 = 0x5A, - PF_11 = 0x5B, - PF_12 = 0x5C, - PF_13 = 0x5D, - PF_14 = 0x5E, - PF_15 = 0x5F, - - PG_0 = 0x60, - PG_1 = 0x61, - PG_2 = 0x62, - PG_3 = 0x63, - PG_4 = 0x64, - PG_5 = 0x65, - PG_6 = 0x66, - PG_7 = 0x67, - PG_8 = 0x68, - PG_9 = 0x69, - PG_10 = 0x6A, - PG_11 = 0x6B, - PG_12 = 0x6C, - PG_13 = 0x6D, - PG_14 = 0x6E, - PG_15 = 0x6F, - - PH_0 = 0x70, - PH_1 = 0x71, - - // Not connected - NC = (int)0xFFFFFFFF, - - //Module pins. - P_1 = PB_12, - P_2 = PA_4, - P_3 = PB_10, - P_4 = PC_12, - P_5 = PC_15, - P_6 = PB_1, - P_7 = PB_0, - P_8 = PA_5, - P_9 = PC_13, - P_10 = PB_6, - P_11 = PB_7, - P_12 = NC, - P_13 = NC, - P_14 = NC, - P_15 = NC, - P_16 = NC, - P_17 = NC, - P_18 = NC, - P_19 = NC, - P_20 = NC, - P_21 = NC, - P_22 = PB_9, - P_23 = PC_3, - P_24 = PB_13, - P_25 = PC_2, - P_26 = NC, - P_27 = PC_0, - P_28 = NC, - P_29 = NC, - P_30 = NC, - P_31 = PA_7, - P_32 = PC_4, - P_33 = PC_11, - P_34 = PC_5, - P_35 = PB_2, - P_36 = PA_6, - P_37 = NC, - P_38 = PA_10, - P_39 = PA_9, - P_40 = PA_14, - P_41 = PB_3, - P_42 = PB_4, - P_43 = PA_15, - P_44 = PA_13, - P_45 = NC, - P_46 = NC, - P_47 = NC, - P_48 = NC, - P_49 = NC, - P_50 = NC, - P_51 = PA_12, - P_52 = PA_11, - P_53 = PB_14, - P_54 = NC, - P_55 = NC, - P_56 = NC, - P_57 = NC, - P_58 = NC, - P_59 = NC, - P_60 = NC, - P_61 = NC, - P_62 = NC, - P_63 = NC, - P_64 = NC, - P_65 = NC, - P_66 = NC, - P_67 = NC, - P_68 = NC, - P_69 = PC_14, - P_70 = NC, - P_71 = NC, - P_72 = NC, - P_73 = NC, - P_74 = NC, - P_75 = NC, - P_76 = NC, - P_77 = NC, - P_78 = NC, - P_79 = NC, - P_80 = NC, - P_81 = NC, - P_82 = NC, - P_83 = NC, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, - - - // Generic signals namings -#ifdef MBED_CONF_TARGET_LED1 - LED1 = MBED_CONF_TARGET_LED1, -#else - LED1 = PA_7, -#endif -#ifdef MBED_CONF_TARGET_LED2 - LED2 = MBED_CONF_TARGET_LED2, -#else - LED2 = PC_4, -#endif -#ifdef MBED_CONF_TARGET_LED3 - LED3 = MBED_CONF_TARGET_LED3, -#else - LED3 = PC_11, -#endif - LED_RED = LED1, - LED_BLUE = LED2, - LED_GREEN = LED3, - USER_BUTTON = PB_14, - - // Standardized button names - BUTTON1 = USER_BUTTON, - - I2C_SCL = P_10, - I2C_SDA = P_11, - - SPI_MOSI = P_23, - SPI_MISO = P_25, - SPI_SCK = P_24, - SPI_CS = P_22, - - // STDIO for console print -#ifdef MBED_CONF_TARGET_STDIO_UART_TX - STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, -#elif MBED_CONF_TARGET_USB_TX - STDIO_UART_TX = MBED_CONF_TARGET_USB_TX, -#else - STDIO_UART_TX = PA_9, -#endif - -#ifdef MBED_CONF_TARGET_STDIO_UART_RX - STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, -#elif MBED_CONF_TARGET_USB_RX - STDIO_UART_TX = MBED_CONF_TARGET_USB_RX, -#else - STDIO_UART_RX = PA_10, -#endif - //DAPLink - USBRX = STDIO_UART_RX, - USBTX = STDIO_UART_TX, - - //MTB Aliases - //Left side (top view) - PB7 = I2C_SDA, - PB6 = I2C_SCL, - PC3 = SPI_MOSI, - PC2 = SPI_MISO, - PB13 = SPI_SCK, - PB14 = USER_BUTTON, - GP1 = PC_15, - -//AIN0 -//AIN1 -//AIN2 - - //Right side (top view) - GP3 = PB_2, - GP2 = PC_5, - GP4 = PC_12, - GP5 = PB_10, //A0 for LCD - GP6 = PA_4, //RESET for LCD - GP7 = PB_12, //CS for LCD - GP8 = PC_0, - -//TX2 = WL_GPIO1 -//RX2 = WL_GPIO2 - -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/system_clock.c deleted file mode 100644 index 32546de20a2..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/system_clock.c +++ /dev/null @@ -1,220 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) - * | 3- USE_PLL_HSI (internal 16 MHz) - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 100 - * AHBCLK (MHz) | 100 - * APB1CLK (MHz) | 50 - * APB2CLK (MHz) | 100 - * USB capable | YES - *----------------------------------------------------------------------------- -**/ - -#include "stm32f4xx.h" -#include "mbed_error.h" - -// clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) -#define USE_PLL_HSI 0x2 // Use HSI internal clock - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -uint8_t SetSysClock_PLL_HSI(void); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ - - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ - -void SetSysClock(void) -{ -#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) - /* 1- Try to start with HSE and external clock */ - if (SetSysClock_PLL_HSE(1) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) - /* 2- If fail try to start with HSE and external xtal */ - if (SetSysClock_PLL_HSE(0) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSI) - /* 3- If fail start with HSI clock */ - uint8_t ret_HSIclk_status = SetSysClock_PLL_HSI(); - if (ret_HSIclk_status == 0) -#endif - { - { - error("SetSysClock failed\n"); - } - } - } - } - - /* Output clock on MCO2 pin(PC9) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); -} - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ - } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ - } - - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - - RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) - RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 200 MHz (1 MHz * 200) - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2) - RCC_OscInitStruct.PLL.PLLQ = 7; - RCC_OscInitStruct.PLL.PLLR = 2; - - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLLSAI output as USB clock source */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; - PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; - PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; - PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; - PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; - PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; - PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; - - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //if (bypass == 0) - // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal - //else - // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSI oscillator and activate PLL with HSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) - RCC_OscInitStruct.PLL.PLLN = 100; // VCO output clock = 200 MHz (2 MHz * 100) - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2) - RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; - - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLLSAI output as USB clock source */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; - PeriphClkInitStruct.PLLI2S.PLLI2SM = 16; - PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; - PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; - PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; - PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; - PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; - - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_MTB_STM_S2LP/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_MTB_STM_S2LP/PeripheralNames.h deleted file mode 100644 index ae50b3171e6..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_MTB_STM_S2LP/PeripheralNames.h +++ /dev/null @@ -1,102 +0,0 @@ -/* mbed Microcontroller Library -* SPDX-License-Identifier: BSD-3-Clause - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE, - ADC_2 = (int)ADC2_BASE, - ADC_3 = (int)ADC3_BASE -} ADCName; - -typedef enum { - DAC_1 = (int)DAC_BASE -} DACName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE, - UART_4 = (int)UART4_BASE, - UART_5 = (int)UART5_BASE, - UART_6 = (int)USART6_BASE, - UART_7 = (int)UART7_BASE, - UART_8 = (int)UART8_BASE -} UARTName; - - -#define SPI_COUNT 6 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE, - SPI_4 = (int)SPI4_BASE, - SPI_5 = (int)SPI5_BASE, - SPI_6 = (int)SPI6_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE, - I2C_3 = (int)I2C3_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE, - PWM_5 = (int)TIM5_BASE, - PWM_8 = (int)TIM8_BASE, - PWM_9 = (int)TIM9_BASE, - PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE, - PWM_12 = (int)TIM12_BASE, - PWM_13 = (int)TIM13_BASE, - PWM_14 = (int)TIM14_BASE -} PWMName; - -typedef enum { - CAN_1 = (int)CAN1_BASE, - CAN_2 = (int)CAN2_BASE -} CANName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_MTB_STM_S2LP/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_MTB_STM_S2LP/PeripheralPins.c deleted file mode 100644 index 9cf05f63590..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_MTB_STM_S2LP/PeripheralPins.c +++ /dev/null @@ -1,363 +0,0 @@ -/* mbed Microcontroller Library -* SPDX-License-Identifier: BSD-3-Clause - ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "PeripheralPins.h" -#include "mbed_toolchain.h" - -//============================================================================== -// Notes -// -// - The pins mentioned Px_y_ALTz are alternative possibilities which use other -// HW peripheral instances. You can use them the same way as any other "normal" -// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board -// pinout image on mbed.org. -// -// - The pins which are connected to other components present on the board have -// the comment "Connected to xxx". The pin function may not work properly in this -// case. These pins may not be displayed on the board pinout image on mbed.org. -// Please read the board reference manual and schematic for more information. -// -// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented -// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. -// -//============================================================================== - - -//*** ADC *** - -MBED_WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 - {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 - {PA_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0] - {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0] - {PA_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0] - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO] - {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO] - {PA_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO] - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 - {PA_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 - {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 - {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 - {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 - {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV] - {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV] - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to LD1 - {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // Connected to LD1 - {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 - {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 - {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 - {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 - {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Connected to RMII_MDC [LAN8742A-CZ-TR_MDC] - {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 // Connected to RMII_MDC [LAN8742A-CZ-TR_MDC] - {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11 // Connected to RMII_MDC [LAN8742A-CZ-TR_MDC] - {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 - {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 - {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 - {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 - {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13 - {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // Connected to RMII_RXD0 [LAN8742A-CZ-TR_RXD0] - {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 // Connected to RMII_RXD0 [LAN8742A-CZ-TR_RXD0] - {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // Connected to RMII_RXD1 [LAN8742A-CZ-TR_RXD1] - {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 // Connected to RMII_RXD1 [LAN8742A-CZ-TR_RXD1] - {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9 - {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14 - {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15 - {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 - {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 - {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 - {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 - {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, - {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, - {NC, NC, 0} -}; - -//*** DAC *** - -MBED_WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 - {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 - {NC, NC, 0} -}; - -//*** I2C *** - -MBED_WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LD2 [Blue] - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to USB_SOF [TP1] - {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM5 cannot be used because already used by the us_ticker -MBED_WEAK const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0] -// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0] - {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO] -// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO] - {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO] - {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 -// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV] - {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV] - {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV] - {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV] - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to USB_SOF [TP1] - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to USB_VBUS - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to USB_ID - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_DM - {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD1 - {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to LD1 - {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD1 - {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to LD2 [Blue] - {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1] - {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD3 [Red] - {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD3 [Red] - {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 // Connected to LD3 [Red] - {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 - {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 - {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {NC, NC, 0} -}; - -//*** SERIAL *** - -MBED_WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO] - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_VBUS - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX - {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, - {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, - {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0] - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_ID - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LD2 [Blue] - {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX - {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, - {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, - {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0] - {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DP - {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD3 [Red] - {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DM - {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1] - {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to RMII_TXD0 [LAN8742A-CZ-TR_TXD0] - {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -//*** SPI *** - -MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV] - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, - {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, - {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, - {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LD3 [Red] - {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, - {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1] - {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, - {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to RMII_TXD0 [LAN8742A-CZ-TR_TXD0] - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, - {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, - {NC, NC, 0} -}; - -//*** CAN *** - -MBED_WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DM - {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_CAN_TD[] = { - {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DP - {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1] - {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_MTB_STM_S2LP/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_MTB_STM_S2LP/PinNames.h deleted file mode 100644 index 591a31ee72c..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_MTB_STM_S2LP/PinNames.h +++ /dev/null @@ -1,389 +0,0 @@ -/* mbed Microcontroller Library -* SPDX-License-Identifier: BSD-3-Clause - ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ALT0 = 0x100, - ALT1 = 0x200, - ALT2 = 0x300, - ALT3 = 0x400 -} ALTx; - -typedef enum { - PA_0 = 0x00, - PA_0_ALT0 = PA_0 | ALT0, - PA_0_ALT1 = PA_0 | ALT1, - PA_1 = 0x01, - PA_1_ALT0 = PA_1 | ALT0, - PA_1_ALT1 = PA_1 | ALT1, - PA_2 = 0x02, - PA_2_ALT0 = PA_2 | ALT0, - PA_2_ALT1 = PA_2 | ALT1, - PA_3 = 0x03, - PA_3_ALT0 = PA_3 | ALT0, - PA_3_ALT1 = PA_3 | ALT1, - PA_4 = 0x04, - PA_4_ALT0 = PA_4 | ALT0, - PA_5 = 0x05, - PA_5_ALT0 = PA_5 | ALT0, - PA_5_ALT1 = PA_5 | ALT1, - PA_6 = 0x06, - PA_6_ALT0 = PA_6 | ALT0, - PA_7 = 0x07, - PA_7_ALT0 = PA_7 | ALT0, - PA_7_ALT1 = PA_7 | ALT1, - PA_7_ALT2 = PA_7 | ALT2, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - PA_15_ALT0 = PA_15 | ALT0, - - PB_0 = 0x10, - PB_0_ALT0 = PB_0 | ALT0, - PB_0_ALT1 = PB_0 | ALT1, - PB_1 = 0x11, - PB_1_ALT0 = PB_1 | ALT0, - PB_1_ALT1 = PB_1 | ALT1, - PB_2 = 0x12, - PB_3 = 0x13, - PB_3_ALT0 = PB_3 | ALT0, - PB_4 = 0x14, - PB_4_ALT0 = PB_4 | ALT0, - PB_5 = 0x15, - PB_5_ALT0 = PB_5 | ALT0, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_8_ALT0 = PB_8 | ALT0, - PB_9 = 0x19, - PB_9_ALT0 = PB_9 | ALT0, - PB_10 = 0x1A, - PB_11 = 0x1B, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_14 = 0x1E, - PB_14_ALT0 = PB_14 | ALT0, - PB_14_ALT1 = PB_14 | ALT1, - PB_15 = 0x1F, - PB_15_ALT0 = PB_15 | ALT0, - PB_15_ALT1 = PB_15 | ALT1, - - PC_0 = 0x20, - PC_0_ALT0 = PC_0 | ALT0, - PC_0_ALT1 = PC_0 | ALT1, - PC_1 = 0x21, - PC_1_ALT0 = PC_1 | ALT0, - PC_1_ALT1 = PC_1 | ALT1, - PC_2 = 0x22, - PC_2_ALT0 = PC_2 | ALT0, - PC_2_ALT1 = PC_2 | ALT1, - PC_3 = 0x23, - PC_3_ALT0 = PC_3 | ALT0, - PC_3_ALT1 = PC_3 | ALT1, - PC_4 = 0x24, - PC_4_ALT0 = PC_4 | ALT0, - PC_5 = 0x25, - PC_5_ALT0 = PC_5 | ALT0, - PC_6 = 0x26, - PC_6_ALT0 = PC_6 | ALT0, - PC_7 = 0x27, - PC_7_ALT0 = PC_7 | ALT0, - PC_8 = 0x28, - PC_8_ALT0 = PC_8 | ALT0, - PC_9 = 0x29, - PC_9_ALT0 = PC_9 | ALT0, - PC_10 = 0x2A, - PC_10_ALT0 = PC_10 | ALT0, - PC_11 = 0x2B, - PC_11_ALT0 = PC_11 | ALT0, - PC_12 = 0x2C, - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, - - PD_0 = 0x30, - PD_1 = 0x31, - PD_2 = 0x32, - PD_3 = 0x33, - PD_4 = 0x34, - PD_5 = 0x35, - PD_6 = 0x36, - PD_7 = 0x37, - PD_8 = 0x38, - PD_9 = 0x39, - PD_10 = 0x3A, - PD_11 = 0x3B, - PD_12 = 0x3C, - PD_13 = 0x3D, - PD_14 = 0x3E, - PD_15 = 0x3F, - - PE_0 = 0x40, - PE_1 = 0x41, - PE_2 = 0x42, - PE_3 = 0x43, - PE_4 = 0x44, - PE_5 = 0x45, - PE_6 = 0x46, - PE_7 = 0x47, - PE_8 = 0x48, - PE_9 = 0x49, - PE_10 = 0x4A, - PE_11 = 0x4B, - PE_12 = 0x4C, - PE_13 = 0x4D, - PE_14 = 0x4E, - PE_15 = 0x4F, - - PF_0 = 0x50, - PF_1 = 0x51, - PF_2 = 0x52, - PF_3 = 0x53, - PF_4 = 0x54, - PF_5 = 0x55, - PF_6 = 0x56, - PF_7 = 0x57, - PF_8 = 0x58, - PF_9 = 0x59, - PF_10 = 0x5A, - PF_11 = 0x5B, - PF_12 = 0x5C, - PF_13 = 0x5D, - PF_14 = 0x5E, - PF_15 = 0x5F, - - PG_0 = 0x60, - PG_1 = 0x61, - PG_2 = 0x62, - PG_3 = 0x63, - PG_4 = 0x64, - PG_5 = 0x65, - PG_6 = 0x66, - PG_7 = 0x67, - PG_8 = 0x68, - PG_9 = 0x69, - PG_10 = 0x6A, - PG_11 = 0x6B, - PG_12 = 0x6C, - PG_13 = 0x6D, - PG_14 = 0x6E, - PG_15 = 0x6F, - - PH_0 = 0x70, - PH_1 = 0x71, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, - - // Not connected - NC = (int)0xFFFFFFFF, - - // STDIO for console print -#ifdef MBED_CONF_TARGET_STDIO_UART_TX - STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, -#else - STDIO_UART_TX = PA_9, -#endif -#ifdef MBED_CONF_TARGET_STDIO_UART_RX - STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, -#else - STDIO_UART_RX = PA_10, -#endif - - // Generic signals namings - LED1 = PE_2, // LD1 = RED - LED2 = PE_3, // Blue - LED3 = PE_4, // Green - - LED_RED = LED1, - LED_BLUE = LED2, - LED_GREEN = LED3, - - // Standardized button names - USER_BUTTON = PB_0, - BUTTON1 = USER_BUTTON, - - SERIAL_TX = STDIO_UART_TX, // Virtual Com Port - SERIAL_RX = STDIO_UART_RX, // Virtual Com Port - USBTX = STDIO_UART_TX, // Virtual Com Port - USBRX = STDIO_UART_RX, // Virtual Com Port - - SERIAL_TX1 = PE_8, - SERIAL_RX1 = PE_7, - - I2C0_SCL = PB_6, - I2C0_SDA = PB_7, - - I2C1_SCL = PB_8, - I2C1_SDA = PC_9, - - //Default I2C - I2C_SCL = I2C0_SCL, - I2C_SDA = I2C0_SDA, - - SPI0_MOSI = PA_7, - SPI0_MISO = PA_6, - SPI0_SCK = PA_5, - SPI0_CS = PC_0, - - SPI1_MOSI = PB_15, - SPI1_MISO = PB_14, - SPI1_SCK = PB_10, - SPI1_CS = PD_1, //MX25R Chip Select - - SPI2_MOSI = PC_12, - SPI2_MISO = PC_11, - SPI2_SCK = PC_10, - SPI2_CS = NC, - - /* - SPI3_MOSI = PE_6, - SPI3_MISO = PE_5, - SPI3_SCK = PE_12, - SPI3_CS = PE_11, - */ - //Default SPI, connected to S2_LP on MCB. - SPI_MOSI = SPI0_MOSI, - SPI_MISO = SPI0_MISO, - SPI_SCK = SPI0_SCK, - SPI_CS = SPI0_CS, - - /**** ETHERNET pins ****/ - ETH_COL = PA_3, - ETH_CRS = PA_0, - ETH_CRS_DV = PA_7, - ETH_MDC = PC_1, - ETH_MDIO = PA_2, - ETH_PPS_OUT = PG_8, - ETH_PPS_OUT_ALT0 = PB_5, - ETH_REF_CLK = PA_1, - ETH_RXD0 = PC_4, - ETH_RXD1 = PC_5, - ETH_RXD2 = PB_0, - ETH_RXD3 = PB_1, - ETH_RX_CLK = PA_1, - ETH_RX_DV = PA_7, - ETH_RX_ER = PB_10, - ETH_TXD0 = PB_12, - ETH_TXD0_ALT0 = PG_13, - ETH_TXD1 = PB_13, - ETH_TXD1_ALT0 = PG_14, - ETH_TXD2 = PC_2, - ETH_TXD3 = PE_2, - ETH_TXD3_ALT0 = PB_8, - ETH_TX_CLK = PC_3, - ETH_TX_EN = PB_11, - ETH_TX_EN_ALT0 = PG_11, - - /**** OSCILLATOR pins ****/ - RCC_OSC32_IN = PC_14, - RCC_OSC32_OUT = PC_15, - RCC_OSC_IN = PH_0, - RCC_OSC_OUT = PH_1, - - /**** DEBUG pins ****/ - SYS_JTCK_SWCLK = PA_14, - SYS_JTDI = PA_15, - SYS_JTDO_SWO = PB_3, - SYS_JTMS_SWDIO = PA_13, - SYS_JTRST = PB_4, - SYS_TRACECLK = PE_2, - SYS_TRACED0 = PE_3, - SYS_TRACED1 = PE_4, - SYS_TRACED2 = PE_5, - SYS_TRACED3 = PE_6, - SYS_WKUP = PA_0, - - UART1_TX = PE_8, - UART1_RX = PE_7, - - UART2_TX = PE_1, - UART2_RX = PE_0, - - /* - CAN1_TXD = PD_1, - CAN1_RXD = PD_0, - */ - - //MTB aliases. - TX1 = UART1_TX, - RX1 = UART1_RX, - SDA1 = I2C0_SDA, - SCL1 = I2C0_SCL, - MOSI1 = SPI1_MOSI, - MISO1 = SPI1_MISO, - SCK1 = PB_10, - GP0 = USER_BUTTON, - GP1 = PB_1, - AIN0 = PA_0, - AIN1 = PA_1, - AIN2 = PA_2, - PWM0 = LED_RED, - PWM1 = LED_BLUE, - PWM2 = LED_GREEN, - GP2 = PE_5, // SD card Chip Select line. Could also be PD_2. - GP3 = PE_6, - SCK2 = PC_10, - MISO2 = PC_11, - MOSI2 = PC_12, - SCL2 = I2C1_SCL, - SDA2 = I2C1_SDA, - RX2 = UART2_RX, - TX2 = UART2_TX, - GP4 = PE_9, - GP5 = PE_10, //LCD-A0 - GP6 = PE_13, //LCD Reset - GP7 = PE_14, //LCD CS - GP8 = PE_15, - -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_MTB_STM_S2LP/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_MTB_STM_S2LP/system_clock.c deleted file mode 100644 index d0be666b9b1..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_MTB_STM_S2LP/system_clock.c +++ /dev/null @@ -1,196 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* SPDX-License-Identifier: Apache-2.0 - -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) | - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) | CLOCK_SOURCE_USB=1 - * | 3- USE_PLL_HSI (internal 16 MHz clock) | - *----------------------------------------------------------------------------------- - * SYSCLK(MHz) | 180 | 168 - * AHBCLK (MHz) | 180 | 168 - * APB1CLK (MHz) | 45 | 42 - * APB2CLK (MHz) | 90 | 84 - * USB capable (48 MHz) | NO | YES (HSI calibration needed) - *----------------------------------------------------------------------------------- -**/ - -#include "stm32f4xx.h" -#include "mbed_error.h" - -// clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) -#define USE_PLL_HSI 0x2 // Use HSI internal clock - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -uint8_t SetSysClock_PLL_HSI(void); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ - - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ - -void SetSysClock(void) -{ -#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) - /* 1- Try to start with HSE and external clock */ - if (SetSysClock_PLL_HSE(1) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) - /* 2- If fail try to start with HSE and external xtal */ - if (SetSysClock_PLL_HSE(0) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSI) - /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) -#endif - { - { - error("SetSysClock failed\n"); - } - } - } - } -} - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - // Enable HSE oscillator and activate PLL with HSE as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT - } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN - } - - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 8; -#if (CLOCK_SOURCE_USB) - RCC_OscInitStruct.PLL.PLLN = 336; -#else - RCC_OscInitStruct.PLL.PLLN = 360; -#endif - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if CLOCK_SOURCE_USB defined - RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if CLOCK_SOURCE_USB defined - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - // Activate the OverDrive to reach the 180 MHz Frequency - if (HAL_PWREx_EnableOverDrive() != HAL_OK) { - return 0; // FAIL - } - - // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { - return 0; // FAIL - } - - // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3); - - return 1; -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - // Enable HSI oscillator and activate PLL with HSI as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = 8; -#if (CLOCK_SOURCE_USB) - RCC_OscInitStruct.PLL.PLLN = 168; -#else - RCC_OscInitStruct.PLL.PLLN = 180; -#endif - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if CLOCK_SOURCE_USB defined - RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if CLOCK_SOURCE_USB defined - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - // Activate the OverDrive to reach the 180 MHz Frequency - if (HAL_PWREx_EnableOverDrive() != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { - return 0; // FAIL - } - - // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3); - - return 1; -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MTB_STM32_F439/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MTB_STM32_F439/PeripheralNames.h deleted file mode 100644 index 926b6f09335..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MTB_STM32_F439/PeripheralNames.h +++ /dev/null @@ -1,101 +0,0 @@ -/* mbed Microcontroller Library -* SPDX-License-Identifier: BSD-3-Clause - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE, - ADC_2 = (int)ADC2_BASE, - ADC_3 = (int)ADC3_BASE -} ADCName; - -typedef enum { - DAC_1 = (int)DAC_BASE -} DACName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE, - UART_4 = (int)UART4_BASE, - UART_5 = (int)UART5_BASE, - UART_6 = (int)USART6_BASE, - UART_7 = (int)UART7_BASE, - UART_8 = (int)UART8_BASE -} UARTName; - -#define DEVICE_SPI_COUNT 6 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE, - SPI_4 = (int)SPI4_BASE, - SPI_5 = (int)SPI5_BASE, - SPI_6 = (int)SPI6_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE, - I2C_3 = (int)I2C3_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE, - PWM_5 = (int)TIM5_BASE, - PWM_8 = (int)TIM8_BASE, - PWM_9 = (int)TIM9_BASE, - PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE, - PWM_12 = (int)TIM12_BASE, - PWM_13 = (int)TIM13_BASE, - PWM_14 = (int)TIM14_BASE -} PWMName; - -typedef enum { - CAN_1 = (int)CAN1_BASE, - CAN_2 = (int)CAN2_BASE -} CANName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MTB_STM32_F439/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MTB_STM32_F439/PeripheralPins.c deleted file mode 100644 index 3ac9afa7a35..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MTB_STM32_F439/PeripheralPins.c +++ /dev/null @@ -1,364 +0,0 @@ -/* mbed Microcontroller Library - -* SPDX-License-Identifier: BSD-3-Clause - ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "PeripheralPins.h" -#include "mbed_toolchain.h" - -//============================================================================== -// Notes -// -// - The pins mentioned Px_y_ALTz are alternative possibilities which use other -// HW peripheral instances. You can use them the same way as any other "normal" -// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board -// pinout image on mbed.org. -// -// - The pins which are connected to other components present on the board have -// the comment "Connected to xxx". The pin function may not work properly in this -// case. These pins may not be displayed on the board pinout image on mbed.org. -// Please read the board reference manual and schematic for more information. -// -// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented -// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. -// -//============================================================================== - - -//*** ADC *** - -MBED_WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 - {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 - {PA_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0] - {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0] - {PA_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0] - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO] - {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO] - {PA_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO] - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 - {PA_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 - {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 - {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 - {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 - {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV] - {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV] - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 - {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 - {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 - {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 - {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 - {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 - {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Connected to RMII_MDC [LAN8742A-CZ-TR_MDC] - {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 // Connected to RMII_MDC [LAN8742A-CZ-TR_MDC] - {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11 // Connected to RMII_MDC [LAN8742A-CZ-TR_MDC] - {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 - {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 - {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 - {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 - {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13 - {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // Connected to RMII_RXD0 [LAN8742A-CZ-TR_RXD0] - {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 // Connected to RMII_RXD0 [LAN8742A-CZ-TR_RXD0] - {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // Connected to RMII_RXD1 [LAN8742A-CZ-TR_RXD1] - {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 // Connected to RMII_RXD1 [LAN8742A-CZ-TR_RXD1] - {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9 - {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14 - {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15 - {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 - {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 - {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 - {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 - {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, - {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, - {NC, NC, 0} -}; - -//*** DAC *** - -MBED_WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 - {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 - {NC, NC, 0} -}; - -//*** I2C *** - -MBED_WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM5 cannot be used because already used by the us_ticker -MBED_WEAK const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0] -// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0] - {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO] -// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO] - {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO] - {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 -// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV] - {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV] - {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV] - {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV] - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to USB_VBUS - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to USB_ID - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_DM - {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1] - {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 - {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 - {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 - {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {NC, NC, 0} -}; - -//*** SERIAL *** - -MBED_WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to RMII_MDIO [LAN8742A-CZ-TR_MDIO] - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_VBUS - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX - {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, - {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, - {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0] - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_ID - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LD2 [Blue] - {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX - {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, - {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, - {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0] - {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DP - {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DM - {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1] - {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to RMII_TXD0 [LAN8742A-CZ-TR_TXD0] - {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, - {NC, NC, 0} -}; - -//*** SPI *** - -MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV] - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, - {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, - {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, - {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, - {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1] - {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, - {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to RMII_TXD0 [LAN8742A-CZ-TR_TXD0] - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, - {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, - {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, - {NC, NC, 0} -}; - -//*** CAN *** - -MBED_WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DM - {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_CAN_TD[] = { - {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DP - {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1] - {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MTB_STM32_F439/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MTB_STM32_F439/PinNames.h deleted file mode 100644 index 5b5e5a53fb9..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MTB_STM32_F439/PinNames.h +++ /dev/null @@ -1,383 +0,0 @@ -/* mbed Microcontroller Library - -* SPDX-License-Identifier: BSD-3-Clause - ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ALT0 = 0x100, - ALT1 = 0x200, - ALT2 = 0x300, - ALT3 = 0x400 -} ALTx; - -typedef enum { - PA_0 = 0x00, - PA_0_ALT0 = PA_0 | ALT0, - PA_0_ALT1 = PA_0 | ALT1, - PA_1 = 0x01, - PA_1_ALT0 = PA_1 | ALT0, - PA_1_ALT1 = PA_1 | ALT1, - PA_2 = 0x02, - PA_2_ALT0 = PA_2 | ALT0, - PA_2_ALT1 = PA_2 | ALT1, - PA_3 = 0x03, - PA_3_ALT0 = PA_3 | ALT0, - PA_3_ALT1 = PA_3 | ALT1, - PA_4 = 0x04, - PA_4_ALT0 = PA_4 | ALT0, - PA_5 = 0x05, - PA_5_ALT0 = PA_5 | ALT0, - PA_5_ALT1 = PA_5 | ALT1, - PA_6 = 0x06, - PA_6_ALT0 = PA_6 | ALT0, - PA_7 = 0x07, - PA_7_ALT0 = PA_7 | ALT0, - PA_7_ALT1 = PA_7 | ALT1, - PA_7_ALT2 = PA_7 | ALT2, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - PA_15_ALT0 = PA_15 | ALT0, - - PB_0 = 0x10, - PB_0_ALT0 = PB_0 | ALT0, - PB_0_ALT1 = PB_0 | ALT1, - PB_1 = 0x11, - PB_1_ALT0 = PB_1 | ALT0, - PB_1_ALT1 = PB_1 | ALT1, - PB_2 = 0x12, - PB_3 = 0x13, - PB_3_ALT0 = PB_3 | ALT0, - PB_4 = 0x14, - PB_4_ALT0 = PB_4 | ALT0, - PB_5 = 0x15, - PB_5_ALT0 = PB_5 | ALT0, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_8_ALT0 = PB_8 | ALT0, - PB_9 = 0x19, - PB_9_ALT0 = PB_9 | ALT0, - PB_10 = 0x1A, - PB_11 = 0x1B, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_14 = 0x1E, - PB_14_ALT0 = PB_14 | ALT0, - PB_14_ALT1 = PB_14 | ALT1, - PB_15 = 0x1F, - PB_15_ALT0 = PB_15 | ALT0, - PB_15_ALT1 = PB_15 | ALT1, - - PC_0 = 0x20, - PC_0_ALT0 = PC_0 | ALT0, - PC_0_ALT1 = PC_0 | ALT1, - PC_1 = 0x21, - PC_1_ALT0 = PC_1 | ALT0, - PC_1_ALT1 = PC_1 | ALT1, - PC_2 = 0x22, - PC_2_ALT0 = PC_2 | ALT0, - PC_2_ALT1 = PC_2 | ALT1, - PC_3 = 0x23, - PC_3_ALT0 = PC_3 | ALT0, - PC_3_ALT1 = PC_3 | ALT1, - PC_4 = 0x24, - PC_4_ALT0 = PC_4 | ALT0, - PC_5 = 0x25, - PC_5_ALT0 = PC_5 | ALT0, - PC_6 = 0x26, - PC_6_ALT0 = PC_6 | ALT0, - PC_7 = 0x27, - PC_7_ALT0 = PC_7 | ALT0, - PC_8 = 0x28, - PC_8_ALT0 = PC_8 | ALT0, - PC_9 = 0x29, - PC_9_ALT0 = PC_9 | ALT0, - PC_10 = 0x2A, - PC_10_ALT0 = PC_10 | ALT0, - PC_11 = 0x2B, - PC_11_ALT0 = PC_11 | ALT0, - PC_12 = 0x2C, - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, - - PD_0 = 0x30, - PD_1 = 0x31, - PD_2 = 0x32, - PD_3 = 0x33, - PD_4 = 0x34, - PD_5 = 0x35, - PD_6 = 0x36, - PD_7 = 0x37, - PD_8 = 0x38, - PD_9 = 0x39, - PD_10 = 0x3A, - PD_11 = 0x3B, - PD_12 = 0x3C, - PD_13 = 0x3D, - PD_14 = 0x3E, - PD_15 = 0x3F, - - PE_0 = 0x40, - PE_1 = 0x41, - PE_2 = 0x42, - PE_3 = 0x43, - PE_4 = 0x44, - PE_5 = 0x45, - PE_6 = 0x46, - PE_7 = 0x47, - PE_8 = 0x48, - PE_9 = 0x49, - PE_10 = 0x4A, - PE_11 = 0x4B, - PE_12 = 0x4C, - PE_13 = 0x4D, - PE_14 = 0x4E, - PE_15 = 0x4F, - - PF_0 = 0x50, - PF_1 = 0x51, - PF_2 = 0x52, - PF_3 = 0x53, - PF_4 = 0x54, - PF_5 = 0x55, - PF_6 = 0x56, - PF_7 = 0x57, - PF_8 = 0x58, - PF_9 = 0x59, - PF_10 = 0x5A, - PF_11 = 0x5B, - PF_12 = 0x5C, - PF_13 = 0x5D, - PF_14 = 0x5E, - PF_15 = 0x5F, - - PG_0 = 0x60, - PG_1 = 0x61, - PG_2 = 0x62, - PG_3 = 0x63, - PG_4 = 0x64, - PG_5 = 0x65, - PG_6 = 0x66, - PG_7 = 0x67, - PG_8 = 0x68, - PG_9 = 0x69, - PG_10 = 0x6A, - PG_11 = 0x6B, - PG_12 = 0x6C, - PG_13 = 0x6D, - PG_14 = 0x6E, - PG_15 = 0x6F, - - PH_0 = 0x70, - PH_1 = 0x71, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, - - // Not connected - NC = (int)0xFFFFFFFF, - - // STDIO for console print -#ifdef MBED_CONF_TARGET_STDIO_UART_TX - STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, -#else - STDIO_UART_TX = PA_9, -#endif -#ifdef MBED_CONF_TARGET_STDIO_UART_RX - STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, -#else - STDIO_UART_RX = PA_10, -#endif - - // Generic signals namings - LED1 = PE_2, // LD1 = RED - LED2 = PE_3, // BLUE - LED3 = PE_4, // GREEN - - LED_RED = LED1, - LED_BLUE = LED2, - LED_GREEN = LED3, - - USER_BUTTON = PC_13, - // Standardized button names - BUTTON1 = USER_BUTTON, - SERIAL_TX = STDIO_UART_TX, // Virtual Com Port - SERIAL_RX = STDIO_UART_RX, // Virtual Com Port - USBTX = STDIO_UART_TX, // Virtual Com Port - USBRX = STDIO_UART_RX, // Virtual Com Port - - SERIAL_TX1 = PD_5, - SERIAL_RX1 = PD_6, - SERIAL_CTS1 = PD_3, - SERIAL_RTS1 = PD_4, - - SERIAL_TX2 = PE_1, - SERIAL_RX2 = PE_0, - - I2C0_SCL = PB_6, - I2C0_SDA = PB_7, - - I2C1_SCL = PB_8, - I2C1_SDA = PC_9, - - SPI0_MOSI = PB_5, - SPI0_MISO = PA_6, - SPI0_SCK = PA_5, - SPI0_CS = PA_15, - - SPI1_MOSI = PB_15, - SPI1_MISO = PB_14, - SPI1_SCK = PD_3, - SPI1_CS = PB_9, - - SPI2_MOSI = PC_12, - SPI2_MISO = PC_11, - SPI2_SCK = PC_10, -// SPI2_CS = NC,//Use any GPIO - - SPI3_MOSI = PE_6, - SPI3_MISO = PE_5, - SPI3_SCK = PE_12, - SPI3_CS = PE_11, - - //Default SPI - SPI_MOSI = SPI0_MOSI, - SPI_MISO = SPI0_MISO, - SPI_SCK = SPI0_SCK, - /**************** - //IMPORTANT NOTE: The default CS for SPI is marked as the CS line for the SPI Flash - on the MCB reference hardware. Please change as appropriate. - ****************/ - SPI_CS = PD_2, - - CAN1_RX = PD_0, //Test point on MCB - CAN1_TX = PD_1, //Test point on MCB - - /**** ETHERNET pins ****/ - ETH_COL = PA_3, - ETH_CRS = PA_0, - ETH_CRS_DV = PA_7, - ETH_MDC = PC_1, - ETH_MDIO = PA_2, - ETH_PPS_OUT = PG_8, - ETH_PPS_OUT_ALT0 = PB_5, - ETH_REF_CLK = PA_1, - ETH_RXD0 = PC_4, - ETH_RXD1 = PC_5, - ETH_RXD2 = PB_0, - ETH_RXD3 = PB_1, - ETH_RX_CLK = PA_1, - ETH_RX_DV = PA_7, - ETH_RX_ER = PB_10, - ETH_TXD0 = PB_12, - ETH_TXD0_ALT0 = PG_13, - ETH_TXD1 = PB_13, - ETH_TXD1_ALT0 = PG_14, - ETH_TXD2 = PC_2, - ETH_TXD3 = PB_8, - ETH_TXD3_ALT0 = PE_2, - ETH_TX_CLK = PC_3, - ETH_TX_EN = PB_11, - ETH_TX_EN_ALT0 = PG_11, - - /**** OSCILLATOR pins ****/ - RCC_OSC32_IN = PC_14, - RCC_OSC32_OUT = PC_15, - RCC_OSC_IN = PH_0, - RCC_OSC_OUT = PH_1, - - /**** DEBUG pins ****/ - SYS_JTCK_SWCLK = PA_14, - SYS_JTDO_SWO = PB_3, - SYS_JTMS_SWDIO = PA_13, - - /**** MTB aliases ****/ - TX1 = PD_5, - RX1 = PD_6, - SDA1 = PB_7, - SCL1 = PB_6, - MOSI1 = PB_5, - MISO1 = PA_6, - SCK1 = PA_5, - GP0 = PC_13, - GP1 = PC_10, - AIN0 = PC_11, //Also CTS1 via jumper on MCB - AIN1 = PC_12, //Also RTS1 via jumper on MCB - AIN2 = PC_0, - - GP2 = PE_5, //SD card CS - GP3 = PA_15, //Also SPI0_CS - SCK2 = PD_3, - MISO2 = PB_14, - MOSI2 = PB_15, - SCL2 = PB_8, - SDA2 = PC_9, - RX2 = PE_0, - TX2 = PE_1, - GP4 = PE_9, - GP5 = PE_10, //A0 for LCD on MTB - GP6 = PE_13, //RESET for LCD on MTB - GP7 = PB_9, //LCD CS - GP8 = PE_15, - - /**** MODEM pins ****/ - /* - MDMTXD = PD_5, - MDMRXD = PD_6, - MDMRTS = PD_4, - MDMCTS = PD_3 - */ - -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MTB_STM32_F439/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MTB_STM32_F439/system_clock.c deleted file mode 100644 index 8670ce44a7f..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MTB_STM32_F439/system_clock.c +++ /dev/null @@ -1,190 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2019 ARM Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) | - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) | CLOCK_SOURCE_USB=1 - * | 3- USE_PLL_HSI (internal 16 MHz clock) | - *----------------------------------------------------------------------------------- - * SYSCLK(MHz) | 180 | 168 - * AHBCLK (MHz) | 180 | 168 - * APB1CLK (MHz) | 45 | 42 - * APB2CLK (MHz) | 90 | 84 - * USB capable (48 MHz) | NO | YES (HSI calibration needed) - *----------------------------------------------------------------------------------- -**/ - -#include "stm32f4xx.h" -#include "mbed_error.h" - -// clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) -#define USE_PLL_HSI 0x2 // Use HSI internal clock - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -uint8_t SetSysClock_PLL_HSI(void); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ - - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ - -void SetSysClock(void) -{ -#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) - /* 1- Try to start with HSE and external clock */ - if (SetSysClock_PLL_HSE(1) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) - /* 2- If fail try to start with HSE and external xtal */ - if (SetSysClock_PLL_HSE(0) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSI) - /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) -#endif - { - { - error("SetSysClock failed\n"); - } - } - } - } -} - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - // Enable HSE oscillator and activate PLL with HSE as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT - } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN - } - - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 8; -#if (CLOCK_SOURCE_USB) - RCC_OscInitStruct.PLL.PLLN = 336; -#else - RCC_OscInitStruct.PLL.PLLN = 360; -#endif - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if CLOCK_SOURCE_USB defined - RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if CLOCK_SOURCE_USB defined - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - // Activate the OverDrive to reach the 180 MHz Frequency - if (HAL_PWREx_EnableOverDrive() != HAL_OK) { - return 0; // FAIL - } - - // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { - return 0; // FAIL - } - - return 1; -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - // Enable HSI oscillator and activate PLL with HSI as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = 8; -#if (CLOCK_SOURCE_USB) - RCC_OscInitStruct.PLL.PLLN = 168; -#else - RCC_OscInitStruct.PLL.PLLN = 180; -#endif - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if CLOCK_SOURCE_USB defined - RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if CLOCK_SOURCE_USB defined - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - // Activate the OverDrive to reach the 180 MHz Frequency - if (HAL_PWREx_EnableOverDrive() != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { - return 0; // FAIL - } - - return 1; -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/PeripheralNames.h deleted file mode 100644 index 37701983a51..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/PeripheralNames.h +++ /dev/null @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2017, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE -} ADCName; - -typedef enum { - DAC_1 = (int)DAC_BASE -} DACName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_4 = (int)USART4_BASE, - UART_5 = (int)USART5_BASE, - LPUART_1 = (int)LPUART1_BASE -} UARTName; - -#define DEVICE_SPI_COUNT 2 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE, - I2C_3 = (int)I2C3_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)LPTIM1_BASE, - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_21 = (int)TIM21_BASE, - PWM_22 = (int)TIM22_BASE -} PWMName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/PeripheralPins.c deleted file mode 100644 index 5b770da24e5..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/PeripheralPins.c +++ /dev/null @@ -1,165 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2017, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "PeripheralPins.h" - -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== - -//*** ADC *** - -const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // BLUE-LED - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // POT - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // BUTTON - {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // RED-LED - {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // GREEN-LED - {NC, NC, 0} -}; - -const PinMap PinMap_ADC_Internal[] = { - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC_IN17 // VREFINT - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18 // VSENSE - {NC, NC, 0} -}; - -//*** DAC *** - -const PinMap PinMap_DAC[] = { - {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // RED-LED - {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // GREEN-LED - {NC, NC, 0} -}; - -//*** I2C *** - -const PinMap PinMap_I2C_SDA[] = { - {PA_10, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // SDA - {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PA_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, - {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // SCL - {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, - {NC, NC, 0} -}; - -//*** PWM *** -// Pins using TIM21 cannot be used as TIM21 is already used by ticker. -const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 -// {PA_2, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1 - {PA_2_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 -// {PA_3, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // TIM21_CH2 - {PA_3_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 - {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 - {PB_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPTIM1, 0, 0)}, // TIM2_CH2 - {PB_5, PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 2, 0)}, // TIM22_CH2 - {PB_5_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM3, 2, 0)}, // TIM3_CH2 -// {PB_13, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 1, 0)}, // TIM21_CH1 -// {PB_14, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 2, 0)}, // TIM21_CH2 - {NC, NC, 0} -}; - -//*** SERIAL *** - -const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_14_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // SWCLK - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PA_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // SWDIO - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RTS[] = { - {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, - {PB_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_CTS[] = { - {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, - {NC, NC, 0} -}; - -//*** SPI *** - -const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // MOSI - {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, // MOSI - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, - {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, // MISO - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // SCK - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, // SCK - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, - {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, // /SD_CS - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/PinNames.h deleted file mode 100644 index 719c7030505..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/PinNames.h +++ /dev/null @@ -1,155 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2017, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ALT0 = 0x100, - ALT1 = 0x200, - ALT2 = 0x300, - ALT3 = 0x400 -} ALTx; - -typedef enum { - PA_0 = 0x00, - PA_1 = 0x01, - PA_2 = 0x02, - PA_2_ALT0 = PA_2 | ALT0, - PA_3 = 0x03, - PA_3_ALT0 = PA_3 | ALT0, - PA_4 = 0x04, - PA_5 = 0x05, - PA_6 = 0x06, - PA_7 = 0x07, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_14_ALT0 = PA_14 | ALT0, - PA_15 = 0x0F, - - PB_0 = 0x10, - PB_1 = 0x11, - PB_2 = 0x12, - PB_3 = 0x13, - PB_4 = 0x14, - PB_5 = 0x15, - PB_5_ALT0 = PB_5 | ALT0, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_9 = 0x19, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_14 = 0x1E, - PB_15 = 0x1F, - - PC_0 = 0x20, - PC_1 = 0x21, - PC_2 = 0x22, - PC_13 = 0x2D, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, - - // STDIO for console print -#ifdef MBED_CONF_TARGET_STDIO_UART_TX - STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, -#else - STDIO_UART_TX = PA_9, -#endif -#ifdef MBED_CONF_TARGET_STDIO_UART_RX - STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, -#else - STDIO_UART_RX = PA_10, -#endif - - // Generic signals namings - LED1 = PA_4, // Red - LED2 = PA_5, // Blue - LED3 = PA_0, // Green - USER_BUTTON = PA_3, - BUTTON1 = USER_BUTTON, - SERIAL_TX = STDIO_UART_TX, - SERIAL_RX = STDIO_UART_RX, - USBTX = SERIAL_TX, - USBRX = SERIAL_RX, - I2C_SCL = PB_8, - I2C_SDA = PB_9, - SPI_MOSI = PB_15, - SPI_MISO = PB_14, - SPI_SCK = PB_13, - SD_CS = PB_12, - LCD_A0 = PB_2, - LCD_RESET = PB_5, - LCD_NCS = PB_6, - - LORA_SPI_MOSI = PA_7, - LORA_SPI_MISO = PA_6, - LORA_SPI_SCLK = PB_3, - LORA_CS = PA_15, - LORA_RESET = PC_0, - LORA_DIO0 = PB_4, - LORA_DIO1 = PB_1, - LORA_DIO2 = PB_0, - LORA_DIO3 = PC_13, - LORA_ANT_RX = PA_1, - LORA_ANT_TX = PC_2, - LORA_ANT_BOOST = PC_1, - - //USB pins - USB_DM = PA_11, - USB_DP = PA_12, - - // Flash - FLASH_NCS = PA_8, - POT = PA_2, // ADC2 - input ! - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/system_clock.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/system_clock.c deleted file mode 100644 index ca7af4e7dad..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/system_clock.c +++ /dev/null @@ -1,149 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------- - * System clock source | internal 16 MHz - *----------------------------------------------------------------- - * SYSCLK(MHz) | 32 - * AHBCLK (MHz) | 32 - * APB1CLK (MHz) | 32 - * USB capable | YES - *----------------------------------------------------------------- - */ - -#include "stm32l0xx.h" -#include "mbed_error.h" - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. - This value must be a multiple of 0x100. */ - -uint8_t SetSysClock_PLL_HSI(void); - -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /*!< Set MSION bit */ - RCC->CR |= (uint32_t)0x00000100U; - - /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ - RCC->CFGR &= (uint32_t) 0x88FF400CU; - - /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFF6U; - - /*!< Reset HSI48ON bit */ - RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; - - /*!< Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFFU; - - /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ - RCC->CFGR &= (uint32_t)0xFF02FFFFU; - - /*!< Disable all interrupts */ - RCC->CIER = 0x00000000U; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -void SetSysClock(void) -{ - if (SetSysClock_PLL_HSI() == 0) { - { - error("SetSysClock failed\n"); - } - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1); -} - -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */ - // PLLCLK = (16 MHz * 4)/2 = 32 MHz - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4; - RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { - return 0; // FAIL - } - - RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz - - return 1; // OK -} - diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/PeripheralNames.h deleted file mode 100644 index 613085a9dcc..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/PeripheralNames.h +++ /dev/null @@ -1,78 +0,0 @@ -/* mbed Microcontroller Library - * - * SPDX-License-Identifier: BSD-3-Clause - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE -} ADCName; - -typedef enum { - DAC_1 = (int)DAC_BASE -} DACName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE -} UARTName; - -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE -} I2CName; - -typedef enum { - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE, // used as us_ticker - PWM_9 = (int)TIM9_BASE, - PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE -} PWMName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/PeripheralPins.c deleted file mode 100644 index 144294fde40..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/PeripheralPins.c +++ /dev/null @@ -1,131 +0,0 @@ -/* mbed Microcontroller Library - * - * SPDX-License-Identifier: BSD-3-Clause - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "PeripheralPins.h" - -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== - -//*** ADC *** - -const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1 - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3 - {PB_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18 - {PB_13, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC_IN19 - {PB_14, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC_IN20 - {PB_15, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 21, 0)}, // ADC_IN21 - {NC, NC, 0} -}; - -const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, - {NC, NC, 0} -}; - -//*** DAC *** - -const PinMap PinMap_DAC[] = { - {NC, NC, 0} -}; - -//*** I2C *** - -const PinMap PinMap_I2C_SDA[] = { - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM4 cannot be used because already used by the us_ticker. -const PinMap PinMap_PWM[] = { - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PB_13, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 -// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - {PB_14, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - {PB_12, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 -// {PB_8, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - {PB_15, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - {NC, NC, 0} -}; - -//*** SERIAL *** - -const PinMap PinMap_UART_TX[] = { - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {NC, NC, 0} -}; - -//*** SPI *** - -const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PB_0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/PinNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/PinNames.h deleted file mode 100644 index ae049b6fa56..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/PinNames.h +++ /dev/null @@ -1,210 +0,0 @@ -/* mbed Microcontroller Library - * - * SPDX-License-Identifier: BSD-3-Clause - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PA_0 = 0x00, - PA_1 = 0x01, - PA_2 = 0x02, - PA_3 = 0x03, - PA_4 = 0x04, - PA_5 = 0x05, - PA_6 = 0x06, - PA_7 = 0x07, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - - PB_0 = 0x10, - PB_1 = 0x11, - PB_2 = 0x12, - PB_3 = 0x13, - PB_4 = 0x14, - PB_5 = 0x15, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_9 = 0x19, - PB_10 = 0x1A, - PB_11 = 0x1B, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_14 = 0x1E, - PB_15 = 0x1F, - - PC_0 = 0x20, - PC_1 = 0x21, - PC_2 = 0x22, - PC_3 = 0x23, - PC_4 = 0x24, - PC_5 = 0x25, - PC_6 = 0x26, - PC_7 = 0x27, - PC_8 = 0x28, - PC_9 = 0x29, - PC_10 = 0x2A, - PC_11 = 0x2B, - PC_12 = 0x2C, - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, - - // Not connected - NC = (int)0xFFFFFFFF, - - //Module pins. Refer iM880B_Datasheet (https://wireless-solutions.de/products/radiomodules/im880b-l.html) - P_1 = NC, // GND - P_2 = PA_14, // Digital IO / JTCK / SWCLK - P_3 = PA_13, // Digital IO / JTMS / SWDIO - P_4 = PB_3, // Digital IO / JTDO - P_5 = PA_15, // Digital IO / JTDI - P_6 = NC, // GND - P_7 = NC, // NRST - P_8 = PA_11, // Digital IO / USART1-CTS - P_9 = PA_12, // Digital IO / USART1-RTS - P_10 = NC, - P_11 = NC, // GND - P_12 = PB_14, // Digital IO / SPI2_MISO / ADC_IN20 - P_13 = PB_15, // Digital IO / SPI2_MOSI / ADC_IN21 - P_14 = PB_13, // Digital IO / SPI2_CLK / ADC_IN19 - P_15 = PB_12, // Digital IO / SPI2_NSS / ADC_IN18 - P_16 = NC, // GND - P_17 = NC, // VDD - P_18 = PA_10, // Digital IO / USART1-RX - P_19 = PA_9, // Digital IO / USART1-TX - P_20 = PA_8, // Digital IO - P_21 = PB_8, // Digital IO / I2C1-SCL - P_22 = NC, // GND - P_23 = PB_9, // Digital IO / I2C1-SDA - P_24 = PA_1, // Digital IO / ADC_IN1 - P_25 = PA_0, // Digital IO / WKUP1 / ADC_IN0 - P_26 = NC, // BOOT0 - P_27 = NC, // GND - P_28 = NC, - P_29 = PA_3, // Digital IO / ADC_IN3 - P_30 = NC, // GND - P_31 = NC, // RF_50R - P_32 = NC, // GND - - // LoRa - SPI_RF_RESET = PA_2, - SPI_RF_MOSI = PA_7, // SPI1_MOSI - SPI_RF_MISO = PA_6, // SPI1_MISO - SPI_RF_SCK = PA_5, // SPI1_CLK - SPI_RF_NSS = PB_0, - - DIO0 = PB_1, - DIO1 = PB_10, - DIO2 = PB_11, - DIO3 = PB_7, - DIO4 = PB_5, - DIO5 = PB_4, - - // Antenna tx - ANT_CTX_PA = PA_4, - // Antenna rx - ANT_CRX_RX = PC_13, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - - // LED - LED1 = PA_3, - LED2 = PA_0, - LED3 = PA_1, - LED4 = PA_8, - - //Standardized button name - SW1 = PB_15, - BUTTON1 = SW1, - - // Wake Pin - WAKE = SW1, - - // UART 1 - UART1_TX = PA_9, - UART1_RX = PA_10, - UART1_CTS = NC, - UART1_RTS = NC, - - UART_TX = UART1_TX, - UART_RX = UART1_RX, - UART_CTS = UART1_CTS, - UART_RTS = UART1_RTS, - - STDIO_UART_TX = UART_TX, - STDIO_UART_RX = UART_RX, - - // DAPLink - USBTX = UART_TX, - USBRX = UART_RX, - SWDIO = NC, - SWCLK = NC, - - // SPI - SPI2_MOSI = PB_15, - SPI2_MISO = PB_14, - SPI2_SCK = PB_13, - SPI2_NSS = PB_12, - - SPI_MOSI = SPI2_MOSI, - SPI_MISO = SPI2_MISO, - SPI_SCK = SPI2_SCK, - SPI_NSS = SPI2_NSS, - - // I2C - I2C1_SCL = PB_8, - I2C1_SDA = PB_9, - - I2C_SCL = I2C1_SCL, - I2C_SDA = I2C1_SDA -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xba.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xba.S deleted file mode 100644 index 4b7709241d5..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xba.S +++ /dev/null @@ -1,278 +0,0 @@ -;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32l151xb.s -;* Author : MCD Application Team -;* Version : V2.2.0 -;* Date : 01-July-2016 -;* Description : STM32L151XB Devices vector for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* COPYRIGHT(c) 2016 STMicroelectronics -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp - DCD RTC_WKUP_IRQHandler ; RTC Wakeup - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD USB_HP_IRQHandler ; USB High Priority - DCD USB_LP_IRQHandler ; USB Low Priority - DCD DAC_IRQHandler ; DAC - DCD COMP_IRQHandler ; COMP through EXTI Line - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD 0 ; Reserved - DCD TIM9_IRQHandler ; TIM9 - DCD TIM10_IRQHandler ; TIM10 - DCD TIM11_IRQHandler ; TIM11 - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT USB_HP_IRQHandler [WEAK] - EXPORT USB_LP_IRQHandler [WEAK] - EXPORT DAC_IRQHandler [WEAK] - EXPORT COMP_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM9_IRQHandler [WEAK] - EXPORT TIM10_IRQHandler [WEAK] - EXPORT TIM11_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USB_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_IRQHandler -USB_HP_IRQHandler -USB_LP_IRQHandler -DAC_IRQHandler -COMP_IRQHandler -EXTI9_5_IRQHandler -TIM9_IRQHandler -TIM10_IRQHandler -TIM11_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -USB_FS_WKUP_IRQHandler -TIM6_IRQHandler -TIM7_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_ARM_MICRO/stm32l151cba.sct b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_ARM_MICRO/stm32l151cba.sct deleted file mode 100644 index faa62adce06..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_ARM_MICRO/stm32l151cba.sct +++ /dev/null @@ -1,76 +0,0 @@ -#! armcc -E -; Scatter-Loading Description File -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2015, STMicroelectronics -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 -#endif - -; STM32L151CB: 128KB FLASH -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x20000 -#endif - -; 32KB SRAM -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x20000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x8000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 61 vectors = 244 bytes (0xF4) 8-byte aligned = 0xF8 (0xF4 + 0x4) to be reserved in RAM -#define VECTOR_SIZE 0xF8 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_ARM_STD/startup_stm32l151xba.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_ARM_STD/startup_stm32l151xba.S deleted file mode 100644 index 4b7709241d5..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_ARM_STD/startup_stm32l151xba.S +++ /dev/null @@ -1,278 +0,0 @@ -;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32l151xb.s -;* Author : MCD Application Team -;* Version : V2.2.0 -;* Date : 01-July-2016 -;* Description : STM32L151XB Devices vector for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* COPYRIGHT(c) 2016 STMicroelectronics -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp - DCD RTC_WKUP_IRQHandler ; RTC Wakeup - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD USB_HP_IRQHandler ; USB High Priority - DCD USB_LP_IRQHandler ; USB Low Priority - DCD DAC_IRQHandler ; DAC - DCD COMP_IRQHandler ; COMP through EXTI Line - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD 0 ; Reserved - DCD TIM9_IRQHandler ; TIM9 - DCD TIM10_IRQHandler ; TIM10 - DCD TIM11_IRQHandler ; TIM11 - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT USB_HP_IRQHandler [WEAK] - EXPORT USB_LP_IRQHandler [WEAK] - EXPORT DAC_IRQHandler [WEAK] - EXPORT COMP_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM9_IRQHandler [WEAK] - EXPORT TIM10_IRQHandler [WEAK] - EXPORT TIM11_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USB_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_IRQHandler -USB_HP_IRQHandler -USB_LP_IRQHandler -DAC_IRQHandler -COMP_IRQHandler -EXTI9_5_IRQHandler -TIM9_IRQHandler -TIM10_IRQHandler -TIM11_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -USB_FS_WKUP_IRQHandler -TIM6_IRQHandler -TIM7_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_ARM_STD/stm32l151cba.sct b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_ARM_STD/stm32l151cba.sct deleted file mode 100644 index a542c6a2138..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_ARM_STD/stm32l151cba.sct +++ /dev/null @@ -1,53 +0,0 @@ -#! armcc -E -; Scatter-Loading Description File -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2015, STMicroelectronics -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -; STM32L151CB: 128KB FLASH + 32KB SRAM -LR_IROM1 0x08000000 0x20000 { ; load region size_region - - ER_IROM1 0x08000000 0x20000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - ; 61 vectors = 244 bytes (0xF4) 8-byte aligned = 0xF8 (0xF4 + 0x4) to be reserved in RAM - RW_IRAM1 (0x20000000+0xF8) (0x8000-0xF8-Stack_Size) { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_STACK (0x20000000+0x8000) EMPTY -Stack_Size { ; stack - } -} - diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_GCC_ARM/STM32L151XB-A.ld b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_GCC_ARM/STM32L151XB-A.ld deleted file mode 100644 index 589c7489f63..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_GCC_ARM/STM32L151XB-A.ld +++ /dev/null @@ -1,164 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - /* 128KB FLASH, 32KB RAM, Reserve up till 0xF4. There are 61 vectors = 244 - * bytes (0xF4) in RAM. 8-byte aligned(0xF4) = 0xF8 - */ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128k - RAM (rwx) : ORIGIN = 0x200000F8, LENGTH = 0x8000-0xF8 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * _estack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - _sidata = .; - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xba.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xba.S deleted file mode 100644 index 4eb489bf738..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xba.S +++ /dev/null @@ -1,363 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32l151xb.s - * @author MCD Application Team - * @version V2.2.0 - * @date 01-July-2016 - * @brief STM32L151XB Devices vector table for - * Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system intitialization function.*/ - bl SystemInit - -/** - * Calling the crt0 'cold-start' entry point. There __libc_init_array is called - * and when existing hardware_init_hook() and software_init_hook() before - * starting main(). software_init_hook() is available and has to be called due - * to initializsation when using rtos. -*/ - bl _start - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_STAMP_IRQHandler - .word RTC_WKUP_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_IRQHandler - .word USB_HP_IRQHandler - .word USB_LP_IRQHandler - .word DAC_IRQHandler - .word COMP_IRQHandler - .word EXTI9_5_IRQHandler - .word 0 - .word TIM9_IRQHandler - .word TIM10_IRQHandler - .word TIM11_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word USB_FS_WKUP_IRQHandler - .word TIM6_IRQHandler - .word TIM7_IRQHandler - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_STAMP_IRQHandler - .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak USB_HP_IRQHandler - .thumb_set USB_HP_IRQHandler,Default_Handler - - .weak USB_LP_IRQHandler - .thumb_set USB_LP_IRQHandler,Default_Handler - - .weak DAC_IRQHandler - .thumb_set DAC_IRQHandler,Default_Handler - - .weak COMP_IRQHandler - .thumb_set COMP_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM9_IRQHandler - .thumb_set TIM9_IRQHandler,Default_Handler - - .weak TIM10_IRQHandler - .thumb_set TIM10_IRQHandler,Default_Handler - - .weak TIM11_IRQHandler - .thumb_set TIM11_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak USB_FS_WKUP_IRQHandler - .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_IAR/startup_stm32l151xba.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_IAR/startup_stm32l151xba.S deleted file mode 100644 index 7f9d93bea85..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_IAR/startup_stm32l151xba.S +++ /dev/null @@ -1,471 +0,0 @@ -;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32l152xc.s -;* Author : MCD Application Team -;* Version : V2.2.0 -;* Date : 01-July-2016 -;* Description : STM32L152XC Devices vector for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;*

© COPYRIGHT(c) 2016 STMicroelectronics

-;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp - DCD RTC_WKUP_IRQHandler ; RTC Wakeup - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD USB_HP_IRQHandler ; USB High Priority - DCD USB_LP_IRQHandler ; USB Low Priority - DCD DAC_IRQHandler ; DAC - DCD COMP_IRQHandler ; COMP through EXTI Line - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD 0 ; Reserved - DCD TIM9_IRQHandler ; TIM9 - DCD TIM10_IRQHandler ; TIM10 - DCD TIM11_IRQHandler ; TIM11 - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PVD_IRQHandler - B PVD_IRQHandler - - - PUBWEAK TAMPER_STAMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TAMPER_STAMP_IRQHandler - B TAMPER_STAMP_IRQHandler - - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RCC_IRQHandler - B RCC_IRQHandler - - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - - PUBWEAK DMA1_Channel5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel5_IRQHandler - B DMA1_Channel5_IRQHandler - - - PUBWEAK DMA1_Channel6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel6_IRQHandler - B DMA1_Channel6_IRQHandler - - - PUBWEAK DMA1_Channel7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel7_IRQHandler - B DMA1_Channel7_IRQHandler - - - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC1_IRQHandler - B ADC1_IRQHandler - - - PUBWEAK USB_HP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_HP_IRQHandler - B USB_HP_IRQHandler - - - PUBWEAK USB_LP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_LP_IRQHandler - B USB_LP_IRQHandler - - - PUBWEAK DAC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DAC_IRQHandler - B DAC_IRQHandler - - - PUBWEAK COMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -COMP_IRQHandler - B COMP_IRQHandler - - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - - PUBWEAK TIM9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM9_IRQHandler - B TIM9_IRQHandler - - - PUBWEAK TIM10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM10_IRQHandler - B TIM10_IRQHandler - - - PUBWEAK TIM11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM11_IRQHandler - B TIM11_IRQHandler - - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_IRQHandler - B USART1_IRQHandler - - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_IRQHandler - B USART2_IRQHandler - - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_IRQHandler - B USART3_IRQHandler - - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - - PUBWEAK USB_FS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_FS_WKUP_IRQHandler - B USB_FS_WKUP_IRQHandler - - - PUBWEAK TIM6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM6_IRQHandler - B TIM6_IRQHandler - - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_IAR/stm32l152xba.icf b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_IAR/stm32l152xba.icf deleted file mode 100644 index 9e92d0a8828..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/TOOLCHAIN_IAR/stm32l152xba.icf +++ /dev/null @@ -1,32 +0,0 @@ -if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } -if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x20000; } -/* [ROM = 128kb = 0x20000] */ -define symbol __intvec_start__ = MBED_APP_START; -define symbol __region_ROM_start__ = MBED_APP_START; -define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; - -/* [RAM = 32kb = 0x8000] Vector table dynamic copy: 61 vectors = 244 bytes (0xF4) to be reserved in RAM */ -define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x200000F7; /* Add 4 more bytes to be aligned on 8 bytes */ -define symbol __region_RAM_start__ = 0x200000F8; -define symbol __region_RAM_end__ = 0x20007FFF; - -/* Memory regions */ -define memory mem with size = 4G; -define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; -define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; - -/* Stack and Heap */ -define symbol __size_cstack__ = 0x1200; -define symbol __size_heap__ = 0x1200; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block STACKHEAP with fixed order { block HEAP, block CSTACK }; - -initialize by copy with packing = zeros { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, block STACKHEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/cmsis.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/cmsis.h deleted file mode 100644 index 85991b65500..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/cmsis.h +++ /dev/null @@ -1,40 +0,0 @@ -/* mbed Microcontroller Library - * - * SPDX-License-Identifier: Apache-2.0 - * A generic CMSIS include header - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "stm32l1xx.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/cmsis_nvic.h deleted file mode 100644 index 7d03d4bd693..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/cmsis_nvic.h +++ /dev/null @@ -1,43 +0,0 @@ -/* mbed Microcontroller Library - * - * SPDX-License-Identifier: Apache-2.0 - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -// STM32L151CB -// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F -// MCU Peripherals: 45 vectors = 180 bytes from 0x40 to 0xF3 -// Total: 61 vectors = 244 bytes (0xF4) to be reserved in RAM -#define NVIC_NUM_VECTORS 61 -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/stm32l151xba.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/stm32l151xba.h deleted file mode 100644 index 6c4eced4c69..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/stm32l151xba.h +++ /dev/null @@ -1,8169 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l151xba.h - * @author MCD Application Team - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32L1xx devices. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware - * - * - * SPDX-License-Identifier: Apache-2.0 - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l151xba - * @{ - */ - -#ifndef __STM32L151xBA_H -#define __STM32L151xBA_H - -#ifdef __cplusplus - extern "C" { -#endif - - - /** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ -#define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */ -#define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32L1xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - - /*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32L specific Interrupt Numbers ***********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ - USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ - DAC_IRQn = 21, /*!< DAC Interrupt */ - COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ - TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ - TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ - TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32l1xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ - __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ - uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx - * @{ - */ - -#ifndef __STM32L1XX_H -#define __STM32L1XX_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L1) -#define STM32L1 -#endif /* STM32L1 */ - -//MODTRONIX BEGIN - HAL Defines /////////////////////////////////////////////// -//Provide place for adding HAL defines. Alternative to adding them in IDE project properties. -//Add project defines here, or add them to your toolchain compiler preprocessor - -//Defines what ports to use for default serial port. -//0 = B10/B11 -//1 = A2/A3 -#if !defined (MX_DEFAULT_SERIAL_PINS) -#define MX_DEFAULT_SERIAL_PINS 0 /*!< Use B10/B11 for default serial port, in stead of A2/A3 */ -#endif - -//MODTRONIX END /////////////////////////////////////////////////////////////// - -/* Uncomment the line below according to the target STM32L device used in your - application - */ - -#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \ - !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xDX) && !defined (STM32L151xE) && \ - !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xDX) && !defined (STM32L152xE) && \ - !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xDX) && !defined (STM32L162xE) - /* #define STM32L100xB */ /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */ - /* #define STM32L100xBA */ /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */ - /* #define STM32L100xC */ /*!< STM32L100RC Devices */ - /* #define STM32L151xB */ /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */ - #define STM32L151xBA /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */ - /* #define STM32L151xC */ /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */ - /* #define STM32L151xCA */ /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */ - /* #define STM32L151xD */ /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */ - /* #define STM32L151xDX */ /*!< STM32L151VD-X Devices */ - /* #define STM32L151xE */ /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */ - /* #define STM32L152xB */ /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */ - /* #define STM32L152xBA */ /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */ - /* #define STM32L152xC */ /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */ - /* #define STM32L152xCA */ /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */ - /* #define STM32L152xD */ /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */ - /* #define STM32L152xDX */ /*!< STM32L152VD-X Devices */ - /* #define STM32L152xE */ /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */ - /* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */ - /* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */ - /* #define STM32L162xD */ /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */ - /* #define STM32L162xDX */ /*!< STM32L162VD-X Devices */ - /* #define STM32L162xE */ /*!< STM32L162RE, STM32L162VE and STM32L162ZE */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ -#define USE_HAL_DRIVER -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number - */ -#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ -#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L1xx_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L1xx_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L100xB) - #include "stm32l100xb.h" -#elif defined(STM32L100xBA) - #include "stm32l100xba.h" -#elif defined(STM32L100xC) - #include "stm32l100xc.h" -#elif defined(STM32L151xB) - #include "stm32l151xb.h" -#elif defined(STM32L151xBA) - #include "stm32l151xba.h" -#elif defined(STM32L151xC) - #include "stm32l151xc.h" -#elif defined(STM32L151xCA) - #include "stm32l151xca.h" -#elif defined(STM32L151xD) - #include "stm32l151xd.h" -#elif defined(STM32L151xDX) - #include "stm32l151xdx.h" -#elif defined(STM32L151xE) - #include "stm32l151xe.h" -#elif defined(STM32L152xB) - #include "stm32l152xb.h" -#elif defined(STM32L152xBA) - #include "stm32l152xba.h" -#elif defined(STM32L152xC) - #include "stm32l152xc.h" -#elif defined(STM32L152xCA) - #include "stm32l152xca.h" -#elif defined(STM32L152xD) - #include "stm32l152xd.h" -#elif defined(STM32L152xDX) - #include "stm32l152xdx.h" -#elif defined(STM32L152xE) - #include "stm32l152xe.h" -#elif defined(STM32L162xC) - #include "stm32l162xc.h" -#elif defined(STM32L162xCA) - #include "stm32l162xca.h" -#elif defined(STM32L162xD) - #include "stm32l162xd.h" -#elif defined(STM32L162xDX) - #include "stm32l162xdx.h" -#elif defined(STM32L162xE) - #include "stm32l162xe.h" -#else - #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l1xx_hal.h" -#endif /* USE_HAL_DRIVER */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L1xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/system_clock.c deleted file mode 100644 index feea5d65bd9..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/system_clock.c +++ /dev/null @@ -1,154 +0,0 @@ -/* mbed Microcontroller Library -* -* SPDX-License-Identifier: Apache-2.0 -* Copyright (c) 2006-2017 ARM Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI - * | (external 16 MHz clock) | (internal 16 MHz) - * | 2- PLL_HSE_XTAL | - * | (external 16 MHz xtal) | - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 32 | 32 - *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 32 | 32 - *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 32 | 32 - *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 32 | 32 - *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | YES | NO - *----------------------------------------------------------------------------- - ****************************************************************************** - */ - -#include "stm32l1xx.h" - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - -uint8_t SetSysClock_PLL_HSE(void); - - -/** - * @brief Setup the microcontroller system. - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /*!< Set MSION bit */ - RCC->CR |= (uint32_t)0x00000100; - - /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ - RCC->CFGR &= (uint32_t)0x88FFC00C; - - /*!< Reset HSION, HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xEEFEFFFE; - - /*!< Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ - RCC->CFGR &= (uint32_t)0xFF02FFFF; - - /*!< Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif - -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -void SetSysClock(void) -{ - if (SetSysClock_PLL_HSE() == 0) { - while(1) { - // [TODO] Put something here to tell the user that a problem occured... - } - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); -} - -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - // SYSCLK = 32 MHz ((16 MHz * 4) / 2) - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; - RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */ - while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {}; - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 16 MHz - - return 1; // OK -} diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/system_stm32l1xx.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/system_stm32l1xx.h deleted file mode 100644 index 62427e2ef17..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/system_stm32l1xx.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l1xx.h - * @author MCD Application Team - * @version V2.2.0 - * @date 01-July-2016 - * @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices. - * - * SPDX-License-Identifier: Apache-2.0 - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L1XX_H -#define __SYSTEM_STM32L1XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L1xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L1xx_System_Exported_types - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -/* -*/ -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L1XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/us_ticker_data.h deleted file mode 100644 index c0cbc745ac1..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/device/us_ticker_data.h +++ /dev/null @@ -1,47 +0,0 @@ -/* mbed Microcontroller Library - * - * SPDX-License-Identifier: Apache-2.0 - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __US_TICKER_DATA_H -#define __US_TICKER_DATA_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "stm32l1xx.h" -#include "stm32l1xx_ll_tim.h" -#include "cmsis_nvic.h" - -#define TIM_MST TIM4 -#define TIM_MST_IRQ TIM4_IRQn -#define TIM_MST_RCC __TIM4_CLK_ENABLE() -#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM4() - -#define TIM_MST_RESET_ON __TIM4_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM4_RELEASE_RESET() - -#define TIM_MST_BIT_WIDTH 16 // 16 or 32 - -#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) - - -#ifdef __cplusplus -} -#endif - -#endif // __US_TICKER_DATA_H - diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/objects.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/objects.h deleted file mode 100644 index ca543956fe0..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_IM880B/objects.h +++ /dev/null @@ -1,66 +0,0 @@ -/* mbed Microcontroller Library - * - * SPDX-License-Identifier: Apache-2.0 - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - IRQn_Type irq_n; - uint32_t irq_index; - uint32_t event; - PinName pin; -}; - -struct port_s { - PortName port; - uint32_t mask; - PinDirection direction; - __IO uint32_t *reg_in; - __IO uint32_t *reg_out; -}; - -#define GPIO_IP_WITHOUT_BRR -#include "common_objects.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PeripheralNames.h deleted file mode 100644 index 79c5f2352b5..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PeripheralNames.h +++ /dev/null @@ -1,83 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE -} ADCName; - -typedef enum { - DAC_1 = (int)DAC_BASE -} DACName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE -} UARTName; - -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - -#define DEVICE_SPI_COUNT 3 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE -} I2CName; - -typedef enum { - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE, - PWM_5 = (int)TIM5_BASE, - PWM_9 = (int)TIM9_BASE, - PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE -} PWMName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PeripheralPins.c deleted file mode 100644 index 2c04e23884e..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PeripheralPins.c +++ /dev/null @@ -1,136 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "PeripheralPins.h" - -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== - -//*** ADC *** - -const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0 - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3 - {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4 - {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5 - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8 - {PB_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18 - {PB_13, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC_IN19 - {PB_14, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC_IN20 - {PB_15, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 21, 0)}, // ADC_IN21 - {NC, NC, 0} -}; - -const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, - {NC, NC, 0} -}; - -//*** DAC *** - -const PinMap PinMap_DAC[] = { - {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 (Warning: LED1 is also on this pin) - {NC, NC, 0} -}; - -//*** I2C *** - -const PinMap PinMap_I2C_SDA[] = { - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM2 cannot be used because it is used to clock the SE -// TIM5 cannot be used because already used by the us_ticker. -const PinMap PinMap_PWM[] = { - {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_12, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - {PB_13, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 - {PB_14, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - {PB_15, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - {NC, NC, 0} -}; - -//*** SERIAL *** - -const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {NC, NC, 0} -}; - -//*** SPI *** - -const PinMap PinMap_SPI_MOSI[] = { - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SCLK[] = { - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PinNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PinNames.h deleted file mode 100644 index cd2a07cb6d9..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PinNames.h +++ /dev/null @@ -1,244 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PA_0 = 0x00, - PA_1 = 0x01, - PA_2 = 0x02, - PA_3 = 0x03, - PA_4 = 0x04, - PA_5 = 0x05, - PA_6 = 0x06, - PA_7 = 0x07, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - - PB_0 = 0x10, - PB_1 = 0x11, - PB_2 = 0x12, - PB_3 = 0x13, - PB_4 = 0x14, - PB_5 = 0x15, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_9 = 0x19, - PB_10 = 0x1A, - PB_11 = 0x1B, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_14 = 0x1E, - PB_15 = 0x1F, - - PC_0 = 0x20, - PC_1 = 0x21, - PC_2 = 0x22, - PC_3 = 0x23, - PC_4 = 0x24, - PC_5 = 0x25, - PC_6 = 0x26, - PC_7 = 0x27, - PC_8 = 0x28, - PC_9 = 0x29, - PC_10 = 0x2A, - PC_11 = 0x2B, - PC_12 = 0x2C, - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, - - PD_2 = 0x32, - - PH_0 = 0x70, - PH_1 = 0x71, - - // Not connected - NC = (int)0xFFFFFFFF, - - //Module pins. Refer device "S000645" guide, version 2.1 - P_1 = NC, - P_2 = NC, - P_3 = NC, - P_4 = NC, - P_5 = NC, - P_6 = NC, - P_7 = NC, - P_8 = NC, - P_9 = PB_12, - P_10 = PB_13, - P_11 = PB_15, - P_12 = PB_14, - P_13 = PA_9, //UART_TX - P_14 = PA_10, //UART_RX - P_15 = PA_2, - P_16 = PA_3, - P_17 = NC, - P_18 = NC, - P_19 = NC, - P_20 = NC, - P_21 = NC, - P_22 = NC, - P_23 = PB_2, - P_24 = PB_0, - P_25 = PA_5, - P_26 = PA_4, - P_27 = PB_8, - P_28 = PB_9, - P_29 = PA_14, - P_30 = PA_13, - P_31 = PA_12, //UART1_RTS - P_32 = PA_11, //UART1_CTS - P_33 = NC, //NRST - P_34 = PA_0, //WAKE - P_35 = NC, - P_36 = NC, - P_37 = NC, - P_38 = NC, - P_39 = NC, - P_40 = NC, - P_41 = NC, - P_42 = NC, - P_43 = NC, - P_44 = NC, - P_45 = NC, - P_46 = NC, - P_47 = NC, - P_48 = NC, - P_49 = NC, - P_50 = NC, - P_51 = NC, - P_52 = NC, - P_53 = NC, - P_54 = NC, - P_55 = NC, - P_56 = NC, - P_57 = NC, - P_58 = NC, - - // LoRa - LORA_RESET = PA_1, - LORA_MOSI = PB_5, - LORA_MISO = PB_4, - LORA_SCK = PB_3, - LORA_NSS = PA_15, - LORA_DIO0 = PA_6, - LORA_DIO1 = PA_7, - LORA_DIO2 = PA_8, - LORA_DIO3 = PB_1, - LORA_DIO4 = PC_13, - - // Secure Element - SE_RESET = PB_7, - SE_CTRL = PB_6, - SE_IO = PB_10, - SE_CLK = PB_11, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - - // GPIOs - GPIO0 = PA_4, // analog out capable, analog in capable. Also used as A0 for LCD on MTB - GPIO1 = PA_5, // analog out capable, analog in capable. Also used as RESET for LCD on MTB - GPIO2 = PB_0, // analog in capable, pwm capable // CS for LCD on MTB - GPIO3 = PB_2, - - // LED - LED1 = GPIO3, - LED2 = GPIO3, - - //Standardized button name - SW1 = PA_0, - BUTTON1 = SW1, - - // Wake Pin - WAKE = SW1, - - // UART 1 - UART1_TX = PA_9, - UART1_RX = PA_10, - UART1_CTS = PA_11, - UART1_RTS = PA_12, - - UART_TX = UART1_TX, - UART_RX = UART1_RX, - UART_CTS = UART1_CTS, - UART_RTS = UART1_RTS, - - //UART 2 - UART2_TX = PA_2, - UART2_RX = PA_3, - - // DAPLink - USBTX = MBED_CONF_TARGET_STDIO_UART_TX, - USBRX = MBED_CONF_TARGET_STDIO_UART_RX, - SWDIO = PA_13, - SWCLK = PA_14, - - // SPI - SPI1_MOSI = PB_15, - SPI1_MISO = PB_14, - SPI1_SCK = PB_13, - SPI1_NSS = PB_12, - - SPI_MOSI = SPI1_MOSI, - SPI_MISO = SPI1_MISO, - SPI_SCK = SPI1_SCK, - SPI_NSS = SPI1_NSS, - - // I2C - I2C0_SCL = PB_8, - I2C0_SDA = PB_9, - - I2C_SCL = I2C0_SCL, - I2C_SDA = I2C0_SDA, - -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S deleted file mode 100644 index 15ae7743651..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S +++ /dev/null @@ -1,306 +0,0 @@ -;********************* (C) COPYRIGHT 2017 STMicroelectronics ******************** -;* File Name : startup_stm32l151xc.s -;* Author : MCD Application Team -;* Version : 21-April-2017 -;* Date : V2.2.1 -;* Description : STM32L151XC Devices vector for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* COPYRIGHT(c) 2017 STMicroelectronics -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp - DCD RTC_WKUP_IRQHandler ; RTC Wakeup - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD USB_HP_IRQHandler ; USB High Priority - DCD USB_LP_IRQHandler ; USB Low Priority - DCD DAC_IRQHandler ; DAC - DCD COMP_IRQHandler ; COMP through EXTI Line - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD 0 ; Reserved - DCD TIM9_IRQHandler ; TIM9 - DCD TIM10_IRQHandler ; TIM10 - DCD TIM11_IRQHandler ; TIM11 - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - DCD 0 ; Reserved - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 - DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 - DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 - DCD 0 ; Reserved - DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT USB_HP_IRQHandler [WEAK] - EXPORT USB_LP_IRQHandler [WEAK] - EXPORT DAC_IRQHandler [WEAK] - EXPORT COMP_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM9_IRQHandler [WEAK] - EXPORT TIM10_IRQHandler [WEAK] - EXPORT TIM11_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USB_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT DMA2_Channel1_IRQHandler [WEAK] - EXPORT DMA2_Channel2_IRQHandler [WEAK] - EXPORT DMA2_Channel3_IRQHandler [WEAK] - EXPORT DMA2_Channel4_IRQHandler [WEAK] - EXPORT DMA2_Channel5_IRQHandler [WEAK] - EXPORT COMP_ACQ_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_IRQHandler -USB_HP_IRQHandler -USB_LP_IRQHandler -DAC_IRQHandler -COMP_IRQHandler -EXTI9_5_IRQHandler -TIM9_IRQHandler -TIM10_IRQHandler -TIM11_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -USB_FS_WKUP_IRQHandler -TIM6_IRQHandler -TIM7_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -DMA2_Channel1_IRQHandler -DMA2_Channel2_IRQHandler -DMA2_Channel3_IRQHandler -DMA2_Channel4_IRQHandler -DMA2_Channel5_IRQHandler -COMP_ACQ_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct deleted file mode 100644 index 7b625b8337b..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct +++ /dev/null @@ -1,76 +0,0 @@ -#! armcc -E -; Scatter-Loading Description File -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2015, STMicroelectronics -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 -#endif - -; STM32L151RC: 256KB FLASH -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x40000 -#endif - -; 32KB SRAM -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x20000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x8000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 73 vectors = 292 bytes (0x124) 8-byte aligned = 0x128 (0x124 + 0x4) to be reserved in RAM -#define VECTOR_SIZE 0x128 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S deleted file mode 100644 index 15ae7743651..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S +++ /dev/null @@ -1,306 +0,0 @@ -;********************* (C) COPYRIGHT 2017 STMicroelectronics ******************** -;* File Name : startup_stm32l151xc.s -;* Author : MCD Application Team -;* Version : 21-April-2017 -;* Date : V2.2.1 -;* Description : STM32L151XC Devices vector for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* COPYRIGHT(c) 2017 STMicroelectronics -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp - DCD RTC_WKUP_IRQHandler ; RTC Wakeup - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD USB_HP_IRQHandler ; USB High Priority - DCD USB_LP_IRQHandler ; USB Low Priority - DCD DAC_IRQHandler ; DAC - DCD COMP_IRQHandler ; COMP through EXTI Line - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD 0 ; Reserved - DCD TIM9_IRQHandler ; TIM9 - DCD TIM10_IRQHandler ; TIM10 - DCD TIM11_IRQHandler ; TIM11 - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - DCD 0 ; Reserved - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 - DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 - DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 - DCD 0 ; Reserved - DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT USB_HP_IRQHandler [WEAK] - EXPORT USB_LP_IRQHandler [WEAK] - EXPORT DAC_IRQHandler [WEAK] - EXPORT COMP_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM9_IRQHandler [WEAK] - EXPORT TIM10_IRQHandler [WEAK] - EXPORT TIM11_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USB_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT DMA2_Channel1_IRQHandler [WEAK] - EXPORT DMA2_Channel2_IRQHandler [WEAK] - EXPORT DMA2_Channel3_IRQHandler [WEAK] - EXPORT DMA2_Channel4_IRQHandler [WEAK] - EXPORT DMA2_Channel5_IRQHandler [WEAK] - EXPORT COMP_ACQ_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_IRQHandler -USB_HP_IRQHandler -USB_LP_IRQHandler -DAC_IRQHandler -COMP_IRQHandler -EXTI9_5_IRQHandler -TIM9_IRQHandler -TIM10_IRQHandler -TIM11_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -USB_FS_WKUP_IRQHandler -TIM6_IRQHandler -TIM7_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -DMA2_Channel1_IRQHandler -DMA2_Channel2_IRQHandler -DMA2_Channel3_IRQHandler -DMA2_Channel4_IRQHandler -DMA2_Channel5_IRQHandler -COMP_ACQ_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_STD/stm32l151rc.sct b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_STD/stm32l151rc.sct deleted file mode 100644 index 7d19f13b729..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_STD/stm32l151rc.sct +++ /dev/null @@ -1,62 +0,0 @@ -#! armcc -E -; Scatter-Loading Description File -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2015, STMicroelectronics -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x40000 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -; STM32L151RC: 256KB FLASH + 32KB SRAM -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - ; 73 vectors = 292 bytes (0x124) + 0x4(8-byte aligned) to be reserved in RAM - RW_IRAM1 (0x20000000+0x128) (0x8000-0x128-Stack_Size) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_STACK (0x20000000+0x8000) EMPTY -Stack_Size { ; stack - } -} - diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_GCC_ARM/STM32L151XC.ld b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_GCC_ARM/STM32L151XC.ld deleted file mode 100644 index 959a0e912b0..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_GCC_ARM/STM32L151XC.ld +++ /dev/null @@ -1,172 +0,0 @@ -/* Linker script to configure memory regions. */ -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 256k -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - /* 256KB FLASH, 32KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292 - * bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138 - * 8-byte aligned(0x13C) = 0x140 - */ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - RAM (rwx) : ORIGIN = 0x20000140, LENGTH = 0x8000-0x140 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * _estack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - _sidata = .; - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S deleted file mode 100644 index 3464c26a831..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S +++ /dev/null @@ -1,401 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32l151xc.s - * @author MCD Application Team - * @brief STM32L151XC Devices vector table for - * Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main - bl _start -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_STAMP_IRQHandler - .word RTC_WKUP_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_IRQHandler - .word USB_HP_IRQHandler - .word USB_LP_IRQHandler - .word DAC_IRQHandler - .word COMP_IRQHandler - .word EXTI9_5_IRQHandler - .word 0 - .word TIM9_IRQHandler - .word TIM10_IRQHandler - .word TIM11_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word USB_FS_WKUP_IRQHandler - .word TIM6_IRQHandler - .word TIM7_IRQHandler - .word 0 - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word 0 - .word 0 - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_IRQHandler - .word DMA2_Channel5_IRQHandler - .word 0 - .word COMP_ACQ_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x108. This is for boot in RAM mode for - STM32L151XC devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_STAMP_IRQHandler - .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak USB_HP_IRQHandler - .thumb_set USB_HP_IRQHandler,Default_Handler - - .weak USB_LP_IRQHandler - .thumb_set USB_LP_IRQHandler,Default_Handler - - .weak DAC_IRQHandler - .thumb_set DAC_IRQHandler,Default_Handler - - .weak COMP_IRQHandler - .thumb_set COMP_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM9_IRQHandler - .thumb_set TIM9_IRQHandler,Default_Handler - - .weak TIM10_IRQHandler - .thumb_set TIM10_IRQHandler,Default_Handler - - .weak TIM11_IRQHandler - .thumb_set TIM11_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak USB_FS_WKUP_IRQHandler - .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_IRQHandler - .thumb_set DMA2_Channel4_IRQHandler,Default_Handler - - .weak DMA2_Channel5_IRQHandler - .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - - .weak COMP_ACQ_IRQHandler - .thumb_set COMP_ACQ_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_IAR/startup_stm32l152xc.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_IAR/startup_stm32l152xc.S deleted file mode 100644 index 58174bedae6..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_IAR/startup_stm32l152xc.S +++ /dev/null @@ -1,536 +0,0 @@ -;********************* (C) COPYRIGHT 2017 STMicroelectronics ******************** -;* File Name : startup_stm32l152xc.s -;* Author : MCD Application Team -;* Version : 21-April-2017 -;* Date : V2.2.1 -;* Description : STM32L152XC Devices vector for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;*

© COPYRIGHT(c) 2017 STMicroelectronics

-;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp - DCD RTC_WKUP_IRQHandler ; RTC Wakeup - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD USB_HP_IRQHandler ; USB High Priority - DCD USB_LP_IRQHandler ; USB Low Priority - DCD DAC_IRQHandler ; DAC - DCD COMP_IRQHandler ; COMP through EXTI Line - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD LCD_IRQHandler ; LCD - DCD TIM9_IRQHandler ; TIM9 - DCD TIM10_IRQHandler ; TIM10 - DCD TIM11_IRQHandler ; TIM11 - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - DCD 0 ; Reserved - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 - DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 - DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 - DCD 0 ; Reserved - DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PVD_IRQHandler - B PVD_IRQHandler - - - PUBWEAK TAMPER_STAMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TAMPER_STAMP_IRQHandler - B TAMPER_STAMP_IRQHandler - - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RCC_IRQHandler - B RCC_IRQHandler - - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - - PUBWEAK DMA1_Channel5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel5_IRQHandler - B DMA1_Channel5_IRQHandler - - - PUBWEAK DMA1_Channel6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel6_IRQHandler - B DMA1_Channel6_IRQHandler - - - PUBWEAK DMA1_Channel7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel7_IRQHandler - B DMA1_Channel7_IRQHandler - - - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC1_IRQHandler - B ADC1_IRQHandler - - - PUBWEAK USB_HP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_HP_IRQHandler - B USB_HP_IRQHandler - - - PUBWEAK USB_LP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_LP_IRQHandler - B USB_LP_IRQHandler - - - PUBWEAK DAC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DAC_IRQHandler - B DAC_IRQHandler - - - PUBWEAK COMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -COMP_IRQHandler - B COMP_IRQHandler - - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - - PUBWEAK LCD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LCD_IRQHandler - B LCD_IRQHandler - - - PUBWEAK TIM9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM9_IRQHandler - B TIM9_IRQHandler - - - PUBWEAK TIM10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM10_IRQHandler - B TIM10_IRQHandler - - - PUBWEAK TIM11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM11_IRQHandler - B TIM11_IRQHandler - - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_IRQHandler - B USART1_IRQHandler - - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_IRQHandler - B USART2_IRQHandler - - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_IRQHandler - B USART3_IRQHandler - - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - - PUBWEAK USB_FS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_FS_WKUP_IRQHandler - B USB_FS_WKUP_IRQHandler - - - PUBWEAK TIM6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM6_IRQHandler - B TIM6_IRQHandler - - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK SPI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI3_IRQHandler - B SPI3_IRQHandler - - - PUBWEAK DMA2_Channel1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Channel1_IRQHandler - B DMA2_Channel1_IRQHandler - - - PUBWEAK DMA2_Channel2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Channel2_IRQHandler - B DMA2_Channel2_IRQHandler - - - PUBWEAK DMA2_Channel3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Channel3_IRQHandler - B DMA2_Channel3_IRQHandler - - - PUBWEAK DMA2_Channel4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Channel4_IRQHandler - B DMA2_Channel4_IRQHandler - - - PUBWEAK DMA2_Channel5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Channel5_IRQHandler - B DMA2_Channel5_IRQHandler - - - PUBWEAK COMP_ACQ_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -COMP_ACQ_IRQHandler - B COMP_ACQ_IRQHandler - - END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_IAR/stm32l152xc.icf b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_IAR/stm32l152xc.icf deleted file mode 100644 index 27b7a51140e..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_IAR/stm32l152xc.icf +++ /dev/null @@ -1,35 +0,0 @@ -if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } -if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x40000; } -/* [ROM = 256kb = 0x40000] */ -define symbol __intvec_start__ = MBED_APP_START; -define symbol __region_ROM_start__ = MBED_APP_START; -define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; - -/* [RAM = 32kb = 0x8000] Vector table dynamic copy: 73 vectors = 292 bytes (0x124) to be reserved in RAM */ -define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x20000127; /* Add 4 more bytes to be aligned on 8 bytes */ -define symbol __region_RAM_start__ = 0x20000128; -define symbol __region_RAM_end__ = 0x20007FFF; - -/* Memory regions */ -define memory mem with size = 4G; -define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; -define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; - -/* Stack and Heap */ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __size_heap__ = 0x800; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block STACKHEAP with fixed order { block HEAP, block CSTACK }; - -initialize by copy with packing = zeros { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, block STACKHEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/cmsis_nvic.h deleted file mode 100644 index 6f8097c63bd..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/cmsis_nvic.h +++ /dev/null @@ -1,41 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -// STM32L151CC -// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F -// MCU Peripherals: 57 vectors = 228 bytes from 0x40 to 0x123 -// Total: 73 vectors = 292 bytes (0x124) to be reserved in RAM -#define NVIC_NUM_VECTORS 73 -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/stm32l151xc.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/stm32l151xc.h deleted file mode 100644 index 003da03da15..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/stm32l151xc.h +++ /dev/null @@ -1,9070 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l151xc.h - * @author MCD Application Team - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32L1xx devices. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l151xc - * @{ - */ - -#ifndef __STM32L151xC_H -#define __STM32L151xC_H - -#ifdef __cplusplus - extern "C" { -#endif - - - /** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ -#define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */ -#define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32L1xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - - /*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32L specific Interrupt Numbers ***********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ - USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ - DAC_IRQn = 21, /*!< DAC Interrupt */ - COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ - TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ - TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ - TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ - TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ - DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ - COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32l1xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ - __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ - uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2017 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx - * @{ - */ - -#ifndef __STM32L1XX_H -#define __STM32L1XX_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L1) -#define STM32L1 -#endif /* STM32L1 */ - -/* Uncomment the line below according to the target STM32L device used in your - application - */ - -#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \ - !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xDX) && !defined (STM32L151xE) && \ - !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xDX) && !defined (STM32L152xE) && \ - !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xDX) && !defined (STM32L162xE) - /* #define STM32L100xB */ /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */ - /* #define STM32L100xBA */ /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */ - /* #define STM32L100xC */ /*!< STM32L100RC Devices */ - /* #define STM32L151xB */ /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */ - /* #define STM32L151xBA */ /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */ - #define STM32L151xC /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */ - /* #define STM32L151xCA */ /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */ - /* #define STM32L151xD */ /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */ - /* #define STM32L151xDX */ /*!< STM32L151VD-X Devices */ - /* #define STM32L151xE */ /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */ - /* #define STM32L152xB */ /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */ - /* #define STM32L152xBA */ /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */ - /* #define STM32L152xC */ /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */ - /* #define STM32L152xCA */ /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */ - /* #define STM32L152xD */ /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */ - /* #define STM32L152xDX */ /*!< STM32L152VD-X Devices */ - /* #define STM32L152xE */ /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */ - /* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */ - /* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */ - /* #define STM32L162xD */ /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */ - /* #define STM32L162xDX */ /*!< STM32L162VD-X Devices */ - /* #define STM32L162xE */ /*!< STM32L162RE, STM32L162VE and STM32L162ZE */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ -#define USE_HAL_DRIVER -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number - */ -#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ -#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ -#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L1xx_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L1xx_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L100xB) - #include "stm32l100xb.h" -#elif defined(STM32L100xBA) - #include "stm32l100xba.h" -#elif defined(STM32L100xC) - #include "stm32l100xc.h" -#elif defined(STM32L151xB) - #include "stm32l151xb.h" -#elif defined(STM32L151xBA) - #include "stm32l151xba.h" -#elif defined(STM32L151xC) - #include "stm32l151xc.h" -#elif defined(STM32L151xCA) - #include "stm32l151xca.h" -#elif defined(STM32L151xD) - #include "stm32l151xd.h" -#elif defined(STM32L151xDX) - #include "stm32l151xdx.h" -#elif defined(STM32L151xE) - #include "stm32l151xe.h" -#elif defined(STM32L152xB) - #include "stm32l152xb.h" -#elif defined(STM32L152xBA) - #include "stm32l152xba.h" -#elif defined(STM32L152xC) - #include "stm32l152xc.h" -#elif defined(STM32L152xCA) - #include "stm32l152xca.h" -#elif defined(STM32L152xD) - #include "stm32l152xd.h" -#elif defined(STM32L152xDX) - #include "stm32l152xdx.h" -#elif defined(STM32L152xE) - #include "stm32l152xe.h" -#elif defined(STM32L162xC) - #include "stm32l162xc.h" -#elif defined(STM32L162xCA) - #include "stm32l162xca.h" -#elif defined(STM32L162xD) - #include "stm32l162xd.h" -#elif defined(STM32L162xDX) - #include "stm32l162xdx.h" -#elif defined(STM32L162xE) - #include "stm32l162xe.h" -#else - #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l1xx_hal.h" -#endif /* USE_HAL_DRIVER */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L1xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_clock.c deleted file mode 100644 index 6d1889d50a1..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_clock.c +++ /dev/null @@ -1,252 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI - * | (external 24 MHz clock) | (internal 16 MHz) - * | 2- PLL_HSE_XTAL | - * | (external 24 MHz xtal) | - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 32 | 32 - *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 32 | 32 - *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 32 | 32 - *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 32 | 32 - *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | YES | NO - *----------------------------------------------------------------------------- - ****************************************************************************** - */ - -#include "stm32l1xx.h" -#include "stdio.h" -#include "mbed_debug.h" - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - -/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ -#define USE_PLL_HSE_EXTC (0) /* Use external clock */ -#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ - - -#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) -uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif - -uint8_t SetSysClock_PLL_HSI(void); - - -/** - * @brief Setup the microcontroller system. - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /*!< Set MSION bit */ - RCC->CR |= (uint32_t)0x00000100; - - /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ - RCC->CFGR &= (uint32_t)0x88FFC00C; - - /*!< Reset HSION, HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xEEFEFFFE; - - /*!< Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ - RCC->CFGR &= (uint32_t)0xFF02FFFF; - - /*!< Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - - -#if defined(__ICCARM__) -#pragma section=".intvec" -#define FLASH_VTOR_BASE ((uint32_t)__section_begin(".intvec")) -#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - extern uint32_t Load$$LR$$LR_IROM1$$Base[]; -#define FLASH_VTOR_BASE ((uint32_t)Load$$LR$$LR_IROM1$$Base) -#elif defined(__GNUC__) - extern uint32_t g_pfnVectors[]; -#define FLASH_VTOR_BASE ((uint32_t)g_pfnVectors) -#else -#error "Flash vector address not set for this toolchain" -#endif - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_VTOR_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif - -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -void SetSysClock(void) -{ - /* 1- Try to start with HSE and external clock */ -#if USE_PLL_HSE_EXTC != 0 - if (SetSysClock_PLL_HSE(1) == 0) -#endif - { - /* 2- If fail try to start with HSE and external xtal */ -#if USE_PLL_HSE_XTAL != 0 - if (SetSysClock_PLL_HSE(0) == 0) -#endif - { - /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) { - while(1) { - // [TODO] Put something here to tell the user that a problem occured... - } - } - } - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); -} - -#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Used to gain time after DeepSleep in case HSI is used */ - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { - return 0; - } - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 24 MHz xtal on OSC_IN/OSC_OUT */ - } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 24 MHz clock on OSC_IN */ - } - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - // SYSCLK = 32 MHz ((24 MHz * 4) / 3) - // USBCLK = 48 MHz ((24 MHz * 4) / 2) --> USB OK - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; - RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3; - - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //if (bypass == 0) - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - //else - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz - - return 1; // OK -} -#endif - -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSI oscillator and activate PLL with HSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - // SYSCLK = 32 MHz ((16 MHz * 4) / 2) - // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; - RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */ - while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {}; - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz - - return 1; // OK -} - - diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_stm32l1xx.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_stm32l1xx.h deleted file mode 100644 index ace20a831f9..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_stm32l1xx.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l1xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L1XX_H -#define __SYSTEM_STM32L1XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L1xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L1xx_System_Exported_types - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -/* -*/ -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L1XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/us_ticker_data.h deleted file mode 100644 index b32bd97db96..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/us_ticker_data.h +++ /dev/null @@ -1,45 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __US_TICKER_DATA_H -#define __US_TICKER_DATA_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "stm32l1xx.h" -#include "stm32l1xx_ll_tim.h" -#include "cmsis_nvic.h" - -#define TIM_MST TIM5 -#define TIM_MST_IRQ TIM5_IRQn -#define TIM_MST_RCC __TIM5_CLK_ENABLE() -#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() - -#define TIM_MST_RESET_ON __TIM5_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() - -#define TIM_MST_BIT_WIDTH 32 // 16 or 32 - -#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) - - -#ifdef __cplusplus -} -#endif - -#endif // __US_TICKER_DATA_H - diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/objects.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/objects.h deleted file mode 100644 index 6751a6a3c23..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/objects.h +++ /dev/null @@ -1,64 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - IRQn_Type irq_n; - uint32_t irq_index; - uint32_t event; - PinName pin; -}; - -struct port_s { - PortName port; - uint32_t mask; - PinDirection direction; - __IO uint32_t *reg_in; - __IO uint32_t *reg_out; -}; - -#define GPIO_IP_WITHOUT_BRR -#include "common_objects.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.c deleted file mode 100644 index e241fcd67c5..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.c +++ /dev/null @@ -1,287 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, MultiTech Systems - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of MultiTech nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "xdot_eeprom.h" - -#define XDOT_EEPROM_START 0x08080000 -#define XDOT_EEPROM_SIZE 0x00002000 - -typedef union { - uint32_t *w; - uint8_t *b; -} b2w; - -typedef union { - uint16_t *hw; - uint8_t *b; -} b2hw; - -enum { - byte_write = 0, - hword_write, - word_write -}; - -static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data) -{ - if (addr > XDOT_EEPROM_SIZE - 1) { - return -1; - } - - if (HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_BYTE, XDOT_EEPROM_START + addr, (uint32_t)data) != HAL_OK) { - return -1; - } else { - return 0; - } -} - -static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data) -{ - if (addr > XDOT_EEPROM_SIZE - 2) { - return -1; - } - - if (HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_HALFWORD, XDOT_EEPROM_START + addr, (uint32_t)data) != HAL_OK) { - return -1; - } else { - return 0; - } -} - -static int xdot_eeprom_write_word(uint32_t addr, uint32_t data) -{ - if (addr > XDOT_EEPROM_SIZE - 4) { - return -1; - } - - if (HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_WORD, XDOT_EEPROM_START + addr, (uint32_t)data) != HAL_OK) { - return -1; - } else { - return 0; - } -} - -static int xdot_eeprom_read_byte(uint32_t addr, uint8_t *data) -{ - if (addr > XDOT_EEPROM_SIZE - 1) { - return -1; - } - - *data = (*((uint8_t *)(XDOT_EEPROM_START + addr))); - - return 0; -} - - -int xdot_eeprom_write_buf(uint32_t addr, uint8_t *buf, uint32_t size) -{ - uint32_t bytes_written = 0; - - if (addr + size > XDOT_EEPROM_SIZE) { - return -1; - } - - HAL_FLASHEx_DATAEEPROM_Unlock(); - - while (bytes_written < size) { - uint32_t bytes_remaining = size - bytes_written; - uint32_t current_addr = addr + bytes_written; - uint8_t write_type = 0xFF; - uint8_t mismatch[4]; - uint8_t match_byte = 0xFF; - b2w byte2word; - b2hw byte2hword; - //printf("0x%04X (%lu) bytes remaining\r\n", bytes_remaining, bytes_remaining); - //printf("addr 0x%04X\t%d\r\n", current_addr, current_addr % 4); - - mismatch[0] = mismatch[1] = mismatch[2] = mismatch[3] = 0; - - if ((current_addr % 4 == 0) && bytes_remaining >= 4) { - // aligned for word write - //printf("aligned for word write\r\n"); - //printf("addr\tcurrent\t\tnew\r\n"); - for (int i = 0; i < 4; i++) { - if (xdot_eeprom_read_byte(current_addr + i, &match_byte)) { - HAL_FLASHEx_DATAEEPROM_Lock(); - return -1; - } - //printf("0x%04X\t0x%08X\t0x%08X\t", current_addr + i, match_byte, buf[bytes_written + i]); - if (match_byte != buf[bytes_written + i]) { - mismatch[i] = 1; - } - //printf("%smatch\r\n", mismatch[i] ? "mis" : ""); - } - if (!(mismatch[0] || mismatch[1] || mismatch[2] || mismatch[3])) { - //printf("all match - no write necessary\r\n"); - bytes_written += 4; - continue; - } - if ((mismatch[0] || mismatch[1]) && (mismatch[2] || mismatch[3])) { - // if at least one of byte 1 or byte 2 and one of byte 3 or byte 4 needs to be written, write a word - // this should also account for all 3 or 4 byte combinations as well - write_type = word_write; - } else if ((mismatch[0] && mismatch[1]) || (mismatch[2] && mismatch[3])) { - // if only bytes 1 and 2 or only bytes 3 and 4 need to be written, write a half-word - write_type = hword_write; - // increment bytes_written if we're skipping bytes that match - if (mismatch[2] && mismatch[3]) { - bytes_written += 2; - current_addr += 2; - } - } else if (mismatch[0] || mismatch[1] || mismatch[2] || mismatch[3]) { - // anything else is just a byte write - write_type = byte_write; - // increment bytes_written if we're skipping bytes that match - if (mismatch[1]) { - bytes_written += 1; - current_addr += 1; - } else if (mismatch[2]) { - bytes_written += 2; - current_addr += 2; - } else if (mismatch[3]) { - bytes_written += 3; - current_addr += 3; - } - } - } else if ((current_addr % 2 == 0) && bytes_remaining >= 2) { - // aligned for half word write - //printf("aligned for half word write\r\n"); - //printf("addr\tcurrent\t\tnew\r\n"); - for (int i = 0; i < 2; i++) { - if (xdot_eeprom_read_byte(current_addr + i, &match_byte)) { - HAL_FLASHEx_DATAEEPROM_Lock(); - return -1; - } - //printf("0x%04X\t0x%08X\t0x%08X\t", current_addr + i, match_byte, buf[bytes_written + i]); - if (match_byte != buf[bytes_written + i]) { - mismatch[i] = 1; - } - //printf("%smatch\r\n", mismatch[i] ? "mis" : ""); - } - if (!(mismatch[0] || mismatch[1])) { - //printf("all match - no write necessary\r\n"); - bytes_written += 2; - continue; - } - if (mismatch[0] && mismatch[1]) { - // if bytes 1 and 2 need to be written, we truly want to write a half word - write_type = hword_write; - } else { - // anything else is just a byte write - write_type = byte_write; - // increment bytes_written if we're skipping bytes that match - if (mismatch[1]) { - bytes_written += 1; - current_addr += 1; - } - } - } else { - // aligned for byte write - //printf("aligned for byte write\r\n"); - //printf("addr\tcurrent\t\tnew\r\n"); - for (int i = 0; i < 1; i++) { - if (xdot_eeprom_read_byte(current_addr + i, &match_byte)) { - HAL_FLASHEx_DATAEEPROM_Lock(); - return -1; - } - //printf("0x%04X\t0x%08X\t0x%08X\t", current_addr + i, match_byte, buf[bytes_written + i]); - if (match_byte != buf[bytes_written + i]) { - mismatch[i] = 1; - } - //printf("%smatch\r\n", mismatch[i] ? "mis" : ""); - } - if (! mismatch[0]) { - //printf("all match - no write necessary\r\n"); - bytes_written += 1; - continue; - } - write_type = byte_write; - } - - switch (write_type) { - case word_write: - // we can write a word (32 bits) - //printf("word write\r\n"); - byte2word.b = buf + bytes_written; - if (xdot_eeprom_write_word(current_addr, *byte2word.w)) { - HAL_FLASHEx_DATAEEPROM_Lock(); - return -1; - } - bytes_written += 4; - break; - case hword_write: - // we can write a half-word (16 bits) - //printf("half-word write\r\n"); - byte2hword.b = buf + bytes_written; - if (xdot_eeprom_write_hword(current_addr, *byte2hword.hw)) { - HAL_FLASHEx_DATAEEPROM_Lock(); - return -1; - } - bytes_written += 2; - break; - case byte_write: - // we can write a byte (8 bits) - //printf("byte write\r\n"); - if (xdot_eeprom_write_byte(current_addr, buf[bytes_written])) { - HAL_FLASHEx_DATAEEPROM_Lock(); - return -1; - } - bytes_written += 1; - break; - default: - //printf("no write needed\r\n"); - break; - } - } - - HAL_FLASHEx_DATAEEPROM_Lock(); - - return 0; -} - -int xdot_eeprom_read_buf(uint32_t addr, uint8_t *buf, uint32_t size) -{ - if (addr + size > XDOT_EEPROM_SIZE) { - return -1; - } - - HAL_FLASHEx_DATAEEPROM_Unlock(); - - for (uint32_t i = 0; i < size; i++) { - if (xdot_eeprom_read_byte(addr + i, buf + i)) { - HAL_FLASHEx_DATAEEPROM_Lock(); - return -1; - } - } - - HAL_FLASHEx_DATAEEPROM_Lock(); - - return 0; -} diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.h deleted file mode 100644 index 76bed5aa120..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.h +++ /dev/null @@ -1,63 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, MultiTech Systems - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of MultiTech nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef __XDOT_EEPROM_H__ -#define __XDOT_EEPROM_H__ - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* xdot_eeprom_write_buf - * attempts to write size bytes from buf to addr - * implements read-before-write because writes are expensive - * uses most efficient write possible (byte, half-word, or word write) based on alignment - * and number of bytes that need to be written - * buf must be non-null and size bytes or larger - * valid addresses are 0x0000 - 0x1FFF - * returns 0 if all data was successfully written otherwise -1 - */ -int xdot_eeprom_write_buf(uint32_t addr, uint8_t *buf, uint32_t size); - -/* xdot_eeprom_read_buf - * attempts to read size bytes into buf starting at addr - * buf must be non-null and size bytes or larger - * valid addresses are 0x0000 - 0x1FFF - * returns 0 if all data was successfully read otherwise -1 - */ -int xdot_eeprom_read_buf(uint32_t addr, uint8_t *buf, uint32_t size); - -#ifdef __cplusplus -} -#endif - -#endif /* __XDOT_EEPROM_H__ */ diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_low_power.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_low_power.c deleted file mode 100644 index 7ac5efd4e32..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_low_power.c +++ /dev/null @@ -1,313 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, MultiTech Systems - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of MultiTech nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "xdot_low_power.h" -#include "stdio.h" -#include "mbed_debug.h" - -static uint32_t portA[6]; -static uint32_t portB[6]; -static uint32_t portC[6]; -static uint32_t portH[6]; - -void xdot_disable_systick_int() -{ - SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; -} - -void xdot_enable_systick_int() -{ - SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; -} - -void xdot_save_gpio_state() -{ - portA[0] = GPIOA->MODER; - portA[1] = GPIOA->OTYPER; - portA[2] = GPIOA->OSPEEDR; - portA[3] = GPIOA->PUPDR; - portA[4] = GPIOA->AFR[0]; - portA[5] = GPIOA->AFR[1]; - - portB[0] = GPIOB->MODER; - portB[1] = GPIOB->OTYPER; - portB[2] = GPIOB->OSPEEDR; - portB[3] = GPIOB->PUPDR; - portB[4] = GPIOB->AFR[0]; - portB[5] = GPIOB->AFR[1]; - - portC[0] = GPIOC->MODER; - portC[1] = GPIOC->OTYPER; - portC[2] = GPIOC->OSPEEDR; - portC[3] = GPIOC->PUPDR; - portC[4] = GPIOC->AFR[0]; - portC[5] = GPIOC->AFR[1]; - - portH[0] = GPIOH->MODER; - portH[1] = GPIOH->OTYPER; - portH[2] = GPIOH->OSPEEDR; - portH[3] = GPIOH->PUPDR; - portH[4] = GPIOH->AFR[0]; - portH[5] = GPIOH->AFR[1]; -} - -void xdot_restore_gpio_state() -{ - GPIOA->MODER = portA[0]; - GPIOA->OTYPER = portA[1]; - GPIOA->OSPEEDR = portA[2]; - GPIOA->PUPDR = portA[3]; - GPIOA->AFR[0] = portA[4]; - GPIOA->AFR[1] = portA[5]; - - GPIOB->MODER = portB[0]; - GPIOB->OTYPER = portB[1]; - GPIOB->OSPEEDR = portB[2]; - GPIOB->PUPDR = portB[3]; - GPIOB->AFR[0] = portB[4]; - GPIOB->AFR[1] = portB[5]; - - GPIOC->MODER = portC[0]; - GPIOC->OTYPER = portC[1]; - GPIOC->OSPEEDR = portC[2]; - GPIOC->PUPDR = portC[3]; - GPIOC->AFR[0] = portC[4]; - GPIOC->AFR[1] = portC[5]; - - GPIOH->MODER = portH[0]; - GPIOH->OTYPER = portH[1]; - GPIOH->OSPEEDR = portH[2]; - GPIOH->PUPDR = portH[3]; - GPIOH->AFR[0] = portH[4]; - GPIOH->AFR[1] = portH[5]; -} - -void xdot_enter_stop_mode() -{ - GPIO_InitTypeDef GPIO_InitStruct; - - // disable ADC and DAC - they can consume power in stop mode - ADC1->CR2 &= ~ADC_CR2_ADON; - ADC->CCR &= ~ADC_CCR_TSVREFE; - DAC->CR &= ~DAC_CR_EN1; - DAC->CR &= ~DAC_CR_EN2; - - // enable ULP and enable fast wakeup - HAL_PWREx_EnableUltraLowPower(); - HAL_PWREx_EnableFastWakeUp(); - - // disable HSI, MSI, and LSI if they are running - if (RCC->CR & RCC_CR_HSION) { - RCC->CR &= ~RCC_CR_HSION; - } - if (RCC->CR & RCC_CR_MSION) { - RCC->CR &= ~RCC_CR_MSION; - } - if (RCC->CSR & RCC_CSR_LSION) { - RCC->CSR &= ~RCC_CSR_LSION; - } - - // configure USBTX & USBRX, LORA SPI, LORA_DIO, LORA_RESET, Secure Element, crystal pins, and SWD pins to analog nopull - // the application must do the same with WAKE, GPIO*, UART1_*, I2C_*, and SPI_* - - // GPIO Ports Clock Enable - __GPIOA_CLK_ENABLE(); - __GPIOB_CLK_ENABLE(); - __GPIOC_CLK_ENABLE(); - __GPIOH_CLK_ENABLE(); - - // USBTX & USBRX to analog nopull - GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - // LORA_RESET to analog nopull - GPIO_InitStruct.Pin = GPIO_PIN_1; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - // LORA_MISO to analog nopull - GPIO_InitStruct.Pin = GPIO_PIN_4; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - // LORA_SCK & LORA_MOSI to input pulldown - additional current draw if left floating - GPIO_InitStruct.Pin = GPIO_PIN_3 | GPIO_PIN_5; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_PULLDOWN; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - // LORA_NSS to analog nopull - GPIO_InitStruct.Pin = GPIO_PIN_15; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - // LORA_DIO0 - LORA_DIO2 to analog nopull - GPIO_InitStruct.Pin = GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - // LORA_DIO3 - LORA_DIO4 to analog nopull - GPIO_InitStruct.Pin = GPIO_PIN_6 | GPIO_PIN_7; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - // SE_CTRL, SE_IO, & SE_CLK to analog nopull - GPIO_InitStruct.Pin = GPIO_PIN_1 | GPIO_PIN_10 | GPIO_PIN_11; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - // SE_RESET to analog nopull - GPIO_InitStruct.Pin = GPIO_PIN_13; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - // SWDIO & SWCLK to analog nopull - GPIO_InitStruct.Pin = GPIO_PIN_13 | GPIO_PIN_14; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - // OSC32_IN & OSC32_OUT to analog nopull - GPIO_InitStruct.Pin = GPIO_PIN_14 | GPIO_PIN_15; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - // OSC_IN & OSC_OUT to analog nopull - GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - - // done configuring pins to analog nopull - - // make sure wakeup flag is cleared - PWR->CR |= PWR_CR_CWUF; - - // enter stop mode - don't execute past here until woken up - HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); - - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef HSERCC_OscInitStruct; - /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */ - HSERCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; - HSERCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 24 MHz xtal on OSC_IN/OSC_OUT */ - HSERCC_OscInitStruct.HSIState = RCC_HSI_OFF; - // SYSCLK = 32 MHz ((24 MHz * 4) / 3) - // USBCLK = 48 MHz ((24 MHz * 4) / 2) --> USB OK - HSERCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - HSERCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - HSERCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; - HSERCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3; - if (HAL_RCC_OscConfig(&HSERCC_OscInitStruct) != HAL_OK) { - debug("OSC initialization failed - initiating soft reset\r\n"); - NVIC_SystemReset(); - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { - debug("PLL initialization failed - initiating soft reset\r\n"); - NVIC_SystemReset(); - } - - /* Enable the HSI for ADC peripherals */ - RCC_OscInitTypeDef HSIRCC_OscInitStruct; - HAL_RCC_GetOscConfig(&HSIRCC_OscInitStruct); - if (HSIRCC_OscInitStruct.HSIState != RCC_HSI_ON) { - HSIRCC_OscInitStruct.HSIState = RCC_HSI_ON; - HSIRCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - HSIRCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - HAL_StatusTypeDef ret = HAL_RCC_OscConfig(&HSIRCC_OscInitStruct); - if (ret != HAL_OK) { - debug("HSI initialization failed - ADC will not function properly\r\n"); - } - } - - SystemCoreClockUpdate(); - - // clear wakeup flag in power control register - PWR->CR |= PWR_CR_CWUF; - - // enable the ADC and DAC - ADC->CCR |= ADC_CCR_TSVREFE; - ADC1->CR2 |= ADC_CR2_ADON; - DAC->CR |= DAC_CR_EN1; - DAC->CR |= DAC_CR_EN2; -} - -void xdot_enter_standby_mode() -{ - // enable ULP and enable fast wakeup - HAL_PWREx_EnableUltraLowPower(); - HAL_PWREx_EnableFastWakeUp(); - - // disable HSI, MSI, and LSI if they are running - if (RCC->CR & RCC_CR_HSION) { - RCC->CR &= ~RCC_CR_HSION; - } - if (RCC->CR & RCC_CR_MSION) { - RCC->CR &= ~RCC_CR_MSION; - } - if (RCC->CSR & RCC_CSR_LSION) { - RCC->CSR &= ~RCC_CSR_LSION; - } - - - // make sure wakeup and standby flags are cleared - PWR->CR |= PWR_CR_CWUF; - PWR->CR |= PWR_CR_CSBF; - - // enter standby mode - HAL_PWR_EnterSTANDBYMode(); -} - -void xdot_enable_standby_wake_pin() -{ - HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN1); -} - -void xdot_disable_standby_wake_pin() -{ - HAL_PWR_DisableWakeUpPin(PWR_WAKEUP_PIN1); -} diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_low_power.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_low_power.h deleted file mode 100644 index 1edd7ee6fc7..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_low_power.h +++ /dev/null @@ -1,105 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, MultiTech Systems - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of MultiTech nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef __XDOT_LOW_POWER_H__ -#define __XDOT_LOW_POWER_H__ - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* xdot_disable_systick_int - * disable the systick interrupt - * call this before xdot_enter_stop_mode so systick interrupt doesn't wake up the processor - * only necessary if RTOS is used - */ -void xdot_disable_systick_int(); - -/* xdot_enable_systick_int - * enable the systick interrupt - * call this after xdot_enter_stop_mode so RTOS can function again - * only necessary if RTOS is used - */ -void xdot_enable_systick_int(); - -/* xdot_save_gpio_state - * save current state of all GPIOs - * call this before xdot_enter_stop_mode - * to achieve the lowest possible power consumption possible all GPIO pins must be configured for - * analog mode with no pull resistors enabled before entering STOP mode - * the xdot_enter_stop_mode function does this for USBTX/RX and all internal pins - * after calling xdot_save_gpio_state, the user application must do the same for WAKE, GPIO*, - * UART1_*, I2C_*, and SPI_* pins - * the user application should make a call to xdot_restore_gpio_state after waking from STOP mode - * in order to restore GPIO functionality - */ -void xdot_save_gpio_state(); - -/* xdot_restore_gpio_state - * restore all GPIOs to the state they were in when xdot_save_gpio_state was called - * call this after exiting from STOP mode - */ -void xdot_restore_gpio_state(); - -/* xdot_enter_stop_mode - * put the processor into STOP mode - * RAM and peripheral state is retained - * can be woken up by a number of interrupt sources including GPIOs and internal interrupts - * program execution resumes after this function when the device wakes up - */ -void xdot_enter_stop_mode(); - -/* xdot_enter_standby_mode - * put the processor into STANDBY mode - * RAM and peripheral state is lost - * can be woken up by the RTC alarm and rising edge on WAKE pin (WAKE pin must be configured first) - * program execution starts from the beginning of the application when the device wakes up - */ -void xdot_enter_standby_mode(); - -/* xdot_enable_standby_wake_pin - * configure the WAKE pin as a wakeup source from standby mode - * after this call, a rising edge on the WAKE pin will wake the processor up from standby mode - * this function should be called immediately before xdot_enter_standby_mode - */ -void xdot_enable_standby_wake_pin(); - -/* xdot_disnable_standby_wake_pin - * should be called after waking up from standby mode - */ -void xdot_disable_standby_wake_pin(); - -#ifdef __cplusplus -} -#endif - -#endif /* __XDOT_LOW_POWER_H__ */ diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PeripheralNames.h deleted file mode 100644 index c9640bdc938..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PeripheralNames.h +++ /dev/null @@ -1,77 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE -} ADCName; - -typedef enum { - DAC_1 = (int)DAC_BASE -} DACName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE -} UARTName; - -#define DEVICE_SPI_COUNT 2 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE -} I2CName; - -typedef enum { - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE, // used as us_ticker - PWM_9 = (int)TIM9_BASE, - PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE -} PWMName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PeripheralPins.c deleted file mode 100644 index f7ca4e34f01..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PeripheralPins.c +++ /dev/null @@ -1,128 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "PeripheralPins.h" - -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== - -//*** ADC *** - -const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1 - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - {PB_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18 - {PB_14, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC_IN20 - {PB_15, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 21, 0)}, // ADC_IN21 - {NC, NC, 0} -}; - -const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, - {NC, NC, 0} -}; - -//*** DAC *** - -const PinMap PinMap_DAC[] = { - {NC, NC, 0} -}; - -//*** I2C *** - -const PinMap PinMap_I2C_SDA[] = { - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM5 cannot be used because already used by the us_ticker. -const PinMap PinMap_PWM[] = { - {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {NC, NC, 0} -}; - -//*** SERIAL *** - -const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {NC, NC, 0} -}; - -//*** SPI *** - -const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PinNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PinNames.h deleted file mode 100644 index 3550637433d..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PinNames.h +++ /dev/null @@ -1,148 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PA_0 = 0x00, - PA_1 = 0x01, - PA_2 = 0x02, - PA_3 = 0x03, - PA_4 = 0x04, - PA_5 = 0x05, - PA_6 = 0x06, - PA_7 = 0x07, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - - PB_0 = 0x10, - PB_1 = 0x11, - PB_2 = 0x12, // not used - PB_3 = 0x13, - PB_4 = 0x14, - PB_5 = 0x15, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_9 = 0x19, - PB_10 = 0x1A, - PB_11 = 0x1B, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_14 = 0x1E, - PB_15 = 0x1F, - - PC_13 = 0x2D, - PC_14 = 0x2E, // not used ? - PC_15 = 0x2F, // not used ? - - PH_0 = 0x70, - PH_1 = 0x71, // not used ? - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - - ADC1_0 = PB_14, - ADC1_1 = PB_15, - ADC1_2 = PB_12, - - UARTn_RX = PA_10, - UARTn_TX = PA_9, - - SPI_RF_MOSI = PA_7, - SPI_RF_MISO = PA_6, - SPI_RF_SCK = PA_5, - SPI_RF_CS = PB_0, - SPI_RF_RESET = PB_13, - - DIO0 = PA_11, - DIO1 = PB_1, - DIO2 = PA_3, - DIO3 = PH_0, - DIO4 = PC_13, - //DIO5 = , - - ANT_CTX_PA = PA_4, - ANT_CRX_RX = PB_6, - ANT_CBT_HF = PB_7, - RF_TCXO_EN = PH_1, - - SPI_MISO = PB_4, - SPI_MOSI = PB_5, - SPI_SCK = PB_3, - FLASH_CS = PA_15, - - I2C_SCL = PB_8, - I2C_SDA = PB_0, - - LCD_A0 = PA_8, - LCD_nCS = PA_1, - LCD_nRESET = PA_2, - - // Generic signals namings - LED1 = PA_12, // red - LED2 = PB_10, // blue - LED3 = PB_11, // green - USER_BUTTON = PA_0, - - STDIO_UART_RX = PA_10, - STDIO_UART_TX = PA_9, - - // aliases - POT = ADC1_2, - BUTTON1 = USER_BUTTON, - SERIAL_TX = STDIO_UART_TX, - SERIAL_RX = STDIO_UART_RX, - USBTX = STDIO_UART_TX, - USBRX = STDIO_UART_RX, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xba.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xba.S deleted file mode 100644 index 4b7709241d5..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xba.S +++ /dev/null @@ -1,278 +0,0 @@ -;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32l151xb.s -;* Author : MCD Application Team -;* Version : V2.2.0 -;* Date : 01-July-2016 -;* Description : STM32L151XB Devices vector for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* COPYRIGHT(c) 2016 STMicroelectronics -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp - DCD RTC_WKUP_IRQHandler ; RTC Wakeup - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD USB_HP_IRQHandler ; USB High Priority - DCD USB_LP_IRQHandler ; USB Low Priority - DCD DAC_IRQHandler ; DAC - DCD COMP_IRQHandler ; COMP through EXTI Line - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD 0 ; Reserved - DCD TIM9_IRQHandler ; TIM9 - DCD TIM10_IRQHandler ; TIM10 - DCD TIM11_IRQHandler ; TIM11 - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT USB_HP_IRQHandler [WEAK] - EXPORT USB_LP_IRQHandler [WEAK] - EXPORT DAC_IRQHandler [WEAK] - EXPORT COMP_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM9_IRQHandler [WEAK] - EXPORT TIM10_IRQHandler [WEAK] - EXPORT TIM11_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USB_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_IRQHandler -USB_HP_IRQHandler -USB_LP_IRQHandler -DAC_IRQHandler -COMP_IRQHandler -EXTI9_5_IRQHandler -TIM9_IRQHandler -TIM10_IRQHandler -TIM11_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -USB_FS_WKUP_IRQHandler -TIM6_IRQHandler -TIM7_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_MICRO/stm32l151cba.sct b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_MICRO/stm32l151cba.sct deleted file mode 100644 index faa62adce06..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_MICRO/stm32l151cba.sct +++ /dev/null @@ -1,76 +0,0 @@ -#! armcc -E -; Scatter-Loading Description File -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2015, STMicroelectronics -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 -#endif - -; STM32L151CB: 128KB FLASH -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x20000 -#endif - -; 32KB SRAM -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x20000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x8000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 61 vectors = 244 bytes (0xF4) 8-byte aligned = 0xF8 (0xF4 + 0x4) to be reserved in RAM -#define VECTOR_SIZE 0xF8 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_STD/startup_stm32l151xba.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_STD/startup_stm32l151xba.S deleted file mode 100644 index 4b7709241d5..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_STD/startup_stm32l151xba.S +++ /dev/null @@ -1,278 +0,0 @@ -;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32l151xb.s -;* Author : MCD Application Team -;* Version : V2.2.0 -;* Date : 01-July-2016 -;* Description : STM32L151XB Devices vector for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* COPYRIGHT(c) 2016 STMicroelectronics -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp - DCD RTC_WKUP_IRQHandler ; RTC Wakeup - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD USB_HP_IRQHandler ; USB High Priority - DCD USB_LP_IRQHandler ; USB Low Priority - DCD DAC_IRQHandler ; DAC - DCD COMP_IRQHandler ; COMP through EXTI Line - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD 0 ; Reserved - DCD TIM9_IRQHandler ; TIM9 - DCD TIM10_IRQHandler ; TIM10 - DCD TIM11_IRQHandler ; TIM11 - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT USB_HP_IRQHandler [WEAK] - EXPORT USB_LP_IRQHandler [WEAK] - EXPORT DAC_IRQHandler [WEAK] - EXPORT COMP_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM9_IRQHandler [WEAK] - EXPORT TIM10_IRQHandler [WEAK] - EXPORT TIM11_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USB_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_IRQHandler -USB_HP_IRQHandler -USB_LP_IRQHandler -DAC_IRQHandler -COMP_IRQHandler -EXTI9_5_IRQHandler -TIM9_IRQHandler -TIM10_IRQHandler -TIM11_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -USB_FS_WKUP_IRQHandler -TIM6_IRQHandler -TIM7_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_STD/stm32l151cba.sct b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_STD/stm32l151cba.sct deleted file mode 100644 index a542c6a2138..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_STD/stm32l151cba.sct +++ /dev/null @@ -1,53 +0,0 @@ -#! armcc -E -; Scatter-Loading Description File -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2015, STMicroelectronics -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -; STM32L151CB: 128KB FLASH + 32KB SRAM -LR_IROM1 0x08000000 0x20000 { ; load region size_region - - ER_IROM1 0x08000000 0x20000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - ; 61 vectors = 244 bytes (0xF4) 8-byte aligned = 0xF8 (0xF4 + 0x4) to be reserved in RAM - RW_IRAM1 (0x20000000+0xF8) (0x8000-0xF8-Stack_Size) { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_STACK (0x20000000+0x8000) EMPTY -Stack_Size { ; stack - } -} - diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_GCC_ARM/STM32L151XB-A.ld b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_GCC_ARM/STM32L151XB-A.ld deleted file mode 100644 index 589c7489f63..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_GCC_ARM/STM32L151XB-A.ld +++ /dev/null @@ -1,164 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - /* 128KB FLASH, 32KB RAM, Reserve up till 0xF4. There are 61 vectors = 244 - * bytes (0xF4) in RAM. 8-byte aligned(0xF4) = 0xF8 - */ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128k - RAM (rwx) : ORIGIN = 0x200000F8, LENGTH = 0x8000-0xF8 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * _estack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - _sidata = .; - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xba.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xba.S deleted file mode 100644 index 4eb489bf738..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xba.S +++ /dev/null @@ -1,363 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32l151xb.s - * @author MCD Application Team - * @version V2.2.0 - * @date 01-July-2016 - * @brief STM32L151XB Devices vector table for - * Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system intitialization function.*/ - bl SystemInit - -/** - * Calling the crt0 'cold-start' entry point. There __libc_init_array is called - * and when existing hardware_init_hook() and software_init_hook() before - * starting main(). software_init_hook() is available and has to be called due - * to initializsation when using rtos. -*/ - bl _start - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_STAMP_IRQHandler - .word RTC_WKUP_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_IRQHandler - .word USB_HP_IRQHandler - .word USB_LP_IRQHandler - .word DAC_IRQHandler - .word COMP_IRQHandler - .word EXTI9_5_IRQHandler - .word 0 - .word TIM9_IRQHandler - .word TIM10_IRQHandler - .word TIM11_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word USB_FS_WKUP_IRQHandler - .word TIM6_IRQHandler - .word TIM7_IRQHandler - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_STAMP_IRQHandler - .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak USB_HP_IRQHandler - .thumb_set USB_HP_IRQHandler,Default_Handler - - .weak USB_LP_IRQHandler - .thumb_set USB_LP_IRQHandler,Default_Handler - - .weak DAC_IRQHandler - .thumb_set DAC_IRQHandler,Default_Handler - - .weak COMP_IRQHandler - .thumb_set COMP_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM9_IRQHandler - .thumb_set TIM9_IRQHandler,Default_Handler - - .weak TIM10_IRQHandler - .thumb_set TIM10_IRQHandler,Default_Handler - - .weak TIM11_IRQHandler - .thumb_set TIM11_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak USB_FS_WKUP_IRQHandler - .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_IAR/startup_stm32l151xba.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_IAR/startup_stm32l151xba.S deleted file mode 100644 index 7f9d93bea85..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_IAR/startup_stm32l151xba.S +++ /dev/null @@ -1,471 +0,0 @@ -;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32l152xc.s -;* Author : MCD Application Team -;* Version : V2.2.0 -;* Date : 01-July-2016 -;* Description : STM32L152XC Devices vector for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;*

© COPYRIGHT(c) 2016 STMicroelectronics

-;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp - DCD RTC_WKUP_IRQHandler ; RTC Wakeup - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD USB_HP_IRQHandler ; USB High Priority - DCD USB_LP_IRQHandler ; USB Low Priority - DCD DAC_IRQHandler ; DAC - DCD COMP_IRQHandler ; COMP through EXTI Line - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD 0 ; Reserved - DCD TIM9_IRQHandler ; TIM9 - DCD TIM10_IRQHandler ; TIM10 - DCD TIM11_IRQHandler ; TIM11 - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PVD_IRQHandler - B PVD_IRQHandler - - - PUBWEAK TAMPER_STAMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TAMPER_STAMP_IRQHandler - B TAMPER_STAMP_IRQHandler - - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RCC_IRQHandler - B RCC_IRQHandler - - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - - PUBWEAK DMA1_Channel5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel5_IRQHandler - B DMA1_Channel5_IRQHandler - - - PUBWEAK DMA1_Channel6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel6_IRQHandler - B DMA1_Channel6_IRQHandler - - - PUBWEAK DMA1_Channel7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel7_IRQHandler - B DMA1_Channel7_IRQHandler - - - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC1_IRQHandler - B ADC1_IRQHandler - - - PUBWEAK USB_HP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_HP_IRQHandler - B USB_HP_IRQHandler - - - PUBWEAK USB_LP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_LP_IRQHandler - B USB_LP_IRQHandler - - - PUBWEAK DAC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DAC_IRQHandler - B DAC_IRQHandler - - - PUBWEAK COMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -COMP_IRQHandler - B COMP_IRQHandler - - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - - PUBWEAK TIM9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM9_IRQHandler - B TIM9_IRQHandler - - - PUBWEAK TIM10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM10_IRQHandler - B TIM10_IRQHandler - - - PUBWEAK TIM11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM11_IRQHandler - B TIM11_IRQHandler - - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_IRQHandler - B USART1_IRQHandler - - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_IRQHandler - B USART2_IRQHandler - - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_IRQHandler - B USART3_IRQHandler - - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - - PUBWEAK USB_FS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_FS_WKUP_IRQHandler - B USB_FS_WKUP_IRQHandler - - - PUBWEAK TIM6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM6_IRQHandler - B TIM6_IRQHandler - - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_IAR/stm32l152xba.icf b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_IAR/stm32l152xba.icf deleted file mode 100644 index bf7fd0bc684..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_IAR/stm32l152xba.icf +++ /dev/null @@ -1,35 +0,0 @@ -if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } -if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x20000; } -/* [ROM = 128kb = 0x20000] */ -define symbol __intvec_start__ = MBED_APP_START; -define symbol __region_ROM_start__ = MBED_APP_START; -define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; - -/* [RAM = 32kb = 0x8000] Vector table dynamic copy: 61 vectors = 244 bytes (0xF4) to be reserved in RAM */ -define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x200000F7; /* Add 4 more bytes to be aligned on 8 bytes */ -define symbol __region_RAM_start__ = 0x200000F8; -define symbol __region_RAM_end__ = 0x20007FFF; - -/* Memory regions */ -define memory mem with size = 4G; -define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; -define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; - -/* Stack and Heap */ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __size_heap__ = 0x800; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block STACKHEAP with fixed order { block HEAP, block CSTACK }; - -initialize by copy with packing = zeros { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, block STACKHEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/cmsis_nvic.h deleted file mode 100644 index 24903430612..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/cmsis_nvic.h +++ /dev/null @@ -1,41 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -// STM32L151CB -// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F -// MCU Peripherals: 45 vectors = 180 bytes from 0x40 to 0xF3 -// Total: 61 vectors = 244 bytes (0xF4) to be reserved in RAM -#define NVIC_NUM_VECTORS 61 -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/stm32l151xba.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/stm32l151xba.h deleted file mode 100644 index 961dae32750..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/stm32l151xba.h +++ /dev/null @@ -1,8167 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l151xba.h - * @author MCD Application Team - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32L1xx devices. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l151xba - * @{ - */ - -#ifndef __STM32L151xBA_H -#define __STM32L151xBA_H - -#ifdef __cplusplus - extern "C" { -#endif - - - /** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ -#define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */ -#define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32L1xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - - /*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32L specific Interrupt Numbers ***********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ - USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ - DAC_IRQn = 21, /*!< DAC Interrupt */ - COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ - TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ - TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ - TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32l1xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ - __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ - uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx - * @{ - */ - -#ifndef __STM32L1XX_H -#define __STM32L1XX_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L1) -#define STM32L1 -#endif /* STM32L1 */ - -//MODTRONIX BEGIN - HAL Defines /////////////////////////////////////////////// -//Provide place for adding HAL defines. Alternative to adding them in IDE project properties. -//Add project defines here, or add them to your toolchain compiler preprocessor - -//Defines what ports to use for default serial port. -//0 = B10/B11 -//1 = A2/A3 -#if !defined (MX_DEFAULT_SERIAL_PINS) -#define MX_DEFAULT_SERIAL_PINS 0 /*!< Use B10/B11 for default serial port, in stead of A2/A3 */ -#endif - -//MODTRONIX END /////////////////////////////////////////////////////////////// - -/* Uncomment the line below according to the target STM32L device used in your - application - */ - -#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \ - !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xDX) && !defined (STM32L151xE) && \ - !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xDX) && !defined (STM32L152xE) && \ - !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xDX) && !defined (STM32L162xE) - /* #define STM32L100xB */ /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */ - /* #define STM32L100xBA */ /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */ - /* #define STM32L100xC */ /*!< STM32L100RC Devices */ - /* #define STM32L151xB */ /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */ - #define STM32L151xBA /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */ - /* #define STM32L151xC */ /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */ - /* #define STM32L151xCA */ /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */ - /* #define STM32L151xD */ /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */ - /* #define STM32L151xDX */ /*!< STM32L151VD-X Devices */ - /* #define STM32L151xE */ /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */ - /* #define STM32L152xB */ /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */ - /* #define STM32L152xBA */ /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */ - /* #define STM32L152xC */ /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */ - /* #define STM32L152xCA */ /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */ - /* #define STM32L152xD */ /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */ - /* #define STM32L152xDX */ /*!< STM32L152VD-X Devices */ - /* #define STM32L152xE */ /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */ - /* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */ - /* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */ - /* #define STM32L162xD */ /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */ - /* #define STM32L162xDX */ /*!< STM32L162VD-X Devices */ - /* #define STM32L162xE */ /*!< STM32L162RE, STM32L162VE and STM32L162ZE */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ -#define USE_HAL_DRIVER -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number - */ -#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ -#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L1xx_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L1xx_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L100xB) - #include "stm32l100xb.h" -#elif defined(STM32L100xBA) - #include "stm32l100xba.h" -#elif defined(STM32L100xC) - #include "stm32l100xc.h" -#elif defined(STM32L151xB) - #include "stm32l151xb.h" -#elif defined(STM32L151xBA) - #include "stm32l151xba.h" -#elif defined(STM32L151xC) - #include "stm32l151xc.h" -#elif defined(STM32L151xCA) - #include "stm32l151xca.h" -#elif defined(STM32L151xD) - #include "stm32l151xd.h" -#elif defined(STM32L151xDX) - #include "stm32l151xdx.h" -#elif defined(STM32L151xE) - #include "stm32l151xe.h" -#elif defined(STM32L152xB) - #include "stm32l152xb.h" -#elif defined(STM32L152xBA) - #include "stm32l152xba.h" -#elif defined(STM32L152xC) - #include "stm32l152xc.h" -#elif defined(STM32L152xCA) - #include "stm32l152xca.h" -#elif defined(STM32L152xD) - #include "stm32l152xd.h" -#elif defined(STM32L152xDX) - #include "stm32l152xdx.h" -#elif defined(STM32L152xE) - #include "stm32l152xe.h" -#elif defined(STM32L162xC) - #include "stm32l162xc.h" -#elif defined(STM32L162xCA) - #include "stm32l162xca.h" -#elif defined(STM32L162xD) - #include "stm32l162xd.h" -#elif defined(STM32L162xDX) - #include "stm32l162xdx.h" -#elif defined(STM32L162xE) - #include "stm32l162xe.h" -#else - #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l1xx_hal.h" -#endif /* USE_HAL_DRIVER */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L1xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/system_clock.c deleted file mode 100644 index ba597ba08c1..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/system_clock.c +++ /dev/null @@ -1,154 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI - * | (external 16 MHz clock) | (internal 16 MHz) - * | 2- PLL_HSE_XTAL | - * | (external 16 MHz xtal) | - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 32 | 32 - *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 32 | 32 - *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 32 | 32 - *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 32 | 32 - *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | YES | NO - *----------------------------------------------------------------------------- - ****************************************************************************** - */ - -#include "stm32l1xx.h" - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - -uint8_t SetSysClock_PLL_HSI(void); - - -/** - * @brief Setup the microcontroller system. - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /*!< Set MSION bit */ - RCC->CR |= (uint32_t)0x00000100; - - /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ - RCC->CFGR &= (uint32_t)0x88FFC00C; - - /*!< Reset HSION, HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xEEFEFFFE; - - /*!< Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ - RCC->CFGR &= (uint32_t)0xFF02FFFF; - - /*!< Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif - -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -void SetSysClock(void) -{ - if (SetSysClock_PLL_HSI() == 0) { - while(1) { - // [TODO] Put something here to tell the user that a problem occured... - } - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); -} - -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSI oscillator and activate PLL with HSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - // SYSCLK = 32 MHz ((16 MHz * 4) / 2) - // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; - RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */ - while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {}; - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz - - return 1; // OK -} diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/system_stm32l1xx.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/system_stm32l1xx.h deleted file mode 100644 index 2ca4b5b961a..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/system_stm32l1xx.h +++ /dev/null @@ -1,128 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l1xx.h - * @author MCD Application Team - * @version V2.2.0 - * @date 01-July-2016 - * @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L1XX_H -#define __SYSTEM_STM32L1XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L1xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L1xx_System_Exported_types - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -/* -*/ -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L1XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/us_ticker_data.h deleted file mode 100644 index 1480b81f7a4..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/us_ticker_data.h +++ /dev/null @@ -1,45 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __US_TICKER_DATA_H -#define __US_TICKER_DATA_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "stm32l1xx.h" -#include "stm32l1xx_ll_tim.h" -#include "cmsis_nvic.h" - -#define TIM_MST TIM4 -#define TIM_MST_IRQ TIM4_IRQn -#define TIM_MST_RCC __TIM4_CLK_ENABLE() -#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() - -#define TIM_MST_RESET_ON __TIM4_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM4_RELEASE_RESET() - -#define TIM_MST_BIT_WIDTH 16 // 16 or 32 - -#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) - - -#ifdef __cplusplus -} -#endif - -#endif // __US_TICKER_DATA_H - diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/objects.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/objects.h deleted file mode 100644 index 6751a6a3c23..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/objects.h +++ /dev/null @@ -1,64 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - IRQn_Type irq_n; - uint32_t irq_index; - uint32_t event; - PinName pin; -}; - -struct port_s { - PortName port; - uint32_t mask; - PinDirection direction; - __IO uint32_t *reg_in; - __IO uint32_t *reg_out; -}; - -#define GPIO_IP_WITHOUT_BRR -#include "common_objects.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralNames.h deleted file mode 100644 index d22b1b40d80..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralNames.h +++ /dev/null @@ -1,96 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE -} ADCName; - -typedef enum { - DAC_1 = (int)DAC_BASE -} DACName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE -} UARTName; - -#if (MX_DEFAULT_SERIAL_PINS == 0) -//Use B10/B11 as default serial port -#define STDIO_UART_TX PB_10 -#define STDIO_UART_RX PB_11 -#define STDIO_UART UART_3 -#elif (MX_DEFAULT_SERIAL_PINS == 1) -//Use A2/A3 as default serial port -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 -#else -//Use A2/A3 as default serial port -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 -#endif - -#define DEVICE_SPI_COUNT 3 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE -} I2CName; - -typedef enum { - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE, - PWM_5 = (int)TIM5_BASE, - PWM_9 = (int)TIM9_BASE, - PWM_10 = (int)TIM10_BASE, - PWM_11 = (int)TIM11_BASE -} PWMName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralPins.c deleted file mode 100644 index 2e55298dc0d..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralPins.c +++ /dev/null @@ -1,198 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "PeripheralPins.h" - -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== - -//*** ADC *** - -const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1 - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3 - {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4 - {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5 - {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6 - {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7 - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8 - {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC_IN9 - {PB_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18 - {PB_13, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC_IN19 - {PB_14, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC_IN20 - {PB_15, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 21, 0)}, // ADC_IN21 - {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC_IN10 - {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC_IN11 - {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC_IN12 - {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC_IN13 - {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC_IN14 - {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC_IN15 - {NC, NC, 0} -}; - -const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, - {NC, NC, 0} -}; - -//*** DAC *** - -const PinMap PinMap_DAC[] = { - {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 (Warning: LED1 is also on this pin) - {NC, NC, 0} -}; - -//*** I2C *** - -const PinMap PinMap_I2C_SDA[] = { - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM5 cannot be used because already used by the us_ticker. -const PinMap PinMap_PWM[] = { -// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 -// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 -// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 - {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 -// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 -// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 -// {PA_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 -// {PA_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 -// {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 -// {PB_9, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PB_12, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - {PB_13, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 - {PB_14, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - {PB_15, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {NC, NC, 0} -}; - -//*** SERIAL *** - -const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, -// {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, -// {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {NC, NC, 0} -}; - -const PinMap PinMap_UART_RX[] = { - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, -// {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, -// {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {NC, NC, 0} -}; - -//*** SPI *** - -const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PinNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PinNames.h deleted file mode 100644 index 1cfad048419..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PinNames.h +++ /dev/null @@ -1,146 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PA_0 = 0x00, - PA_1 = 0x01, - PA_2 = 0x02, - PA_3 = 0x03, - PA_4 = 0x04, - PA_5 = 0x05, - PA_6 = 0x06, - PA_7 = 0x07, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - - PB_0 = 0x10, - PB_1 = 0x11, - PB_2 = 0x12, - PB_3 = 0x13, - PB_4 = 0x14, - PB_5 = 0x15, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_9 = 0x19, - PB_10 = 0x1A, - PB_11 = 0x1B, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_14 = 0x1E, - PB_15 = 0x1F, - - PC_0 = 0x20, - PC_1 = 0x21, - PC_2 = 0x22, - PC_3 = 0x23, - PC_4 = 0x24, - PC_5 = 0x25, - PC_6 = 0x26, - PC_7 = 0x27, - PC_8 = 0x28, - PC_9 = 0x29, - PC_10 = 0x2A, - PC_11 = 0x2B, - PC_12 = 0x2C, - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, - - PD_2 = 0x32, - - PH_0 = 0x70, - PH_1 = 0x71, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - - // Generic signals namings - LED1 = PB_2, - LED2 = PB_2, - LED3 = PB_2, - LED4 = PB_2, - USER_BUTTON = PC_3, - // Standardized button names - BUTTON1 = USER_BUTTON, - -#if (MX_DEFAULT_SERIAL_PINS == 0) - //Use B10/B11 as default serial port - SERIAL_TX = PB_10, - SERIAL_RX = PB_11, - USBTX = PB_10, - USBRX = PB_11, -#elif (MX_DEFAULT_SERIAL_PINS == 1) - //Use A2/A3 as default serial port - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, -#else - //Use A2/A3 as default serial port - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, -#endif - - I2C_SCL = PB_8, - I2C_SDA = PB_9, - SPI_MOSI = PB_15, - SPI_MISO = PB_14, - SPI_SCK = PB_13, - SPI_CS = PA_1, - PWM_OUT = PC_7, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S deleted file mode 100644 index 15ae7743651..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S +++ /dev/null @@ -1,306 +0,0 @@ -;********************* (C) COPYRIGHT 2017 STMicroelectronics ******************** -;* File Name : startup_stm32l151xc.s -;* Author : MCD Application Team -;* Version : 21-April-2017 -;* Date : V2.2.1 -;* Description : STM32L151XC Devices vector for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* COPYRIGHT(c) 2017 STMicroelectronics -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp - DCD RTC_WKUP_IRQHandler ; RTC Wakeup - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD USB_HP_IRQHandler ; USB High Priority - DCD USB_LP_IRQHandler ; USB Low Priority - DCD DAC_IRQHandler ; DAC - DCD COMP_IRQHandler ; COMP through EXTI Line - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD 0 ; Reserved - DCD TIM9_IRQHandler ; TIM9 - DCD TIM10_IRQHandler ; TIM10 - DCD TIM11_IRQHandler ; TIM11 - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - DCD 0 ; Reserved - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 - DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 - DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 - DCD 0 ; Reserved - DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT USB_HP_IRQHandler [WEAK] - EXPORT USB_LP_IRQHandler [WEAK] - EXPORT DAC_IRQHandler [WEAK] - EXPORT COMP_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM9_IRQHandler [WEAK] - EXPORT TIM10_IRQHandler [WEAK] - EXPORT TIM11_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USB_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT DMA2_Channel1_IRQHandler [WEAK] - EXPORT DMA2_Channel2_IRQHandler [WEAK] - EXPORT DMA2_Channel3_IRQHandler [WEAK] - EXPORT DMA2_Channel4_IRQHandler [WEAK] - EXPORT DMA2_Channel5_IRQHandler [WEAK] - EXPORT COMP_ACQ_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_IRQHandler -USB_HP_IRQHandler -USB_LP_IRQHandler -DAC_IRQHandler -COMP_IRQHandler -EXTI9_5_IRQHandler -TIM9_IRQHandler -TIM10_IRQHandler -TIM11_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -USB_FS_WKUP_IRQHandler -TIM6_IRQHandler -TIM7_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -DMA2_Channel1_IRQHandler -DMA2_Channel2_IRQHandler -DMA2_Channel3_IRQHandler -DMA2_Channel4_IRQHandler -DMA2_Channel5_IRQHandler -COMP_ACQ_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct deleted file mode 100644 index 7b625b8337b..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct +++ /dev/null @@ -1,76 +0,0 @@ -#! armcc -E -; Scatter-Loading Description File -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2015, STMicroelectronics -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 -#endif - -; STM32L151RC: 256KB FLASH -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x40000 -#endif - -; 32KB SRAM -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x20000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x8000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 73 vectors = 292 bytes (0x124) 8-byte aligned = 0x128 (0x124 + 0x4) to be reserved in RAM -#define VECTOR_SIZE 0x128 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S deleted file mode 100644 index 15ae7743651..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S +++ /dev/null @@ -1,306 +0,0 @@ -;********************* (C) COPYRIGHT 2017 STMicroelectronics ******************** -;* File Name : startup_stm32l151xc.s -;* Author : MCD Application Team -;* Version : 21-April-2017 -;* Date : V2.2.1 -;* Description : STM32L151XC Devices vector for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* COPYRIGHT(c) 2017 STMicroelectronics -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp - DCD RTC_WKUP_IRQHandler ; RTC Wakeup - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD USB_HP_IRQHandler ; USB High Priority - DCD USB_LP_IRQHandler ; USB Low Priority - DCD DAC_IRQHandler ; DAC - DCD COMP_IRQHandler ; COMP through EXTI Line - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD 0 ; Reserved - DCD TIM9_IRQHandler ; TIM9 - DCD TIM10_IRQHandler ; TIM10 - DCD TIM11_IRQHandler ; TIM11 - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - DCD 0 ; Reserved - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 - DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 - DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 - DCD 0 ; Reserved - DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT USB_HP_IRQHandler [WEAK] - EXPORT USB_LP_IRQHandler [WEAK] - EXPORT DAC_IRQHandler [WEAK] - EXPORT COMP_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM9_IRQHandler [WEAK] - EXPORT TIM10_IRQHandler [WEAK] - EXPORT TIM11_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USB_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT DMA2_Channel1_IRQHandler [WEAK] - EXPORT DMA2_Channel2_IRQHandler [WEAK] - EXPORT DMA2_Channel3_IRQHandler [WEAK] - EXPORT DMA2_Channel4_IRQHandler [WEAK] - EXPORT DMA2_Channel5_IRQHandler [WEAK] - EXPORT COMP_ACQ_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_IRQHandler -USB_HP_IRQHandler -USB_LP_IRQHandler -DAC_IRQHandler -COMP_IRQHandler -EXTI9_5_IRQHandler -TIM9_IRQHandler -TIM10_IRQHandler -TIM11_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -USB_FS_WKUP_IRQHandler -TIM6_IRQHandler -TIM7_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -DMA2_Channel1_IRQHandler -DMA2_Channel2_IRQHandler -DMA2_Channel3_IRQHandler -DMA2_Channel4_IRQHandler -DMA2_Channel5_IRQHandler -COMP_ACQ_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_STD/stm32l151rc.sct b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_STD/stm32l151rc.sct deleted file mode 100644 index 9e55e1a4f6c..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_STD/stm32l151rc.sct +++ /dev/null @@ -1,53 +0,0 @@ -#! armcc -E -; Scatter-Loading Description File -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2015, STMicroelectronics -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -; STM32L151RC: 256KB FLASH + 32KB SRAM -LR_IROM1 0x08000000 0x40000 { ; load region size_region - - ER_IROM1 0x08000000 0x40000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - ; 73 vectors = 292 bytes(0x124) 8-byte aligned = 0x128 (0x124 + 0x4)to be reserved in RAM - RW_IRAM1 (0x20000000+0x128) (0x8000-0x128) { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_STACK (0x20000000+0x8000) EMPTY -Stack_Size { ; stack - } -} - diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_GCC_ARM/STM32L151XC.ld b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_GCC_ARM/STM32L151XC.ld deleted file mode 100644 index 848d7d3342a..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_GCC_ARM/STM32L151XC.ld +++ /dev/null @@ -1,165 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY -{ - /* 256KB FLASH, 32KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292 - * bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138 - * 8-byte aligned(0x13C) = 0x140 - */ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256k - RAM (rwx) : ORIGIN = 0x20000140, LENGTH = 0x8000-0x140 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * _estack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - _sidata = .; - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S deleted file mode 100644 index 967be478b66..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S +++ /dev/null @@ -1,405 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32l151xc.s - * @author MCD Application Team - * @brief STM32L151XC Devices vector table for - * Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system intitialization function.*/ - bl SystemInit - -/** - * Calling the crt0 'cold-start' entry point. There __libc_init_array is called - * and when existing hardware_init_hook() and software_init_hook() before - * starting main(). software_init_hook() is available and has to be called due - * to initializsation when using rtos. -*/ - bl _start - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_STAMP_IRQHandler - .word RTC_WKUP_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_IRQHandler - .word USB_HP_IRQHandler - .word USB_LP_IRQHandler - .word DAC_IRQHandler - .word COMP_IRQHandler - .word EXTI9_5_IRQHandler - .word 0 - .word TIM9_IRQHandler - .word TIM10_IRQHandler - .word TIM11_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word USB_FS_WKUP_IRQHandler - .word TIM6_IRQHandler - .word TIM7_IRQHandler - .word 0 - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word 0 - .word 0 - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_IRQHandler - .word DMA2_Channel5_IRQHandler - .word 0 - .word COMP_ACQ_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x108. This is for boot in RAM mode for - STM32L151XC devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_STAMP_IRQHandler - .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak USB_HP_IRQHandler - .thumb_set USB_HP_IRQHandler,Default_Handler - - .weak USB_LP_IRQHandler - .thumb_set USB_LP_IRQHandler,Default_Handler - - .weak DAC_IRQHandler - .thumb_set DAC_IRQHandler,Default_Handler - - .weak COMP_IRQHandler - .thumb_set COMP_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM9_IRQHandler - .thumb_set TIM9_IRQHandler,Default_Handler - - .weak TIM10_IRQHandler - .thumb_set TIM10_IRQHandler,Default_Handler - - .weak TIM11_IRQHandler - .thumb_set TIM11_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak USB_FS_WKUP_IRQHandler - .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_IRQHandler - .thumb_set DMA2_Channel4_IRQHandler,Default_Handler - - .weak DMA2_Channel5_IRQHandler - .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - - .weak COMP_ACQ_IRQHandler - .thumb_set COMP_ACQ_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/cmsis_nvic.h deleted file mode 100644 index 2f5de616487..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/cmsis_nvic.h +++ /dev/null @@ -1,41 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -// STM32L151RC -// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F -// MCU Peripherals: 57 vectors = 228 bytes from 0x40 to 0x123 -// Total: 73 vectors = 292 bytes (0x124) to be reserved in RAM -#define NVIC_NUM_VECTORS 73 -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/stm32l151xc.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/stm32l151xc.h deleted file mode 100644 index 003da03da15..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/stm32l151xc.h +++ /dev/null @@ -1,9070 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l151xc.h - * @author MCD Application Team - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32L1xx devices. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l151xc - * @{ - */ - -#ifndef __STM32L151xC_H -#define __STM32L151xC_H - -#ifdef __cplusplus - extern "C" { -#endif - - - /** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ -#define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */ -#define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32L1xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - - /*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32L specific Interrupt Numbers ***********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ - USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ - DAC_IRQn = 21, /*!< DAC Interrupt */ - COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ - TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ - TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ - TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ - TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ - DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ - COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32l1xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ - __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ - uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2017 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx - * @{ - */ - -#ifndef __STM32L1XX_H -#define __STM32L1XX_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L1) -#define STM32L1 -#endif /* STM32L1 */ - -//MODTRONIX BEGIN - HAL Defines /////////////////////////////////////////////// -//Provide place for adding HAL defines. Alternative to adding them in IDE project properties. -//Add project defines here, or add them to your toolchain compiler preprocessor - -//Defines what ports to use for default serial port. -//0 = B10/B11 -//1 = A2/A3 -#if !defined (MX_DEFAULT_SERIAL_PINS) -#define MX_DEFAULT_SERIAL_PINS 0 /*!< Use B10/B11 for default serial port, in stead of A2/A3 */ -#endif - -//MODTRONIX END /////////////////////////////////////////////////////////////// - -/* Uncomment the line below according to the target STM32L device used in your - application - */ - -#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \ - !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xDX) && !defined (STM32L151xE) && \ - !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xDX) && !defined (STM32L152xE) && \ - !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xDX) && !defined (STM32L162xE) - /* #define STM32L100xB */ /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */ - /* #define STM32L100xBA */ /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */ - /* #define STM32L100xC */ /*!< STM32L100RC Devices */ - /* #define STM32L151xB */ /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */ - /* #define STM32L151xBA */ /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */ - #define STM32L151xC /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */ - /* #define STM32L151xCA */ /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */ - /* #define STM32L151xD */ /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */ - /* #define STM32L151xDX */ /*!< STM32L151VD-X Devices */ - /* #define STM32L151xE */ /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */ - /* #define STM32L152xB */ /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */ - /* #define STM32L152xBA */ /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */ - /* #define STM32L152xC */ /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */ - /* #define STM32L152xCA */ /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */ - /* #define STM32L152xD */ /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */ - /* #define STM32L152xDX */ /*!< STM32L152VD-X Devices */ - /* #define STM32L152xE */ /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */ - /* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */ - /* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */ - /* #define STM32L162xD */ /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */ - /* #define STM32L162xDX */ /*!< STM32L162VD-X Devices */ - /* #define STM32L162xE */ /*!< STM32L162RE, STM32L162VE and STM32L162ZE */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ -#define USE_HAL_DRIVER -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number - */ -#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ -#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ -#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L1xx_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L1xx_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L100xB) - #include "stm32l100xb.h" -#elif defined(STM32L100xBA) - #include "stm32l100xba.h" -#elif defined(STM32L100xC) - #include "stm32l100xc.h" -#elif defined(STM32L151xB) - #include "stm32l151xb.h" -#elif defined(STM32L151xBA) - #include "stm32l151xba.h" -#elif defined(STM32L151xC) - #include "stm32l151xc.h" -#elif defined(STM32L151xCA) - #include "stm32l151xca.h" -#elif defined(STM32L151xD) - #include "stm32l151xd.h" -#elif defined(STM32L151xDX) - #include "stm32l151xdx.h" -#elif defined(STM32L151xE) - #include "stm32l151xe.h" -#elif defined(STM32L152xB) - #include "stm32l152xb.h" -#elif defined(STM32L152xBA) - #include "stm32l152xba.h" -#elif defined(STM32L152xC) - #include "stm32l152xc.h" -#elif defined(STM32L152xCA) - #include "stm32l152xca.h" -#elif defined(STM32L152xD) - #include "stm32l152xd.h" -#elif defined(STM32L152xDX) - #include "stm32l152xdx.h" -#elif defined(STM32L152xE) - #include "stm32l152xe.h" -#elif defined(STM32L162xC) - #include "stm32l162xc.h" -#elif defined(STM32L162xCA) - #include "stm32l162xca.h" -#elif defined(STM32L162xD) - #include "stm32l162xd.h" -#elif defined(STM32L162xDX) - #include "stm32l162xdx.h" -#elif defined(STM32L162xE) - #include "stm32l162xe.h" -#else - #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l1xx_hal.h" -#endif /* USE_HAL_DRIVER */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L1xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_clock.c deleted file mode 100644 index df762686ea8..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_clock.c +++ /dev/null @@ -1,234 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI - * | (external 16 MHz clock) | (internal 16 MHz) - * | 2- PLL_HSE_XTAL | - * | (external 16 MHz xtal) | - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 32 | 32 - *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 32 | 32 - *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 32 | 32 - *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 32 | 32 - *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | YES | NO - *----------------------------------------------------------------------------- - ****************************************************************************** - */ - -#include "stm32l1xx.h" - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - -/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ -#define USE_PLL_HSE_EXTC (0) /* Use external clock */ -#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ - - -#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) -uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif - -uint8_t SetSysClock_PLL_HSI(void); - - -/** - * @brief Setup the microcontroller system. - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /*!< Set MSION bit */ - RCC->CR |= (uint32_t)0x00000100; - - /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ - RCC->CFGR &= (uint32_t)0x88FFC00C; - - /*!< Reset HSION, HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xEEFEFFFE; - - /*!< Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ - RCC->CFGR &= (uint32_t)0xFF02FFFF; - - /*!< Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif - -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -void SetSysClock(void) -{ - /* 1- Try to start with HSE and external clock */ -#if USE_PLL_HSE_EXTC != 0 - if (SetSysClock_PLL_HSE(1) == 0) -#endif - { - /* 2- If fail try to start with HSE and external xtal */ -#if USE_PLL_HSE_XTAL != 0 - if (SetSysClock_PLL_HSE(0) == 0) -#endif - { - /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) { - while(1) { - // [TODO] Put something here to tell the user that a problem occured... - } - } - } - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); -} - -#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Used to gain time after DeepSleep in case HSI is used */ - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { - return 0; - } - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 16 MHz xtal on OSC_IN/OSC_OUT */ - } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 16 MHz clock on OSC_IN */ - } - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - // SYSCLK = 32 MHz ((16 MHz * 6) / 3) - // USBCLK = 48 MHz ((16 MHz * 6) / 2) --> USB OK - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; - RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3; - - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //if (bypass == 0) - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - //else - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz - - return 1; // OK -} -#endif - -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSI oscillator and activate PLL with HSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - // SYSCLK = 32 MHz ((16 MHz * 4) / 2) - // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; - RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */ - while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {}; - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz - - return 1; // OK -} diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_stm32l1xx.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_stm32l1xx.h deleted file mode 100644 index ace20a831f9..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_stm32l1xx.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l1xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L1XX_H -#define __SYSTEM_STM32L1XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L1xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L1xx_System_Exported_types - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -/* -*/ -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L1XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/us_ticker_data.h deleted file mode 100644 index b32bd97db96..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/us_ticker_data.h +++ /dev/null @@ -1,45 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __US_TICKER_DATA_H -#define __US_TICKER_DATA_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "stm32l1xx.h" -#include "stm32l1xx_ll_tim.h" -#include "cmsis_nvic.h" - -#define TIM_MST TIM5 -#define TIM_MST_IRQ TIM5_IRQn -#define TIM_MST_RCC __TIM5_CLK_ENABLE() -#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() - -#define TIM_MST_RESET_ON __TIM5_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() - -#define TIM_MST_BIT_WIDTH 32 // 16 or 32 - -#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) - - -#ifdef __cplusplus -} -#endif - -#endif // __US_TICKER_DATA_H - diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/objects.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/objects.h deleted file mode 100644 index 5ddc595468a..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/objects.h +++ /dev/null @@ -1,63 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - IRQn_Type irq_n; - uint32_t irq_index; - uint32_t event; - PinName pin; -}; - -struct port_s { - PortName port; - uint32_t mask; - PinDirection direction; - __IO uint32_t *reg_in; - __IO uint32_t *reg_out; -}; - -#include "common_objects.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h deleted file mode 100644 index 36105bab3ea..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralNames.h +++ /dev/null @@ -1,97 +0,0 @@ -/* mbed Microcontroller Library - -* SPDX-License-Identifier: BSD-3-Clause - ******************************************************************************* - * Copyright (c) 2017, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE, - ADC_2 = (int)ADC2_BASE, - ADC_3 = (int)ADC3_BASE -} ADCName; - -typedef enum { - DAC_1 = (int)DAC_BASE -} DACName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE, - UART_4 = (int)UART4_BASE, - UART_5 = (int)UART5_BASE, - LPUART_1 = (int)LPUART1_BASE -} UARTName; - -#define DEVICE_SPI_COUNT 3 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE, - I2C_3 = (int)I2C3_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE, - PWM_5 = (int)TIM5_BASE, - PWM_8 = (int)TIM8_BASE, - PWM_15 = (int)TIM15_BASE, - PWM_16 = (int)TIM16_BASE, - PWM_17 = (int)TIM17_BASE -} PWMName; - -typedef enum { - CAN_1 = (int)CAN1_BASE -} CANName; - -typedef enum { - QSPI_1 = (int)QSPI_R_BASE, -} QSPIName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c deleted file mode 100644 index 0b79f9eed30..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PeripheralPins.c +++ /dev/null @@ -1,370 +0,0 @@ -/* mbed Microcontroller Library - -* SPDX-License-Identifier: BSD-3-Clause - ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#include "PeripheralPins.h" -#include "mbed_toolchain.h" - -//============================================================================== -// Notes -// -// - The pins mentioned Px_y_ALTz are alternative possibilities which use other -// HW peripheral instances. You can use them the same way as any other "normal" -// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board -// pinout image on mbed.org. -// -// - The pins which are connected to other components present on the board have -// the comment "Connected to xxx". The pin function may not work properly in this -// case. These pins may not be displayed on the board pinout image on mbed.org. -// Please read the board reference manual and schematic for more information. -// -// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented -// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. -// -//============================================================================== - - -//*** ADC *** - -MBED_WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 - {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 - {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 - {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 - {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 - {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 - {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 - {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 - {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 - {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 - {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 - {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 - {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16 - {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 - {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 - {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 - {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 - {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 - {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 - {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 - {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 - {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 - {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 - {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 17, 0)}, - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 0, 0)}, - {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 18, 0)}, - {NC, NC, 0} -}; - -//*** DAC *** - -MBED_WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 // - {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 // - {NC, NC, 0} -}; - -//*** I2C *** - -MBED_WEAK const PinMap PinMap_I2C_SDA[] = { - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_I2C_SCL[] = { - {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM5 cannot be used because already used by the us_ticker -MBED_WEAK const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - {PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N - {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 -// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - {PA_2_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 - {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 -// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - {PA_3_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 - {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 - {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - {PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 -// {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 -// {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N -// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 -// {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N - {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 - {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 - {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PB_13_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N - {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - {PB_14_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 - {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 - {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PE_0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 - {PE_1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 - {PE_3, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PE_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PE_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PE_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - {NC, NC, 0} -}; - -//*** SERIAL *** - -MBED_WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {NC, NC, 0} -}; - -//*** SPI *** - -MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PD_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PE_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PE_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PE_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PD_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PE_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {NC, NC, 0} -}; - -//*** CAN *** - -MBED_WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_CAN_TD[] = { - {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {NC, NC, 0} -}; - -//*** QUADSPI *** - -MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { - {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 - {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 - {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 - {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 - {PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 - {PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 - {PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 - {PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { - {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK - {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { - {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS - {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h deleted file mode 100644 index c9f7aca3a53..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/PinNames.h +++ /dev/null @@ -1,323 +0,0 @@ -/* mbed Microcontroller Library - -* SPDX-License-Identifier: BSD-3-Clause - ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ALT0 = 0x100, - ALT1 = 0x200, - ALT2 = 0x300, - ALT3 = 0x400 -} ALTx; - -typedef enum { - PA_0 = 0x00, - PA_0_ALT0 = PA_0 | ALT0, - PA_1 = 0x01, - PA_1_ALT0 = PA_1 | ALT0, - PA_2 = 0x02, - PA_2_ALT0 = PA_2 | ALT0, - PA_3 = 0x03, - PA_3_ALT0 = PA_3 | ALT0, - PA_4 = 0x04, - PA_4_ALT0 = PA_4 | ALT0, - PA_5 = 0x05, - PA_5_ALT0 = PA_5 | ALT0, - PA_6 = 0x06, - PA_6_ALT0 = PA_6 | ALT0, - PA_7 = 0x07, - PA_7_ALT0 = PA_7 | ALT0, - PA_7_ALT1 = PA_7 | ALT1, - PA_7_ALT2 = PA_7 | ALT2, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - PA_15_ALT0 = PA_15 | ALT0, - - PB_0 = 0x10, - PB_0_ALT0 = PB_0 | ALT0, - PB_0_ALT1 = PB_0 | ALT1, - PB_1 = 0x11, - PB_1_ALT0 = PB_1 | ALT0, - PB_1_ALT1 = PB_1 | ALT1, - PB_2 = 0x12, - PB_3 = 0x13, - PB_3_ALT0 = PB_3 | ALT0, - PB_4 = 0x14, - PB_4_ALT0 = PB_4 | ALT0, - PB_5 = 0x15, - PB_5_ALT0 = PB_5 | ALT0, - PB_6 = 0x16, - PB_6_ALT0 = PB_6 | ALT0, - PB_7 = 0x17, - PB_7_ALT0 = PB_7 | ALT0, - PB_8 = 0x18, - PB_8_ALT0 = PB_8 | ALT0, - PB_9 = 0x19, - PB_9_ALT0 = PB_9 | ALT0, - PB_10 = 0x1A, - PB_11 = 0x1B, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_13_ALT0 = PB_13 | ALT0, - PB_14 = 0x1E, - PB_14_ALT0 = PB_14 | ALT0, - PB_14_ALT1 = PB_14 | ALT1, - PB_15 = 0x1F, - PB_15_ALT0 = PB_15 | ALT0, - PB_15_ALT1 = PB_15 | ALT1, - - PC_0 = 0x20, - PC_0_ALT0 = PC_0 | ALT0, - PC_0_ALT1 = PC_0 | ALT1, - PC_1 = 0x21, - PC_1_ALT0 = PC_1 | ALT0, - PC_1_ALT1 = PC_1 | ALT1, - PC_2 = 0x22, - PC_2_ALT0 = PC_2 | ALT0, - PC_2_ALT1 = PC_2 | ALT1, - PC_3 = 0x23, - PC_3_ALT0 = PC_3 | ALT0, - PC_3_ALT1 = PC_3 | ALT1, - PC_4 = 0x24, - PC_4_ALT0 = PC_4 | ALT0, - PC_5 = 0x25, - PC_5_ALT0 = PC_5 | ALT0, - PC_6 = 0x26, - PC_6_ALT0 = PC_6 | ALT0, - PC_7 = 0x27, - PC_7_ALT0 = PC_7 | ALT0, - PC_8 = 0x28, - PC_8_ALT0 = PC_8 | ALT0, - PC_9 = 0x29, - PC_9_ALT0 = PC_9 | ALT0, - PC_10 = 0x2A, - PC_10_ALT0 = PC_10 | ALT0, - PC_11 = 0x2B, - PC_11_ALT0 = PC_11 | ALT0, - PC_12 = 0x2C, - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, - - PD_0 = 0x30, - PD_1 = 0x31, - PD_2 = 0x32, - PD_3 = 0x33, - PD_4 = 0x34, - PD_5 = 0x35, - PD_6 = 0x36, - PD_7 = 0x37, - PD_8 = 0x38, - PD_9 = 0x39, - PD_10 = 0x3A, - PD_11 = 0x3B, - PD_12 = 0x3C, - PD_13 = 0x3D, - PD_14 = 0x3E, - PD_15 = 0x3F, - - PE_0 = 0x40, - PE_1 = 0x41, - PE_2 = 0x42, - PE_3 = 0x43, - PE_4 = 0x44, - PE_5 = 0x45, - PE_6 = 0x46, - PE_7 = 0x47, - PE_8 = 0x48, - PE_9 = 0x49, - PE_10 = 0x4A, - PE_11 = 0x4B, - PE_12 = 0x4C, - PE_13 = 0x4D, - PE_14 = 0x4E, - PE_15 = 0x4F, - - PH_0 = 0x70, - PH_1 = 0x71, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, - - // Not connected - NC = (int)0xFFFFFFFF, - - // STDIO for console print -#ifdef MBED_CONF_TARGET_STDIO_UART_TX - STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, -#else - STDIO_UART_TX = PA_9, -#endif -#ifdef MBED_CONF_TARGET_STDIO_UART_RX - STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, -#else - STDIO_UART_RX = PA_10, -#endif - - // Generic signals namings - LED1 = PE_2, // Red LED (LD1) - LED2 = PE_3, // Blue LED (LD2) - LED3 = PE_4, // Green LED (LD3) - - LED_RED = LED1, - LED_BLUE = LED2, - LED_GREEN = LED3, - - USER_BUTTON = PD_4, - BUTTON1 = USER_BUTTON, - - USBTX = STDIO_UART_TX, - USBRX = STDIO_UART_RX, - - UART1_TX = PA_2, - UART1_RX = PA_3, - UART1_CTS = PA_0, - UART1_RTS = PA_1, - - SERIAL_TX = UART1_TX, - SERIAL_RX = UART1_RX, - SERIAL_CTS = UART1_CTS, - SERIAL_RTS = UART1_RTS, - - UART2_TX = PC_4, - UART2_RX = PC_5, - - I2C0_SCL = PB_6, - I2C0_SDA = PB_7, - - I2C1_SCL = PC_0, - I2C1_SDA = PC_1, - - SPI0_MOSI = PB_5, - SPI0_MISO = PA_6, - SPI0_SCK = PA_5, - SPI0_CS = PA_15, - - SPI1_MOSI = PB_15, - SPI1_MISO = PB_14, - SPI1_SCK = PD_3, - SPI1_CS = PB_9, - - SPI2_MOSI = PC_12, - SPI2_MISO = PC_11, - SPI2_SCK = PC_10, - SPI2_CS = PA_4, - - //Default SPI - SPI_MOSI = SPI0_MOSI, - SPI_MISO = SPI0_MISO, - SPI_SCK = SPI0_SCK, - /**************** - //IMPORTANT NOTE: The default CS for SPI is marked as the CS line for the SPI Flash - //on the MCB reference hardware. Please change as appropriate. - ****************/ - SPI_CS = PD_2, - - CAN1_RX = PD_0, //Test point on MCB - CAN1_TX = PD_1, //Test point on MCB - - /**** OSCILLATOR pins ****/ - RCC_OSC32_IN = PC_14, - RCC_OSC32_OUT = PC_15, - RCC_OSC_IN = PH_0, - RCC_OSC_OUT = PH_1, - - /**** DEBUG pins ****/ - SYS_JTCK_SWCLK = PA_14, - SYS_JTDI = PA_15, - SYS_JTDO_SWO = PB_3, - SYS_JTMS_SWDIO = PA_13, - SYS_JTRST = PB_4, - SYS_PVD_IN = PB_7, - SYS_TRACECLK = PE_2, - SYS_TRACED0 = PE_3, - SYS_TRACED1 = PE_4, - SYS_TRACED2 = PE_5, - SYS_TRACED3 = PE_6, - SYS_WKUP1 = PA_0, - SYS_WKUP2 = PC_13, - SYS_WKUP3 = PE_6, - SYS_WKUP4 = PA_2, - SYS_WKUP5 = PC_5, - - //MTB aliases - TX1 = PA_2, - RX1 = PA_3, - SDA1 = PB_7, - SCL1 = PB_6, - MOSI1 = PB_5, - MISO1 = PA_6, - SCK1 = PA_5, - GP0 = PD_4, - GP1 = PC_10, - AIN0 = PA_0, //CTS - AIN1 = PA_1, // RTS - AIN2 = PB_0, - - GP2 = PE_5, //SD card CS - GP3 = PE_6, - SCK2 = PD_3, - MISO2 = PB_14, - MOSI2 = PB_15, - SCL2 = PC_1, - SDA2 = PC_0, - RX2 = PC_5, - TX2 = PC_4, - GP4 = PE_9, - GP5 = PE_10, //A0 for LCD on MTB - GP6 = PE_13, //RESET for LCD on MTB - GP7 = PE_14, //LCD CS - GP8 = PE_15 - -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c deleted file mode 100644 index b2954650e2e..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c +++ /dev/null @@ -1,326 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2019 ARM Limited - -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) - * | 3- USE_PLL_HSI (internal 16 MHz) - * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 80 - * AHBCLK (MHz) | 80 - * APB1CLK (MHz) | 80 - * APB2CLK (MHz) | 80 - * USB capable | YES - *----------------------------------------------------------------------------- -**/ - -#include "stm32l4xx.h" -#include "mbed_error.h" - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -// clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) -#define USE_PLL_HSI 0x2 // Use HSI internal clock -#define USE_PLL_MSI 0x1 // Use MSI internal clock - -#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI) - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -uint8_t SetSysClock_PLL_HSI(void); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ - -#if ((CLOCK_SOURCE) & USE_PLL_MSI) -uint8_t SetSysClock_PLL_MSI(void); -#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ - - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ - -void SetSysClock(void) -{ -#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) - /* 1- Try to start with HSE and external clock */ - if (SetSysClock_PLL_HSE(1) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) - /* 2- If fail try to start with HSE and external xtal */ - if (SetSysClock_PLL_HSE(0) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSI) - /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_MSI) - /* 4- If fail start with MSI clock */ - if (SetSysClock_PLL_MSI() == 0) -#endif - { - { - error("SetSysClock failed\n"); - } - } - } - } - } - - // Output clock on MCO1 pin(PA8) for debugging purpose -#if DEBUG_MCO == 1 - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); -#endif -} - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; - - // Used to gain time after DeepSleep in case HSI is used - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { - return 0; - } - - // Select MSI as system clock source to allow modification of the PLL configuration - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); - - // Enable HSE oscillator and activate PLL with HSE as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI; - if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN - } - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) - RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) - RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) - - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { - return 0; // FAIL - } - - // Select LSE output as LPUART1 clock source - RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPUART1; - RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE; - RCC_PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { - return 0; // FAIL - } - - // Disable MSI Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - // Output clock on MCO1 pin(PA8) for debugging purpose -#if DEBUG_MCO == 2 - if (bypass == 0) { - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - } else { - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz - } -#endif - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; - - // Select MSI as system clock source to allow modification of the PLL configuration - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); - - // Enable HSI oscillator and activate PLL with HSI as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz - RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) - RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) - RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { - return 0; // FAIL - } - - RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { - return 0; // FAIL - } - - // Disable MSI Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - // Output clock on MCO1 pin(PA8) for debugging purpose -#if DEBUG_MCO == 3 - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz -#endif - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ - -#if ((CLOCK_SOURCE) & USE_PLL_MSI) -/******************************************************************************/ -/* PLL (clocked by MSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_MSI(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - -#if MBED_CONF_TARGET_LSE_AVAILABLE - // Enable LSE Oscillator to automatically calibrate the MSI clock - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ - HAL_RCCEx_DisableLSECSS(); -#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ - - /* Enable MSI Oscillator and activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - - RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; - RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; - RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */ - RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */ - RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */ - RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */ - RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */ - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - -#if MBED_CONF_TARGET_LSE_AVAILABLE - /* Enable MSI Auto-calibration through LSE */ - HAL_RCCEx_EnableMSIPLLMode(); -#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ - - /* Select MSI output as USB clock source */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */ - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { - return 0; // FAIL - } - - // Output clock on MCO1 pin(PA8) for debugging purpose -#if DEBUG_MCO == 4 - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz -#endif - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ diff --git a/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.ar b/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.ar deleted file mode 100644 index 0822d510c47..00000000000 Binary files a/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.ar and /dev/null differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.ar b/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.ar deleted file mode 100644 index 3c314df1cd7..00000000000 Binary files a/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.ar and /dev/null differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.a b/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.a deleted file mode 100644 index 2a22ea0fa9c..00000000000 Binary files a/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.a and /dev/null differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.a b/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.a deleted file mode 100644 index 0dc0a952c84..00000000000 Binary files a/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.a and /dev/null differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.a b/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.a deleted file mode 100644 index 38b06796586..00000000000 Binary files a/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.a and /dev/null differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.a b/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.a deleted file mode 100644 index 31ca5bcb24c..00000000000 Binary files a/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.a and /dev/null differ diff --git a/targets/targets.json b/targets/targets.json index 56b9d72ec52..cf074e45800 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -345,345 +345,6 @@ "1114" ] }, - "LPC11U24": { - "inherits": [ - "LPCTarget" - ], - "core": "Cortex-M0", - "default_toolchain": "uARM", - "extra_labels": [ - "NXP", - "LPC11UXX", - "LPC11U24_401" - ], - "macros": [ - "CMSIS_VECTAB_VIRTUAL", - "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"" - ], - "supported_toolchains": [ - "ARM", - "uARM", - "GCC_ARM", - "IAR" - ], - "detect_code": [ - "1040" - ], - "device_has": [ - "ANALOGIN", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "LOCALFILESYSTEM", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SEMIHOST", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE", - "STDIO_MESSAGES", - "USTICKER" - ], - "overrides": { - "tickless-from-us-ticker": true, - "boot-stack-size": "0x400" - }, - "default_lib": "small", - "release_versions": [ - "2" - ], - "device_name": "LPC11U24FBD48/401" - }, - "OC_MBUINO": { - "inherits": [ - "LPC11U24" - ], - "macros": [ - "TARGET_LPC11U24", - "CMSIS_VECTAB_VIRTUAL", - "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"" - ], - "extra_labels": [ - "NXP", - "LPC11UXX" - ], - "device_has": [ - "ANALOGIN", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE", - "STDIO_MESSAGES" - ], - "release_versions": [ - "2" - ], - "detect_code": [ - "1080" - ] - }, - "LPC11U24_301": { - "inherits": [ - "LPCTarget" - ], - "core": "Cortex-M0", - "extra_labels": [ - "NXP", - "LPC11UXX" - ], - "macros": [ - "CMSIS_VECTAB_VIRTUAL", - "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"" - ], - "supported_toolchains": [ - "ARM", - "uARM", - "GCC_ARM", - "IAR" - ], - "device_has": [ - "ANALOGIN", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "LOCALFILESYSTEM", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SEMIHOST", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE", - "STDIO_MESSAGES" - ], - "device_name": "LPC11U24FHI33/301" - }, - "LPC11U34_421": { - "inherits": [ - "LPCTarget" - ], - "core": "Cortex-M0", - "default_toolchain": "uARM", - "extra_labels": [ - "NXP", - "LPC11UXX" - ], - "macros": [ - "CMSIS_VECTAB_VIRTUAL", - "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"" - ], - "supported_toolchains": [ - "ARM", - "uARM", - "GCC_ARM" - ], - "device_has": [ - "ANALOGIN", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE" - ], - "default_lib": "small", - "device_name": "LPC11U34FBD48/311" - }, - "MICRONFCBOARD": { - "inherits": [ - "LPC11U34_421" - ], - "macros_add": [ - "LPC11U34_421", - "APPNEARME_MICRONFCBOARD" - ], - "extra_labels_add": [ - "APPNEARME_MICRONFCBOARD" - ], - "release_versions": [ - "2" - ], - "device_name": "LPC11U34FBD48/311", - "detect_code": [ - "1034" - ] - }, - "LPC11U35_401": { - "inherits": [ - "LPCTarget" - ], - "core": "Cortex-M0", - "default_toolchain": "uARM", - "extra_labels": [ - "NXP", - "LPC11UXX" - ], - "macros": [ - "CMSIS_VECTAB_VIRTUAL", - "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"" - ], - "supported_toolchains": [ - "ARM", - "uARM", - "GCC_ARM", - "IAR" - ], - "device_has": [ - "ANALOGIN", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE", - "USTICKER" - ], - "overrides": { - "tickless-from-us-ticker": true, - "boot-stack-size": "0x400" - }, - "default_lib": "small", - "release_versions": [ - "2" - ], - "device_name": "LPC11U35FBD48/401", - "detect_code": [ - "1061" - ] - }, - "MCU_LPC11U35_501": { - "inherits": [ - "LPCTarget" - ], - "core": "Cortex-M0", - "default_toolchain": "uARM", - "extra_labels": [ - "NXP", - "LPC11UXX" - ], - "macros": [ - "CMSIS_VECTAB_VIRTUAL", - "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"" - ], - "supported_toolchains": [ - "ARM", - "uARM", - "GCC_ARM", - "IAR" - ], - "device_has": [ - "ANALOGIN", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE" - ], - "default_lib": "small", - "device_name": "LPC11U35FHI33/501", - "public": false - }, - "LPC11U35_501": { - "inherits": [ - "MCU_LPC11U35_501" - ], - "release_versions": [ - "2" - ], - "detect_code": [ - "9007" - ] - }, - "LPC11U35_501_IBDAP": { - "inherits": [ - "MCU_LPC11U35_501" - ], - "release_versions": [ - "2" - ] - }, - "LPC11U35_Y5_MBUG": { - "inherits": [ - "MCU_LPC11U35_501" - ], - "release_versions": [ - "2" - ], - "detect_code": [ - "4000" - ] - }, - "LPC11U37_501": { - "inherits": [ - "LPCTarget" - ], - "core": "Cortex-M0", - "default_toolchain": "uARM", - "extra_labels": [ - "NXP", - "LPC11UXX" - ], - "macros": [ - "CMSIS_VECTAB_VIRTUAL", - "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"" - ], - "supported_toolchains": [ - "ARM", - "uARM", - "GCC_ARM", - "IAR" - ], - "default_lib": "small", - "device_name": "LPC11U37FBD64/501" - }, - "LPCCAPPUCCINO": { - "inherits": [ - "LPC11U37_501" - ], - "device_has": [ - "ANALOGIN", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE" - ], - "device_name": "LPC11U37FBD64/501" - }, "LPC11U68": { "supported_form_factors": [ "ARDUINO" @@ -1389,70 +1050,6 @@ "IAR" ] }, - "LPC11U37H_401": { - "supported_form_factors": [ - "ARDUINO" - ], - "core": "Cortex-M0", - "default_toolchain": "uARM", - "extra_labels": [ - "NXP", - "LPC11UXX" - ], - "macros": [ - "CMSIS_VECTAB_VIRTUAL", - "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"" - ], - "supported_toolchains": [ - "ARM", - "uARM", - "GCC_ARM" - ], - "inherits": [ - "LPCTarget" - ], - "device_has": [ - "ANALOGIN", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE" - ], - "default_lib": "small", - "release_versions": [ - "2" - ], - "device_name": "LPC11U37HFBD64/401" - }, - "ELEKTOR_COCORICO": { - "core": "Cortex-M0+", - "default_toolchain": "uARM", - "extra_labels": [ - "NXP", - "LPC81X" - ], - "supported_toolchains": [ - "uARM", - "GCC_ARM", - "IAR" - ], - "inherits": [ - "LPCTarget" - ], - "is_disk_virtual": true, - "detect_code": [ - "C000" - ], - "default_lib": "small", - "device_name": "LPC812M101JDH16" - }, "KL05Z": { "supported_form_factors": [ "ARDUINO" @@ -1638,68 +1235,19 @@ "core": "Cortex-M4", "extra_labels": [ "Freescale", - "K20XX" - ], - "is_disk_virtual": true, - "supported_toolchains": [ - "GCC_ARM", - "ARM", - "IAR" - ], - "detect_code": [ - "0230" - ], - "device_has": [ - "ANALOGIN", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SEMIHOST", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE", - "STDIO_MESSAGES" - ], - "release_versions": [ - "2" - ], - "device_name": "MK20DX128xxx5" - }, - "TEENSY3_1": { - "inherits": [ - "Target" - ], - "core": "Cortex-M4", - "extra_labels": [ - "Freescale", - "K20XX", - "K20DX256" + "K20XX" ], - "OUTPUT_EXT": "hex", "is_disk_virtual": true, "supported_toolchains": [ "GCC_ARM", - "ARM" + "ARM", + "IAR" ], - "post_binary_hook": { - "function": "TEENSY3_1Code.binary_hook", - "toolchains": [ - "ARM_STD", - "ARM_MICRO", - "GCC_ARM" - ] - }, "detect_code": [ "0230" ], "device_has": [ "ANALOGIN", - "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", @@ -1717,7 +1265,7 @@ "release_versions": [ "2" ], - "device_name": "MK20DX256xxx7" + "device_name": "MK20DX128xxx5" }, "MCU_K22F512": { "core": "Cortex-M4F", @@ -1960,18 +1508,6 @@ ], "device_name": "MKL82Z128xxx7" }, - "USENSE": { - "inherits": [ - "KL82Z" - ], - "extra_labels_remove": [ - "FRDM" - ], - "device_has_remove": [ - "QSPI" - ], - "supported_form_factors": [] - }, "KW24D": { "supported_form_factors": [ "ARDUINO" @@ -2705,21 +2241,6 @@ ], "device_name": "MK82FN256xxx15" }, - "UBRIDGE": { - "inherits": [ - "K82F" - ], - "extra_labels_remove": [ - "FRDM" - ], - "components_remove": [ - "SPIF" - ], - "device_has_remove": [ - "QSPI" - ], - "supported_form_factors": [] - }, "FAMILY_STM32": { "inherits": [ "Target" @@ -3965,90 +3486,6 @@ "0451" ] }, - "USI_WM_BN_BM_22": { - "inherits": [ - "FAMILY_STM32" - ], - "supported_toolchains": [ - "ARM", - "GCC_ARM", - "IAR" - ], - "components_add": [ - "SPIF", - "FLASHIAP" - ], - "core": "Cortex-M4F", - "extra_labels_add": [ - "STM32F4", - "STM32F412xG", - "WICED", - "CYW4343X", - "CORDIO" - ], - "features": [ - "BLE" - ], - "macros_add": [ - "STM32F412Zx" - ], - "device_has_add": [ - "SERIAL_ASYNCH", - "TRNG", - "FLASH", - "MPU" - ], - "release_versions": [ - "5" - ], - "device_name": "STM32F412ZG", - "bootloader_supported": true, - "public": false, - "config": { - "clock_source": { - "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSI", - "macro_name": "CLOCK_SOURCE" - } - }, - "overrides": { - "network-default-interface-type": "WIFI" - } - }, - "MTB_USI_WM_BN_BM_22": { - "overrides": { - "lse_available": 0 - }, - "device_has_remove": [ - "LPTICKER" - ], - "features_remove": [ - "BLE" - ], - "inherits": [ - "USI_WM_BN_BM_22" - ], - "detect_code": [ - "0462" - ] - }, - "MTB_ADV_WISE_1530": { - "inherits": [ - "USI_WM_BN_BM_22" - ], - "config": { - "led1": "PA_4", - "led2": "PC_12", - "led3": "NC" - }, - "overrides": { - "stdio_uart_tx": "PB_10", - "stdio_uart_rx": "PC_11" - }, - "detect_code": [ - "0459" - ] - }, "DISCO_F413ZH": { "components_add": [ "QSPIF", @@ -4222,53 +3659,6 @@ ] } }, - "MTB_STM_S2LP": { - "inherits": [ - "FAMILY_STM32" - ], - "core": "Cortex-M4F", - "config": { - "clock_source": { - "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (8MHz) | USE_PLL_HSI", - "value": "USE_PLL_HSE_XTAL", - "macro_name": "CLOCK_SOURCE" - }, - "clock_source_usb": { - "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)", - "value": "1", - "macro_name": "CLOCK_SOURCE_USB" - } - }, - "extra_labels_add": [ - "STM32F4", - "STM32F429xI" - ], - "components_add": [ - "FLASHIAP" - ], - "macros_add": [ - "STM32F429xx" - ], - "device_has_add": [ - "ANALOGOUT", - "CAN", - "SERIAL_ASYNCH", - "TRNG", - "FLASH", - "MPU" - ], - "detect_code": [ - "0467" - ], - "release_versions": [ - "5" - ], - "device_name": "STM32F429ZI", - "bootloader_supported": true, - "overrides": { - "network-default-interface-type": "MESH" - } - }, "NUCLEO_F439ZI": { "inherits": [ "FAMILY_STM32" @@ -4319,44 +3709,6 @@ "network-default-interface-type": "ETHERNET" } }, - "MTB_STM32_F439": { - "inherits": [ - "FAMILY_STM32" - ], - "core": "Cortex-M4F", - "config": { - "clock_source": { - "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (8MHz) | USE_PLL_HSI", - "value": "USE_PLL_HSE_XTAL", - "macro_name": "CLOCK_SOURCE" - } - }, - "extra_labels_add": [ - "STM32F4", - "STM32F439xI" - ], - "macros_add": [ - "STM32F439xx", - "MBEDTLS_CONFIG_HW_SUPPORT" - ], - "device_has_add": [ - "ANALOGOUT", - "CAN", - "SERIAL_ASYNCH", - "SERIAL_FC", - "TRNG", - "FLASH", - "MPU" - ], - "detect_code": [ - "0469" - ], - "release_versions": [ - "5" - ], - "device_name": "STM32F439VI", - "bootloader_supported": true - }, "NUCLEO_F446RE": { "inherits": [ "FAMILY_STM32" @@ -5863,49 +5215,6 @@ "0830" ] }, - "OLIMEX_STM32E407_F407ZG": { - "inherits": [ - "FAMILY_STM32" - ], - "core": "Cortex-M4F", - "extra_labels_add": [ - "STM32F4", - "STM32F407xG" - ], - "macros_add": [ - "STM32F407xx" - ], - "config": { - "clock_source": { - "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI", - "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI", - "macro_name": "CLOCK_SOURCE" - }, - "hse_value": { - "macro_name": "HSE_VALUE", - "value": "12000000" - } - }, - "overrides": { - "lse_available": 0 - }, - "device_has_add": [ - "ANALOGOUT", - "TRNG", - "FLASH", - "MPU", - "EMAC", - "CAN", - "USBDEVICE" - ], - "device_has_remove": [ - "LPTICKER" - ], - "release_versions": [ - "5" - ], - "device_name": "STM32F407ZG" - }, "DISCO_F429ZI": { "inherits": [ "FAMILY_STM32" @@ -6110,46 +5419,18 @@ }, "lpticker_lptim": { "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", - "value": 1 - } - }, - "macros_add": [ - "MBED_TICKLESS", - "EXTRA_IDLE_STACK_REQUIRED" - ], - "overrides": { - "lpticker_delay_ticks": 0 - }, - "detect_code": [ - "0833" - ], - "device_has_add": [ - "ANALOGOUT", - "CRC", - "SERIAL_ASYNCH", - "TRNG", - "FLASH", - "MPU" - ], - "release_versions": [ - "2", - "5" - ], - "device_name": "STM32L072CZ" - }, - "MTB_MURATA_ABZ": { - "inherits": [ - "FAMILY_STM32" - ], - "core": "Cortex-M0+", - "extra_labels_add": [ - "STM32L0", - "STM32L0x2xZ", - "STM32L082CZ", - "STM32L082xx" + "value": 1 + } + }, + "macros_add": [ + "MBED_TICKLESS", + "EXTRA_IDLE_STACK_REQUIRED" ], + "overrides": { + "lpticker_delay_ticks": 0 + }, "detect_code": [ - "0456" + "0833" ], "device_has_add": [ "ANALOGOUT", @@ -6159,13 +5440,11 @@ "FLASH", "MPU" ], - "device_has_remove": [ - "LPTICKER" - ], "release_versions": [ + "2", "5" ], - "device_name": "STM32L082CZ" + "device_name": "STM32L072CZ" }, "DISCO_F746NG": { "inherits": [ @@ -6365,50 +5644,6 @@ ] } }, - "MTB_STM_L475": { - "inherits": [ - "FAMILY_STM32" - ], - "core": "Cortex-M4F", - "extra_labels_add": [ - "STM32L4", - "STM32L475xG", - "STM32L475VG" - ], - "config": { - "clock_source": { - "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (8MHz) | USE_PLL_HSI | USE_PLL_MSI", - "value": "USE_PLL_HSE_XTAL", - "macro_name": "CLOCK_SOURCE" - }, - "lpticker_lptim": { - "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", - "value": 0 - } - }, - "detect_code": [ - "0468" - ], - "macros_add": [ - "STM32L475xx", - "USBHOST_OTHER", - "MBED_SPLIT_HEAP" - ], - "device_has_add": [ - "ANALOGOUT", - "CAN", - "CRC", - "SERIAL_FC", - "TRNG", - "FLASH", - "MPU" - ], - "release_versions": [ - "5" - ], - "device_name": "STM32L475VG", - "bootloader_supported": true - }, "DISCO_L476VG": { "components_add": [ "QSPIF", @@ -6725,47 +5960,6 @@ "device_name": "STM32L471QG", "bootloader_supported": true }, - "MTB_MTS_DRAGONFLY": { - "inherits": [ - "FAMILY_STM32" - ], - "core": "Cortex-M4F", - "extra_labels_add": [ - "STM32F4" - ], - "overrides": { - "lse_available": 0 - }, - "macros_add": [ - "STM32F411xE", - "HSE_VALUE=26000000" - ], - "device_has_add": [ - "MPU" - ], - "device_has_remove": [ - "SERIAL_FC", - "LPTICKER" - ], - "post_binary_hook": { - "function": "MTSCode.combine_bins_mtb_mts_dragonfly", - "toolchains": [ - "GCC_ARM", - "ARM_STD", - "ARM_MICRO", - "IAR" - ] - }, - "release_versions": [ - "2", - "5" - ], - "device_name": "STM32F411RE", - "bootloader_supported": true, - "detect_code": [ - "0454" - ] - }, "XDOT_L151CC": { "inherits": [ "FAMILY_STM32" @@ -6812,80 +6006,6 @@ "8080" ] }, - "MTB_MTS_XDOT": { - "inherits": [ - "FAMILY_STM32" - ], - "core": "Cortex-M3", - "default_toolchain": "ARM", - "extra_labels_add": [ - "STM32L1", - "STM32L151CC" - ], - "config": { - "hse_value": { - "value": "24000000", - "macro_name": "HSE_VALUE" - } - }, - "overrides": { - "stdio_uart_tx": "PA_2", - "stdio_uart_rx": "PA_3" - }, - "supported_toolchains": [ - "ARM", - "GCC_ARM", - "IAR" - ], - "device_has_add": [ - "ANALOGOUT", - "FLASH", - "MPU" - ], - "device_has_remove": [ - "SERIAL_FC" - ], - "release_versions": [ - "5" - ], - "device_name": "STM32L151CC", - "bootloader_supported": true, - "detect_code": [ - "0453" - ] - }, - "MTB_RAK811": { - "inherits": [ - "FAMILY_STM32" - ], - "core": "Cortex-M3", - "default_toolchain": "ARM", - "extra_labels_add": [ - "STM32L1", - "STM32L151xBA", - "STM32L151CBA" - ], - "supported_toolchains": [ - "ARM", - "GCC_ARM", - "IAR" - ], - "device_has_add": [ - "ANALOGOUT", - "MPU" - ], - "device_has_remove": [ - "SERIAL_FC" - ], - "release_versions": [ - "5" - ], - "device_name": "STM32L151CBxxA", - "bootloader_supported": true, - "detect_code": [ - "0457" - ] - }, "MOTE_L152RC": { "inherits": [ "FAMILY_STM32" @@ -7050,35 +6170,6 @@ "C036" ] }, - "NZ32_SC151": { - "inherits": [ - "FAMILY_STM32" - ], - "core": "Cortex-M3", - "default_toolchain": "uARM", - "program_cycle_s": 1.5, - "extra_labels_add": [ - "STM32L1", - "STM32L151RC" - ], - "overrides": { - "lse_available": 0 - }, - "supported_toolchains": [ - "ARM", - "uARM", - "GCC_ARM" - ], - "device_has_add": [ - "ANALOGOUT", - "MPU" - ], - "device_has_remove": [ - "LPTICKER" - ], - "default_lib": "small", - "device_name": "STM32L151RC" - }, "MCU_NRF51": { "inherits": [ "Target" @@ -7864,58 +6955,6 @@ "TARGET_MTM_CONNECT04S" ] }, - "MTB_LAIRD_BL600": { - "inherits": [ - "MCU_NRF51_32K_UNIFIED" - ], - "device_has": [ - "USTICKER", - "LPTICKER", - "ANALOGIN", - "I2C", - "I2C_ASYNCH", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SERIAL_ASYNCH", - "SERIAL_FC", - "SLEEP", - "SPI", - "SPI_ASYNCH", - "SPISLAVE" - ], - "device_name": "nRF51822_xxAC", - "release_versions": [ - "5" - ], - "extra_labels_add": [ - "MTB_LAIRD_BL600" - ], - "config": { - "usb_tx": { - "help": "Value SIO_21", - "value": "SIO_21" - }, - "usb_rx": { - "help": "Value SIO_22", - "value": "SIO_22" - }, - "stdio_uart": { - "help": "Value: UART_0", - "value": "UART_0", - "macro_name": "STDIO_UART" - } - }, - "overrides": { - "uart_hwfc": 0 - }, - "detect_code": [ - "0452" - ] - }, "TY51822R3": { "inherits": [ "MCU_NRF51_32K_UNIFIED" @@ -10266,54 +9305,20 @@ ], "release_versions": [ "2", - "5" - ], - "device_name": "nRF51822_xxAC" - }, - "NRF51_DONGLE": { - "inherits": [ - "MCU_NRF51_32K_UNIFIED" - ], - "progen": { - "target": "nrf51-dongle" - }, - "device_has": [ - "USTICKER", - "LPTICKER", - "I2C", - "I2C_ASYNCH", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SERIAL_ASYNCH", - "SLEEP", - "SPI", - "SPI_ASYNCH", - "SPISLAVE" - ], - "release_versions": [ - "2", - "5" - ], - "detect_code": [ - "1120" + "5" ], "device_name": "nRF51822_xxAC" }, - "OSHCHIP": { + "NRF51_DONGLE": { "inherits": [ "MCU_NRF51_32K_UNIFIED" ], - "overrides": { - "lf_clock_src": "NRF_LF_SRC_RC" + "progen": { + "target": "nrf51-dongle" }, "device_has": [ "USTICKER", "LPTICKER", - "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", @@ -10322,10 +9327,19 @@ "PORTOUT", "PWMOUT", "SERIAL", + "SERIAL_ASYNCH", "SLEEP", "SPI", + "SPI_ASYNCH", "SPISLAVE" ], + "release_versions": [ + "2", + "5" + ], + "detect_code": [ + "1120" + ], "device_name": "nRF51822_xxAC" }, "MCU_NRF52832": { @@ -10452,34 +9466,6 @@ "1101" ] }, - "RIOT_MICRO_MODULE": { - "inherits": [ - "MCU_NRF52832" - ], - "release_versions": [ - "5" - ], - "public": false, - "overrides": { - "network-default-interface-type": "CELLULAR" - }, - "bootloader_supported": false - }, - "RM6100": { - "inherits": [ - "RIOT_MICRO_MODULE" - ], - "device_name": "nRF52832_xxAA" - }, - "RM7100": { - "inherits": [ - "RIOT_MICRO_MODULE" - ], - "macros_add": [ - "CONFIG_NFCT_PINS_AS_GPIOS" - ], - "device_name": "nRF52832_xxAA" - }, "SDT52832B": { "inherits": [ "MCU_NRF52832" @@ -10556,113 +9542,6 @@ "1237" ] }, - "MTB_UBLOX_NINA_B1": { - "inherits": [ - "MCU_NRF52832" - ], - "release_versions": [ - "5" - ], - "device_name": "nRF52832_xxAA", - "macros_add": [ - "CONFIG_GPIO_AS_PINRESET", - "NRF52_PAN_12", - "NRF52_PAN_15", - "NRF52_PAN_20", - "NRF52_PAN_30", - "NRF52_PAN_31", - "NRF52_PAN_36", - "NRF52_PAN_51", - "NRF52_PAN_53", - "NRF52_PAN_54", - "NRF52_PAN_55", - "NRF52_PAN_58", - "NRF52_PAN_62", - "NRF52_PAN_63", - "NRF52_PAN_64" - ], - "detect_code": [ - "0455" - ] - }, - "MTB_LAIRD_BL652": { - "inherits": [ - "MCU_NRF52832" - ], - "release_versions": [ - "5" - ], - "device_name": "nRF52832_xxAA", - "macros_add": [ - "CONFIG_GPIO_AS_PINRESET", - "NRF52_PAN_12", - "NRF52_PAN_15", - "NRF52_PAN_20", - "NRF52_PAN_30", - "NRF52_PAN_31", - "NRF52_PAN_36", - "NRF52_PAN_51", - "NRF52_PAN_53", - "NRF52_PAN_54", - "NRF52_PAN_55", - "NRF52_PAN_58", - "NRF52_PAN_62", - "NRF52_PAN_63", - "NRF52_PAN_64" - ], - "overrides": { - "lf_clock_src": "NRF_LF_SRC_RC", - "console-uart-flow-control": null - }, - "detect_code": [ - "0461" - ] - }, - "MTB_MURATA_WSM_BL241": { - "inherits": [ - "MCU_NRF52832" - ], - "release_versions": [ - "5" - ], - "device_name": "nRF52832_xxAA", - "detect_code": [ - "0466" - ], - "macros_add": [ - "CONFIG_GPIO_AS_PINRESET", - "NRF52_PAN_12", - "NRF52_PAN_15", - "NRF52_PAN_20", - "NRF52_PAN_30", - "NRF52_PAN_31", - "NRF52_PAN_36", - "NRF52_PAN_51", - "NRF52_PAN_53", - "NRF52_PAN_54", - "NRF52_PAN_55", - "NRF52_PAN_58", - "NRF52_PAN_62", - "NRF52_PAN_63", - "NRF52_PAN_64" - ], - "overrides": { - "lf_clock_src": "NRF_LF_SRC_XTAL", - "console-uart-flow-control": null - } - }, - "MTB_ACONNO_ACN52832": { - "inherits": [ - "MCU_NRF52832" - ], - "release_versions": [ - "5" - ], - "device_name": "nRF52832_xxAA", - "detect_code": [ - "0472" - ] - }, "DELTA_DFBM_NQ620": { "supported_form_factors": [ "ARDUINO" @@ -10848,67 +9727,6 @@ "CONFIG_GPIO_AS_PINRESET" ] }, - "MTB_LAIRD_BL654": { - "inherits": [ - "MCU_NRF52840" - ], - "detect_code": [ - "0465" - ], - "features_remove": [ - "CRYPTOCELL310" - ], - "macros_remove": [ - "MBEDTLS_CONFIG_HW_SUPPORT" - ], - "macros_add": [ - "NRFX_RNG_ENABLED=1", - "RNG_ENABLED=1", - "NRF_QUEUE_ENABLED=1", - "CONFIG_GPIO_AS_PINRESET" - ], - "overrides": { - "lf_clock_src": "NRF_LF_SRC_RC", - "console-uart-flow-control": null - } - }, - "MAKERDIARY_NRF52840_MDK": { - "inherits": [ - "MCU_NRF52840" - ], - "detect_code": [ - "1026" - ], - "device_has_remove": [ - "ITM" - ], - "macros_add": [ - "CONFIG_GPIO_AS_PINRESET" - ] - }, - "BLUEPILL_F103C8": { - "inherits": [ - "FAMILY_STM32" - ], - "core": "Cortex-M3", - "default_toolchain": "GCC_ARM", - "extra_labels_add": [ - "STM32F1", - "STM32F103C8" - ], - "supported_toolchains": [ - "GCC_ARM" - ], - "device_has_add": [ - "CAN", - "SERIAL_ASYNCH", - "FLASH" - ], - "device_has_remove": [ - "STDIO_MESSAGES", - "LPTICKER" - ] - }, "NUMAKER_PFM_NUC472": { "core": "Cortex-M4F", "components_add": [ @@ -11876,56 +10694,6 @@ "network-default-interface-type": "WIFI" } }, - "SAKURAIO_EVB_01": { - "inherits": [ - "FAMILY_STM32" - ], - "supported_form_factors": [], - "core": "Cortex-M4F", - "extra_labels_add": [ - "STM32F4", - "STM32F411xE" - ], - "macros_add": [ - "STM32F411xE" - ], - "device_has": [ - "ANALOGIN", - "I2C", - "I2CSLAVE", - "I2C_ASYNCH", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE", - "SPI_ASYNCH", - "STDIO_MESSAGES", - "MPU" - ], - "config": { - "clock_source": { - "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSI", - "macro_name": "CLOCK_SOURCE" - } - }, - "device_has_add": [ - "SERIAL_ASYNCH", - "FLASH" - ], - "release_versions": [ - "2" - ], - "device_name": "STM32F411RE", - "detect_code": [ - "C008" - ] - }, "TMPM46B": { "inherits": [ "Target" @@ -13164,37 +11932,6 @@ } } }, - "IM880B": { - "inherits": [ - "FAMILY_STM32" - ], - "core": "Cortex-M3", - "default_toolchain": "ARM", - "extra_labels_add": [ - "STM32L1", - "STM32L151xBA", - "STM32L151CBA" - ], - "supported_toolchains": [ - "ARM", - "GCC_ARM", - "IAR" - ], - "device_has_add": [ - "ANALOGOUT", - "MPU" - ], - "device_has_remove": [ - "SERIAL_FC" - ], - "macros_add": [ - "HSE_VALUE=16000000" - ], - "release_versions": [ - "5" - ], - "device_name": "STM32L151CBxxA" - }, "MCU_M261": { "core": "Cortex-M23", "default_toolchain": "ARMC6", diff --git a/tools/bootloaders/MTB_MTS_DRAGONFLY/LICENSE.txt b/tools/bootloaders/MTB_MTS_DRAGONFLY/LICENSE.txt deleted file mode 100644 index d648fd563a7..00000000000 --- a/tools/bootloaders/MTB_MTS_DRAGONFLY/LICENSE.txt +++ /dev/null @@ -1,49 +0,0 @@ -Permissive Binary License - -Version 1.0, September 2015 - -Redistribution. Redistribution and use in binary form, without -modification, are permitted provided that the following conditions are -met: - -1) Redistributions must reproduce the above copyright notice and the - following disclaimer in the documentation and/or other materials - provided with the distribution. - -2) Unless to the extent explicitly permitted by law, no reverse - engineering, decompilation, or disassembly of this software is - permitted. - -3) Redistribution as part of a software development kit must include the - accompanying file named “DEPENDENCIES” and any dependencies listed in - that file. - -4) Neither the name of the copyright holder nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - -Limited patent license. The copyright holders (and contributors) grant a -worldwide, non-exclusive, no-charge, royalty-free patent license to -make, have made, use, offer to sell, sell, import, and otherwise -transfer this software, where such license applies only to those patent -claims licensable by the copyright holders (and contributors) that are -necessarily infringed by this software. This patent license shall not -apply to any combinations that include this software. No hardware is -licensed hereunder. - -If you institute patent litigation against any entity (including a -cross-claim or counterclaim in a lawsuit) alleging that the software -itself infringes your patent(s), then your rights granted under this -license shall terminate as of the date such litigation is filed. - -DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND -CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT -NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/tools/bootloaders/MTB_MTS_DRAGONFLY/bootloader.bin b/tools/bootloaders/MTB_MTS_DRAGONFLY/bootloader.bin deleted file mode 100644 index e5c640df1c3..00000000000 Binary files a/tools/bootloaders/MTB_MTS_DRAGONFLY/bootloader.bin and /dev/null differ diff --git a/tools/export/coide/nz32_sc151.coproj.tmpl b/tools/export/coide/nz32_sc151.coproj.tmpl deleted file mode 100644 index 22adf11a3bb..00000000000 --- a/tools/export/coide/nz32_sc151.coproj.tmpl +++ /dev/null @@ -1,90 +0,0 @@ - - - - - - - - - - - - - - - - {% for file in source_files %} - - {% endfor %} - {% for file in header_files %} - - {% endfor %} - - diff --git a/tools/export/lpcxpresso/lpc11u35_401_cproject.tmpl b/tools/export/lpcxpresso/lpc11u35_401_cproject.tmpl deleted file mode 100644 index 5d6714345a8..00000000000 --- a/tools/export/lpcxpresso/lpc11u35_401_cproject.tmpl +++ /dev/null @@ -1,51 +0,0 @@ -{% extends "lpcxpresso/cproject_cortexm0_common.tmpl" %} - -{% block startup_file %}cr_startup_lpc11xx.c{% endblock %} - -{% block cpu_config %}<?xml version="1.0" encoding="UTF-8"?> -<TargetConfig> -<Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC11U35/401" property_count="5" version="70002"/> -<infoList vendor="NXP"> -<info chip="LPC11U35/401" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x0001BC40" name="LPC11U35/401" stub="crt_emu_lpc11_13_nxp"> -<chip> -<name>LPC11U35/401</name> -<family>LPC11Uxx</family> -<vendor>NXP (formerly Philips)</vendor> -<reset board="None" core="Real" sys="Real"/> -<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> -<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> -<memory id="RAM" type="RAM"/> -<memory id="Periph" is_volatile="true" type="Peripheral"/> -<memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/> -<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> -<memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/> -<peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/> -<peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/> -<peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/> -<peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/> -<peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/> -<peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/> -<peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/> -<peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/> -<peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/> -<peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/> -<peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/> -<peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/> -<peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/> -<peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> -<peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/> -<peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/> -<peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/> -<peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/> -<peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/> -<peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/> -<peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/> -</chip> -<processor> -<name gcc_name="cortex-m0">Cortex-M0</name> -<family>Cortex-M</family> -</processor> -<link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/> -</info> -</infoList> -</TargetConfig>{% endblock %} diff --git a/tools/export/lpcxpresso/lpc11u35_401_project.tmpl b/tools/export/lpcxpresso/lpc11u35_401_project.tmpl deleted file mode 100644 index 8b0351edb0f..00000000000 --- a/tools/export/lpcxpresso/lpc11u35_401_project.tmpl +++ /dev/null @@ -1 +0,0 @@ -{% extends "lpcxpresso/project_common.tmpl" %} diff --git a/tools/export/lpcxpresso/lpc11u35_501_cproject.tmpl b/tools/export/lpcxpresso/lpc11u35_501_cproject.tmpl deleted file mode 100644 index 28c3ad01dc7..00000000000 --- a/tools/export/lpcxpresso/lpc11u35_501_cproject.tmpl +++ /dev/null @@ -1,51 +0,0 @@ -{% extends "lpcxpresso/cproject_cortexm0_common.tmpl" %} - -{% block startup_file %}cr_startup_lpc11xx.c{% endblock %} - -{% block cpu_config %}<?xml version="1.0" encoding="UTF-8"?> -<TargetConfig> -<Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC11U35/501" property_count="5" version="70002"/> -<infoList vendor="NXP"> -<info chip="LPC11U35/501" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x0001BC40" name="LPC11U35/501" stub="crt_emu_lpc11_13_nxp"> -<chip> -<name>LPC11U35/501</name> -<family>LPC11Uxx</family> -<vendor>NXP (formerly Philips)</vendor> -<reset board="None" core="Real" sys="Real"/> -<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> -<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> -<memory id="RAM" type="RAM"/> -<memory id="Periph" is_volatile="true" type="Peripheral"/> -<memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/> -<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> -<memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/> -<peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/> -<peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/> -<peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/> -<peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/> -<peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/> -<peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/> -<peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/> -<peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/> -<peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/> -<peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/> -<peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/> -<peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/> -<peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/> -<peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> -<peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/> -<peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/> -<peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/> -<peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/> -<peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/> -<peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/> -<peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/> -</chip> -<processor> -<name gcc_name="cortex-m0">Cortex-M0</name> -<family>Cortex-M</family> -</processor> -<link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/> -</info> -</infoList> -</TargetConfig>{% endblock %} diff --git a/tools/export/lpcxpresso/lpc11u35_501_project.tmpl b/tools/export/lpcxpresso/lpc11u35_501_project.tmpl deleted file mode 100644 index 8b0351edb0f..00000000000 --- a/tools/export/lpcxpresso/lpc11u35_501_project.tmpl +++ /dev/null @@ -1 +0,0 @@ -{% extends "lpcxpresso/project_common.tmpl" %} diff --git a/tools/export/lpcxpresso/lpc11u37h_401_cproject.tmpl b/tools/export/lpcxpresso/lpc11u37h_401_cproject.tmpl deleted file mode 100644 index 614f61fb4e5..00000000000 --- a/tools/export/lpcxpresso/lpc11u37h_401_cproject.tmpl +++ /dev/null @@ -1,51 +0,0 @@ -{% extends "lpcxpresso/cproject_cortexm0_common.tmpl" %} - -{% block startup_file %}cr_startup_lpc11xx.c{% endblock %} - -{% block cpu_config %}<?xml version="1.0" encoding="UTF-8"?> -<TargetConfig> -<Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC11U37H/401" property_count="5" version="70002"/> -<infoList vendor="NXP"> -<info chip="LPC11U37H/401" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x0001BC40" name="LPC11U37H/401" stub="crt_emu_lpc11_13_nxp"> -<chip> -<name>LPC11U37H/401</name> -<family>LPC11Uxx</family> -<vendor>NXP (formerly Philips)</vendor> -<reset board="None" core="Real" sys="Real"/> -<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> -<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> -<memory id="RAM" type="RAM"/> -<memory id="Periph" is_volatile="true" type="Peripheral"/> -<memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/> -<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> -<memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/> -<peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/> -<peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/> -<peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/> -<peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/> -<peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/> -<peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/> -<peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/> -<peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/> -<peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/> -<peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/> -<peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/> -<peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/> -<peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/> -<peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> -<peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/> -<peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/> -<peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/> -<peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/> -<peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/> -<peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/> -<peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/> -</chip> -<processor> -<name gcc_name="cortex-m0">Cortex-M0</name> -<family>Cortex-M</family> -</processor> -<link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/> -</info> -</infoList> -</TargetConfig>{% endblock %} diff --git a/tools/export/lpcxpresso/lpc11u37h_401_project.tmpl b/tools/export/lpcxpresso/lpc11u37h_401_project.tmpl deleted file mode 100644 index 8b0351edb0f..00000000000 --- a/tools/export/lpcxpresso/lpc11u37h_401_project.tmpl +++ /dev/null @@ -1 +0,0 @@ -{% extends "lpcxpresso/project_common.tmpl" %} diff --git a/tools/export/lpcxpresso/lpc11u68_cproject.tmpl b/tools/export/lpcxpresso/lpc11u68_cproject.tmpl deleted file mode 100644 index 3c37890c5ac..00000000000 --- a/tools/export/lpcxpresso/lpc11u68_cproject.tmpl +++ /dev/null @@ -1,60 +0,0 @@ -{% extends "lpcxpresso/cproject_cortexm0_common.tmpl" %} - -{% block startup_file %}startup_LPC11U68.cpp{% endblock %} - -{% block cpu_config %}<?xml version="1.0" encoding="UTF-8"?> -<TargetConfig> -<Properties property_0="" property_2="LPC11U6x_256K.cfx" property_3="NXP" property_4="LPC11U68" property_count="5" version="70200"/> -<infoList vendor="NXP"> <info chip="LPC11U68" flash_driver="LPC11U6x_256K.cfx" match_id="0x0" name="LPC11U68" stub="crt_emu_cm3_gen"> <chip> <name> LPC11U68</name> -<family> LPC11U6x</family> -<vendor> NXP (formerly Philips)</vendor> -<reset board="None" core="Real" sys="Real"/> -<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> -<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> -<memory id="RAM" type="RAM"/> -<memory id="Periph" is_volatile="true" type="Peripheral"/> -<memoryInstance derived_from="Flash" id="MFlash256" location="0x0" size="0x40000"/> -<memoryInstance derived_from="RAM" id="Ram0_32" location="0x10000000" size="0x8000"/> -<memoryInstance derived_from="RAM" id="Ram1_2" location="0x20000000" size="0x800"/> -<memoryInstance derived_from="RAM" id="Ram2USB_2" location="0x20004000" size="0x800"/> -<peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/> -<peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/> -<peripheralInstance derived_from="I2C0" determined="infoFile" id="I2C0" location="0x40000000"/> -<peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/> -<peripheralInstance derived_from="USART0" determined="infoFile" id="USART0" location="0x40008000"/> -<peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/> -<peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/> -<peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/> -<peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/> -<peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/> -<peripheralInstance derived_from="I2C1" determined="infoFile" id="I2C1" location="0x40020000"/> -<peripheralInstance derived_from="RTC" determined="infoFile" id="RTC" location="0x40024000"/> -<peripheralInstance derived_from="DMATRIGMUX" determined="infoFile" id="DMATRIGMUX" location="0x40028000"/> -<peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/> -<peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/> -<peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/> -<peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> -<peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/> -<peripheralInstance derived_from="USART4" determined="infoFile" id="USART4" location="0x4004c000"/> -<peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/> -<peripheralInstance derived_from="GINT0" determined="infoFile" id="GINT0" location="0x4005c000"/> -<peripheralInstance derived_from="GINT1" determined="infoFile" id="GINT1" location="0x40060000"/> -<peripheralInstance derived_from="USART1" determined="infoFile" id="USART1" location="0x4006c000"/> -<peripheralInstance derived_from="USART2" determined="infoFile" id="USART2" location="0x40070000"/> -<peripheralInstance derived_from="USART3" determined="infoFile" id="USART3" location="0x40074000"/> -<peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/> -<peripheralInstance derived_from="CRC" determined="infoFile" id="CRC" location="0x50000000"/> -<peripheralInstance derived_from="DMA" determined="infoFile" id="DMA" location="0x50004000"/> -<peripheralInstance derived_from="SCT0" determined="infoFile" id="SCT0" location="0x5000c000"/> -<peripheralInstance derived_from="SCT1" determined="infoFile" id="SCT1" location="0x5000e000"/> -<peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0xa0000000"/> -<peripheralInstance derived_from="PINT" determined="infoFile" id="PINT" location="0xa0004000"/> -</chip> -<processor> -<name gcc_name="cortex-m0">Cortex-M0</name> -<family>Cortex-M</family> -</processor> -<link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/> -</info> -</infoList> -</TargetConfig>{% endblock %} diff --git a/tools/export/lpcxpresso/lpc11u68_project.tmpl b/tools/export/lpcxpresso/lpc11u68_project.tmpl deleted file mode 100644 index 8b0351edb0f..00000000000 --- a/tools/export/lpcxpresso/lpc11u68_project.tmpl +++ /dev/null @@ -1 +0,0 @@ -{% extends "lpcxpresso/project_common.tmpl" %} diff --git a/tools/export/lpcxpresso/lpccappuccino_cproject.tmpl b/tools/export/lpcxpresso/lpccappuccino_cproject.tmpl deleted file mode 100644 index 0fce5208a26..00000000000 --- a/tools/export/lpcxpresso/lpccappuccino_cproject.tmpl +++ /dev/null @@ -1,51 +0,0 @@ -{% extends "lpcxpresso/cproject_cortexm0_common.tmpl" %} - -{% block startup_file %}cr_startup_lpc11xx.c{% endblock %} - -{% block cpu_config %}<?xml version="1.0" encoding="UTF-8"?> -<TargetConfig> -<Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC11U37/501" property_count="5" version="70002"/> -<infoList vendor="NXP"> -<info chip="LPC11U37/501" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x0001BC40" name="LPC11U37/501" stub="crt_emu_lpc11_13_nxp"> -<chip> -<name>LPC11U37/501</name> -<family>LPC11Uxx</family> -<vendor>NXP (formerly Philips)</vendor> -<reset board="None" core="Real" sys="Real"/> -<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> -<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> -<memory id="RAM" type="RAM"/> -<memory id="Periph" is_volatile="true" type="Peripheral"/> -<memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/> -<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> -<memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/> -<peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/> -<peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/> -<peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/> -<peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/> -<peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/> -<peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/> -<peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/> -<peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/> -<peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/> -<peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/> -<peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/> -<peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/> -<peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/> -<peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> -<peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/> -<peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/> -<peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/> -<peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/> -<peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/> -<peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/> -<peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/> -</chip> -<processor> -<name gcc_name="cortex-m0">Cortex-M0</name> -<family>Cortex-M</family> -</processor> -<link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/> -</info> -</infoList> -</TargetConfig>{% endblock %} diff --git a/tools/export/lpcxpresso/lpccappuccino_project.tmpl b/tools/export/lpcxpresso/lpccappuccino_project.tmpl deleted file mode 100644 index 8b0351edb0f..00000000000 --- a/tools/export/lpcxpresso/lpccappuccino_project.tmpl +++ /dev/null @@ -1 +0,0 @@ -{% extends "lpcxpresso/project_common.tmpl" %} diff --git a/tools/export/mcuxpresso/lpc11u35_401_cproject.tmpl b/tools/export/mcuxpresso/lpc11u35_401_cproject.tmpl deleted file mode 100644 index 6d94414bbcf..00000000000 --- a/tools/export/mcuxpresso/lpc11u35_401_cproject.tmpl +++ /dev/null @@ -1,49 +0,0 @@ -{% extends "mcuxpresso/.cproject.tmpl" %} - -{% block cpu_config %}<?xml version="1.0" encoding="UTF-8"?> -<TargetConfig> -<Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC11U35/401" property_count="5" version="70002"/> -<infoList vendor="NXP"> -<info chip="LPC11U35/401" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x0001BC40" name="LPC11U35/401" stub="crt_emu_lpc11_13_nxp"> -<chip> -<name>LPC11U35/401</name> -<family>LPC11Uxx</family> -<vendor>NXP (formerly Philips)</vendor> -<reset board="None" core="Real" sys="Real"/> -<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> -<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> -<memory id="RAM" type="RAM"/> -<memory id="Periph" is_volatile="true" type="Peripheral"/> -<memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/> -<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> -<memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/> -<peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/> -<peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/> -<peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/> -<peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/> -<peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/> -<peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/> -<peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/> -<peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/> -<peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/> -<peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/> -<peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/> -<peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/> -<peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/> -<peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> -<peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/> -<peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/> -<peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/> -<peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/> -<peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/> -<peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/> -<peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/> -</chip> -<processor> -<name gcc_name="cortex-m0">Cortex-M0</name> -<family>Cortex-M</family> -</processor> -<link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/> -</info> -</infoList> -</TargetConfig>{% endblock %} diff --git a/tools/export/mcuxpresso/lpccappuccino_cproject.tmpl b/tools/export/mcuxpresso/lpccappuccino_cproject.tmpl deleted file mode 100644 index 1d18842b3d1..00000000000 --- a/tools/export/mcuxpresso/lpccappuccino_cproject.tmpl +++ /dev/null @@ -1,49 +0,0 @@ -{% extends "mcuxpresso/.cproject.tmpl" %} - -{% block cpu_config %}<?xml version="1.0" encoding="UTF-8"?> -<TargetConfig> -<Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC11U37/501" property_count="5" version="70002"/> -<infoList vendor="NXP"> -<info chip="LPC11U37/501" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x0001BC40" name="LPC11U37/501" stub="crt_emu_lpc11_13_nxp"> -<chip> -<name>LPC11U37/501</name> -<family>LPC11Uxx</family> -<vendor>NXP (formerly Philips)</vendor> -<reset board="None" core="Real" sys="Real"/> -<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> -<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> -<memory id="RAM" type="RAM"/> -<memory id="Periph" is_volatile="true" type="Peripheral"/> -<memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/> -<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> -<memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/> -<peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/> -<peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/> -<peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/> -<peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/> -<peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/> -<peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/> -<peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/> -<peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/> -<peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/> -<peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/> -<peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/> -<peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/> -<peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/> -<peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> -<peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/> -<peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/> -<peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/> -<peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/> -<peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/> -<peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/> -<peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/> -</chip> -<processor> -<name gcc_name="cortex-m0">Cortex-M0</name> -<family>Cortex-M</family> -</processor> -<link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/> -</info> -</infoList> -</TargetConfig>{% endblock %} diff --git a/tools/export/sw4stm32/__init__.py b/tools/export/sw4stm32/__init__.py index 8bfa8fbb17c..da6a7e1e048 100644 --- a/tools/export/sw4stm32/__init__.py +++ b/tools/export/sw4stm32/__init__.py @@ -103,11 +103,6 @@ class Sw4STM32(GNUARMEclipse): 'name': 'DISCO-L072CZ-LRWAN1', 'mcuId': 'STM32L072CZTx' }, - 'MTB_MURATA_ABZ': - { - 'name': 'MTB-MURATA-ABZ', - 'mcuId': 'STM32L0x2xZ' - }, 'DISCO_L475VG_IOT01A': { 'name': 'STM32L475G-DISCO', @@ -248,11 +243,6 @@ class Sw4STM32(GNUARMEclipse): 'name': 'NUCLEO-L073RZ', 'mcuId': 'STM32L073RZTx' }, - 'MTB_RAK811': - { - 'name': 'MTB-RAK-811', - 'mcuId': 'STM32L151CBUxA' - }, 'NUCLEO_L152RE': { 'name': 'NUCLEO-L152RE', diff --git a/tools/targets/__init__.py b/tools/targets/__init__.py index 51107957878..ce4d15536e0 100644 --- a/tools/targets/__init__.py +++ b/tools/targets/__init__.py @@ -567,11 +567,6 @@ def combine_bins_mts_dragonfly(t_self, resources, elf, binf): """A hoof for the MTS Dragonfly""" MTSCode._combine_bins_helper("MTS_DRAGONFLY_F411RE", binf) - @staticmethod - def combine_bins_mtb_mts_dragonfly(t_self, resources, elf, binf): - """A hook for the MTB MTS Dragonfly""" - MTSCode._combine_bins_helper("MTB_MTS_DRAGONFLY", binf) - class MCU_NRF51Code(object): """NRF51 Hooks""" diff --git a/tools/test/examples/examples.json b/tools/test/examples/examples.json index 3d57587e259..1afdb7f53fa 100644 --- a/tools/test/examples/examples.json +++ b/tools/test/examples/examples.json @@ -164,7 +164,7 @@ "sub-repo-example": false, "subs": [], "features" : [], - "targets" : ["DISCO_L072CZ_LRWAN1", "MTB_MTS_XDOT", "MTS_MDOT_F411RE"], + "targets" : ["DISCO_L072CZ_LRWAN1", "MTS_MDOT_F411RE"], "toolchains" : [], "exporters": [], "compile" : true, diff --git a/tools/test_configs/NIDDInterface.json b/tools/test_configs/NIDDInterface.json index 21beb203e9d..8f7e5e17492 100644 --- a/tools/test_configs/NIDDInterface.json +++ b/tools/test_configs/NIDDInterface.json @@ -49,10 +49,6 @@ "platform.default-serial-baud-rate": 115200, "mbed-trace.enable": true, "cellular.debug-at": true - }, - "MTB_STM_L475": { - "UBLOX_N2XX.tx": "TX1", - "UBLOX_N2XX.rx": "RX1" } } } diff --git a/tools/test_configs/Wi-SUNInterface.json b/tools/test_configs/Wi-SUNInterface.json index 683f13ef370..1b11537ce70 100644 --- a/tools/test_configs/Wi-SUNInterface.json +++ b/tools/test_configs/Wi-SUNInterface.json @@ -42,9 +42,6 @@ }, "NUCLEO_F429ZI": { "s2lp.provide-default" : true - }, - "MTB_STM_S2LP": { - "s2lp.provide-default" : true } } } diff --git a/tools/test_configs/target_configs.json b/tools/test_configs/target_configs.json index 08a8d93bb55..c01a11e4889 100644 --- a/tools/test_configs/target_configs.json +++ b/tools/test_configs/target_configs.json @@ -19,15 +19,6 @@ "default_test_configuration": "NONE", "test_configurations": ["ISM43362_WIFI"] }, - "MTB_ADV_WISE_1530": { - "nsapi.socket-stats-enable": true, - "default_test_configuration": "NONE", - "test_configurations": ["HEAPBLOCKDEVICE_AND_WIFI"] - }, - "MTB_USI_WM_BN_BM_22": { - "default_test_configuration": "NONE", - "test_configurations": ["HEAPBLOCKDEVICE_AND_WIFI"] - }, "WIO_EMW3166": { "default_test_configuration": "NONE", "test_configurations": ["HEAPBLOCKDEVICE_AND_WIFI"]