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Merge pull request #13826 from arduino/portenta-mainline
Add Arduino Portenta H7 as target
2 parents 6e81af2 + 62b6cc9 commit d0cd5fa

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19 files changed

+1737
-7
lines changed

19 files changed

+1737
-7
lines changed

‎connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/CMakeLists.txt

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,19 +3,21 @@
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if("DISCO_H747I" IN_LIST MBED_TARGET_LABELS)
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add_subdirectory(TARGET_DISCO_H747I)
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elseif("PORTENTA_H7" IN_LIST MBED_TARGET_LABELS)
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add_subdirectory(TARGET_PORTENTA_H7)
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elseif("NUCLEO_H743ZI" IN_LIST MBED_TARGET_LABELS)
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add_subdirectory(TARGET_NUCLEO_H743ZI)
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elseif("NUCLEO_H743ZI2" IN_LIST MBED_TARGET_LABELS)
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add_subdirectory(TARGET_NUCLEO_H743ZI2)
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endif()
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target_include_directories(mbed-emac
13-
PRIVATE
15+
INTERFACE
1416
.
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./lan8742
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)
1719

1820
target_sources(mbed-emac
19-
PRIVATE
21+
INTERFACE
2022
lan8742/lan8742.c
2123
)

‎connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/CMakeLists.txt

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
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# Copyright (c) 2020 ARM Limited. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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target_sources(mbed-emac
5+
INTERFACE
6+
stm32h7_eth_init.c
7+
)

‎connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c

Lines changed: 177 additions & 0 deletions
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@@ -0,0 +1,177 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2018, STMicroelectronics
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* Copyright (c) 2020, Arduino SA
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define ETHERNET 1
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#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT
35+
36+
#include "stm32h7xx_hal.h"
37+
#include "portenta_power.h"
38+
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#define ETH_TX_EN_Pin GPIO_PIN_11
40+
#define ETH_TX_EN_GPIO_Port GPIOG
41+
#define ETH_TXD1_Pin GPIO_PIN_12
42+
#define ETH_TXD1_GPIO_Port GPIOG
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#define ETH_TXD0_Pin GPIO_PIN_13
44+
#define ETH_TXD0_GPIO_Port GPIOG
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#define ETH_MDC_SAI4_D1_Pin GPIO_PIN_1
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#define ETH_MDC_SAI4_D1_GPIO_Port GPIOC
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#define ETH_MDIO_Pin GPIO_PIN_2
48+
#define ETH_MDIO_GPIO_Port GPIOA
49+
#define ETH_REF_CLK_Pin GPIO_PIN_1
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#define ETH_REF_CLK_GPIO_Port GPIOA
51+
#define ETH_CRS_DV_Pin GPIO_PIN_7
52+
#define ETH_CRS_DV_GPIO_Port GPIOA
53+
#define ETH_RXD0_Pin GPIO_PIN_4
54+
#define ETH_RXD0_GPIO_Port GPIOC
55+
#define ETH_RXD1_Pin GPIO_PIN_5
56+
#define ETH_RXD1_GPIO_Port GPIOC
57+
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/**
59+
* Override HAL Eth Init function
60+
*/
61+
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
62+
{
63+
GPIO_InitTypeDef GPIO_InitStruct;
64+
if(heth->Instance == ETH)
65+
{
66+
enableEthPowerSupply();
67+
68+
#if !(defined(DUAL_CORE) && defined(CORE_CM4))
69+
/* Disable DCache for STM32H7 family */
70+
SCB_DisableDCache();
71+
#endif
72+
73+
/* GPIO Ports Clock Enable */
74+
__HAL_RCC_GPIOA_CLK_ENABLE();
75+
// __HAL_RCC_GPIOB_CLK_ENABLE();
76+
__HAL_RCC_GPIOC_CLK_ENABLE();
77+
__HAL_RCC_GPIOG_CLK_ENABLE();
78+
// __HAL_RCC_GPIOH_CLK_ENABLE();
79+
80+
/* Enable Peripheral clock */
81+
__HAL_RCC_ETH1MAC_CLK_ENABLE();
82+
__HAL_RCC_ETH1TX_CLK_ENABLE();
83+
__HAL_RCC_ETH1RX_CLK_ENABLE();
84+
85+
/* Set pinstrap for 100mbit */
86+
// TODO
87+
88+
/* Reset ETH Phy */
89+
__HAL_RCC_GPIOJ_CLK_ENABLE();
90+
GPIO_InitTypeDef gpio_eth_rst_init_structure;
91+
gpio_eth_rst_init_structure.Pin = GPIO_PIN_15;
92+
gpio_eth_rst_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
93+
gpio_eth_rst_init_structure.Pull = GPIO_NOPULL;
94+
gpio_eth_rst_init_structure.Speed = GPIO_SPEED_FREQ_LOW;
95+
HAL_GPIO_Init(GPIOJ, &gpio_eth_rst_init_structure);
96+
97+
gpio_eth_rst_init_structure.Pin = ETH_RXD0_Pin | ETH_RXD1_Pin;
98+
HAL_GPIO_Init(GPIOC, &gpio_eth_rst_init_structure);
99+
HAL_GPIO_WritePin(GPIOC, ETH_RXD0_Pin, 1);
100+
HAL_GPIO_WritePin(GPIOC, ETH_RXD1_Pin, 1);
101+
gpio_eth_rst_init_structure.Pin = ETH_CRS_DV_Pin;
102+
HAL_GPIO_Init(GPIOA, &gpio_eth_rst_init_structure);
103+
HAL_GPIO_WritePin(GPIOA, ETH_CRS_DV_Pin, 1);
104+
105+
HAL_Delay(25);
106+
HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0);
107+
HAL_Delay(100);
108+
HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 1);
109+
110+
/**ETH GPIO Configuration
111+
PG11 ------> ETH_TX_EN
112+
PG12 ------> ETH_TXD1
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PG13 ------> ETH_TXD0
114+
PC1 ------> ETH_MDC
115+
PA2 ------> ETH_MDIO
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PA1 ------> ETH_REF_CLK
117+
PA7 ------> ETH_CRS_DV
118+
PC4 ------> ETH_RXD0
119+
PC5 ------> ETH_RXD1
120+
*/
121+
GPIO_InitStruct.Pin = ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin;
122+
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
123+
GPIO_InitStruct.Pull = GPIO_NOPULL;
124+
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
125+
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
126+
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
127+
128+
GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin;
129+
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
130+
GPIO_InitStruct.Pull = GPIO_NOPULL;
131+
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
132+
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
133+
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
134+
135+
GPIO_InitStruct.Pin = ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin;
136+
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
137+
GPIO_InitStruct.Pull = GPIO_NOPULL;
138+
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
139+
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
140+
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
141+
}
142+
}
143+
144+
/**
145+
* Override HAL Eth DeInit function
146+
*/
147+
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
148+
{
149+
if(heth->Instance == ETH)
150+
{
151+
/* Peripheral clock disable */
152+
__HAL_RCC_ETH1MAC_CLK_DISABLE();
153+
__HAL_RCC_ETH1TX_CLK_DISABLE();
154+
__HAL_RCC_ETH1RX_CLK_DISABLE();
155+
156+
/**ETH GPIO Configuration
157+
PG11 ------> ETH_TX_EN
158+
PG12 ------> ETH_TXD1
159+
PG13 ------> ETH_TXD0
160+
PC1 ------> ETH_MDC
161+
PA2 ------> ETH_MDIO
162+
PA1 ------> ETH_REF_CLK
163+
PA7 ------> ETH_CRS_DV
164+
PC4 ------> ETH_RXD0
165+
PC5 ------> ETH_RXD1
166+
*/
167+
HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin);
168+
169+
HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin);
170+
171+
HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin);
172+
173+
HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0);
174+
}
175+
}
176+
177+
#endif /* USE_USER_DEFINED_HAL_ETH_MSPINIT */

‎connectivity/drivers/emac/TARGET_STM/stm32xx_emac.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -654,8 +654,10 @@ int STM32_EMAC::low_level_input(emac_mem_buf_t **buf)
654654
/* Build Rx descriptor to be ready for next data reception */
655655
HAL_ETH_BuildRxDescriptors(&EthHandle);
656656

657+
#if !(defined(DUAL_CORE) && defined(CORE_CM4))
657658
/* Invalidate data cache for ETH Rx Buffers */
658659
SCB_InvalidateDCache_by_Addr((uint32_t *)RxBuff.buffer, frameLength);
660+
#endif
659661

660662
*buf = pbuf_alloc(PBUF_RAW, frameLength, PBUF_POOL);
661663
if (*buf) {

‎connectivity/lwipstack/mbed_lib.json

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Original file line numberDiff line numberDiff line change
@@ -210,6 +210,9 @@
210210
"MIMXRT1050_EVK": {
211211
"mem-size": 36560
212212
},
213+
"PORTENTA_H7": {
214+
"mem-size": 16000
215+
},
213216
"FVP_MPS2_M3": {
214217
"mem-size": 36560
215218
},

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/CMakeLists.txt

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,12 +3,18 @@
33

44
if("DISCO_H747I" IN_LIST MBED_TARGET_LABELS)
55
add_subdirectory(TARGET_DISCO_H747I)
6-
elseif("STM32H747xI_CM4" IN_LIST MBED_TARGET_LABELS)
7-
add_subdirectory(TARGET_STM32H747xI_CM4)
6+
elseif("PORTENTA_H7" IN_LIST MBED_TARGET_LABELS)
7+
add_subdirectory(TARGET_PORTENTA_H7)
88
elseif("STM32H7A3xIQ" IN_LIST MBED_TARGET_LABELS)
99
add_subdirectory(TARGET_STM32H7A3xIQ)
1010
endif()
1111

12+
if("STM32H747xI_CM7" IN_LIST MBED_TARGET_LABELS)
13+
add_subdirectory(TARGET_STM32H747xI_CM7)
14+
elseif("STM32H747xI_CM4" IN_LIST MBED_TARGET_LABELS)
15+
add_subdirectory(TARGET_STM32H747xI_CM4)
16+
endif()
17+
1218
target_sources(mbed-core
1319
INTERFACE
1420
system_clock.c

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/CMakeLists.txt

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
# Copyright (c) 2020 ARM Limited. All rights reserved.
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
target_sources(mbed-core
5+
INTERFACE
6+
PeripheralPins.c
7+
system_clock_override.c
8+
portenta_power.cpp
9+
)
10+
11+
target_include_directories(mbed-core
12+
INTERFACE
13+
.
14+
)
15+

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