PSOC6: update the HAL implementation to latest PDL

Integrate the latest fixes to the PSoC 6 HAL.

Author: vmedcy

targets/TARGET_Cypress/TARGET_PSOC6/PeripheralPins.h

@@ -1,6 +1,8 @@
 /*
  * mbed Microcontroller Library
  * Copyright (c) 2017-2018 Future Electronics
+ * Copyright (c) 2018-2019 Cypress Semiconductor Corporation
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.

targets/TARGET_Cypress/TARGET_PSOC6/analogin_api.c

@@ -1,6 +1,8 @@
 /*
  * mbed Microcontroller Library
  * Copyright (c) 2017-2018 Future Electronics
+ * Copyright (c) 2018-2019 Cypress Semiconductor Corporation
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -18,6 +20,7 @@
 #include "device.h"
 #include "analogin_api.h"
 #include "cy_sar.h"
+#include "cy_sysanalog.h"
 #include "psoc6_utils.h"
 #include "mbed_assert.h"
 #include "mbed_error.h"
@@ -41,6 +44,7 @@ const uint32_t SAR_BASE_CLOCK_HZ = 18000000;    // 18 MHz or less
     CY_SAR_CHAN_SAMPLE_TIME_0 \
 )
 
+#define CY_SAR_PORT_9   (9uL)  
 
 /** Global SAR configuration data, modified as channels are configured.
  */
@@ -106,10 +110,14 @@ static void sar_init(analogin_t *obj)
         }
         Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT,
                                    sar_clock_divider,
-                                   ((CY_CLK_PERICLK_FREQ_HZ + SAR_BASE_CLOCK_HZ / 2) / SAR_BASE_CLOCK_HZ) - 1);
+                                   ((cy_PeriClkFreqHz + SAR_BASE_CLOCK_HZ / 2) / SAR_BASE_CLOCK_HZ) - 1);
         Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, sar_clock_divider);
         Cy_SysClk_PeriphAssignDivider(obj->clock, CY_SYSCLK_DIV_8_BIT, sar_clock_divider);
 
+        /* Init and Enable the Analog Reference for SAR ADC operation */
+        Cy_SysAnalog_Init(&Cy_SysAnalog_Fast_Local);
+        Cy_SysAnalog_Enable();
+
         Cy_SAR_Init(obj->base, &sar_config);
         Cy_SAR_Enable(obj->base);
     }
@@ -123,21 +131,24 @@ void analogin_init(analogin_t *obj, PinName pin)
     MBED_ASSERT(obj);
     MBED_ASSERT(pin != (PinName)NC);
 
-
     sar = pinmap_peripheral(pin, PinMap_ADC);
     if (sar != (uint32_t)NC) {
-        if (cy_reserve_io_pin(pin)) {
+
+        if ((0 != cy_reserve_io_pin(pin)) && !sar_initialized) {
             error("ANALOG IN pin reservation conflict.");
         }
-        obj->base = (SAR_Type*)CY_PERIPHERAL_BASE(sar);
+
+        /* Initialize object */
+        obj->base = (SAR_Type *) CY_PERIPHERAL_BASE(sar);
         obj->pin = pin;
         obj->channel_mask = 1 << CY_PIN(pin);
 
-        // Configure clock.
+        /* Configure SAR hardware */
         sar_function = pinmap_function(pin, PinMap_ADC);
         obj->clock = CY_PIN_CLOCK(sar_function);
         sar_init(obj);
         pin_function(pin, sar_function);
+
     } else {
         error("ANALOG IN pinout mismatch.");
     }
@@ -153,16 +164,43 @@ float analogin_read(analogin_t *obj)
 uint16_t analogin_read_u16(analogin_t *obj)
 {
     uint32_t result = 0;
+    uint32_t port = CY_PORT(obj->pin);
+    GPIO_PRT_Type *portPrt = Cy_GPIO_PortToAddr(port);
 
     Cy_SAR_SetChanMask(obj->base, obj->channel_mask);
-    Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, obj->channel_mask, CY_SAR_SWITCH_CLOSE);
+
+    /* The port 10 uses the direct connection to the pin */
+    if (CY_SAR_PORT_9 != port) {
+        /* Connect the SAR Vplus input to the pin directly */
+        Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, obj->channel_mask, CY_SAR_SWITCH_CLOSE);
+    }
+    else {
+        /* Connect the SAR Vplus input to the AMUXA bus */
+        Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Msk, CY_SAR_SWITCH_CLOSE);
+        
+        /* Connect the AMUXA bus to the pin */
+        Cy_GPIO_SetHSIOM(portPrt, CY_PIN(obj->pin), HSIOM_SEL_AMUXA);
+    }
+
     Cy_SAR_StartConvert(obj->base, CY_SAR_START_CONVERT_SINGLE_SHOT);
     if (Cy_SAR_IsEndConversion(obj->base, CY_SAR_WAIT_FOR_RESULT) == CY_SAR_SUCCESS) {
         result = Cy_SAR_GetResult32(obj->base, CY_PIN(obj->pin));
     } else {
         error("ANALOG IN: measurement failed!");
     }
-    Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, obj->channel_mask, CY_SAR_SWITCH_OPEN);
+ 
+    if (CY_SAR_PORT_9 != port) {
+        /* Disconnect the SAR Vplus input from the pin */
+        Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, obj->channel_mask, CY_SAR_SWITCH_OPEN);
+    }
+    else {
+        /* Disconnect the AMUXA bus from the pin */
+        Cy_GPIO_SetHSIOM(portPrt, CY_PIN(obj->pin), HSIOM_SEL_GPIO);
+        
+        /* Disconnect the SAR Vplus input from the AMUXA bus */
+        Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Msk, CY_SAR_SWITCH_OPEN);
+    }
+
     // We are running 16x oversampling extending results to 16 bits.
     return (uint16_t)(result);
 }

targets/TARGET_Cypress/TARGET_PSOC6/analogout_api.c

@@ -1,6 +1,8 @@
 /*
  * mbed Microcontroller Library
  * Copyright (c) 2017-2018 Future Electronics
+ * Copyright (c) 2018-2019 Cypress Semiconductor Corporation
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -66,11 +68,10 @@ static void ctdac_init(dac_t *obj)
         dac_clock_divider = cy_clk_allocate_divider(CY_SYSCLK_DIV_8_BIT);
         if (dac_clock_divider == CY_INVALID_DIVIDER) {
             error("CTDAC clock divider allocation failed.");
-            return;
         }
         Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT,
                                    dac_clock_divider,
-                                   ((CY_CLK_PERICLK_FREQ_HZ + CTDAC_BASE_CLOCK_HZ / 2) / CTDAC_BASE_CLOCK_HZ) - 1);
+                                   ((cy_PeriClkFreqHz + CTDAC_BASE_CLOCK_HZ / 2) / CTDAC_BASE_CLOCK_HZ) - 1);
         Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, dac_clock_divider);
         Cy_SysClk_PeriphAssignDivider(obj->clock, CY_SYSCLK_DIV_8_BIT, dac_clock_divider);
 
@@ -90,25 +91,37 @@ void analogout_init(dac_t *obj, PinName pin)
 
     dac = pinmap_peripheral(pin, PinMap_DAC);
     if (dac != (uint32_t)NC) {
-        if (cy_reserve_io_pin(pin)) {
+
+        if ((0 != cy_reserve_io_pin(pin)) && !ctdac_initialized) {
             error("ANALOG OUT pin reservation conflict.");
         }
-        obj->base = (CTDAC_Type*)CY_PERIPHERAL_BASE(dac);
+
+        /* Initialize object */
+        obj->base = (CTDAC_Type *)CY_PERIPHERAL_BASE(dac);
         obj->pin = pin;
 
-        // Configure clock.
+        /* Configure CTDAC hardware */
         dac_function = pinmap_function(pin, PinMap_DAC);
         obj->clock = CY_PIN_CLOCK(dac_function);
         pin_function(pin, dac_function);
+
+        if (AOUT != pin) {
+            const PinName directOutput = AOUT;
+
+            /* Connect AOUT to the AMUXA bus to drive output */
+            Cy_GPIO_SetHSIOM(Cy_GPIO_PortToAddr(CY_PORT(directOutput)), CY_PIN(directOutput), HSIOM_SEL_AMUXA);
+        }
+
         ctdac_init(obj);
+
     } else {
         error("ANALOG OUT pinout mismatch.");
     }
 }
 
 void analogout_free(dac_t *obj)
 {
-    // Not supported yet.
+    /* MBED AnalogIn driver does not call this function in destructor */
 }
 
 void analogout_write(dac_t *obj, float value)

targets/TARGET_Cypress/TARGET_PSOC6/flash_api.c

@@ -16,7 +16,7 @@
 
 #include "device.h"
 #include "flash_api.h"
-#include "drivers/peripheral/flash/cy_flash.h"
+#include "cy_flash.h"
 
 #if DEVICE_FLASH
 

targets/TARGET_Cypress/TARGET_PSOC6/gpio_api.c

@@ -1,6 +1,8 @@
 /*
  * mbed Microcontroller Library
  * Copyright (c) 2017-2018 Future Electronics
+ * Copyright (c) 2018-2019 Cypress Semiconductor Corporation
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -60,19 +62,14 @@ void gpio_init(gpio_t *obj, PinName pin)
 
     MBED_ASSERT(CY_PIN(obj->pin) < 8); // PSoC6 architecture supports 8 pins per port.
 
-    /*
-     * Perform i/o reservation only if this is called outside of critical section/interrupt context.
-     * This is a workaround for mbed_die() implementation, which configures LED1 inside critical section.
-     * Normally user is advised to perform all of the i/o configuration at the program beginning,
-     * or elsewhere in the running thread context. when we detect that we are in the wrong context here,
-     * we assume it's explicitly called from mbed_die() or other fault handling, so eventual forcing
-     * of the pin mode is deliberate and should not cause more problems.
-     */
+    /* Ignore pin reservation result because there is not possibility to release
+     * reserved HW resource. The MBED does not provide proper destructors for
+     * doing that.
+    */
     if (!(IsIrqMode() || IsIrqMasked())) {
-        if (cy_reserve_io_pin(pin)) {
-            error("GPIO pin reservation conflict.");
-        }
+        (void) cy_reserve_io_pin(pin);
     }
+
     obj->port = Cy_GPIO_PortToAddr(CY_PORT(obj->pin));
 
     const uint32_t outputVal = 0;

targets/TARGET_Cypress/TARGET_PSOC6/gpio_irq_api.c

@@ -1,6 +1,8 @@
 /*
  * mbed Microcontroller Library
  * Copyright (c) 2017-2018 Future Electronics
+ * Copyright (c) 2018-2019 Cypress Semiconductor Corporation
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -48,7 +50,15 @@ static void gpio_irq_dispatcher(uint32_t port_id)
             gpio_irq_t *obj = irq_objects[port_id][pin];
             MBED_ASSERT(obj);
             Cy_GPIO_ClearInterrupt(port, pin);
-            event = (obj->mode == IRQ_FALL)? IRQ_FALL : IRQ_RISE;
+            /*    event = (obj->mode == IRQ_FALL)? IRQ_FALL : IRQ_RISE; */
+
+            /* Read pin to determine the edge to support "both" mode */
+            event = (0UL != Cy_GPIO_Read(port, pin)) ? IRQ_RISE : IRQ_FALL;
+            if (0UL == (obj->mode & event)) {
+                /* In case of very short pulse, actually both edges are occurred, so indicating only the supported one */
+                event = obj->mode;
+            } /* Otherwise the determined edge is supported (0UL != (obj->mode & event)), so indicating it as is */
+
             obj->handler(obj->id_arg, event);
         }
     }
@@ -182,10 +192,11 @@ static int gpio_irq_setup_channel(gpio_irq_t *obj)
         irq_config.cm0pSrc = obj->cm0p_irq_src;
 #endif
         if (Cy_SysInt_Init(&irq_config, irq_dispatcher_table[obj->port_id]) != CY_SYSINT_SUCCESS) {
-            return(-1);
+            return (-1);
         }
 
         irq_port_usage[obj->port_id].pin_mask |= (1 << obj->pin);
+        gpio_irq_enable(obj);
         NVIC_EnableIRQ(irqn);
     }
 
@@ -204,6 +215,9 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
         }
         obj->handler = handler;
         obj->id_arg = id;
+        /* Save reference to current object */
+        irq_objects[obj->port_id][obj->pin] = obj;
+
         return gpio_irq_setup_channel(obj);
     } else {
         return (-1);

targets/TARGET_Cypress/TARGET_PSOC6/gpio_object.h

@@ -1,6 +1,8 @@
 /*
  * mbed Microcontroller Library
  * Copyright (c) 2017-2018 Future Electronics
+ * Copyright (c) 2018-2019 Cypress Semiconductor Corporation
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -22,7 +24,7 @@
 #include "PinNamesTypes.h"
 #include "PinNames.h"
 
-#include "drivers/peripheral/gpio/cy_gpio.h"
+#include "cy_gpio.h"
 
 #ifdef __cplusplus
 extern "C" {