Skip to content

Commit 5af16c9

Browse files
0xc01700xc0170
authored
Merge pull request #2079 from fvincenzo/master
[BEETLE] Add BLE support
2 parents ebfe44c + 3785de8 commit 5af16c9

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

74 files changed

+9921
-96
lines changed

‎hal/targets.json

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1522,7 +1522,8 @@
15221522
"template": ["uvision5_arm_beetle_soc.uvproj.tmpl"]
15231523
}
15241524
},
1525-
"device_has": ["ANALOGIN", "CLCD", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI"]
1525+
"device_has": ["ANALOGIN", "CLCD", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI"],
1526+
"features": ["BLE"]
15261527
},
15271528
"RZ_A1H": {
15281529
"supported_form_factors": ["ARDUINO"],

‎hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_ARM_STD/BEETLE.sct

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ LR_IROM1 0x00000000 0x00040000 { ; load region size_region
2727
*.o (RESET, +FIRST)
2828
*(InRoot$$Sections)
2929
.ANY (+RO)
30+
CORDIO_RO_2.1.o (*)
3031
}
3132
; Total: 80 vectors = 320 bytes (0x140) to be reserved in RAM
3233
RW_IRAM1 (0x20000000+0x140) (0x20000-0x140) { ; RW data

‎hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_GCC_ARM/BEETLE.ld

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,12 @@ SECTIONS
7070
. = ALIGN(4);
7171
} > VECTORS
7272

73+
.cordio :
74+
{
75+
*CORDIO_RO_2.1.o
76+
*TRIM_2.1.o
77+
} > FLASH
78+
7379
.text :
7480
{
7581
*(.text*)

‎hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.c

Lines changed: 61 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -35,10 +35,10 @@ int EFlash_IdCheck()
3535
{
3636
unsigned int eflash_id;
3737

38-
eflash_id = readl(SYS_EFLASH_PIDR2) & (EFLASH_DES_1 | EFLASH_JEDEC);
38+
eflash_id = EFlash_Readl(SYS_EFLASH_PIDR2) & (EFLASH_DES_1 | EFLASH_JEDEC);
3939

40-
if (readl(SYS_EFLASH_PIDR0) != FLS_PID0
41-
|| readl(SYS_EFLASH_PIDR1) != FLS_PID1
40+
if (EFlash_Readl(SYS_EFLASH_PIDR0) != FLS_PID0
41+
|| EFlash_Readl(SYS_EFLASH_PIDR1) != FLS_PID1
4242
|| eflash_id != FLS_PID2)
4343
/* port ID and ARM ID does not match */
4444
return 1;
@@ -52,7 +52,7 @@ int EFlash_ReturnBank1BaseAddress()
5252
unsigned int hwparams0;
5353
int baseaddr;
5454

55-
hwparams0 = readl(SYS_EFLASH_HWPARAMS0) & EFLASH_FLASHSIZE;
55+
hwparams0 = EFlash_Readl(SYS_EFLASH_HWPARAMS0) & EFLASH_FLASHSIZE;
5656

5757
switch(hwparams0)
5858
{
@@ -73,31 +73,35 @@ int EFlash_ReturnBank1BaseAddress()
7373
return baseaddr;
7474
}
7575

76-
/* EFlash_Initialize: eFlash Initialize function */
77-
void EFlash_Initialize()
76+
/* EFlash_DriverInitialize: eFlash Driver Initialize function */
77+
void EFlash_DriverInitialize()
7878
{
7979
/* Find the start address of banks */
8080
eflash.basebank0 = 0x0;
8181
eflash.basebank0_me = 0x40000000;
8282
eflash.basebank1 = EFlash_ReturnBank1BaseAddress();
8383
eflash.basebank1_me = 0x80000000;
84+
}
8485

86+
/* EFlash_ClockConfig: eFlash Clock Configuration */
87+
void EFlash_ClockConfig()
88+
{
8589
/* Wait until eFlash controller gets unlocked */
86-
while ((readl(SYS_EFLASH_STATUS) & EFLASH_LOCK_MASK) == EFLASH_LOCK);
90+
while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_LOCK_MASK) == EFLASH_LOCK);
8791

8892
/*
89-
* Configure to use external clock
90-
* EXTCL = 31250 ns ->
91-
* 1 ms = 32 clock count 32khz ext_clk -> ER_CLK_COUNT = 32
92-
* 1 us = 84 clock count system_clk -> WR_CLK_COUNT = 84
93-
* EXT_CLK_CONF = 0x1 [Erase] External clock used for erase counters (>1ms)
94-
* HCLK used for write counters
95-
* RD_CLK_COUNT = 0x3
96-
*/
97-
writel(SYS_EFLASH_CONFIG0, 0x00200B43);
93+
* Configure to use external clock
94+
* EXTCL = 31250 ns ->
95+
* 1 ms = 32 clock count 32khz ext_clk -> ER_CLK_COUNT = 32
96+
* 1 us = 84 clock count system_clk -> WR_CLK_COUNT = 84
97+
* EXT_CLK_CONF = 0x1 [Erase] External clock used for erase counters (>1ms)
98+
* HCLK used for write counters
99+
* RD_CLK_COUNT = 0x3
100+
*/
101+
EFlash_Writel(SYS_EFLASH_CONFIG0, 0x00200B43);
98102

99103
/* Wait until eFlash controller gets unlocked */
100-
while ((readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY);
104+
while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY);
101105
}
102106

103107
/*
@@ -116,87 +120,87 @@ void EFlash_Erase(int mode)
116120
{
117121
case 0:
118122
/* Wait until eFlash controller gets unlocked */
119-
while ((readl(SYS_EFLASH_STATUS)
123+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
120124
& EFLASH_LOCK_MASK) == EFLASH_LOCK);
121125
/* Erase Block #0 */
122-
writel(SYS_EFLASH_WADDR, eflash.basebank0);
123-
writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
126+
EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank0);
127+
EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
124128
/* Wait until eFlash controller is not busy */
125-
while ((readl(SYS_EFLASH_STATUS)
129+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
126130
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
127131
break;
128132
case 1:
129133
/* Wait until eFlash controller gets unlocked */
130-
while ((readl(SYS_EFLASH_STATUS)
134+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
131135
& EFLASH_LOCK_MASK) == EFLASH_LOCK);
132136
/* Erase Block #1 */
133-
writel(SYS_EFLASH_WADDR, eflash.basebank1);
134-
writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
137+
EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank1);
138+
EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
135139
/* Wait until eFlash controller is not busy */
136-
while ((readl(SYS_EFLASH_STATUS)
140+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
137141
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
138142
break;
139143
case 2:
140144
/* Wait until eFlash controller gets unlocked */
141-
while ((readl(SYS_EFLASH_STATUS)
145+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
142146
& EFLASH_LOCK_MASK) == EFLASH_LOCK);
143147
/* Erase Block #0 + info pages */
144-
writel(SYS_EFLASH_WADDR, eflash.basebank0_me);
145-
writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
148+
EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank0_me);
149+
EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
146150
/* Wait until eFlash controller is not busy */
147-
while ((readl(SYS_EFLASH_STATUS)
151+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
148152
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
149153
break;
150154
case 3:
151155
/* Wait until eFlash controller gets unlocked */
152-
while ((readl(SYS_EFLASH_STATUS)
156+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
153157
& EFLASH_LOCK_MASK) == EFLASH_LOCK);
154158
/* Erase Block #1 + info pages */
155-
writel(SYS_EFLASH_WADDR, eflash.basebank1_me);
156-
writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
159+
EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank1_me);
160+
EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
157161
/* Wait until eFlash controller is not busy */
158-
while ((readl(SYS_EFLASH_STATUS)
162+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
159163
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
160164
break;
161165
case 4:
162166
/* Wait until eFlash controller gets unlocked */
163-
while ((readl(SYS_EFLASH_STATUS)
167+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
164168
& EFLASH_LOCK_MASK) == EFLASH_LOCK);
165169
/* Erase Block #0 */
166-
writel(SYS_EFLASH_WADDR, eflash.basebank0);
167-
writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
170+
EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank0);
171+
EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
168172
/* Wait until eFlash controller is not busy */
169-
while ((readl(SYS_EFLASH_STATUS)
173+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
170174
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
171175
/* Wait until eFlash controller gets unlocked */
172-
while ((readl(SYS_EFLASH_STATUS)
176+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
173177
& EFLASH_LOCK_MASK) == EFLASH_LOCK);
174178
/* Erase Block #1 */
175-
writel(SYS_EFLASH_WADDR, eflash.basebank1);
176-
writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
179+
EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank1);
180+
EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
177181
/* Wait until eFlash controller gets unlocked */
178182
/* Wait until eFlash controller is not busy */
179-
while ((readl(SYS_EFLASH_STATUS)
183+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
180184
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
181185
break;
182186
case 5:
183187
/* Wait until eFlash controller gets unlocked */
184-
while ((readl(SYS_EFLASH_STATUS)
188+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
185189
& EFLASH_LOCK_MASK) == EFLASH_LOCK);
186190
/* Erase Block #0 + info pages */
187-
writel(SYS_EFLASH_WADDR, eflash.basebank0_me);
188-
writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
191+
EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank0_me);
192+
EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
189193
/* Wait until eFlash controller is not busy */
190-
while ((readl(SYS_EFLASH_STATUS)
194+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
191195
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
192196
/* Wait until eFlash controller gets unlocked */
193-
while ((readl(SYS_EFLASH_STATUS)
197+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
194198
& EFLASH_LOCK_MASK) == EFLASH_LOCK);
195199
/* Erase Block #1 + info pages */
196-
writel(SYS_EFLASH_WADDR, eflash.basebank1_me);
197-
writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
200+
EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank1_me);
201+
EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
198202
/* Wait until eFlash controller is not busy */
199-
while ((readl(SYS_EFLASH_STATUS)
203+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
200204
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
201205
break;
202206
default:
@@ -208,10 +212,10 @@ void EFlash_Erase(int mode)
208212
void EFlash_ErasePage(unsigned int waddr)
209213
{
210214
/* Erase the page starting a waddr */
211-
writel(SYS_EFLASH_WADDR, waddr);
212-
writel(SYS_EFLASH_CTRL, EFLASH_ERASE);
215+
EFlash_Writel(SYS_EFLASH_WADDR, waddr);
216+
EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_ERASE);
213217
/* Wait until eFlash controller gets unlocked */
214-
while ((readl(SYS_EFLASH_STATUS)
218+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
215219
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
216220
}
217221

@@ -224,13 +228,13 @@ void EFlash_ErasePage(unsigned int waddr)
224228
void EFlash_Write(unsigned int waddr, unsigned int data)
225229
{
226230
/* Set Write Data Register */
227-
writel(SYS_EFLASH_WDATA, data);
231+
EFlash_Writel(SYS_EFLASH_WDATA, data);
228232
/* Set Write Address Register */
229-
writel(SYS_EFLASH_WADDR, waddr);
233+
EFlash_Writel(SYS_EFLASH_WADDR, waddr);
230234
/* Start Write Operation through CTRL register */
231-
writel(SYS_EFLASH_CTRL, EFLASH_WRITE);
235+
EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_WRITE);
232236
/* Wait until eFlash controller gets unlocked */
233-
while ((readl(SYS_EFLASH_STATUS)
237+
while ((EFlash_Readl(SYS_EFLASH_STATUS)
234238
& EFLASH_BUSY_MASK) == EFLASH_BUSY);
235239

236240
/* Flash Cache invalidate if FCache enabled */
@@ -275,7 +279,7 @@ int EFlash_WritePage(unsigned int waddr, unsigned int page_size,
275279
*/
276280
unsigned int EFlash_Read(unsigned int waddr)
277281
{
278-
unsigned int eflash_read = readl(waddr);
282+
unsigned int eflash_read = EFlash_Readl(waddr);
279283
return eflash_read;
280284
}
281285

‎hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.h

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -62,8 +62,8 @@ extern "C" {
6262
#define EFLASH_REVISION 0xF0 /* Revision number */
6363

6464
/* Macros */
65-
#define readl(reg) *(volatile unsigned int *)reg
66-
#define writel(reg, val) *(unsigned int *)reg = val;
65+
#define EFlash_Readl(reg) *(volatile unsigned int *)reg
66+
#define EFlash_Writel(reg, val) *(volatile unsigned int *)reg = val;
6767

6868
/* peripheral and component ID values */
6969
#define FLS_PID4 0x14
@@ -80,8 +80,12 @@ extern "C" {
8080
#define FLS_CID3 0xB1
8181

8282
/* Functions */
83-
/* EFlash_Initialize: eFlash Initialize function */
84-
void EFlash_Initialize(void);
83+
/* EFlash_DriverInitialize: eFlash Driver Initialize function */
84+
void EFlash_DriverInitialize(void);
85+
86+
/* EFlash_ClockConfig: eFlash Clock Configuration */
87+
void EFlash_ClockConfig(void);
88+
8589
/*
8690
* EFlash_Erase: Erases flash banks
8791
* Mode:

0 commit comments

Comments
 (0)