Merge pull request #9 from meriac/master

Migrate existing uVisor patches

Author: mshawcroft

core/uvisor-mbed-lib.lib

@@ -0,0 +1 @@
+https://github.com/ARMmbed/uvisor-mbed-lib/#32b6df4

hal/common/retarget.cpp

@@ -469,21 +469,27 @@ extern "C" uint32_t  __HeapLimit;
 #undef errno
 extern "C" int errno;
 
-// For ARM7 only
-register unsigned char * stack_ptr __asm ("sp");
+// Stack pointer handling
+#ifdef  __ICCARM__
+#define __current_sp() __get_SP()
+#else
+static inline unsigned int __current_sp(void)
+{
+    register unsigned sp asm("sp");
+    return sp;
+}
+#endif /* __ICCARM__ */
 
 // Dynamic memory allocation related syscall.
 extern "C" caddr_t _sbrk(int incr) {
     static unsigned char* heap = (unsigned char*)&__end__;
     unsigned char*        prev_heap = heap;
     unsigned char*        new_heap = heap + incr;
 
-#if defined(TARGET_ARM7)
-    if (new_heap >= stack_ptr) {
-#elif defined(TARGET_CORTEX_A)
+#if defined(TARGET_CORTEX_A)
     if (new_heap >= (unsigned char*)&__HeapLimit) {     /* __HeapLimit is end of heap section */
 #else
-    if (new_heap >= (unsigned char*)__get_MSP()) {
+    if (new_heap >= (unsigned char*)__current_sp()) {
 #endif
         errno = ENOMEM;
         return (caddr_t)-1;

hal/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_GCC_ARM/K64FN1M0xxx12.ld

@@ -7,7 +7,7 @@ MEMORY
   VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400
   FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
   FLASH (rx)            : ORIGIN = 0x00000410, LENGTH = 0x00100000 - 0x00000410
-  RAM (rwx)             : ORIGIN = 0x1FFF0198, LENGTH = 0x00040000 - 0x00000198
+  RAM (rwx)             : ORIGIN = 0x1FFF0200, LENGTH = 0x00040000 - 0x00000200
 }
 
 /* Linker script to place sections and symbol values. Should be used together
@@ -55,8 +55,41 @@ SECTIONS
          . = ALIGN(4);
     } > FLASH_PROTECTION
 
+    /* Ensure that the uVisor .bss is the first section in the public SRAM. */
+    .uvisor.bss (NOLOAD):
+    {
+        . = ALIGN(32);
+        __uvisor_bss_start = .;
+
+        /* uVisor main .bss (protected) */
+        . = ALIGN(32);
+        __uvisor_bss_main_start = .;
+        KEEP(*(.keep.uvisor.bss.main))
+        . = ALIGN(32);
+        __uvisor_bss_main_end = .;
+
+        /* Secure boxes .bss (protected) */
+        . = ALIGN(32);
+        __uvisor_bss_boxes_start = .;
+        KEEP(*(.keep.uvisor.bss.boxes))
+        . = ALIGN(32);
+        __uvisor_bss_boxes_end = .;
+
+        . = ALIGN(32);
+        __uvisor_bss_end = .;
+    } > RAM
+
     .text :
     {
+        /* uVisor code and data */
+        /* Note: This is the location of the uVisor binary in flash. Make sure
+         * this position correspond to the FLASH_OFFSET set in the uVisor
+         * configuration. */
+        . = ALIGN(4);
+        __uvisor_main_start = .;
+        *(.uvisor.main)
+        __uvisor_main_end = .;
+
         *(.text*)
 
         KEEP(*(.init))
@@ -93,10 +126,10 @@ SECTIONS
     } > FLASH
     __exidx_end = .;
 
-    __etext = .;
-
-    .data : AT (__etext)
+    .data :
     {
+        PROVIDE( __etext = LOADADDR(.data) );
+
         __data_start__ = .;
         *(vtable)
         *(.data*)
@@ -126,6 +159,44 @@ SECTIONS
         /* All data end */
         __data_end__ = .;
 
+    } > RAM AT>FLASH
+
+    /* uVisor configuration data */
+    .uvisor.secure :
+    {
+        . = ALIGN(32);
+        __uvisor_secure_start = .;
+
+        /* Secure boxes configuration tables (protected) */
+        . = ALIGN(32);
+        __uvisor_cfgtbl_start = .;
+        KEEP(*(.keep.uvisor.cfgtbl))
+        . = ALIGN(32);
+        __uvisor_cfgtbl_end = .;
+
+        /* Pointers to the secure boxes configuration tables (protected) */
+        /* Note: Do not add any further alignment here, as we use this pointer
+         * table to enumerate boxes. */
+        __uvisor_cfgtbl_ptr_start = .;
+        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
+        KEEP(*(.keep.uvisor.cfgtbl_ptr))
+        __uvisor_cfgtbl_ptr_end = .;
+
+        . = ALIGN(32);
+        __uvisor_secure_end = .;
+    } >FLASH
+
+    /* Uninitialized memory section
+     * The C/C++ library initialization will not touch this section. Data
+     * written here will keep its value on reboots (assuming no power loss). */
+    .uninitialized (NOLOAD):
+    {
+        . = ALIGN(32);
+        __uninitialized_start = .;
+        *(.uninitialized)
+        KEEP(*(.keep.uninitialized))
+        . = ALIGN(32);
+        __uninitialized_end = .;
     } > RAM
 
     .bss :
@@ -160,5 +231,13 @@ SECTIONS
 
     /* Check if data + heap + stack exceeds RAM limit */
     ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+    /* Provide physical memory boundaries for uVisor. */
+    __uvisor_flash_start = ORIGIN(VECTORS);
+    __uvisor_flash_offset = ORIGIN(FLASH);
+    __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
+    __uvisor_sram_start = ORIGIN(RAM) - 0x200;
+    __uvisor_sram_offset = ORIGIN(RAM);
+    __uvisor_sram_end = ORIGIN(RAM) + LENGTH(RAM);
 }
 

hal/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S

@@ -229,6 +229,8 @@ disable_watchdog:
 
     ldr   r0, =SystemInit
     blx   r0
+    ldr   r0, =uvisor_init
+    blx   r0
     ldr   r0, =_start
     bx    r0
     .pool

hal/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/interrupt/fsl_interrupt_manager.h

@@ -89,7 +89,7 @@ static inline void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
     assert(irqNumber <= FSL_FEATURE_INTERRUPT_IRQ_MAX);
 
     /* call core API to enable the IRQ*/
-    NVIC_EnableIRQ(irqNumber);
+    vIRQ_EnableIRQ(irqNumber);
 }
 
 /*!
@@ -108,7 +108,7 @@ static inline void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
     assert(irqNumber <= FSL_FEATURE_INTERRUPT_IRQ_MAX);
 
     /* call core API to disable the IRQ*/
-    NVIC_DisableIRQ(irqNumber);
+    vIRQ_DisableIRQ(irqNumber);
 }
 
 /*!

hal/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/fsl_bitaccess.h

@@ -9,6 +9,9 @@
 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
 **     All rights reserved.
 **
+**     (C) COPYRIGHT 2015-2015 ARM Limited
+**     ALL RIGHTS RESERVED
+**
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -62,6 +65,10 @@
 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
 **         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2015-07-30) (ARM)
+**         Macros for bitband address calculation have been decoupled from the
+**         actual address de-referencing in BITBAND_ACCESSxx macros;
+**         Added fallback macros for default read/write operations
 **
 ** ###################################################################
 */
@@ -72,6 +79,51 @@
 
 #include <stdint.h>
 #include <stdlib.h>
+#include "uvisor-lib/uvisor-lib.h"
+
+/*
+ * Fallback macros for write/read operations
+ */
+#ifndef ADDRESS_READ
+/* the conditional statement will be optimised away since the compiler already
+ * knows the sizeof(type) */
+#define ADDRESS_READ(type, addr) \
+    (sizeof(type) == 4 ? *((volatile uint32_t *) (addr)) : \
+     sizeof(type) == 2 ? *((volatile uint16_t *) (addr)) : \
+     sizeof(type) == 1 ? *((volatile uint8_t  *) (addr)) : 0)
+#endif
+
+#ifndef ADDRESS_WRITE
+/* the switch statement will be optimised away since the compiler already knows
+ * the sizeof(type) */
+#define ADDRESS_WRITE(type, addr, val) \
+    { \
+        switch(sizeof(type)) \
+        { \
+            case 4: \
+                *((volatile uint32_t *) (addr)) = (uint32_t) (val); \
+                break; \
+            case 2: \
+                *((volatile uint16_t *) (addr)) = (uint16_t) (val); \
+                break; \
+            case 1: \
+                *((volatile uint8_t  *) (addr)) = (uint8_t ) (val); \
+                break; \
+        } \
+    }
+#endif
+
+#ifndef UNION_READ
+#define UNION_READ(type, addr, fieldU, fieldB) ((*((volatile type *) (addr))).fieldB)
+#endif
+
+/*
+ * Macros to translate a pair of regular address and bit to their bit band alias
+ */
+#define BITBAND_ADDRESS(Reg,Bit)   (0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+#define BITBAND_ADDRESS32(Reg,Bit) ((uint32_t volatile*)BITBAND_ADDRESS(Reg,Bit))
+#define BITBAND_ADDRESS16(Reg,Bit) ((uint16_t volatile*)BITBAND_ADDRESS(Reg,Bit))
+#define BITBAND_ADDRESS8(Reg,Bit)  ((uint8_t  volatile*)BITBAND_ADDRESS(Reg,Bit))
 
 /**
  * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
@@ -80,7 +132,7 @@
  * @param Bit Bit number to access.
  * @return Value of the targeted bit in the bit band region.
  */
-#define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
+#define BITBAND_ACCESS32(Reg,Bit) (*BITBAND_ADDRESS32(Reg,Bit))
 
 /**
  * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region
@@ -89,7 +141,7 @@
  * @param Bit Bit number to access.
  * @return Value of the targeted bit in the bit band region.
  */
-#define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
+#define BITBAND_ACCESS16(Reg,Bit) (*BITBAND_ADDRESS16(Reg,Bit))
 
 /**
  * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region
@@ -98,7 +150,7 @@
  * @param Bit Bit number to access.
  * @return Value of the targeted bit in the bit band region.
  */
-#define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
+#define BITBAND_ACCESS8(Reg,Bit) (*BITBAND_ADDRESS8(Reg,Bit))
 
 /*
  * Macros for single instance registers