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Merge pull request #14482 from jeromecoutant/PR_L4_SYSCLOCK
STM32L4: align all system_clock files
2 parents 7328e58 + 1a27351 commit 0075eea

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12 files changed

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‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/system_clock.c

Lines changed: 46 additions & 83 deletions
Original file line numberDiff line numberDiff line change
@@ -1,46 +1,40 @@
11
/* mbed Microcontroller Library
2-
* Copyright (c) 2016-2020 STMicroelectronics
3-
* SPDX-License-Identifier: Apache-2.0
2+
* SPDX-License-Identifier: BSD-3-Clause
3+
******************************************************************************
44
*
5-
* Licensed under the Apache License, Version 2.0 (the "License");
6-
* you may not use this file except in compliance with the License.
7-
* You may obtain a copy of the License at
5+
* Copyright (c) 2015-2021 STMicroelectronics.
6+
* All rights reserved.
87
*
9-
* http://www.apache.org/licenses/LICENSE-2.0
8+
* This software component is licensed by ST under BSD 3-Clause license,
9+
* the "License"; You may not use this file except in compliance with the
10+
* License. You may obtain a copy of the License at:
11+
* opensource.org/licenses/BSD-3-Clause
1012
*
11-
* Unless required by applicable law or agreed to in writing, software
12-
* distributed under the License is distributed on an "AS IS" BASIS,
13-
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14-
* See the License for the specific language governing permissions and
15-
* limitations under the License.
13+
******************************************************************************
1614
*/
1715

1816
/**
19-
* This file configures the system clock as follows:
20-
*=============================================================================
21-
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
22-
* | (external 8 MHz clock) | (internal 16 MHz)
23-
* | 2- PLL_HSE_XTAL | or PLL_MSI
24-
* | (external 8 MHz xtal) | (internal 4 MHz)
17+
* This file configures the system clock depending on config from targets.json:
2518
*-----------------------------------------------------------------------------
26-
* SYSCLK(MHz) | 48 | 80
19+
* System clock source | 1- USE_PLL_HSE_EXTC (external clock)
20+
* | 2- USE_PLL_HSE_XTAL (external xtal)
21+
* | 3- USE_PLL_HSI (internal 16 MHz)
22+
* | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
2723
*-----------------------------------------------------------------------------
28-
* AHBCLK (MHz) | 48 | 80
29-
*-----------------------------------------------------------------------------
30-
* APB1CLK (MHz) | 48 | 80
31-
*-----------------------------------------------------------------------------
32-
* APB2CLK (MHz) | 48 | 80
33-
*-----------------------------------------------------------------------------
34-
* USB capable (48 MHz precise clock) | YES | NO
24+
* SYSCLK(MHz) | 80
25+
* AHBCLK (MHz) | 80
26+
* APB1CLK (MHz) | 80
27+
* APB2CLK (MHz) | 80
28+
* USB capable | YES
3529
*-----------------------------------------------------------------------------
3630
**/
3731

3832
#include "stm32l4xx.h"
3933
#include "mbed_error.h"
4034

4135
// clock source is selected with CLOCK_SOURCE in json config
42-
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
43-
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
36+
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN)
37+
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (OSC_IN/OSC_OUT)
4438
#define USE_PLL_HSI 0x2 // Use HSI internal clock
4539
#define USE_PLL_MSI 0x1 // Use MSI internal clock
4640

@@ -62,13 +56,13 @@ uint8_t SetSysClock_PLL_MSI(void);
6256
/**
6357
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
6458
* AHB/APBx prescalers and Flash settings
65-
* @note This function should be called only once the RCC clock configuration
66-
* is reset to the default reset state (done in SystemInit() function).
59+
* @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c)
60+
* and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c)
6761
* @param None
6862
* @retval None
6963
*/
7064

71-
void SetSysClock(void)
65+
MBED_WEAK void SetSysClock(void)
7266
{
7367
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
7468
/* 1- Try to start with HSE and external clock */
@@ -114,42 +108,35 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
114108
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
115109
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
116110

117-
// Used to gain time after DeepSleep in case HSI is used
118-
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
119-
return 0;
120-
}
121-
122-
// Select MSI as system clock source to allow modification of the PLL configuration
123-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
124-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
125-
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
126-
127111
// Enable HSE oscillator and activate PLL with HSE as source
128-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
112+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
129113
if (bypass == 0) {
130-
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
114+
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External xtal on OSC_IN/OSC_OUT
131115
} else {
132-
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
116+
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External clock on OSC_IN
133117
}
134-
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
135-
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
118+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
136119
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
120+
#if HSE_VALUE==8000000
137121
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
122+
#else
123+
#error Unsupported externall clock value, check HSE_VALUE define
124+
#endif
138125
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
139-
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
126+
RCC_OscInitStruct.PLL.PLLP = 7;
140127
RCC_OscInitStruct.PLL.PLLQ = 2;
141-
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
128+
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
142129

143130
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
144131
return 0; // FAIL
145132
}
146133

147134
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
148135
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
149-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
150-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
151-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
152-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
136+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
137+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
138+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
139+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
153140
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
154141
return 0; // FAIL
155142
}
@@ -169,12 +156,6 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
169156
}
170157
#endif /* DEVICE_USBDEVICE */
171158

172-
// Disable MSI Oscillator
173-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
174-
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
175-
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
176-
HAL_RCC_OscConfig(&RCC_OscInitStruct);
177-
178159
// Output clock on MCO1 pin(PA8) for debugging purpose
179160
#if DEBUG_MCO == 2
180161
if (bypass == 0) {
@@ -198,23 +179,17 @@ uint8_t SetSysClock_PLL_HSI(void)
198179
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
199180
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
200181

201-
// Select MSI as system clock source to allow modification of the PLL configuration
202-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
203-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
204-
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
205-
206182
// Enable HSI oscillator and activate PLL with HSI as source
207-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
208-
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
183+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
209184
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
210185
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
211186
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
212187
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
213-
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
188+
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
214189
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
215-
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
190+
RCC_OscInitStruct.PLL.PLLP = 7;
216191
RCC_OscInitStruct.PLL.PLLQ = 2;
217-
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
192+
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
218193
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
219194
return 0; // FAIL
220195
}
@@ -244,12 +219,6 @@ uint8_t SetSysClock_PLL_HSI(void)
244219
}
245220
#endif /* DEVICE_USBDEVICE */
246221

247-
// Disable MSI Oscillator
248-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
249-
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
250-
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
251-
HAL_RCC_OscConfig(&RCC_OscInitStruct);
252-
253222
// Output clock on MCO1 pin(PA8) for debugging purpose
254223
#if DEBUG_MCO == 3
255224
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
@@ -263,7 +232,7 @@ uint8_t SetSysClock_PLL_HSI(void)
263232
/******************************************************************************/
264233
/* PLL (clocked by MSI) used as System clock source */
265234
/******************************************************************************/
266-
uint8_t SetSysClock_PLL_MSI(void)
235+
MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
267236
{
268237
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
269238
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
@@ -273,21 +242,15 @@ uint8_t SetSysClock_PLL_MSI(void)
273242
// Enable LSE Oscillator to automatically calibrate the MSI clock
274243
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
275244
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
276-
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
245+
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC32_IN/OSC32_OUT
277246
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
278247
return 0; // FAIL
279248
}
280-
281-
/* Enable the CSS interrupt in case LSE signal is corrupted or not present */
282-
HAL_RCCEx_DisableLSECSS();
283249
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
284250

285251
/* Enable MSI Oscillator and activate PLL with MSI as source */
286-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
287-
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
288-
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
289-
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
290-
252+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
253+
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
291254
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
292255
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
293256
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;

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